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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <asm/hazards.h>
18#include <asm/war.h>
19
20/*
21 * The following macros are especially useful for __asm__
22 * inline assembler.
23 */
24#ifndef __STR
25#define __STR(x) #x
26#endif
27#ifndef STR
28#define STR(x) __STR(x)
29#endif
30
31/*
32 * Configure language
33 */
34#ifdef __ASSEMBLY__
35#define _ULCAST_
36#else
37#define _ULCAST_ (unsigned long)
38#endif
39
40/*
41 * Coprocessor 0 register names
42 */
43#define CP0_INDEX $0
44#define CP0_RANDOM $1
45#define CP0_ENTRYLO0 $2
46#define CP0_ENTRYLO1 $3
47#define CP0_CONF $3
48#define CP0_CONTEXT $4
49#define CP0_PAGEMASK $5
50#define CP0_WIRED $6
51#define CP0_INFO $7
52#define CP0_BADVADDR $8
53#define CP0_COUNT $9
54#define CP0_ENTRYHI $10
55#define CP0_COMPARE $11
56#define CP0_STATUS $12
57#define CP0_CAUSE $13
58#define CP0_EPC $14
59#define CP0_PRID $15
60#define CP0_CONFIG $16
61#define CP0_LLADDR $17
62#define CP0_WATCHLO $18
63#define CP0_WATCHHI $19
64#define CP0_XCONTEXT $20
65#define CP0_FRAMEMASK $21
66#define CP0_DIAGNOSTIC $22
67#define CP0_DEBUG $23
68#define CP0_DEPC $24
69#define CP0_PERFORMANCE $25
70#define CP0_ECC $26
71#define CP0_CACHEERR $27
72#define CP0_TAGLO $28
73#define CP0_TAGHI $29
74#define CP0_ERROREPC $30
75#define CP0_DESAVE $31
76
77/*
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ...
82 */
83#define CP0_IBASE $0
84#define CP0_IBOUND $1
85#define CP0_DBASE $2
86#define CP0_DBOUND $3
87#define CP0_CALG $17
88#define CP0_IWATCH $18
89#define CP0_DWATCH $19
90
91/*
92 * Coprocessor 0 Set 1 register names
93 */
94#define CP0_S1_DERRADDR0 $26
95#define CP0_S1_DERRADDR1 $27
96#define CP0_S1_INTCONTROL $20
97
98/*
99 * Coprocessor 0 Set 2 register names
100 */
101#define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103/*
104 * Coprocessor 0 Set 3 register names
105 */
106#define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108/*
109 * TX39 Series
110 */
111#define CP0_TX39_CACHE $7
112
113/*
114 * Coprocessor 1 (FPU) register names
115 */
116#define CP1_REVISION $0
117#define CP1_STATUS $31
118
119/*
120 * FPU Status Register Values
121 */
122/*
123 * Status Register Values
124 */
125
126#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127#define FPU_CSR_COND 0x00800000 /* $fcc0 */
128#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136
137/*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
139 * and should be written as zero.
140 */
141#define FPU_CSR_RSVD 0x001c0000
142
143/*
144 * X the exception cause indicator
145 * E the exception enable
146 * S the sticky/flag bit
147*/
148#define FPU_CSR_ALL_X 0x0003f000
149#define FPU_CSR_UNI_X 0x00020000
150#define FPU_CSR_INV_X 0x00010000
151#define FPU_CSR_DIV_X 0x00008000
152#define FPU_CSR_OVF_X 0x00004000
153#define FPU_CSR_UDF_X 0x00002000
154#define FPU_CSR_INE_X 0x00001000
155
156#define FPU_CSR_ALL_E 0x00000f80
157#define FPU_CSR_INV_E 0x00000800
158#define FPU_CSR_DIV_E 0x00000400
159#define FPU_CSR_OVF_E 0x00000200
160#define FPU_CSR_UDF_E 0x00000100
161#define FPU_CSR_INE_E 0x00000080
162
163#define FPU_CSR_ALL_S 0x0000007c
164#define FPU_CSR_INV_S 0x00000040
165#define FPU_CSR_DIV_S 0x00000020
166#define FPU_CSR_OVF_S 0x00000010
167#define FPU_CSR_UDF_S 0x00000008
168#define FPU_CSR_INE_S 0x00000004
169
170/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171#define FPU_CSR_RM 0x00000003
172#define FPU_CSR_RN 0x0 /* nearest */
173#define FPU_CSR_RZ 0x1 /* towards zero */
174#define FPU_CSR_RU 0x2 /* towards +Infinity */
175#define FPU_CSR_RD 0x3 /* towards -Infinity */
176
177
178/*
179 * Values for PageMask register
180 */
181#ifdef CONFIG_CPU_VR41XX
182
183/* Why doesn't stupidity hurt ... */
184
185#define PM_1K 0x00000000
186#define PM_4K 0x00001800
187#define PM_16K 0x00007800
188#define PM_64K 0x0001f800
189#define PM_256K 0x0007f800
190
191#else
192
193#define PM_4K 0x00000000
194#define PM_8K 0x00002000
195#define PM_16K 0x00006000
196#define PM_32K 0x0000e000
197#define PM_64K 0x0001e000
198#define PM_128K 0x0003e000
199#define PM_256K 0x0007e000
200#define PM_512K 0x000fe000
201#define PM_1M 0x001fe000
202#define PM_2M 0x003fe000
203#define PM_4M 0x007fe000
204#define PM_8M 0x00ffe000
205#define PM_16M 0x01ffe000
206#define PM_32M 0x03ffe000
207#define PM_64M 0x07ffe000
208#define PM_256M 0x1fffe000
209#define PM_1G 0x7fffe000
210
211#endif
212
213/*
214 * Default page size for a given kernel configuration
215 */
216#ifdef CONFIG_PAGE_SIZE_4KB
217#define PM_DEFAULT_MASK PM_4K
218#elif defined(CONFIG_PAGE_SIZE_8KB)
219#define PM_DEFAULT_MASK PM_8K
220#elif defined(CONFIG_PAGE_SIZE_16KB)
221#define PM_DEFAULT_MASK PM_16K
222#elif defined(CONFIG_PAGE_SIZE_32KB)
223#define PM_DEFAULT_MASK PM_32K
224#elif defined(CONFIG_PAGE_SIZE_64KB)
225#define PM_DEFAULT_MASK PM_64K
226#else
227#error Bad page size configuration!
228#endif
229
230/*
231 * Default huge tlb size for a given kernel configuration
232 */
233#ifdef CONFIG_PAGE_SIZE_4KB
234#define PM_HUGE_MASK PM_1M
235#elif defined(CONFIG_PAGE_SIZE_8KB)
236#define PM_HUGE_MASK PM_4M
237#elif defined(CONFIG_PAGE_SIZE_16KB)
238#define PM_HUGE_MASK PM_16M
239#elif defined(CONFIG_PAGE_SIZE_32KB)
240#define PM_HUGE_MASK PM_64M
241#elif defined(CONFIG_PAGE_SIZE_64KB)
242#define PM_HUGE_MASK PM_256M
243#elif defined(CONFIG_HUGETLB_PAGE)
244#error Bad page size configuration for hugetlbfs!
245#endif
246
247/*
248 * Values used for computation of new tlb entries
249 */
250#define PL_4K 12
251#define PL_16K 14
252#define PL_64K 16
253#define PL_256K 18
254#define PL_1M 20
255#define PL_4M 22
256#define PL_16M 24
257#define PL_64M 26
258#define PL_256M 28
259
260/*
261 * PageGrain bits
262 */
263#define PG_RIE (_ULCAST_(1) << 31)
264#define PG_XIE (_ULCAST_(1) << 30)
265#define PG_ELPA (_ULCAST_(1) << 29)
266#define PG_ESP (_ULCAST_(1) << 28)
267
268/*
269 * R4x00 interrupt enable / cause bits
270 */
271#define IE_SW0 (_ULCAST_(1) << 8)
272#define IE_SW1 (_ULCAST_(1) << 9)
273#define IE_IRQ0 (_ULCAST_(1) << 10)
274#define IE_IRQ1 (_ULCAST_(1) << 11)
275#define IE_IRQ2 (_ULCAST_(1) << 12)
276#define IE_IRQ3 (_ULCAST_(1) << 13)
277#define IE_IRQ4 (_ULCAST_(1) << 14)
278#define IE_IRQ5 (_ULCAST_(1) << 15)
279
280/*
281 * R4x00 interrupt cause bits
282 */
283#define C_SW0 (_ULCAST_(1) << 8)
284#define C_SW1 (_ULCAST_(1) << 9)
285#define C_IRQ0 (_ULCAST_(1) << 10)
286#define C_IRQ1 (_ULCAST_(1) << 11)
287#define C_IRQ2 (_ULCAST_(1) << 12)
288#define C_IRQ3 (_ULCAST_(1) << 13)
289#define C_IRQ4 (_ULCAST_(1) << 14)
290#define C_IRQ5 (_ULCAST_(1) << 15)
291
292/*
293 * Bitfields in the R4xx0 cp0 status register
294 */
295#define ST0_IE 0x00000001
296#define ST0_EXL 0x00000002
297#define ST0_ERL 0x00000004
298#define ST0_KSU 0x00000018
299# define KSU_USER 0x00000010
300# define KSU_SUPERVISOR 0x00000008
301# define KSU_KERNEL 0x00000000
302#define ST0_UX 0x00000020
303#define ST0_SX 0x00000040
304#define ST0_KX 0x00000080
305#define ST0_DE 0x00010000
306#define ST0_CE 0x00020000
307
308/*
309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310 * cacheops in userspace. This bit exists only on RM7000 and RM9000
311 * processors.
312 */
313#define ST0_CO 0x08000000
314
315/*
316 * Bitfields in the R[23]000 cp0 status register.
317 */
318#define ST0_IEC 0x00000001
319#define ST0_KUC 0x00000002
320#define ST0_IEP 0x00000004
321#define ST0_KUP 0x00000008
322#define ST0_IEO 0x00000010
323#define ST0_KUO 0x00000020
324/* bits 6 & 7 are reserved on R[23]000 */
325#define ST0_ISC 0x00010000
326#define ST0_SWC 0x00020000
327#define ST0_CM 0x00080000
328
329/*
330 * Bits specific to the R4640/R4650
331 */
332#define ST0_UM (_ULCAST_(1) << 4)
333#define ST0_IL (_ULCAST_(1) << 23)
334#define ST0_DL (_ULCAST_(1) << 24)
335
336/*
337 * Enable the MIPS MDMX and DSP ASEs
338 */
339#define ST0_MX 0x01000000
340
341/*
342 * Bitfields in the TX39 family CP0 Configuration Register 3
343 */
344#define TX39_CONF_ICS_SHIFT 19
345#define TX39_CONF_ICS_MASK 0x00380000
346#define TX39_CONF_ICS_1KB 0x00000000
347#define TX39_CONF_ICS_2KB 0x00080000
348#define TX39_CONF_ICS_4KB 0x00100000
349#define TX39_CONF_ICS_8KB 0x00180000
350#define TX39_CONF_ICS_16KB 0x00200000
351
352#define TX39_CONF_DCS_SHIFT 16
353#define TX39_CONF_DCS_MASK 0x00070000
354#define TX39_CONF_DCS_1KB 0x00000000
355#define TX39_CONF_DCS_2KB 0x00010000
356#define TX39_CONF_DCS_4KB 0x00020000
357#define TX39_CONF_DCS_8KB 0x00030000
358#define TX39_CONF_DCS_16KB 0x00040000
359
360#define TX39_CONF_CWFON 0x00004000
361#define TX39_CONF_WBON 0x00002000
362#define TX39_CONF_RF_SHIFT 10
363#define TX39_CONF_RF_MASK 0x00000c00
364#define TX39_CONF_DOZE 0x00000200
365#define TX39_CONF_HALT 0x00000100
366#define TX39_CONF_LOCK 0x00000080
367#define TX39_CONF_ICE 0x00000020
368#define TX39_CONF_DCE 0x00000010
369#define TX39_CONF_IRSIZE_SHIFT 2
370#define TX39_CONF_IRSIZE_MASK 0x0000000c
371#define TX39_CONF_DRSIZE_SHIFT 0
372#define TX39_CONF_DRSIZE_MASK 0x00000003
373
374/*
375 * Status register bits available in all MIPS CPUs.
376 */
377#define ST0_IM 0x0000ff00
378#define STATUSB_IP0 8
379#define STATUSF_IP0 (_ULCAST_(1) << 8)
380#define STATUSB_IP1 9
381#define STATUSF_IP1 (_ULCAST_(1) << 9)
382#define STATUSB_IP2 10
383#define STATUSF_IP2 (_ULCAST_(1) << 10)
384#define STATUSB_IP3 11
385#define STATUSF_IP3 (_ULCAST_(1) << 11)
386#define STATUSB_IP4 12
387#define STATUSF_IP4 (_ULCAST_(1) << 12)
388#define STATUSB_IP5 13
389#define STATUSF_IP5 (_ULCAST_(1) << 13)
390#define STATUSB_IP6 14
391#define STATUSF_IP6 (_ULCAST_(1) << 14)
392#define STATUSB_IP7 15
393#define STATUSF_IP7 (_ULCAST_(1) << 15)
394#define STATUSB_IP8 0
395#define STATUSF_IP8 (_ULCAST_(1) << 0)
396#define STATUSB_IP9 1
397#define STATUSF_IP9 (_ULCAST_(1) << 1)
398#define STATUSB_IP10 2
399#define STATUSF_IP10 (_ULCAST_(1) << 2)
400#define STATUSB_IP11 3
401#define STATUSF_IP11 (_ULCAST_(1) << 3)
402#define STATUSB_IP12 4
403#define STATUSF_IP12 (_ULCAST_(1) << 4)
404#define STATUSB_IP13 5
405#define STATUSF_IP13 (_ULCAST_(1) << 5)
406#define STATUSB_IP14 6
407#define STATUSF_IP14 (_ULCAST_(1) << 6)
408#define STATUSB_IP15 7
409#define STATUSF_IP15 (_ULCAST_(1) << 7)
410#define ST0_CH 0x00040000
411#define ST0_NMI 0x00080000
412#define ST0_SR 0x00100000
413#define ST0_TS 0x00200000
414#define ST0_BEV 0x00400000
415#define ST0_RE 0x02000000
416#define ST0_FR 0x04000000
417#define ST0_CU 0xf0000000
418#define ST0_CU0 0x10000000
419#define ST0_CU1 0x20000000
420#define ST0_CU2 0x40000000
421#define ST0_CU3 0x80000000
422#define ST0_XX 0x80000000 /* MIPS IV naming */
423
424/*
425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
426 *
427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
428 */
429#define INTCTLB_IPPCI 26
430#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
431#define INTCTLB_IPTI 29
432#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
433
434/*
435 * Bitfields and bit numbers in the coprocessor 0 cause register.
436 *
437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
438 */
439#define CAUSEB_EXCCODE 2
440#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
441#define CAUSEB_IP 8
442#define CAUSEF_IP (_ULCAST_(255) << 8)
443#define CAUSEB_IP0 8
444#define CAUSEF_IP0 (_ULCAST_(1) << 8)
445#define CAUSEB_IP1 9
446#define CAUSEF_IP1 (_ULCAST_(1) << 9)
447#define CAUSEB_IP2 10
448#define CAUSEF_IP2 (_ULCAST_(1) << 10)
449#define CAUSEB_IP3 11
450#define CAUSEF_IP3 (_ULCAST_(1) << 11)
451#define CAUSEB_IP4 12
452#define CAUSEF_IP4 (_ULCAST_(1) << 12)
453#define CAUSEB_IP5 13
454#define CAUSEF_IP5 (_ULCAST_(1) << 13)
455#define CAUSEB_IP6 14
456#define CAUSEF_IP6 (_ULCAST_(1) << 14)
457#define CAUSEB_IP7 15
458#define CAUSEF_IP7 (_ULCAST_(1) << 15)
459#define CAUSEB_IV 23
460#define CAUSEF_IV (_ULCAST_(1) << 23)
461#define CAUSEB_CE 28
462#define CAUSEF_CE (_ULCAST_(3) << 28)
463#define CAUSEB_TI 30
464#define CAUSEF_TI (_ULCAST_(1) << 30)
465#define CAUSEB_BD 31
466#define CAUSEF_BD (_ULCAST_(1) << 31)
467
468/*
469 * Bits in the coprocessor 0 config register.
470 */
471/* Generic bits. */
472#define CONF_CM_CACHABLE_NO_WA 0
473#define CONF_CM_CACHABLE_WA 1
474#define CONF_CM_UNCACHED 2
475#define CONF_CM_CACHABLE_NONCOHERENT 3
476#define CONF_CM_CACHABLE_CE 4
477#define CONF_CM_CACHABLE_COW 5
478#define CONF_CM_CACHABLE_CUW 6
479#define CONF_CM_CACHABLE_ACCELERATED 7
480#define CONF_CM_CMASK 7
481#define CONF_BE (_ULCAST_(1) << 15)
482
483/* Bits common to various processors. */
484#define CONF_CU (_ULCAST_(1) << 3)
485#define CONF_DB (_ULCAST_(1) << 4)
486#define CONF_IB (_ULCAST_(1) << 5)
487#define CONF_DC (_ULCAST_(7) << 6)
488#define CONF_IC (_ULCAST_(7) << 9)
489#define CONF_EB (_ULCAST_(1) << 13)
490#define CONF_EM (_ULCAST_(1) << 14)
491#define CONF_SM (_ULCAST_(1) << 16)
492#define CONF_SC (_ULCAST_(1) << 17)
493#define CONF_EW (_ULCAST_(3) << 18)
494#define CONF_EP (_ULCAST_(15)<< 24)
495#define CONF_EC (_ULCAST_(7) << 28)
496#define CONF_CM (_ULCAST_(1) << 31)
497
498/* Bits specific to the R4xx0. */
499#define R4K_CONF_SW (_ULCAST_(1) << 20)
500#define R4K_CONF_SS (_ULCAST_(1) << 21)
501#define R4K_CONF_SB (_ULCAST_(3) << 22)
502
503/* Bits specific to the R5000. */
504#define R5K_CONF_SE (_ULCAST_(1) << 12)
505#define R5K_CONF_SS (_ULCAST_(3) << 20)
506
507/* Bits specific to the RM7000. */
508#define RM7K_CONF_SE (_ULCAST_(1) << 3)
509#define RM7K_CONF_TE (_ULCAST_(1) << 12)
510#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
511#define RM7K_CONF_TC (_ULCAST_(1) << 17)
512#define RM7K_CONF_SI (_ULCAST_(3) << 20)
513#define RM7K_CONF_SC (_ULCAST_(1) << 31)
514
515/* Bits specific to the R10000. */
516#define R10K_CONF_DN (_ULCAST_(3) << 3)
517#define R10K_CONF_CT (_ULCAST_(1) << 5)
518#define R10K_CONF_PE (_ULCAST_(1) << 6)
519#define R10K_CONF_PM (_ULCAST_(3) << 7)
520#define R10K_CONF_EC (_ULCAST_(15)<< 9)
521#define R10K_CONF_SB (_ULCAST_(1) << 13)
522#define R10K_CONF_SK (_ULCAST_(1) << 14)
523#define R10K_CONF_SS (_ULCAST_(7) << 16)
524#define R10K_CONF_SC (_ULCAST_(7) << 19)
525#define R10K_CONF_DC (_ULCAST_(7) << 26)
526#define R10K_CONF_IC (_ULCAST_(7) << 29)
527
528/* Bits specific to the VR41xx. */
529#define VR41_CONF_CS (_ULCAST_(1) << 12)
530#define VR41_CONF_P4K (_ULCAST_(1) << 13)
531#define VR41_CONF_BP (_ULCAST_(1) << 16)
532#define VR41_CONF_M16 (_ULCAST_(1) << 20)
533#define VR41_CONF_AD (_ULCAST_(1) << 23)
534
535/* Bits specific to the R30xx. */
536#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
537#define R30XX_CONF_REV (_ULCAST_(1) << 22)
538#define R30XX_CONF_AC (_ULCAST_(1) << 23)
539#define R30XX_CONF_RF (_ULCAST_(1) << 24)
540#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
541#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
542#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
543#define R30XX_CONF_SB (_ULCAST_(1) << 30)
544#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
545
546/* Bits specific to the TX49. */
547#define TX49_CONF_DC (_ULCAST_(1) << 16)
548#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
549#define TX49_CONF_HALT (_ULCAST_(1) << 18)
550#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
551
552/* Bits specific to the MIPS32/64 PRA. */
553#define MIPS_CONF_MT (_ULCAST_(7) << 7)
554#define MIPS_CONF_AR (_ULCAST_(7) << 10)
555#define MIPS_CONF_AT (_ULCAST_(3) << 13)
556#define MIPS_CONF_M (_ULCAST_(1) << 31)
557
558/*
559 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
560 */
561#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
562#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
563#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
564#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
565#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
566#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
567#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
568#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
569#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
570#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
571#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
572#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
573#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
574#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
575
576#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
577#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
578#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
579#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
580#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
581#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
582#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
583#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
584
585#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
586#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
587#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
588#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
589#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
590#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
591#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
592#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
593#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
594
595#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
596#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
597#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
598
599#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
600
601#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
602
603
604/*
605 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
606 */
607#define MIPS_FPIR_S (_ULCAST_(1) << 16)
608#define MIPS_FPIR_D (_ULCAST_(1) << 17)
609#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
610#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
611#define MIPS_FPIR_W (_ULCAST_(1) << 20)
612#define MIPS_FPIR_L (_ULCAST_(1) << 21)
613#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
614
615#ifndef __ASSEMBLY__
616
617/*
618 * Functions to access the R10000 performance counters. These are basically
619 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
620 * performance counter number encoded into bits 1 ... 5 of the instruction.
621 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
622 * disassembler these will look like an access to sel 0 or 1.
623 */
624#define read_r10k_perf_cntr(counter) \
625({ \
626 unsigned int __res; \
627 __asm__ __volatile__( \
628 "mfpc\t%0, %1" \
629 : "=r" (__res) \
630 : "i" (counter)); \
631 \
632 __res; \
633})
634
635#define write_r10k_perf_cntr(counter,val) \
636do { \
637 __asm__ __volatile__( \
638 "mtpc\t%0, %1" \
639 : \
640 : "r" (val), "i" (counter)); \
641} while (0)
642
643#define read_r10k_perf_event(counter) \
644({ \
645 unsigned int __res; \
646 __asm__ __volatile__( \
647 "mfps\t%0, %1" \
648 : "=r" (__res) \
649 : "i" (counter)); \
650 \
651 __res; \
652})
653
654#define write_r10k_perf_cntl(counter,val) \
655do { \
656 __asm__ __volatile__( \
657 "mtps\t%0, %1" \
658 : \
659 : "r" (val), "i" (counter)); \
660} while (0)
661
662
663/*
664 * Macros to access the system control coprocessor
665 */
666
667#define __read_32bit_c0_register(source, sel) \
668({ int __res; \
669 if (sel == 0) \
670 __asm__ __volatile__( \
671 "mfc0\t%0, " #source "\n\t" \
672 : "=r" (__res)); \
673 else \
674 __asm__ __volatile__( \
675 ".set\tmips32\n\t" \
676 "mfc0\t%0, " #source ", " #sel "\n\t" \
677 ".set\tmips0\n\t" \
678 : "=r" (__res)); \
679 __res; \
680})
681
682#define __read_64bit_c0_register(source, sel) \
683({ unsigned long long __res; \
684 if (sizeof(unsigned long) == 4) \
685 __res = __read_64bit_c0_split(source, sel); \
686 else if (sel == 0) \
687 __asm__ __volatile__( \
688 ".set\tmips3\n\t" \
689 "dmfc0\t%0, " #source "\n\t" \
690 ".set\tmips0" \
691 : "=r" (__res)); \
692 else \
693 __asm__ __volatile__( \
694 ".set\tmips64\n\t" \
695 "dmfc0\t%0, " #source ", " #sel "\n\t" \
696 ".set\tmips0" \
697 : "=r" (__res)); \
698 __res; \
699})
700
701#define __write_32bit_c0_register(register, sel, value) \
702do { \
703 if (sel == 0) \
704 __asm__ __volatile__( \
705 "mtc0\t%z0, " #register "\n\t" \
706 : : "Jr" ((unsigned int)(value))); \
707 else \
708 __asm__ __volatile__( \
709 ".set\tmips32\n\t" \
710 "mtc0\t%z0, " #register ", " #sel "\n\t" \
711 ".set\tmips0" \
712 : : "Jr" ((unsigned int)(value))); \
713} while (0)
714
715#define __write_64bit_c0_register(register, sel, value) \
716do { \
717 if (sizeof(unsigned long) == 4) \
718 __write_64bit_c0_split(register, sel, value); \
719 else if (sel == 0) \
720 __asm__ __volatile__( \
721 ".set\tmips3\n\t" \
722 "dmtc0\t%z0, " #register "\n\t" \
723 ".set\tmips0" \
724 : : "Jr" (value)); \
725 else \
726 __asm__ __volatile__( \
727 ".set\tmips64\n\t" \
728 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
729 ".set\tmips0" \
730 : : "Jr" (value)); \
731} while (0)
732
733#define __read_ulong_c0_register(reg, sel) \
734 ((sizeof(unsigned long) == 4) ? \
735 (unsigned long) __read_32bit_c0_register(reg, sel) : \
736 (unsigned long) __read_64bit_c0_register(reg, sel))
737
738#define __write_ulong_c0_register(reg, sel, val) \
739do { \
740 if (sizeof(unsigned long) == 4) \
741 __write_32bit_c0_register(reg, sel, val); \
742 else \
743 __write_64bit_c0_register(reg, sel, val); \
744} while (0)
745
746/*
747 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
748 */
749#define __read_32bit_c0_ctrl_register(source) \
750({ int __res; \
751 __asm__ __volatile__( \
752 "cfc0\t%0, " #source "\n\t" \
753 : "=r" (__res)); \
754 __res; \
755})
756
757#define __write_32bit_c0_ctrl_register(register, value) \
758do { \
759 __asm__ __volatile__( \
760 "ctc0\t%z0, " #register "\n\t" \
761 : : "Jr" ((unsigned int)(value))); \
762} while (0)
763
764/*
765 * These versions are only needed for systems with more than 38 bits of
766 * physical address space running the 32-bit kernel. That's none atm :-)
767 */
768#define __read_64bit_c0_split(source, sel) \
769({ \
770 unsigned long long __val; \
771 unsigned long __flags; \
772 \
773 local_irq_save(__flags); \
774 if (sel == 0) \
775 __asm__ __volatile__( \
776 ".set\tmips64\n\t" \
777 "dmfc0\t%M0, " #source "\n\t" \
778 "dsll\t%L0, %M0, 32\n\t" \
779 "dsra\t%M0, %M0, 32\n\t" \
780 "dsra\t%L0, %L0, 32\n\t" \
781 ".set\tmips0" \
782 : "=r" (__val)); \
783 else \
784 __asm__ __volatile__( \
785 ".set\tmips64\n\t" \
786 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
787 "dsll\t%L0, %M0, 32\n\t" \
788 "dsra\t%M0, %M0, 32\n\t" \
789 "dsra\t%L0, %L0, 32\n\t" \
790 ".set\tmips0" \
791 : "=r" (__val)); \
792 local_irq_restore(__flags); \
793 \
794 __val; \
795})
796
797#define __write_64bit_c0_split(source, sel, val) \
798do { \
799 unsigned long __flags; \
800 \
801 local_irq_save(__flags); \
802 if (sel == 0) \
803 __asm__ __volatile__( \
804 ".set\tmips64\n\t" \
805 "dsll\t%L0, %L0, 32\n\t" \
806 "dsrl\t%L0, %L0, 32\n\t" \
807 "dsll\t%M0, %M0, 32\n\t" \
808 "or\t%L0, %L0, %M0\n\t" \
809 "dmtc0\t%L0, " #source "\n\t" \
810 ".set\tmips0" \
811 : : "r" (val)); \
812 else \
813 __asm__ __volatile__( \
814 ".set\tmips64\n\t" \
815 "dsll\t%L0, %L0, 32\n\t" \
816 "dsrl\t%L0, %L0, 32\n\t" \
817 "dsll\t%M0, %M0, 32\n\t" \
818 "or\t%L0, %L0, %M0\n\t" \
819 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
820 ".set\tmips0" \
821 : : "r" (val)); \
822 local_irq_restore(__flags); \
823} while (0)
824
825#define read_c0_index() __read_32bit_c0_register($0, 0)
826#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
827
828#define read_c0_random() __read_32bit_c0_register($1, 0)
829#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
830
831#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
832#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
833
834#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
835#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
836
837#define read_c0_conf() __read_32bit_c0_register($3, 0)
838#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
839
840#define read_c0_context() __read_ulong_c0_register($4, 0)
841#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
842
843#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
844#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
845
846#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
847#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
848
849#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
850#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
851
852#define read_c0_wired() __read_32bit_c0_register($6, 0)
853#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
854
855#define read_c0_info() __read_32bit_c0_register($7, 0)
856
857#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
858#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
859
860#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
861#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
862
863#define read_c0_count() __read_32bit_c0_register($9, 0)
864#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
865
866#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
867#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
868
869#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
870#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
871
872#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
873#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
874
875#define read_c0_compare() __read_32bit_c0_register($11, 0)
876#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
877
878#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
879#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
880
881#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
882#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
883
884#define read_c0_status() __read_32bit_c0_register($12, 0)
885#ifdef CONFIG_MIPS_MT_SMTC
886#define write_c0_status(val) \
887do { \
888 __write_32bit_c0_register($12, 0, val); \
889 __ehb(); \
890} while (0)
891#else
892/*
893 * Legacy non-SMTC code, which may be hazardous
894 * but which might not support EHB
895 */
896#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
897#endif /* CONFIG_MIPS_MT_SMTC */
898
899#define read_c0_cause() __read_32bit_c0_register($13, 0)
900#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
901
902#define read_c0_epc() __read_ulong_c0_register($14, 0)
903#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
904
905#define read_c0_prid() __read_32bit_c0_register($15, 0)
906
907#define read_c0_config() __read_32bit_c0_register($16, 0)
908#define read_c0_config1() __read_32bit_c0_register($16, 1)
909#define read_c0_config2() __read_32bit_c0_register($16, 2)
910#define read_c0_config3() __read_32bit_c0_register($16, 3)
911#define read_c0_config4() __read_32bit_c0_register($16, 4)
912#define read_c0_config5() __read_32bit_c0_register($16, 5)
913#define read_c0_config6() __read_32bit_c0_register($16, 6)
914#define read_c0_config7() __read_32bit_c0_register($16, 7)
915#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
916#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
917#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
918#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
919#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
920#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
921#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
922#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
923
924/*
925 * The WatchLo register. There may be up to 8 of them.
926 */
927#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
928#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
929#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
930#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
931#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
932#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
933#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
934#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
935#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
936#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
937#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
938#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
939#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
940#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
941#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
942#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
943
944/*
945 * The WatchHi register. There may be up to 8 of them.
946 */
947#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
948#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
949#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
950#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
951#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
952#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
953#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
954#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
955
956#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
957#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
958#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
959#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
960#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
961#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
962#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
963#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
964
965#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
966#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
967
968#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
969#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
970
971#define read_c0_framemask() __read_32bit_c0_register($21, 0)
972#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
973
974/* RM9000 PerfControl performance counter control register */
975#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
976#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
977
978#define read_c0_diag() __read_32bit_c0_register($22, 0)
979#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
980
981#define read_c0_diag1() __read_32bit_c0_register($22, 1)
982#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
983
984#define read_c0_diag2() __read_32bit_c0_register($22, 2)
985#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
986
987#define read_c0_diag3() __read_32bit_c0_register($22, 3)
988#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
989
990#define read_c0_diag4() __read_32bit_c0_register($22, 4)
991#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
992
993#define read_c0_diag5() __read_32bit_c0_register($22, 5)
994#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
995
996#define read_c0_debug() __read_32bit_c0_register($23, 0)
997#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
998
999#define read_c0_depc() __read_ulong_c0_register($24, 0)
1000#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1001
1002/*
1003 * MIPS32 / MIPS64 performance counters
1004 */
1005#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1006#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1007#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1008#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1009#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1010#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1011#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1012#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1013#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1014#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1015#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1016#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1017#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1018#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1019#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1020#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1021#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1022#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1023#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1024#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1025#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1026#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1027#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1028#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1029
1030/* RM9000 PerfCount performance counter register */
1031#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
1032#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1033
1034#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1035#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1036
1037#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1038#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1039
1040#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1041
1042#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1043#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1044
1045#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1046#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1047
1048#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1049#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1050
1051#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1052#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1053
1054#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1055#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1056
1057#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1058#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1059
1060#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1061#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1062
1063/* MIPSR2 */
1064#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1065#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1066
1067#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1068#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1069
1070#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1071#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1072
1073#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1074#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1075
1076#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1077#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1078
1079
1080/* Cavium OCTEON (cnMIPS) */
1081#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1082#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1083
1084#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1085#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1086
1087#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1088#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1089/*
1090 * The cacheerr registers are not standardized. On OCTEON, they are
1091 * 64 bits wide.
1092 */
1093#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1094#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1095
1096#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1097#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1098
1099/* BMIPS3300 */
1100#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1101#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1102
1103#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1104#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1105
1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108
1109/* BMIPS43xx */
1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112
1113#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1114#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1115
1116#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1117#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1118
1119#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1120#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1121
1122#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1123#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1124
1125/* BMIPS5000 */
1126#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1127#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1128
1129#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1130#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1131
1132#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1133#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1134
1135#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1136#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1137
1138#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1139#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1140
1141#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1142#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1143
1144/*
1145 * Macros to access the floating point coprocessor control registers
1146 */
1147#define read_32bit_cp1_register(source) \
1148({ int __res; \
1149 __asm__ __volatile__( \
1150 ".set\tpush\n\t" \
1151 ".set\treorder\n\t" \
1152 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1153 ".set\tmips1\n\t" \
1154 "cfc1\t%0,"STR(source)"\n\t" \
1155 ".set\tpop" \
1156 : "=r" (__res)); \
1157 __res;})
1158
1159#define rddsp(mask) \
1160({ \
1161 unsigned int __res; \
1162 \
1163 __asm__ __volatile__( \
1164 " .set push \n" \
1165 " .set noat \n" \
1166 " # rddsp $1, %x1 \n" \
1167 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1168 " move %0, $1 \n" \
1169 " .set pop \n" \
1170 : "=r" (__res) \
1171 : "i" (mask)); \
1172 __res; \
1173})
1174
1175#define wrdsp(val, mask) \
1176do { \
1177 __asm__ __volatile__( \
1178 " .set push \n" \
1179 " .set noat \n" \
1180 " move $1, %0 \n" \
1181 " # wrdsp $1, %x1 \n" \
1182 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1183 " .set pop \n" \
1184 : \
1185 : "r" (val), "i" (mask)); \
1186} while (0)
1187
1188#if 0 /* Need DSP ASE capable assembler ... */
1189#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1190#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1191#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1192#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1193
1194#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1195#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1196#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1197#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1198
1199#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1200#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1201#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1202#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1203
1204#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1205#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1206#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1207#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1208
1209#else
1210
1211#define mfhi0() \
1212({ \
1213 unsigned long __treg; \
1214 \
1215 __asm__ __volatile__( \
1216 " .set push \n" \
1217 " .set noat \n" \
1218 " # mfhi %0, $ac0 \n" \
1219 " .word 0x00000810 \n" \
1220 " move %0, $1 \n" \
1221 " .set pop \n" \
1222 : "=r" (__treg)); \
1223 __treg; \
1224})
1225
1226#define mfhi1() \
1227({ \
1228 unsigned long __treg; \
1229 \
1230 __asm__ __volatile__( \
1231 " .set push \n" \
1232 " .set noat \n" \
1233 " # mfhi %0, $ac1 \n" \
1234 " .word 0x00200810 \n" \
1235 " move %0, $1 \n" \
1236 " .set pop \n" \
1237 : "=r" (__treg)); \
1238 __treg; \
1239})
1240
1241#define mfhi2() \
1242({ \
1243 unsigned long __treg; \
1244 \
1245 __asm__ __volatile__( \
1246 " .set push \n" \
1247 " .set noat \n" \
1248 " # mfhi %0, $ac2 \n" \
1249 " .word 0x00400810 \n" \
1250 " move %0, $1 \n" \
1251 " .set pop \n" \
1252 : "=r" (__treg)); \
1253 __treg; \
1254})
1255
1256#define mfhi3() \
1257({ \
1258 unsigned long __treg; \
1259 \
1260 __asm__ __volatile__( \
1261 " .set push \n" \
1262 " .set noat \n" \
1263 " # mfhi %0, $ac3 \n" \
1264 " .word 0x00600810 \n" \
1265 " move %0, $1 \n" \
1266 " .set pop \n" \
1267 : "=r" (__treg)); \
1268 __treg; \
1269})
1270
1271#define mflo0() \
1272({ \
1273 unsigned long __treg; \
1274 \
1275 __asm__ __volatile__( \
1276 " .set push \n" \
1277 " .set noat \n" \
1278 " # mflo %0, $ac0 \n" \
1279 " .word 0x00000812 \n" \
1280 " move %0, $1 \n" \
1281 " .set pop \n" \
1282 : "=r" (__treg)); \
1283 __treg; \
1284})
1285
1286#define mflo1() \
1287({ \
1288 unsigned long __treg; \
1289 \
1290 __asm__ __volatile__( \
1291 " .set push \n" \
1292 " .set noat \n" \
1293 " # mflo %0, $ac1 \n" \
1294 " .word 0x00200812 \n" \
1295 " move %0, $1 \n" \
1296 " .set pop \n" \
1297 : "=r" (__treg)); \
1298 __treg; \
1299})
1300
1301#define mflo2() \
1302({ \
1303 unsigned long __treg; \
1304 \
1305 __asm__ __volatile__( \
1306 " .set push \n" \
1307 " .set noat \n" \
1308 " # mflo %0, $ac2 \n" \
1309 " .word 0x00400812 \n" \
1310 " move %0, $1 \n" \
1311 " .set pop \n" \
1312 : "=r" (__treg)); \
1313 __treg; \
1314})
1315
1316#define mflo3() \
1317({ \
1318 unsigned long __treg; \
1319 \
1320 __asm__ __volatile__( \
1321 " .set push \n" \
1322 " .set noat \n" \
1323 " # mflo %0, $ac3 \n" \
1324 " .word 0x00600812 \n" \
1325 " move %0, $1 \n" \
1326 " .set pop \n" \
1327 : "=r" (__treg)); \
1328 __treg; \
1329})
1330
1331#define mthi0(x) \
1332do { \
1333 __asm__ __volatile__( \
1334 " .set push \n" \
1335 " .set noat \n" \
1336 " move $1, %0 \n" \
1337 " # mthi $1, $ac0 \n" \
1338 " .word 0x00200011 \n" \
1339 " .set pop \n" \
1340 : \
1341 : "r" (x)); \
1342} while (0)
1343
1344#define mthi1(x) \
1345do { \
1346 __asm__ __volatile__( \
1347 " .set push \n" \
1348 " .set noat \n" \
1349 " move $1, %0 \n" \
1350 " # mthi $1, $ac1 \n" \
1351 " .word 0x00200811 \n" \
1352 " .set pop \n" \
1353 : \
1354 : "r" (x)); \
1355} while (0)
1356
1357#define mthi2(x) \
1358do { \
1359 __asm__ __volatile__( \
1360 " .set push \n" \
1361 " .set noat \n" \
1362 " move $1, %0 \n" \
1363 " # mthi $1, $ac2 \n" \
1364 " .word 0x00201011 \n" \
1365 " .set pop \n" \
1366 : \
1367 : "r" (x)); \
1368} while (0)
1369
1370#define mthi3(x) \
1371do { \
1372 __asm__ __volatile__( \
1373 " .set push \n" \
1374 " .set noat \n" \
1375 " move $1, %0 \n" \
1376 " # mthi $1, $ac3 \n" \
1377 " .word 0x00201811 \n" \
1378 " .set pop \n" \
1379 : \
1380 : "r" (x)); \
1381} while (0)
1382
1383#define mtlo0(x) \
1384do { \
1385 __asm__ __volatile__( \
1386 " .set push \n" \
1387 " .set noat \n" \
1388 " move $1, %0 \n" \
1389 " # mtlo $1, $ac0 \n" \
1390 " .word 0x00200013 \n" \
1391 " .set pop \n" \
1392 : \
1393 : "r" (x)); \
1394} while (0)
1395
1396#define mtlo1(x) \
1397do { \
1398 __asm__ __volatile__( \
1399 " .set push \n" \
1400 " .set noat \n" \
1401 " move $1, %0 \n" \
1402 " # mtlo $1, $ac1 \n" \
1403 " .word 0x00200813 \n" \
1404 " .set pop \n" \
1405 : \
1406 : "r" (x)); \
1407} while (0)
1408
1409#define mtlo2(x) \
1410do { \
1411 __asm__ __volatile__( \
1412 " .set push \n" \
1413 " .set noat \n" \
1414 " move $1, %0 \n" \
1415 " # mtlo $1, $ac2 \n" \
1416 " .word 0x00201013 \n" \
1417 " .set pop \n" \
1418 : \
1419 : "r" (x)); \
1420} while (0)
1421
1422#define mtlo3(x) \
1423do { \
1424 __asm__ __volatile__( \
1425 " .set push \n" \
1426 " .set noat \n" \
1427 " move $1, %0 \n" \
1428 " # mtlo $1, $ac3 \n" \
1429 " .word 0x00201813 \n" \
1430 " .set pop \n" \
1431 : \
1432 : "r" (x)); \
1433} while (0)
1434
1435#endif
1436
1437/*
1438 * TLB operations.
1439 *
1440 * It is responsibility of the caller to take care of any TLB hazards.
1441 */
1442static inline void tlb_probe(void)
1443{
1444 __asm__ __volatile__(
1445 ".set noreorder\n\t"
1446 "tlbp\n\t"
1447 ".set reorder");
1448}
1449
1450static inline void tlb_read(void)
1451{
1452#if MIPS34K_MISSED_ITLB_WAR
1453 int res = 0;
1454
1455 __asm__ __volatile__(
1456 " .set push \n"
1457 " .set noreorder \n"
1458 " .set noat \n"
1459 " .set mips32r2 \n"
1460 " .word 0x41610001 # dvpe $1 \n"
1461 " move %0, $1 \n"
1462 " ehb \n"
1463 " .set pop \n"
1464 : "=r" (res));
1465
1466 instruction_hazard();
1467#endif
1468
1469 __asm__ __volatile__(
1470 ".set noreorder\n\t"
1471 "tlbr\n\t"
1472 ".set reorder");
1473
1474#if MIPS34K_MISSED_ITLB_WAR
1475 if ((res & _ULCAST_(1)))
1476 __asm__ __volatile__(
1477 " .set push \n"
1478 " .set noreorder \n"
1479 " .set noat \n"
1480 " .set mips32r2 \n"
1481 " .word 0x41600021 # evpe \n"
1482 " ehb \n"
1483 " .set pop \n");
1484#endif
1485}
1486
1487static inline void tlb_write_indexed(void)
1488{
1489 __asm__ __volatile__(
1490 ".set noreorder\n\t"
1491 "tlbwi\n\t"
1492 ".set reorder");
1493}
1494
1495static inline void tlb_write_random(void)
1496{
1497 __asm__ __volatile__(
1498 ".set noreorder\n\t"
1499 "tlbwr\n\t"
1500 ".set reorder");
1501}
1502
1503/*
1504 * Manipulate bits in a c0 register.
1505 */
1506#ifndef CONFIG_MIPS_MT_SMTC
1507/*
1508 * SMTC Linux requires shutting-down microthread scheduling
1509 * during CP0 register read-modify-write sequences.
1510 */
1511#define __BUILD_SET_C0(name) \
1512static inline unsigned int \
1513set_c0_##name(unsigned int set) \
1514{ \
1515 unsigned int res, new; \
1516 \
1517 res = read_c0_##name(); \
1518 new = res | set; \
1519 write_c0_##name(new); \
1520 \
1521 return res; \
1522} \
1523 \
1524static inline unsigned int \
1525clear_c0_##name(unsigned int clear) \
1526{ \
1527 unsigned int res, new; \
1528 \
1529 res = read_c0_##name(); \
1530 new = res & ~clear; \
1531 write_c0_##name(new); \
1532 \
1533 return res; \
1534} \
1535 \
1536static inline unsigned int \
1537change_c0_##name(unsigned int change, unsigned int val) \
1538{ \
1539 unsigned int res, new; \
1540 \
1541 res = read_c0_##name(); \
1542 new = res & ~change; \
1543 new |= (val & change); \
1544 write_c0_##name(new); \
1545 \
1546 return res; \
1547}
1548
1549#else /* SMTC versions that manage MT scheduling */
1550
1551#include <linux/irqflags.h>
1552
1553/*
1554 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1555 * header file recursion.
1556 */
1557static inline unsigned int __dmt(void)
1558{
1559 int res;
1560
1561 __asm__ __volatile__(
1562 " .set push \n"
1563 " .set mips32r2 \n"
1564 " .set noat \n"
1565 " .word 0x41610BC1 # dmt $1 \n"
1566 " ehb \n"
1567 " move %0, $1 \n"
1568 " .set pop \n"
1569 : "=r" (res));
1570
1571 instruction_hazard();
1572
1573 return res;
1574}
1575
1576#define __VPECONTROL_TE_SHIFT 15
1577#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1578
1579#define __EMT_ENABLE __VPECONTROL_TE
1580
1581static inline void __emt(unsigned int previous)
1582{
1583 if ((previous & __EMT_ENABLE))
1584 __asm__ __volatile__(
1585 " .set mips32r2 \n"
1586 " .word 0x41600be1 # emt \n"
1587 " ehb \n"
1588 " .set mips0 \n");
1589}
1590
1591static inline void __ehb(void)
1592{
1593 __asm__ __volatile__(
1594 " .set mips32r2 \n"
1595 " ehb \n" " .set mips0 \n");
1596}
1597
1598/*
1599 * Note that local_irq_save/restore affect TC-specific IXMT state,
1600 * not Status.IE as in non-SMTC kernel.
1601 */
1602
1603#define __BUILD_SET_C0(name) \
1604static inline unsigned int \
1605set_c0_##name(unsigned int set) \
1606{ \
1607 unsigned int res; \
1608 unsigned int new; \
1609 unsigned int omt; \
1610 unsigned long flags; \
1611 \
1612 local_irq_save(flags); \
1613 omt = __dmt(); \
1614 res = read_c0_##name(); \
1615 new = res | set; \
1616 write_c0_##name(new); \
1617 __emt(omt); \
1618 local_irq_restore(flags); \
1619 \
1620 return res; \
1621} \
1622 \
1623static inline unsigned int \
1624clear_c0_##name(unsigned int clear) \
1625{ \
1626 unsigned int res; \
1627 unsigned int new; \
1628 unsigned int omt; \
1629 unsigned long flags; \
1630 \
1631 local_irq_save(flags); \
1632 omt = __dmt(); \
1633 res = read_c0_##name(); \
1634 new = res & ~clear; \
1635 write_c0_##name(new); \
1636 __emt(omt); \
1637 local_irq_restore(flags); \
1638 \
1639 return res; \
1640} \
1641 \
1642static inline unsigned int \
1643change_c0_##name(unsigned int change, unsigned int newbits) \
1644{ \
1645 unsigned int res; \
1646 unsigned int new; \
1647 unsigned int omt; \
1648 unsigned long flags; \
1649 \
1650 local_irq_save(flags); \
1651 \
1652 omt = __dmt(); \
1653 res = read_c0_##name(); \
1654 new = res & ~change; \
1655 new |= (newbits & change); \
1656 write_c0_##name(new); \
1657 __emt(omt); \
1658 local_irq_restore(flags); \
1659 \
1660 return res; \
1661}
1662#endif
1663
1664__BUILD_SET_C0(status)
1665__BUILD_SET_C0(cause)
1666__BUILD_SET_C0(config)
1667__BUILD_SET_C0(intcontrol)
1668__BUILD_SET_C0(intctl)
1669__BUILD_SET_C0(srsmap)
1670__BUILD_SET_C0(brcm_config_0)
1671__BUILD_SET_C0(brcm_bus_pll)
1672__BUILD_SET_C0(brcm_reset)
1673__BUILD_SET_C0(brcm_cmt_intr)
1674__BUILD_SET_C0(brcm_cmt_ctrl)
1675__BUILD_SET_C0(brcm_config)
1676__BUILD_SET_C0(brcm_mode)
1677
1678#endif /* !__ASSEMBLY__ */
1679
1680#endif /* _ASM_MIPSREGS_H */