Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2020 Christoph Hellwig.
4 *
5 * DMA operations that map physical memory directly without using an IOMMU.
6 */
7#include <linux/memblock.h> /* for max_pfn */
8#include <linux/export.h>
9#include <linux/mm.h>
10#include <linux/dma-map-ops.h>
11#include <linux/scatterlist.h>
12#include <linux/pfn.h>
13#include <linux/vmalloc.h>
14#include <linux/set_memory.h>
15#include <linux/slab.h>
16#include "direct.h"
17
18/*
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
20 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct to work properly.
22 */
23unsigned int zone_dma_bits __ro_after_init = 24;
24
25static inline dma_addr_t phys_to_dma_direct(struct device *dev,
26 phys_addr_t phys)
27{
28 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted(dev, phys);
30 return phys_to_dma(dev, phys);
31}
32
33static inline struct page *dma_direct_to_page(struct device *dev,
34 dma_addr_t dma_addr)
35{
36 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
37}
38
39u64 dma_direct_get_required_mask(struct device *dev)
40{
41 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, phys);
43
44 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
45}
46
47static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
48 u64 *phys_limit)
49{
50 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
51
52 /*
53 * Optimistically try the zone that the physical address mask falls
54 * into first. If that returns memory that isn't actually addressable
55 * we will fallback to the next lower zone and try again.
56 *
57 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
58 * zones.
59 */
60 *phys_limit = dma_to_phys(dev, dma_limit);
61 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
62 return GFP_DMA;
63 if (*phys_limit <= DMA_BIT_MASK(32))
64 return GFP_DMA32;
65 return 0;
66}
67
68static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
69{
70 dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
71
72 if (dma_addr == DMA_MAPPING_ERROR)
73 return false;
74 return dma_addr + size - 1 <=
75 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
76}
77
78static int dma_set_decrypted(struct device *dev, void *vaddr, size_t size)
79{
80 if (!force_dma_unencrypted(dev))
81 return 0;
82 return set_memory_decrypted((unsigned long)vaddr, PFN_UP(size));
83}
84
85static int dma_set_encrypted(struct device *dev, void *vaddr, size_t size)
86{
87 int ret;
88
89 if (!force_dma_unencrypted(dev))
90 return 0;
91 ret = set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
92 if (ret)
93 pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
94 return ret;
95}
96
97static void __dma_direct_free_pages(struct device *dev, struct page *page,
98 size_t size)
99{
100 if (swiotlb_free(dev, page, size))
101 return;
102 dma_free_contiguous(dev, page, size);
103}
104
105static struct page *dma_direct_alloc_swiotlb(struct device *dev, size_t size)
106{
107 struct page *page = swiotlb_alloc(dev, size);
108
109 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
110 swiotlb_free(dev, page, size);
111 return NULL;
112 }
113
114 return page;
115}
116
117static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
118 gfp_t gfp, bool allow_highmem)
119{
120 int node = dev_to_node(dev);
121 struct page *page = NULL;
122 u64 phys_limit;
123
124 WARN_ON_ONCE(!PAGE_ALIGNED(size));
125
126 if (is_swiotlb_for_alloc(dev))
127 return dma_direct_alloc_swiotlb(dev, size);
128
129 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
130 &phys_limit);
131 page = dma_alloc_contiguous(dev, size, gfp);
132 if (page) {
133 if (!dma_coherent_ok(dev, page_to_phys(page), size) ||
134 (!allow_highmem && PageHighMem(page))) {
135 dma_free_contiguous(dev, page, size);
136 page = NULL;
137 }
138 }
139again:
140 if (!page)
141 page = alloc_pages_node(node, gfp, get_order(size));
142 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
143 dma_free_contiguous(dev, page, size);
144 page = NULL;
145
146 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
147 phys_limit < DMA_BIT_MASK(64) &&
148 !(gfp & (GFP_DMA32 | GFP_DMA))) {
149 gfp |= GFP_DMA32;
150 goto again;
151 }
152
153 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
154 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
155 goto again;
156 }
157 }
158
159 return page;
160}
161
162/*
163 * Check if a potentially blocking operations needs to dip into the atomic
164 * pools for the given device/gfp.
165 */
166static bool dma_direct_use_pool(struct device *dev, gfp_t gfp)
167{
168 return !gfpflags_allow_blocking(gfp) && !is_swiotlb_for_alloc(dev);
169}
170
171static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
172 dma_addr_t *dma_handle, gfp_t gfp)
173{
174 struct page *page;
175 u64 phys_mask;
176 void *ret;
177
178 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)))
179 return NULL;
180
181 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
182 &phys_mask);
183 page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
184 if (!page)
185 return NULL;
186 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
187 return ret;
188}
189
190static void *dma_direct_alloc_no_mapping(struct device *dev, size_t size,
191 dma_addr_t *dma_handle, gfp_t gfp)
192{
193 struct page *page;
194
195 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
196 if (!page)
197 return NULL;
198
199 /* remove any dirty cache lines on the kernel alias */
200 if (!PageHighMem(page))
201 arch_dma_prep_coherent(page, size);
202
203 /* return the page pointer as the opaque cookie */
204 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
205 return page;
206}
207
208void *dma_direct_alloc(struct device *dev, size_t size,
209 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
210{
211 bool remap = false, set_uncached = false;
212 struct page *page;
213 void *ret;
214
215 size = PAGE_ALIGN(size);
216 if (attrs & DMA_ATTR_NO_WARN)
217 gfp |= __GFP_NOWARN;
218
219 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
220 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev))
221 return dma_direct_alloc_no_mapping(dev, size, dma_handle, gfp);
222
223 if (!dev_is_dma_coherent(dev)) {
224 /*
225 * Fallback to the arch handler if it exists. This should
226 * eventually go away.
227 */
228 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
229 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
230 !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
231 !is_swiotlb_for_alloc(dev))
232 return arch_dma_alloc(dev, size, dma_handle, gfp,
233 attrs);
234
235 /*
236 * If there is a global pool, always allocate from it for
237 * non-coherent devices.
238 */
239 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL))
240 return dma_alloc_from_global_coherent(dev, size,
241 dma_handle);
242
243 /*
244 * Otherwise remap if the architecture is asking for it. But
245 * given that remapping memory is a blocking operation we'll
246 * instead have to dip into the atomic pools.
247 */
248 remap = IS_ENABLED(CONFIG_DMA_DIRECT_REMAP);
249 if (remap) {
250 if (dma_direct_use_pool(dev, gfp))
251 return dma_direct_alloc_from_pool(dev, size,
252 dma_handle, gfp);
253 } else {
254 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED))
255 return NULL;
256 set_uncached = true;
257 }
258 }
259
260 /*
261 * Decrypting memory may block, so allocate the memory from the atomic
262 * pools if we can't block.
263 */
264 if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
265 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
266
267 /* we always manually zero the memory once we are done */
268 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
269 if (!page)
270 return NULL;
271
272 /*
273 * dma_alloc_contiguous can return highmem pages depending on a
274 * combination the cma= arguments and per-arch setup. These need to be
275 * remapped to return a kernel virtual address.
276 */
277 if (PageHighMem(page)) {
278 remap = true;
279 set_uncached = false;
280 }
281
282 if (remap) {
283 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
284
285 if (force_dma_unencrypted(dev))
286 prot = pgprot_decrypted(prot);
287
288 /* remove any dirty cache lines on the kernel alias */
289 arch_dma_prep_coherent(page, size);
290
291 /* create a coherent mapping */
292 ret = dma_common_contiguous_remap(page, size, prot,
293 __builtin_return_address(0));
294 if (!ret)
295 goto out_free_pages;
296 } else {
297 ret = page_address(page);
298 if (dma_set_decrypted(dev, ret, size))
299 goto out_free_pages;
300 }
301
302 memset(ret, 0, size);
303
304 if (set_uncached) {
305 arch_dma_prep_coherent(page, size);
306 ret = arch_dma_set_uncached(ret, size);
307 if (IS_ERR(ret))
308 goto out_encrypt_pages;
309 }
310
311 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
312 return ret;
313
314out_encrypt_pages:
315 if (dma_set_encrypted(dev, page_address(page), size))
316 return NULL;
317out_free_pages:
318 __dma_direct_free_pages(dev, page, size);
319 return NULL;
320}
321
322void dma_direct_free(struct device *dev, size_t size,
323 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
324{
325 unsigned int page_order = get_order(size);
326
327 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
328 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev)) {
329 /* cpu_addr is a struct page cookie, not a kernel address */
330 dma_free_contiguous(dev, cpu_addr, size);
331 return;
332 }
333
334 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
335 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
336 !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
337 !dev_is_dma_coherent(dev) &&
338 !is_swiotlb_for_alloc(dev)) {
339 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
340 return;
341 }
342
343 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
344 !dev_is_dma_coherent(dev)) {
345 if (!dma_release_from_global_coherent(page_order, cpu_addr))
346 WARN_ON_ONCE(1);
347 return;
348 }
349
350 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
351 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
352 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
353 return;
354
355 if (is_vmalloc_addr(cpu_addr)) {
356 vunmap(cpu_addr);
357 } else {
358 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
359 arch_dma_clear_uncached(cpu_addr, size);
360 if (dma_set_encrypted(dev, cpu_addr, size))
361 return;
362 }
363
364 __dma_direct_free_pages(dev, dma_direct_to_page(dev, dma_addr), size);
365}
366
367struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
368 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
369{
370 struct page *page;
371 void *ret;
372
373 if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
374 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
375
376 page = __dma_direct_alloc_pages(dev, size, gfp, false);
377 if (!page)
378 return NULL;
379
380 ret = page_address(page);
381 if (dma_set_decrypted(dev, ret, size))
382 goto out_free_pages;
383 memset(ret, 0, size);
384 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
385 return page;
386out_free_pages:
387 __dma_direct_free_pages(dev, page, size);
388 return NULL;
389}
390
391void dma_direct_free_pages(struct device *dev, size_t size,
392 struct page *page, dma_addr_t dma_addr,
393 enum dma_data_direction dir)
394{
395 void *vaddr = page_address(page);
396
397 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
398 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
399 dma_free_from_pool(dev, vaddr, size))
400 return;
401
402 if (dma_set_encrypted(dev, vaddr, size))
403 return;
404 __dma_direct_free_pages(dev, page, size);
405}
406
407#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
408 defined(CONFIG_SWIOTLB)
409void dma_direct_sync_sg_for_device(struct device *dev,
410 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
411{
412 struct scatterlist *sg;
413 int i;
414
415 for_each_sg(sgl, sg, nents, i) {
416 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
417
418 if (unlikely(is_swiotlb_buffer(dev, paddr)))
419 swiotlb_sync_single_for_device(dev, paddr, sg->length,
420 dir);
421
422 if (!dev_is_dma_coherent(dev))
423 arch_sync_dma_for_device(paddr, sg->length,
424 dir);
425 }
426}
427#endif
428
429#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
430 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
431 defined(CONFIG_SWIOTLB)
432void dma_direct_sync_sg_for_cpu(struct device *dev,
433 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
434{
435 struct scatterlist *sg;
436 int i;
437
438 for_each_sg(sgl, sg, nents, i) {
439 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
440
441 if (!dev_is_dma_coherent(dev))
442 arch_sync_dma_for_cpu(paddr, sg->length, dir);
443
444 if (unlikely(is_swiotlb_buffer(dev, paddr)))
445 swiotlb_sync_single_for_cpu(dev, paddr, sg->length,
446 dir);
447
448 if (dir == DMA_FROM_DEVICE)
449 arch_dma_mark_clean(paddr, sg->length);
450 }
451
452 if (!dev_is_dma_coherent(dev))
453 arch_sync_dma_for_cpu_all();
454}
455
456/*
457 * Unmaps segments, except for ones marked as pci_p2pdma which do not
458 * require any further action as they contain a bus address.
459 */
460void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
461 int nents, enum dma_data_direction dir, unsigned long attrs)
462{
463 struct scatterlist *sg;
464 int i;
465
466 for_each_sg(sgl, sg, nents, i) {
467 if (sg_is_dma_bus_address(sg))
468 sg_dma_unmark_bus_address(sg);
469 else
470 dma_direct_unmap_page(dev, sg->dma_address,
471 sg_dma_len(sg), dir, attrs);
472 }
473}
474#endif
475
476int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
477 enum dma_data_direction dir, unsigned long attrs)
478{
479 struct pci_p2pdma_map_state p2pdma_state = {};
480 enum pci_p2pdma_map_type map;
481 struct scatterlist *sg;
482 int i, ret;
483
484 for_each_sg(sgl, sg, nents, i) {
485 if (is_pci_p2pdma_page(sg_page(sg))) {
486 map = pci_p2pdma_map_segment(&p2pdma_state, dev, sg);
487 switch (map) {
488 case PCI_P2PDMA_MAP_BUS_ADDR:
489 continue;
490 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
491 /*
492 * Any P2P mapping that traverses the PCI
493 * host bridge must be mapped with CPU physical
494 * address and not PCI bus addresses. This is
495 * done with dma_direct_map_page() below.
496 */
497 break;
498 default:
499 ret = -EREMOTEIO;
500 goto out_unmap;
501 }
502 }
503
504 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
505 sg->offset, sg->length, dir, attrs);
506 if (sg->dma_address == DMA_MAPPING_ERROR) {
507 ret = -EIO;
508 goto out_unmap;
509 }
510 sg_dma_len(sg) = sg->length;
511 }
512
513 return nents;
514
515out_unmap:
516 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
517 return ret;
518}
519
520dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
521 size_t size, enum dma_data_direction dir, unsigned long attrs)
522{
523 dma_addr_t dma_addr = paddr;
524
525 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
526 dev_err_once(dev,
527 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
528 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
529 WARN_ON_ONCE(1);
530 return DMA_MAPPING_ERROR;
531 }
532
533 return dma_addr;
534}
535
536int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
537 void *cpu_addr, dma_addr_t dma_addr, size_t size,
538 unsigned long attrs)
539{
540 struct page *page = dma_direct_to_page(dev, dma_addr);
541 int ret;
542
543 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
544 if (!ret)
545 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
546 return ret;
547}
548
549bool dma_direct_can_mmap(struct device *dev)
550{
551 return dev_is_dma_coherent(dev) ||
552 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
553}
554
555int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
556 void *cpu_addr, dma_addr_t dma_addr, size_t size,
557 unsigned long attrs)
558{
559 unsigned long user_count = vma_pages(vma);
560 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
561 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
562 int ret = -ENXIO;
563
564 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
565 if (force_dma_unencrypted(dev))
566 vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
567
568 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
569 return ret;
570 if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
571 return ret;
572
573 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
574 return -ENXIO;
575 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
576 user_count << PAGE_SHIFT, vma->vm_page_prot);
577}
578
579int dma_direct_supported(struct device *dev, u64 mask)
580{
581 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
582
583 /*
584 * Because 32-bit DMA masks are so common we expect every architecture
585 * to be able to satisfy them - either by not supporting more physical
586 * memory, or by providing a ZONE_DMA32. If neither is the case, the
587 * architecture needs to use an IOMMU instead of the direct mapping.
588 */
589 if (mask >= DMA_BIT_MASK(32))
590 return 1;
591
592 /*
593 * This check needs to be against the actual bit mask value, so use
594 * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
595 * part of the check.
596 */
597 if (IS_ENABLED(CONFIG_ZONE_DMA))
598 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
599 return mask >= phys_to_dma_unencrypted(dev, min_mask);
600}
601
602size_t dma_direct_max_mapping_size(struct device *dev)
603{
604 /* If SWIOTLB is active, use its maximum mapping size */
605 if (is_swiotlb_active(dev) &&
606 (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev)))
607 return swiotlb_max_mapping_size(dev);
608 return SIZE_MAX;
609}
610
611bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
612{
613 return !dev_is_dma_coherent(dev) ||
614 is_swiotlb_buffer(dev, dma_to_phys(dev, dma_addr));
615}
616
617/**
618 * dma_direct_set_offset - Assign scalar offset for a single DMA range.
619 * @dev: device pointer; needed to "own" the alloced memory.
620 * @cpu_start: beginning of memory region covered by this offset.
621 * @dma_start: beginning of DMA/PCI region covered by this offset.
622 * @size: size of the region.
623 *
624 * This is for the simple case of a uniform offset which cannot
625 * be discovered by "dma-ranges".
626 *
627 * It returns -ENOMEM if out of memory, -EINVAL if a map
628 * already exists, 0 otherwise.
629 *
630 * Note: any call to this from a driver is a bug. The mapping needs
631 * to be described by the device tree or other firmware interfaces.
632 */
633int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
634 dma_addr_t dma_start, u64 size)
635{
636 struct bus_dma_region *map;
637 u64 offset = (u64)cpu_start - (u64)dma_start;
638
639 if (dev->dma_range_map) {
640 dev_err(dev, "attempt to add DMA range to existing map\n");
641 return -EINVAL;
642 }
643
644 if (!offset)
645 return 0;
646
647 map = kcalloc(2, sizeof(*map), GFP_KERNEL);
648 if (!map)
649 return -ENOMEM;
650 map[0].cpu_start = cpu_start;
651 map[0].dma_start = dma_start;
652 map[0].offset = offset;
653 map[0].size = size;
654 dev->dma_range_map = map;
655 return 0;
656}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Christoph Hellwig.
4 *
5 * DMA operations that map physical memory directly without using an IOMMU.
6 */
7#include <linux/memblock.h> /* for max_pfn */
8#include <linux/export.h>
9#include <linux/mm.h>
10#include <linux/dma-direct.h>
11#include <linux/scatterlist.h>
12#include <linux/dma-contiguous.h>
13#include <linux/dma-noncoherent.h>
14#include <linux/pfn.h>
15#include <linux/set_memory.h>
16#include <linux/swiotlb.h>
17
18/*
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
20 * some use it for entirely different regions:
21 */
22#ifndef ARCH_ZONE_DMA_BITS
23#define ARCH_ZONE_DMA_BITS 24
24#endif
25
26static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
27{
28 if (!dev->dma_mask) {
29 dev_err_once(dev, "DMA map on device without dma_mask\n");
30 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
31 dev_err_once(dev,
32 "overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
33 &dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
34 }
35 WARN_ON_ONCE(1);
36}
37
38static inline dma_addr_t phys_to_dma_direct(struct device *dev,
39 phys_addr_t phys)
40{
41 if (force_dma_unencrypted(dev))
42 return __phys_to_dma(dev, phys);
43 return phys_to_dma(dev, phys);
44}
45
46u64 dma_direct_get_required_mask(struct device *dev)
47{
48 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT);
49
50 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
51}
52
53static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
54 u64 *phys_mask)
55{
56 if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
57 dma_mask = dev->bus_dma_mask;
58
59 if (force_dma_unencrypted(dev))
60 *phys_mask = __dma_to_phys(dev, dma_mask);
61 else
62 *phys_mask = dma_to_phys(dev, dma_mask);
63
64 /*
65 * Optimistically try the zone that the physical address mask falls
66 * into first. If that returns memory that isn't actually addressable
67 * we will fallback to the next lower zone and try again.
68 *
69 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
70 * zones.
71 */
72 if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
73 return GFP_DMA;
74 if (*phys_mask <= DMA_BIT_MASK(32))
75 return GFP_DMA32;
76 return 0;
77}
78
79static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
80{
81 return phys_to_dma_direct(dev, phys) + size - 1 <=
82 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
83}
84
85struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
86 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
87{
88 size_t alloc_size = PAGE_ALIGN(size);
89 int node = dev_to_node(dev);
90 struct page *page = NULL;
91 u64 phys_mask;
92
93 if (attrs & DMA_ATTR_NO_WARN)
94 gfp |= __GFP_NOWARN;
95
96 /* we always manually zero the memory once we are done: */
97 gfp &= ~__GFP_ZERO;
98 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
99 &phys_mask);
100 page = dma_alloc_contiguous(dev, alloc_size, gfp);
101 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
102 dma_free_contiguous(dev, page, alloc_size);
103 page = NULL;
104 }
105again:
106 if (!page)
107 page = alloc_pages_node(node, gfp, get_order(alloc_size));
108 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
109 dma_free_contiguous(dev, page, size);
110 page = NULL;
111
112 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
113 phys_mask < DMA_BIT_MASK(64) &&
114 !(gfp & (GFP_DMA32 | GFP_DMA))) {
115 gfp |= GFP_DMA32;
116 goto again;
117 }
118
119 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
120 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
121 goto again;
122 }
123 }
124
125 return page;
126}
127
128void *dma_direct_alloc_pages(struct device *dev, size_t size,
129 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
130{
131 struct page *page;
132 void *ret;
133
134 page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
135 if (!page)
136 return NULL;
137
138 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
139 !force_dma_unencrypted(dev)) {
140 /* remove any dirty cache lines on the kernel alias */
141 if (!PageHighMem(page))
142 arch_dma_prep_coherent(page, size);
143 *dma_handle = phys_to_dma(dev, page_to_phys(page));
144 /* return the page pointer as the opaque cookie */
145 return page;
146 }
147
148 if (PageHighMem(page)) {
149 /*
150 * Depending on the cma= arguments and per-arch setup
151 * dma_alloc_contiguous could return highmem pages.
152 * Without remapping there is no way to return them here,
153 * so log an error and fail.
154 */
155 dev_info(dev, "Rejecting highmem page from CMA.\n");
156 __dma_direct_free_pages(dev, size, page);
157 return NULL;
158 }
159
160 ret = page_address(page);
161 if (force_dma_unencrypted(dev)) {
162 set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
163 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
164 } else {
165 *dma_handle = phys_to_dma(dev, page_to_phys(page));
166 }
167 memset(ret, 0, size);
168
169 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
170 dma_alloc_need_uncached(dev, attrs)) {
171 arch_dma_prep_coherent(page, size);
172 ret = uncached_kernel_address(ret);
173 }
174
175 return ret;
176}
177
178void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page)
179{
180 dma_free_contiguous(dev, page, size);
181}
182
183void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
184 dma_addr_t dma_addr, unsigned long attrs)
185{
186 unsigned int page_order = get_order(size);
187
188 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
189 !force_dma_unencrypted(dev)) {
190 /* cpu_addr is a struct page cookie, not a kernel address */
191 __dma_direct_free_pages(dev, size, cpu_addr);
192 return;
193 }
194
195 if (force_dma_unencrypted(dev))
196 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
197
198 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
199 dma_alloc_need_uncached(dev, attrs))
200 cpu_addr = cached_kernel_address(cpu_addr);
201 __dma_direct_free_pages(dev, size, virt_to_page(cpu_addr));
202}
203
204void *dma_direct_alloc(struct device *dev, size_t size,
205 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
206{
207 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
208 dma_alloc_need_uncached(dev, attrs))
209 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
210 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
211}
212
213void dma_direct_free(struct device *dev, size_t size,
214 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
215{
216 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
217 dma_alloc_need_uncached(dev, attrs))
218 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
219 else
220 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
221}
222
223#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
224 defined(CONFIG_SWIOTLB)
225void dma_direct_sync_single_for_device(struct device *dev,
226 dma_addr_t addr, size_t size, enum dma_data_direction dir)
227{
228 phys_addr_t paddr = dma_to_phys(dev, addr);
229
230 if (unlikely(is_swiotlb_buffer(paddr)))
231 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
232
233 if (!dev_is_dma_coherent(dev))
234 arch_sync_dma_for_device(dev, paddr, size, dir);
235}
236EXPORT_SYMBOL(dma_direct_sync_single_for_device);
237
238void dma_direct_sync_sg_for_device(struct device *dev,
239 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
240{
241 struct scatterlist *sg;
242 int i;
243
244 for_each_sg(sgl, sg, nents, i) {
245 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
246
247 if (unlikely(is_swiotlb_buffer(paddr)))
248 swiotlb_tbl_sync_single(dev, paddr, sg->length,
249 dir, SYNC_FOR_DEVICE);
250
251 if (!dev_is_dma_coherent(dev))
252 arch_sync_dma_for_device(dev, paddr, sg->length,
253 dir);
254 }
255}
256EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
257#endif
258
259#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
260 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
261 defined(CONFIG_SWIOTLB)
262void dma_direct_sync_single_for_cpu(struct device *dev,
263 dma_addr_t addr, size_t size, enum dma_data_direction dir)
264{
265 phys_addr_t paddr = dma_to_phys(dev, addr);
266
267 if (!dev_is_dma_coherent(dev)) {
268 arch_sync_dma_for_cpu(dev, paddr, size, dir);
269 arch_sync_dma_for_cpu_all(dev);
270 }
271
272 if (unlikely(is_swiotlb_buffer(paddr)))
273 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
274}
275EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
276
277void dma_direct_sync_sg_for_cpu(struct device *dev,
278 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
279{
280 struct scatterlist *sg;
281 int i;
282
283 for_each_sg(sgl, sg, nents, i) {
284 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
285
286 if (!dev_is_dma_coherent(dev))
287 arch_sync_dma_for_cpu(dev, paddr, sg->length, dir);
288
289 if (unlikely(is_swiotlb_buffer(paddr)))
290 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
291 SYNC_FOR_CPU);
292 }
293
294 if (!dev_is_dma_coherent(dev))
295 arch_sync_dma_for_cpu_all(dev);
296}
297EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
298
299void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
300 size_t size, enum dma_data_direction dir, unsigned long attrs)
301{
302 phys_addr_t phys = dma_to_phys(dev, addr);
303
304 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
305 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
306
307 if (unlikely(is_swiotlb_buffer(phys)))
308 swiotlb_tbl_unmap_single(dev, phys, size, size, dir, attrs);
309}
310EXPORT_SYMBOL(dma_direct_unmap_page);
311
312void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
313 int nents, enum dma_data_direction dir, unsigned long attrs)
314{
315 struct scatterlist *sg;
316 int i;
317
318 for_each_sg(sgl, sg, nents, i)
319 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
320 attrs);
321}
322EXPORT_SYMBOL(dma_direct_unmap_sg);
323#endif
324
325static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
326 size_t size)
327{
328 return swiotlb_force != SWIOTLB_FORCE &&
329 dma_capable(dev, dma_addr, size);
330}
331
332dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
333 unsigned long offset, size_t size, enum dma_data_direction dir,
334 unsigned long attrs)
335{
336 phys_addr_t phys = page_to_phys(page) + offset;
337 dma_addr_t dma_addr = phys_to_dma(dev, phys);
338
339 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) &&
340 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) {
341 report_addr(dev, dma_addr, size);
342 return DMA_MAPPING_ERROR;
343 }
344
345 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
346 arch_sync_dma_for_device(dev, phys, size, dir);
347 return dma_addr;
348}
349EXPORT_SYMBOL(dma_direct_map_page);
350
351int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
352 enum dma_data_direction dir, unsigned long attrs)
353{
354 int i;
355 struct scatterlist *sg;
356
357 for_each_sg(sgl, sg, nents, i) {
358 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
359 sg->offset, sg->length, dir, attrs);
360 if (sg->dma_address == DMA_MAPPING_ERROR)
361 goto out_unmap;
362 sg_dma_len(sg) = sg->length;
363 }
364
365 return nents;
366
367out_unmap:
368 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
369 return 0;
370}
371EXPORT_SYMBOL(dma_direct_map_sg);
372
373dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
374 size_t size, enum dma_data_direction dir, unsigned long attrs)
375{
376 dma_addr_t dma_addr = paddr;
377
378 if (unlikely(!dma_direct_possible(dev, dma_addr, size))) {
379 report_addr(dev, dma_addr, size);
380 return DMA_MAPPING_ERROR;
381 }
382
383 return dma_addr;
384}
385EXPORT_SYMBOL(dma_direct_map_resource);
386
387/*
388 * Because 32-bit DMA masks are so common we expect every architecture to be
389 * able to satisfy them - either by not supporting more physical memory, or by
390 * providing a ZONE_DMA32. If neither is the case, the architecture needs to
391 * use an IOMMU instead of the direct mapping.
392 */
393int dma_direct_supported(struct device *dev, u64 mask)
394{
395 u64 min_mask;
396
397 if (IS_ENABLED(CONFIG_ZONE_DMA))
398 min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
399 else
400 min_mask = DMA_BIT_MASK(32);
401
402 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
403
404 /*
405 * This check needs to be against the actual bit mask value, so
406 * use __phys_to_dma() here so that the SME encryption mask isn't
407 * part of the check.
408 */
409 return mask >= __phys_to_dma(dev, min_mask);
410}
411
412size_t dma_direct_max_mapping_size(struct device *dev)
413{
414 /* If SWIOTLB is active, use its maximum mapping size */
415 if (is_swiotlb_active() &&
416 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
417 return swiotlb_max_mapping_size(dev);
418 return SIZE_MAX;
419}