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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * au1550 psc spi controller driver
4 * may work also with au1200, au1210, au1250
5 * will not work on au1000, au1100 and au1500 (no full spi controller there)
6 *
7 * Copyright (c) 2006 ATRON electronic GmbH
8 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/resource.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/dma-mapping.h>
22#include <linux/completion.h>
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-au1x00/au1xxx_psc.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h>
26
27#include <asm/mach-au1x00/au1550_spi.h>
28
29static unsigned int usedma = 1;
30module_param(usedma, uint, 0644);
31
32/*
33#define AU1550_SPI_DEBUG_LOOPBACK
34*/
35
36
37#define AU1550_SPI_DBDMA_DESCRIPTORS 1
38#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
39
40struct au1550_spi {
41 struct spi_bitbang bitbang;
42
43 volatile psc_spi_t __iomem *regs;
44 int irq;
45
46 unsigned int len;
47 unsigned int tx_count;
48 unsigned int rx_count;
49 const u8 *tx;
50 u8 *rx;
51
52 void (*rx_word)(struct au1550_spi *hw);
53 void (*tx_word)(struct au1550_spi *hw);
54 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
55 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
56
57 struct completion master_done;
58
59 unsigned int usedma;
60 u32 dma_tx_id;
61 u32 dma_rx_id;
62 u32 dma_tx_ch;
63 u32 dma_rx_ch;
64
65 u8 *dma_rx_tmpbuf;
66 unsigned int dma_rx_tmpbuf_size;
67 u32 dma_rx_tmpbuf_addr;
68
69 struct spi_master *master;
70 struct device *dev;
71 struct au1550_spi_info *pdata;
72 struct resource *ioarea;
73};
74
75
76/* we use an 8-bit memory device for dma transfers to/from spi fifo */
77static dbdev_tab_t au1550_spi_mem_dbdev = {
78 .dev_id = DBDMA_MEM_CHAN,
79 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
80 .dev_tsize = 0,
81 .dev_devwidth = 8,
82 .dev_physaddr = 0x00000000,
83 .dev_intlevel = 0,
84 .dev_intpolarity = 0
85};
86
87static int ddma_memid; /* id to above mem dma device */
88
89static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
90
91
92/*
93 * compute BRG and DIV bits to setup spi clock based on main input clock rate
94 * that was specified in platform data structure
95 * according to au1550 datasheet:
96 * psc_tempclk = psc_mainclk / (2 << DIV)
97 * spiclk = psc_tempclk / (2 * (BRG + 1))
98 * BRG valid range is 4..63
99 * DIV valid range is 0..3
100 */
101static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
102{
103 u32 mainclk_hz = hw->pdata->mainclk_hz;
104 u32 div, brg;
105
106 for (div = 0; div < 4; div++) {
107 brg = mainclk_hz / speed_hz / (4 << div);
108 /* now we have BRG+1 in brg, so count with that */
109 if (brg < (4 + 1)) {
110 brg = (4 + 1); /* speed_hz too big */
111 break; /* set lowest brg (div is == 0) */
112 }
113 if (brg <= (63 + 1))
114 break; /* we have valid brg and div */
115 }
116 if (div == 4) {
117 div = 3; /* speed_hz too small */
118 brg = (63 + 1); /* set highest brg and div */
119 }
120 brg--;
121 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
122}
123
124static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
125{
126 hw->regs->psc_spimsk =
127 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
128 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
129 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
130 wmb(); /* drain writebuffer */
131
132 hw->regs->psc_spievent =
133 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
134 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
135 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
136 wmb(); /* drain writebuffer */
137}
138
139static void au1550_spi_reset_fifos(struct au1550_spi *hw)
140{
141 u32 pcr;
142
143 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
144 wmb(); /* drain writebuffer */
145 do {
146 pcr = hw->regs->psc_spipcr;
147 wmb(); /* drain writebuffer */
148 } while (pcr != 0);
149}
150
151/*
152 * dma transfers are used for the most common spi word size of 8-bits
153 * we cannot easily change already set up dma channels' width, so if we wanted
154 * dma support for more than 8-bit words (up to 24 bits), we would need to
155 * setup dma channels from scratch on each spi transfer, based on bits_per_word
156 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
157 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
158 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
159 */
160static void au1550_spi_chipsel(struct spi_device *spi, int value)
161{
162 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
163 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
164 u32 cfg, stat;
165
166 switch (value) {
167 case BITBANG_CS_INACTIVE:
168 if (hw->pdata->deactivate_cs)
169 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
170 cspol);
171 break;
172
173 case BITBANG_CS_ACTIVE:
174 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
175
176 cfg = hw->regs->psc_spicfg;
177 wmb(); /* drain writebuffer */
178 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
179 wmb(); /* drain writebuffer */
180
181 if (spi->mode & SPI_CPOL)
182 cfg |= PSC_SPICFG_BI;
183 else
184 cfg &= ~PSC_SPICFG_BI;
185 if (spi->mode & SPI_CPHA)
186 cfg &= ~PSC_SPICFG_CDE;
187 else
188 cfg |= PSC_SPICFG_CDE;
189
190 if (spi->mode & SPI_LSB_FIRST)
191 cfg |= PSC_SPICFG_MLF;
192 else
193 cfg &= ~PSC_SPICFG_MLF;
194
195 if (hw->usedma && spi->bits_per_word <= 8)
196 cfg &= ~PSC_SPICFG_DD_DISABLE;
197 else
198 cfg |= PSC_SPICFG_DD_DISABLE;
199 cfg = PSC_SPICFG_CLR_LEN(cfg);
200 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
201
202 cfg = PSC_SPICFG_CLR_BAUD(cfg);
203 cfg &= ~PSC_SPICFG_SET_DIV(3);
204 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
205
206 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
207 wmb(); /* drain writebuffer */
208 do {
209 stat = hw->regs->psc_spistat;
210 wmb(); /* drain writebuffer */
211 } while ((stat & PSC_SPISTAT_DR) == 0);
212
213 if (hw->pdata->activate_cs)
214 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
215 cspol);
216 break;
217 }
218}
219
220static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
221{
222 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
223 unsigned int bpw, hz;
224 u32 cfg, stat;
225
226 if (t) {
227 bpw = t->bits_per_word;
228 hz = t->speed_hz;
229 } else {
230 bpw = spi->bits_per_word;
231 hz = spi->max_speed_hz;
232 }
233
234 if (!hz)
235 return -EINVAL;
236
237 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
238
239 cfg = hw->regs->psc_spicfg;
240 wmb(); /* drain writebuffer */
241 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
242 wmb(); /* drain writebuffer */
243
244 if (hw->usedma && bpw <= 8)
245 cfg &= ~PSC_SPICFG_DD_DISABLE;
246 else
247 cfg |= PSC_SPICFG_DD_DISABLE;
248 cfg = PSC_SPICFG_CLR_LEN(cfg);
249 cfg |= PSC_SPICFG_SET_LEN(bpw);
250
251 cfg = PSC_SPICFG_CLR_BAUD(cfg);
252 cfg &= ~PSC_SPICFG_SET_DIV(3);
253 cfg |= au1550_spi_baudcfg(hw, hz);
254
255 hw->regs->psc_spicfg = cfg;
256 wmb(); /* drain writebuffer */
257
258 if (cfg & PSC_SPICFG_DE_ENABLE) {
259 do {
260 stat = hw->regs->psc_spistat;
261 wmb(); /* drain writebuffer */
262 } while ((stat & PSC_SPISTAT_DR) == 0);
263 }
264
265 au1550_spi_reset_fifos(hw);
266 au1550_spi_mask_ack_all(hw);
267 return 0;
268}
269
270/*
271 * for dma spi transfers, we have to setup rx channel, otherwise there is
272 * no reliable way how to recognize that spi transfer is done
273 * dma complete callbacks are called before real spi transfer is finished
274 * and if only tx dma channel is set up (and rx fifo overflow event masked)
275 * spi master done event irq is not generated unless rx fifo is empty (emptied)
276 * so we need rx tmp buffer to use for rx dma if user does not provide one
277 */
278static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
279{
280 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
281 if (!hw->dma_rx_tmpbuf)
282 return -ENOMEM;
283 hw->dma_rx_tmpbuf_size = size;
284 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
285 size, DMA_FROM_DEVICE);
286 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
287 kfree(hw->dma_rx_tmpbuf);
288 hw->dma_rx_tmpbuf = 0;
289 hw->dma_rx_tmpbuf_size = 0;
290 return -EFAULT;
291 }
292 return 0;
293}
294
295static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
296{
297 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
298 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
299 kfree(hw->dma_rx_tmpbuf);
300 hw->dma_rx_tmpbuf = 0;
301 hw->dma_rx_tmpbuf_size = 0;
302}
303
304static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
305{
306 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
307 dma_addr_t dma_tx_addr;
308 dma_addr_t dma_rx_addr;
309 u32 res;
310
311 hw->len = t->len;
312 hw->tx_count = 0;
313 hw->rx_count = 0;
314
315 hw->tx = t->tx_buf;
316 hw->rx = t->rx_buf;
317 dma_tx_addr = t->tx_dma;
318 dma_rx_addr = t->rx_dma;
319
320 /*
321 * check if buffers are already dma mapped, map them otherwise:
322 * - first map the TX buffer, so cache data gets written to memory
323 * - then map the RX buffer, so that cache entries (with
324 * soon-to-be-stale data) get removed
325 * use rx buffer in place of tx if tx buffer was not provided
326 * use temp rx buffer (preallocated or realloc to fit) for rx dma
327 */
328 if (t->tx_buf) {
329 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
330 dma_tx_addr = dma_map_single(hw->dev,
331 (void *)t->tx_buf,
332 t->len, DMA_TO_DEVICE);
333 if (dma_mapping_error(hw->dev, dma_tx_addr))
334 dev_err(hw->dev, "tx dma map error\n");
335 }
336 }
337
338 if (t->rx_buf) {
339 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
340 dma_rx_addr = dma_map_single(hw->dev,
341 (void *)t->rx_buf,
342 t->len, DMA_FROM_DEVICE);
343 if (dma_mapping_error(hw->dev, dma_rx_addr))
344 dev_err(hw->dev, "rx dma map error\n");
345 }
346 } else {
347 if (t->len > hw->dma_rx_tmpbuf_size) {
348 int ret;
349
350 au1550_spi_dma_rxtmp_free(hw);
351 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
352 AU1550_SPI_DMA_RXTMP_MINSIZE));
353 if (ret < 0)
354 return ret;
355 }
356 hw->rx = hw->dma_rx_tmpbuf;
357 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
358 dma_sync_single_for_device(hw->dev, dma_rx_addr,
359 t->len, DMA_FROM_DEVICE);
360 }
361
362 if (!t->tx_buf) {
363 dma_sync_single_for_device(hw->dev, dma_rx_addr,
364 t->len, DMA_BIDIRECTIONAL);
365 hw->tx = hw->rx;
366 }
367
368 /* put buffers on the ring */
369 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
370 t->len, DDMA_FLAGS_IE);
371 if (!res)
372 dev_err(hw->dev, "rx dma put dest error\n");
373
374 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
375 t->len, DDMA_FLAGS_IE);
376 if (!res)
377 dev_err(hw->dev, "tx dma put source error\n");
378
379 au1xxx_dbdma_start(hw->dma_rx_ch);
380 au1xxx_dbdma_start(hw->dma_tx_ch);
381
382 /* by default enable nearly all events interrupt */
383 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
384 wmb(); /* drain writebuffer */
385
386 /* start the transfer */
387 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
388 wmb(); /* drain writebuffer */
389
390 wait_for_completion(&hw->master_done);
391
392 au1xxx_dbdma_stop(hw->dma_tx_ch);
393 au1xxx_dbdma_stop(hw->dma_rx_ch);
394
395 if (!t->rx_buf) {
396 /* using the temporal preallocated and premapped buffer */
397 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
398 DMA_FROM_DEVICE);
399 }
400 /* unmap buffers if mapped above */
401 if (t->rx_buf && t->rx_dma == 0)
402 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
403 DMA_FROM_DEVICE);
404 if (t->tx_buf && t->tx_dma == 0)
405 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
406 DMA_TO_DEVICE);
407
408 return min(hw->rx_count, hw->tx_count);
409}
410
411static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
412{
413 u32 stat, evnt;
414
415 stat = hw->regs->psc_spistat;
416 evnt = hw->regs->psc_spievent;
417 wmb(); /* drain writebuffer */
418 if ((stat & PSC_SPISTAT_DI) == 0) {
419 dev_err(hw->dev, "Unexpected IRQ!\n");
420 return IRQ_NONE;
421 }
422
423 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
424 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
425 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
426 != 0) {
427 /*
428 * due to an spi error we consider transfer as done,
429 * so mask all events until before next transfer start
430 * and stop the possibly running dma immediately
431 */
432 au1550_spi_mask_ack_all(hw);
433 au1xxx_dbdma_stop(hw->dma_rx_ch);
434 au1xxx_dbdma_stop(hw->dma_tx_ch);
435
436 /* get number of transferred bytes */
437 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
438 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
439
440 au1xxx_dbdma_reset(hw->dma_rx_ch);
441 au1xxx_dbdma_reset(hw->dma_tx_ch);
442 au1550_spi_reset_fifos(hw);
443
444 if (evnt == PSC_SPIEVNT_RO)
445 dev_err(hw->dev,
446 "dma transfer: receive FIFO overflow!\n");
447 else
448 dev_err(hw->dev,
449 "dma transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
450 evnt, stat);
451
452 complete(&hw->master_done);
453 return IRQ_HANDLED;
454 }
455
456 if ((evnt & PSC_SPIEVNT_MD) != 0) {
457 /* transfer completed successfully */
458 au1550_spi_mask_ack_all(hw);
459 hw->rx_count = hw->len;
460 hw->tx_count = hw->len;
461 complete(&hw->master_done);
462 }
463 return IRQ_HANDLED;
464}
465
466
467/* routines to handle different word sizes in pio mode */
468#define AU1550_SPI_RX_WORD(size, mask) \
469static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
470{ \
471 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
472 wmb(); /* drain writebuffer */ \
473 if (hw->rx) { \
474 *(u##size *)hw->rx = (u##size)fifoword; \
475 hw->rx += (size) / 8; \
476 } \
477 hw->rx_count += (size) / 8; \
478}
479
480#define AU1550_SPI_TX_WORD(size, mask) \
481static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
482{ \
483 u32 fifoword = 0; \
484 if (hw->tx) { \
485 fifoword = *(u##size *)hw->tx & (u32)(mask); \
486 hw->tx += (size) / 8; \
487 } \
488 hw->tx_count += (size) / 8; \
489 if (hw->tx_count >= hw->len) \
490 fifoword |= PSC_SPITXRX_LC; \
491 hw->regs->psc_spitxrx = fifoword; \
492 wmb(); /* drain writebuffer */ \
493}
494
495AU1550_SPI_RX_WORD(8, 0xff)
496AU1550_SPI_RX_WORD(16, 0xffff)
497AU1550_SPI_RX_WORD(32, 0xffffff)
498AU1550_SPI_TX_WORD(8, 0xff)
499AU1550_SPI_TX_WORD(16, 0xffff)
500AU1550_SPI_TX_WORD(32, 0xffffff)
501
502static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
503{
504 u32 stat, mask;
505 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
506
507 hw->tx = t->tx_buf;
508 hw->rx = t->rx_buf;
509 hw->len = t->len;
510 hw->tx_count = 0;
511 hw->rx_count = 0;
512
513 /* by default enable nearly all events after filling tx fifo */
514 mask = PSC_SPIMSK_SD;
515
516 /* fill the transmit FIFO */
517 while (hw->tx_count < hw->len) {
518
519 hw->tx_word(hw);
520
521 if (hw->tx_count >= hw->len) {
522 /* mask tx fifo request interrupt as we are done */
523 mask |= PSC_SPIMSK_TR;
524 }
525
526 stat = hw->regs->psc_spistat;
527 wmb(); /* drain writebuffer */
528 if (stat & PSC_SPISTAT_TF)
529 break;
530 }
531
532 /* enable event interrupts */
533 hw->regs->psc_spimsk = mask;
534 wmb(); /* drain writebuffer */
535
536 /* start the transfer */
537 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
538 wmb(); /* drain writebuffer */
539
540 wait_for_completion(&hw->master_done);
541
542 return min(hw->rx_count, hw->tx_count);
543}
544
545static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
546{
547 int busy;
548 u32 stat, evnt;
549
550 stat = hw->regs->psc_spistat;
551 evnt = hw->regs->psc_spievent;
552 wmb(); /* drain writebuffer */
553 if ((stat & PSC_SPISTAT_DI) == 0) {
554 dev_err(hw->dev, "Unexpected IRQ!\n");
555 return IRQ_NONE;
556 }
557
558 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
559 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
560 | PSC_SPIEVNT_SD))
561 != 0) {
562 /*
563 * due to an error we consider transfer as done,
564 * so mask all events until before next transfer start
565 */
566 au1550_spi_mask_ack_all(hw);
567 au1550_spi_reset_fifos(hw);
568 dev_err(hw->dev,
569 "pio transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
570 evnt, stat);
571 complete(&hw->master_done);
572 return IRQ_HANDLED;
573 }
574
575 /*
576 * while there is something to read from rx fifo
577 * or there is a space to write to tx fifo:
578 */
579 do {
580 busy = 0;
581 stat = hw->regs->psc_spistat;
582 wmb(); /* drain writebuffer */
583
584 /*
585 * Take care to not let the Rx FIFO overflow.
586 *
587 * We only write a byte if we have read one at least. Initially,
588 * the write fifo is full, so we should read from the read fifo
589 * first.
590 * In case we miss a word from the read fifo, we should get a
591 * RO event and should back out.
592 */
593 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
594 hw->rx_word(hw);
595 busy = 1;
596
597 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
598 hw->tx_word(hw);
599 }
600 } while (busy);
601
602 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
603 wmb(); /* drain writebuffer */
604
605 /*
606 * Restart the SPI transmission in case of a transmit underflow.
607 * This seems to work despite the notes in the Au1550 data book
608 * of Figure 8-4 with flowchart for SPI master operation:
609 *
610 * """Note 1: An XFR Error Interrupt occurs, unless masked,
611 * for any of the following events: Tx FIFO Underflow,
612 * Rx FIFO Overflow, or Multiple-master Error
613 * Note 2: In case of a Tx Underflow Error, all zeroes are
614 * transmitted."""
615 *
616 * By simply restarting the spi transfer on Tx Underflow Error,
617 * we assume that spi transfer was paused instead of zeroes
618 * transmittion mentioned in the Note 2 of Au1550 data book.
619 */
620 if (evnt & PSC_SPIEVNT_TU) {
621 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
622 wmb(); /* drain writebuffer */
623 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
624 wmb(); /* drain writebuffer */
625 }
626
627 if (hw->rx_count >= hw->len) {
628 /* transfer completed successfully */
629 au1550_spi_mask_ack_all(hw);
630 complete(&hw->master_done);
631 }
632 return IRQ_HANDLED;
633}
634
635static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
636{
637 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
638
639 return hw->txrx_bufs(spi, t);
640}
641
642static irqreturn_t au1550_spi_irq(int irq, void *dev)
643{
644 struct au1550_spi *hw = dev;
645
646 return hw->irq_callback(hw);
647}
648
649static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
650{
651 if (bpw <= 8) {
652 if (hw->usedma) {
653 hw->txrx_bufs = &au1550_spi_dma_txrxb;
654 hw->irq_callback = &au1550_spi_dma_irq_callback;
655 } else {
656 hw->rx_word = &au1550_spi_rx_word_8;
657 hw->tx_word = &au1550_spi_tx_word_8;
658 hw->txrx_bufs = &au1550_spi_pio_txrxb;
659 hw->irq_callback = &au1550_spi_pio_irq_callback;
660 }
661 } else if (bpw <= 16) {
662 hw->rx_word = &au1550_spi_rx_word_16;
663 hw->tx_word = &au1550_spi_tx_word_16;
664 hw->txrx_bufs = &au1550_spi_pio_txrxb;
665 hw->irq_callback = &au1550_spi_pio_irq_callback;
666 } else {
667 hw->rx_word = &au1550_spi_rx_word_32;
668 hw->tx_word = &au1550_spi_tx_word_32;
669 hw->txrx_bufs = &au1550_spi_pio_txrxb;
670 hw->irq_callback = &au1550_spi_pio_irq_callback;
671 }
672}
673
674static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
675{
676 u32 stat, cfg;
677
678 /* set up the PSC for SPI mode */
679 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
680 wmb(); /* drain writebuffer */
681 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
682 wmb(); /* drain writebuffer */
683
684 hw->regs->psc_spicfg = 0;
685 wmb(); /* drain writebuffer */
686
687 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
688 wmb(); /* drain writebuffer */
689
690 do {
691 stat = hw->regs->psc_spistat;
692 wmb(); /* drain writebuffer */
693 } while ((stat & PSC_SPISTAT_SR) == 0);
694
695
696 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
697 cfg |= PSC_SPICFG_SET_LEN(8);
698 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
699 /* use minimal allowed brg and div values as initial setting: */
700 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
701
702#ifdef AU1550_SPI_DEBUG_LOOPBACK
703 cfg |= PSC_SPICFG_LB;
704#endif
705
706 hw->regs->psc_spicfg = cfg;
707 wmb(); /* drain writebuffer */
708
709 au1550_spi_mask_ack_all(hw);
710
711 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
712 wmb(); /* drain writebuffer */
713
714 do {
715 stat = hw->regs->psc_spistat;
716 wmb(); /* drain writebuffer */
717 } while ((stat & PSC_SPISTAT_DR) == 0);
718
719 au1550_spi_reset_fifos(hw);
720}
721
722
723static int au1550_spi_probe(struct platform_device *pdev)
724{
725 struct au1550_spi *hw;
726 struct spi_master *master;
727 struct resource *r;
728 int err = 0;
729
730 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
731 if (master == NULL) {
732 dev_err(&pdev->dev, "No memory for spi_master\n");
733 err = -ENOMEM;
734 goto err_nomem;
735 }
736
737 /* the spi->mode bits understood by this driver: */
738 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
739 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
740
741 hw = spi_master_get_devdata(master);
742
743 hw->master = master;
744 hw->pdata = dev_get_platdata(&pdev->dev);
745 hw->dev = &pdev->dev;
746
747 if (hw->pdata == NULL) {
748 dev_err(&pdev->dev, "No platform data supplied\n");
749 err = -ENOENT;
750 goto err_no_pdata;
751 }
752
753 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
754 if (!r) {
755 dev_err(&pdev->dev, "no IRQ\n");
756 err = -ENODEV;
757 goto err_no_iores;
758 }
759 hw->irq = r->start;
760
761 hw->usedma = 0;
762 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
763 if (r) {
764 hw->dma_tx_id = r->start;
765 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
766 if (r) {
767 hw->dma_rx_id = r->start;
768 if (usedma && ddma_memid) {
769 if (pdev->dev.dma_mask == NULL)
770 dev_warn(&pdev->dev, "no dma mask\n");
771 else
772 hw->usedma = 1;
773 }
774 }
775 }
776
777 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778 if (!r) {
779 dev_err(&pdev->dev, "no mmio resource\n");
780 err = -ENODEV;
781 goto err_no_iores;
782 }
783
784 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
785 pdev->name);
786 if (!hw->ioarea) {
787 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
788 err = -ENXIO;
789 goto err_no_iores;
790 }
791
792 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
793 if (!hw->regs) {
794 dev_err(&pdev->dev, "cannot ioremap\n");
795 err = -ENXIO;
796 goto err_ioremap;
797 }
798
799 platform_set_drvdata(pdev, hw);
800
801 init_completion(&hw->master_done);
802
803 hw->bitbang.master = hw->master;
804 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
805 hw->bitbang.chipselect = au1550_spi_chipsel;
806 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
807
808 if (hw->usedma) {
809 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
810 hw->dma_tx_id, NULL, (void *)hw);
811 if (hw->dma_tx_ch == 0) {
812 dev_err(&pdev->dev,
813 "Cannot allocate tx dma channel\n");
814 err = -ENXIO;
815 goto err_no_txdma;
816 }
817 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
818 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
819 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
820 dev_err(&pdev->dev,
821 "Cannot allocate tx dma descriptors\n");
822 err = -ENXIO;
823 goto err_no_txdma_descr;
824 }
825
826
827 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
828 ddma_memid, NULL, (void *)hw);
829 if (hw->dma_rx_ch == 0) {
830 dev_err(&pdev->dev,
831 "Cannot allocate rx dma channel\n");
832 err = -ENXIO;
833 goto err_no_rxdma;
834 }
835 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
836 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
837 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
838 dev_err(&pdev->dev,
839 "Cannot allocate rx dma descriptors\n");
840 err = -ENXIO;
841 goto err_no_rxdma_descr;
842 }
843
844 err = au1550_spi_dma_rxtmp_alloc(hw,
845 AU1550_SPI_DMA_RXTMP_MINSIZE);
846 if (err < 0) {
847 dev_err(&pdev->dev,
848 "Cannot allocate initial rx dma tmp buffer\n");
849 goto err_dma_rxtmp_alloc;
850 }
851 }
852
853 au1550_spi_bits_handlers_set(hw, 8);
854
855 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
856 if (err) {
857 dev_err(&pdev->dev, "Cannot claim IRQ\n");
858 goto err_no_irq;
859 }
860
861 master->bus_num = pdev->id;
862 master->num_chipselect = hw->pdata->num_chipselect;
863
864 /*
865 * precompute valid range for spi freq - from au1550 datasheet:
866 * psc_tempclk = psc_mainclk / (2 << DIV)
867 * spiclk = psc_tempclk / (2 * (BRG + 1))
868 * BRG valid range is 4..63
869 * DIV valid range is 0..3
870 * round the min and max frequencies to values that would still
871 * produce valid brg and div
872 */
873 {
874 int min_div = (2 << 0) * (2 * (4 + 1));
875 int max_div = (2 << 3) * (2 * (63 + 1));
876
877 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
878 master->min_speed_hz =
879 hw->pdata->mainclk_hz / (max_div + 1) + 1;
880 }
881
882 au1550_spi_setup_psc_as_spi(hw);
883
884 err = spi_bitbang_start(&hw->bitbang);
885 if (err) {
886 dev_err(&pdev->dev, "Failed to register SPI master\n");
887 goto err_register;
888 }
889
890 dev_info(&pdev->dev,
891 "spi master registered: bus_num=%d num_chipselect=%d\n",
892 master->bus_num, master->num_chipselect);
893
894 return 0;
895
896err_register:
897 free_irq(hw->irq, hw);
898
899err_no_irq:
900 au1550_spi_dma_rxtmp_free(hw);
901
902err_dma_rxtmp_alloc:
903err_no_rxdma_descr:
904 if (hw->usedma)
905 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
906
907err_no_rxdma:
908err_no_txdma_descr:
909 if (hw->usedma)
910 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
911
912err_no_txdma:
913 iounmap((void __iomem *)hw->regs);
914
915err_ioremap:
916 release_mem_region(r->start, sizeof(psc_spi_t));
917
918err_no_iores:
919err_no_pdata:
920 spi_master_put(hw->master);
921
922err_nomem:
923 return err;
924}
925
926static int au1550_spi_remove(struct platform_device *pdev)
927{
928 struct au1550_spi *hw = platform_get_drvdata(pdev);
929
930 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
931 hw->master->bus_num);
932
933 spi_bitbang_stop(&hw->bitbang);
934 free_irq(hw->irq, hw);
935 iounmap((void __iomem *)hw->regs);
936 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
937
938 if (hw->usedma) {
939 au1550_spi_dma_rxtmp_free(hw);
940 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
941 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
942 }
943
944 spi_master_put(hw->master);
945 return 0;
946}
947
948/* work with hotplug and coldplug */
949MODULE_ALIAS("platform:au1550-spi");
950
951static struct platform_driver au1550_spi_drv = {
952 .probe = au1550_spi_probe,
953 .remove = au1550_spi_remove,
954 .driver = {
955 .name = "au1550-spi",
956 },
957};
958
959static int __init au1550_spi_init(void)
960{
961 /*
962 * create memory device with 8 bits dev_devwidth
963 * needed for proper byte ordering to spi fifo
964 */
965 switch (alchemy_get_cputype()) {
966 case ALCHEMY_CPU_AU1550:
967 case ALCHEMY_CPU_AU1200:
968 case ALCHEMY_CPU_AU1300:
969 break;
970 default:
971 return -ENODEV;
972 }
973
974 if (usedma) {
975 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
976 if (!ddma_memid)
977 printk(KERN_ERR "au1550-spi: cannot add memory dbdma device\n");
978 }
979 return platform_driver_register(&au1550_spi_drv);
980}
981module_init(au1550_spi_init);
982
983static void __exit au1550_spi_exit(void)
984{
985 if (usedma && ddma_memid)
986 au1xxx_ddma_del_device(ddma_memid);
987 platform_driver_unregister(&au1550_spi_drv);
988}
989module_exit(au1550_spi_exit);
990
991MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
992MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
993MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * au1550 psc spi controller driver
4 * may work also with au1200, au1210, au1250
5 * will not work on au1000, au1100 and au1500 (no full spi controller there)
6 *
7 * Copyright (c) 2006 ATRON electronic GmbH
8 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/resource.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/dma-mapping.h>
22#include <linux/completion.h>
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-au1x00/au1xxx_psc.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h>
26
27#include <asm/mach-au1x00/au1550_spi.h>
28
29static unsigned usedma = 1;
30module_param(usedma, uint, 0644);
31
32/*
33#define AU1550_SPI_DEBUG_LOOPBACK
34*/
35
36
37#define AU1550_SPI_DBDMA_DESCRIPTORS 1
38#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
39
40struct au1550_spi {
41 struct spi_bitbang bitbang;
42
43 volatile psc_spi_t __iomem *regs;
44 int irq;
45
46 unsigned len;
47 unsigned tx_count;
48 unsigned rx_count;
49 const u8 *tx;
50 u8 *rx;
51
52 void (*rx_word)(struct au1550_spi *hw);
53 void (*tx_word)(struct au1550_spi *hw);
54 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
55 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
56
57 struct completion master_done;
58
59 unsigned usedma;
60 u32 dma_tx_id;
61 u32 dma_rx_id;
62 u32 dma_tx_ch;
63 u32 dma_rx_ch;
64
65 u8 *dma_rx_tmpbuf;
66 unsigned dma_rx_tmpbuf_size;
67 u32 dma_rx_tmpbuf_addr;
68
69 struct spi_master *master;
70 struct device *dev;
71 struct au1550_spi_info *pdata;
72 struct resource *ioarea;
73};
74
75
76/* we use an 8-bit memory device for dma transfers to/from spi fifo */
77static dbdev_tab_t au1550_spi_mem_dbdev =
78{
79 .dev_id = DBDMA_MEM_CHAN,
80 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
81 .dev_tsize = 0,
82 .dev_devwidth = 8,
83 .dev_physaddr = 0x00000000,
84 .dev_intlevel = 0,
85 .dev_intpolarity = 0
86};
87
88static int ddma_memid; /* id to above mem dma device */
89
90static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
91
92
93/*
94 * compute BRG and DIV bits to setup spi clock based on main input clock rate
95 * that was specified in platform data structure
96 * according to au1550 datasheet:
97 * psc_tempclk = psc_mainclk / (2 << DIV)
98 * spiclk = psc_tempclk / (2 * (BRG + 1))
99 * BRG valid range is 4..63
100 * DIV valid range is 0..3
101 */
102static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
103{
104 u32 mainclk_hz = hw->pdata->mainclk_hz;
105 u32 div, brg;
106
107 for (div = 0; div < 4; div++) {
108 brg = mainclk_hz / speed_hz / (4 << div);
109 /* now we have BRG+1 in brg, so count with that */
110 if (brg < (4 + 1)) {
111 brg = (4 + 1); /* speed_hz too big */
112 break; /* set lowest brg (div is == 0) */
113 }
114 if (brg <= (63 + 1))
115 break; /* we have valid brg and div */
116 }
117 if (div == 4) {
118 div = 3; /* speed_hz too small */
119 brg = (63 + 1); /* set highest brg and div */
120 }
121 brg--;
122 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
123}
124
125static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
126{
127 hw->regs->psc_spimsk =
128 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
129 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
130 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
131 wmb(); /* drain writebuffer */
132
133 hw->regs->psc_spievent =
134 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
135 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
136 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
137 wmb(); /* drain writebuffer */
138}
139
140static void au1550_spi_reset_fifos(struct au1550_spi *hw)
141{
142 u32 pcr;
143
144 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
145 wmb(); /* drain writebuffer */
146 do {
147 pcr = hw->regs->psc_spipcr;
148 wmb(); /* drain writebuffer */
149 } while (pcr != 0);
150}
151
152/*
153 * dma transfers are used for the most common spi word size of 8-bits
154 * we cannot easily change already set up dma channels' width, so if we wanted
155 * dma support for more than 8-bit words (up to 24 bits), we would need to
156 * setup dma channels from scratch on each spi transfer, based on bits_per_word
157 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
158 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
159 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
160 */
161static void au1550_spi_chipsel(struct spi_device *spi, int value)
162{
163 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
164 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
165 u32 cfg, stat;
166
167 switch (value) {
168 case BITBANG_CS_INACTIVE:
169 if (hw->pdata->deactivate_cs)
170 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
171 cspol);
172 break;
173
174 case BITBANG_CS_ACTIVE:
175 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
176
177 cfg = hw->regs->psc_spicfg;
178 wmb(); /* drain writebuffer */
179 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
180 wmb(); /* drain writebuffer */
181
182 if (spi->mode & SPI_CPOL)
183 cfg |= PSC_SPICFG_BI;
184 else
185 cfg &= ~PSC_SPICFG_BI;
186 if (spi->mode & SPI_CPHA)
187 cfg &= ~PSC_SPICFG_CDE;
188 else
189 cfg |= PSC_SPICFG_CDE;
190
191 if (spi->mode & SPI_LSB_FIRST)
192 cfg |= PSC_SPICFG_MLF;
193 else
194 cfg &= ~PSC_SPICFG_MLF;
195
196 if (hw->usedma && spi->bits_per_word <= 8)
197 cfg &= ~PSC_SPICFG_DD_DISABLE;
198 else
199 cfg |= PSC_SPICFG_DD_DISABLE;
200 cfg = PSC_SPICFG_CLR_LEN(cfg);
201 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
202
203 cfg = PSC_SPICFG_CLR_BAUD(cfg);
204 cfg &= ~PSC_SPICFG_SET_DIV(3);
205 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
206
207 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
208 wmb(); /* drain writebuffer */
209 do {
210 stat = hw->regs->psc_spistat;
211 wmb(); /* drain writebuffer */
212 } while ((stat & PSC_SPISTAT_DR) == 0);
213
214 if (hw->pdata->activate_cs)
215 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
216 cspol);
217 break;
218 }
219}
220
221static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
222{
223 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
224 unsigned bpw, hz;
225 u32 cfg, stat;
226
227 if (t) {
228 bpw = t->bits_per_word;
229 hz = t->speed_hz;
230 } else {
231 bpw = spi->bits_per_word;
232 hz = spi->max_speed_hz;
233 }
234
235 if (!hz)
236 return -EINVAL;
237
238 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
239
240 cfg = hw->regs->psc_spicfg;
241 wmb(); /* drain writebuffer */
242 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
243 wmb(); /* drain writebuffer */
244
245 if (hw->usedma && bpw <= 8)
246 cfg &= ~PSC_SPICFG_DD_DISABLE;
247 else
248 cfg |= PSC_SPICFG_DD_DISABLE;
249 cfg = PSC_SPICFG_CLR_LEN(cfg);
250 cfg |= PSC_SPICFG_SET_LEN(bpw);
251
252 cfg = PSC_SPICFG_CLR_BAUD(cfg);
253 cfg &= ~PSC_SPICFG_SET_DIV(3);
254 cfg |= au1550_spi_baudcfg(hw, hz);
255
256 hw->regs->psc_spicfg = cfg;
257 wmb(); /* drain writebuffer */
258
259 if (cfg & PSC_SPICFG_DE_ENABLE) {
260 do {
261 stat = hw->regs->psc_spistat;
262 wmb(); /* drain writebuffer */
263 } while ((stat & PSC_SPISTAT_DR) == 0);
264 }
265
266 au1550_spi_reset_fifos(hw);
267 au1550_spi_mask_ack_all(hw);
268 return 0;
269}
270
271/*
272 * for dma spi transfers, we have to setup rx channel, otherwise there is
273 * no reliable way how to recognize that spi transfer is done
274 * dma complete callbacks are called before real spi transfer is finished
275 * and if only tx dma channel is set up (and rx fifo overflow event masked)
276 * spi master done event irq is not generated unless rx fifo is empty (emptied)
277 * so we need rx tmp buffer to use for rx dma if user does not provide one
278 */
279static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
280{
281 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
282 if (!hw->dma_rx_tmpbuf)
283 return -ENOMEM;
284 hw->dma_rx_tmpbuf_size = size;
285 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
286 size, DMA_FROM_DEVICE);
287 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
288 kfree(hw->dma_rx_tmpbuf);
289 hw->dma_rx_tmpbuf = 0;
290 hw->dma_rx_tmpbuf_size = 0;
291 return -EFAULT;
292 }
293 return 0;
294}
295
296static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
297{
298 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
299 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
300 kfree(hw->dma_rx_tmpbuf);
301 hw->dma_rx_tmpbuf = 0;
302 hw->dma_rx_tmpbuf_size = 0;
303}
304
305static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
306{
307 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
308 dma_addr_t dma_tx_addr;
309 dma_addr_t dma_rx_addr;
310 u32 res;
311
312 hw->len = t->len;
313 hw->tx_count = 0;
314 hw->rx_count = 0;
315
316 hw->tx = t->tx_buf;
317 hw->rx = t->rx_buf;
318 dma_tx_addr = t->tx_dma;
319 dma_rx_addr = t->rx_dma;
320
321 /*
322 * check if buffers are already dma mapped, map them otherwise:
323 * - first map the TX buffer, so cache data gets written to memory
324 * - then map the RX buffer, so that cache entries (with
325 * soon-to-be-stale data) get removed
326 * use rx buffer in place of tx if tx buffer was not provided
327 * use temp rx buffer (preallocated or realloc to fit) for rx dma
328 */
329 if (t->tx_buf) {
330 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
331 dma_tx_addr = dma_map_single(hw->dev,
332 (void *)t->tx_buf,
333 t->len, DMA_TO_DEVICE);
334 if (dma_mapping_error(hw->dev, dma_tx_addr))
335 dev_err(hw->dev, "tx dma map error\n");
336 }
337 }
338
339 if (t->rx_buf) {
340 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
341 dma_rx_addr = dma_map_single(hw->dev,
342 (void *)t->rx_buf,
343 t->len, DMA_FROM_DEVICE);
344 if (dma_mapping_error(hw->dev, dma_rx_addr))
345 dev_err(hw->dev, "rx dma map error\n");
346 }
347 } else {
348 if (t->len > hw->dma_rx_tmpbuf_size) {
349 int ret;
350
351 au1550_spi_dma_rxtmp_free(hw);
352 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
353 AU1550_SPI_DMA_RXTMP_MINSIZE));
354 if (ret < 0)
355 return ret;
356 }
357 hw->rx = hw->dma_rx_tmpbuf;
358 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
359 dma_sync_single_for_device(hw->dev, dma_rx_addr,
360 t->len, DMA_FROM_DEVICE);
361 }
362
363 if (!t->tx_buf) {
364 dma_sync_single_for_device(hw->dev, dma_rx_addr,
365 t->len, DMA_BIDIRECTIONAL);
366 hw->tx = hw->rx;
367 }
368
369 /* put buffers on the ring */
370 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
371 t->len, DDMA_FLAGS_IE);
372 if (!res)
373 dev_err(hw->dev, "rx dma put dest error\n");
374
375 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
376 t->len, DDMA_FLAGS_IE);
377 if (!res)
378 dev_err(hw->dev, "tx dma put source error\n");
379
380 au1xxx_dbdma_start(hw->dma_rx_ch);
381 au1xxx_dbdma_start(hw->dma_tx_ch);
382
383 /* by default enable nearly all events interrupt */
384 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
385 wmb(); /* drain writebuffer */
386
387 /* start the transfer */
388 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
389 wmb(); /* drain writebuffer */
390
391 wait_for_completion(&hw->master_done);
392
393 au1xxx_dbdma_stop(hw->dma_tx_ch);
394 au1xxx_dbdma_stop(hw->dma_rx_ch);
395
396 if (!t->rx_buf) {
397 /* using the temporal preallocated and premapped buffer */
398 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
399 DMA_FROM_DEVICE);
400 }
401 /* unmap buffers if mapped above */
402 if (t->rx_buf && t->rx_dma == 0 )
403 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
404 DMA_FROM_DEVICE);
405 if (t->tx_buf && t->tx_dma == 0 )
406 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
407 DMA_TO_DEVICE);
408
409 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
410}
411
412static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
413{
414 u32 stat, evnt;
415
416 stat = hw->regs->psc_spistat;
417 evnt = hw->regs->psc_spievent;
418 wmb(); /* drain writebuffer */
419 if ((stat & PSC_SPISTAT_DI) == 0) {
420 dev_err(hw->dev, "Unexpected IRQ!\n");
421 return IRQ_NONE;
422 }
423
424 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
425 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
426 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
427 != 0) {
428 /*
429 * due to an spi error we consider transfer as done,
430 * so mask all events until before next transfer start
431 * and stop the possibly running dma immediately
432 */
433 au1550_spi_mask_ack_all(hw);
434 au1xxx_dbdma_stop(hw->dma_rx_ch);
435 au1xxx_dbdma_stop(hw->dma_tx_ch);
436
437 /* get number of transferred bytes */
438 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
439 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
440
441 au1xxx_dbdma_reset(hw->dma_rx_ch);
442 au1xxx_dbdma_reset(hw->dma_tx_ch);
443 au1550_spi_reset_fifos(hw);
444
445 if (evnt == PSC_SPIEVNT_RO)
446 dev_err(hw->dev,
447 "dma transfer: receive FIFO overflow!\n");
448 else
449 dev_err(hw->dev,
450 "dma transfer: unexpected SPI error "
451 "(event=0x%x stat=0x%x)!\n", evnt, stat);
452
453 complete(&hw->master_done);
454 return IRQ_HANDLED;
455 }
456
457 if ((evnt & PSC_SPIEVNT_MD) != 0) {
458 /* transfer completed successfully */
459 au1550_spi_mask_ack_all(hw);
460 hw->rx_count = hw->len;
461 hw->tx_count = hw->len;
462 complete(&hw->master_done);
463 }
464 return IRQ_HANDLED;
465}
466
467
468/* routines to handle different word sizes in pio mode */
469#define AU1550_SPI_RX_WORD(size, mask) \
470static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
471{ \
472 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
473 wmb(); /* drain writebuffer */ \
474 if (hw->rx) { \
475 *(u##size *)hw->rx = (u##size)fifoword; \
476 hw->rx += (size) / 8; \
477 } \
478 hw->rx_count += (size) / 8; \
479}
480
481#define AU1550_SPI_TX_WORD(size, mask) \
482static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
483{ \
484 u32 fifoword = 0; \
485 if (hw->tx) { \
486 fifoword = *(u##size *)hw->tx & (u32)(mask); \
487 hw->tx += (size) / 8; \
488 } \
489 hw->tx_count += (size) / 8; \
490 if (hw->tx_count >= hw->len) \
491 fifoword |= PSC_SPITXRX_LC; \
492 hw->regs->psc_spitxrx = fifoword; \
493 wmb(); /* drain writebuffer */ \
494}
495
496AU1550_SPI_RX_WORD(8,0xff)
497AU1550_SPI_RX_WORD(16,0xffff)
498AU1550_SPI_RX_WORD(32,0xffffff)
499AU1550_SPI_TX_WORD(8,0xff)
500AU1550_SPI_TX_WORD(16,0xffff)
501AU1550_SPI_TX_WORD(32,0xffffff)
502
503static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
504{
505 u32 stat, mask;
506 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
507
508 hw->tx = t->tx_buf;
509 hw->rx = t->rx_buf;
510 hw->len = t->len;
511 hw->tx_count = 0;
512 hw->rx_count = 0;
513
514 /* by default enable nearly all events after filling tx fifo */
515 mask = PSC_SPIMSK_SD;
516
517 /* fill the transmit FIFO */
518 while (hw->tx_count < hw->len) {
519
520 hw->tx_word(hw);
521
522 if (hw->tx_count >= hw->len) {
523 /* mask tx fifo request interrupt as we are done */
524 mask |= PSC_SPIMSK_TR;
525 }
526
527 stat = hw->regs->psc_spistat;
528 wmb(); /* drain writebuffer */
529 if (stat & PSC_SPISTAT_TF)
530 break;
531 }
532
533 /* enable event interrupts */
534 hw->regs->psc_spimsk = mask;
535 wmb(); /* drain writebuffer */
536
537 /* start the transfer */
538 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
539 wmb(); /* drain writebuffer */
540
541 wait_for_completion(&hw->master_done);
542
543 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
544}
545
546static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
547{
548 int busy;
549 u32 stat, evnt;
550
551 stat = hw->regs->psc_spistat;
552 evnt = hw->regs->psc_spievent;
553 wmb(); /* drain writebuffer */
554 if ((stat & PSC_SPISTAT_DI) == 0) {
555 dev_err(hw->dev, "Unexpected IRQ!\n");
556 return IRQ_NONE;
557 }
558
559 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
560 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
561 | PSC_SPIEVNT_SD))
562 != 0) {
563 /*
564 * due to an error we consider transfer as done,
565 * so mask all events until before next transfer start
566 */
567 au1550_spi_mask_ack_all(hw);
568 au1550_spi_reset_fifos(hw);
569 dev_err(hw->dev,
570 "pio transfer: unexpected SPI error "
571 "(event=0x%x stat=0x%x)!\n", evnt, stat);
572 complete(&hw->master_done);
573 return IRQ_HANDLED;
574 }
575
576 /*
577 * while there is something to read from rx fifo
578 * or there is a space to write to tx fifo:
579 */
580 do {
581 busy = 0;
582 stat = hw->regs->psc_spistat;
583 wmb(); /* drain writebuffer */
584
585 /*
586 * Take care to not let the Rx FIFO overflow.
587 *
588 * We only write a byte if we have read one at least. Initially,
589 * the write fifo is full, so we should read from the read fifo
590 * first.
591 * In case we miss a word from the read fifo, we should get a
592 * RO event and should back out.
593 */
594 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
595 hw->rx_word(hw);
596 busy = 1;
597
598 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
599 hw->tx_word(hw);
600 }
601 } while (busy);
602
603 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
604 wmb(); /* drain writebuffer */
605
606 /*
607 * Restart the SPI transmission in case of a transmit underflow.
608 * This seems to work despite the notes in the Au1550 data book
609 * of Figure 8-4 with flowchart for SPI master operation:
610 *
611 * """Note 1: An XFR Error Interrupt occurs, unless masked,
612 * for any of the following events: Tx FIFO Underflow,
613 * Rx FIFO Overflow, or Multiple-master Error
614 * Note 2: In case of a Tx Underflow Error, all zeroes are
615 * transmitted."""
616 *
617 * By simply restarting the spi transfer on Tx Underflow Error,
618 * we assume that spi transfer was paused instead of zeroes
619 * transmittion mentioned in the Note 2 of Au1550 data book.
620 */
621 if (evnt & PSC_SPIEVNT_TU) {
622 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
623 wmb(); /* drain writebuffer */
624 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
625 wmb(); /* drain writebuffer */
626 }
627
628 if (hw->rx_count >= hw->len) {
629 /* transfer completed successfully */
630 au1550_spi_mask_ack_all(hw);
631 complete(&hw->master_done);
632 }
633 return IRQ_HANDLED;
634}
635
636static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
637{
638 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
639 return hw->txrx_bufs(spi, t);
640}
641
642static irqreturn_t au1550_spi_irq(int irq, void *dev)
643{
644 struct au1550_spi *hw = dev;
645 return hw->irq_callback(hw);
646}
647
648static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
649{
650 if (bpw <= 8) {
651 if (hw->usedma) {
652 hw->txrx_bufs = &au1550_spi_dma_txrxb;
653 hw->irq_callback = &au1550_spi_dma_irq_callback;
654 } else {
655 hw->rx_word = &au1550_spi_rx_word_8;
656 hw->tx_word = &au1550_spi_tx_word_8;
657 hw->txrx_bufs = &au1550_spi_pio_txrxb;
658 hw->irq_callback = &au1550_spi_pio_irq_callback;
659 }
660 } else if (bpw <= 16) {
661 hw->rx_word = &au1550_spi_rx_word_16;
662 hw->tx_word = &au1550_spi_tx_word_16;
663 hw->txrx_bufs = &au1550_spi_pio_txrxb;
664 hw->irq_callback = &au1550_spi_pio_irq_callback;
665 } else {
666 hw->rx_word = &au1550_spi_rx_word_32;
667 hw->tx_word = &au1550_spi_tx_word_32;
668 hw->txrx_bufs = &au1550_spi_pio_txrxb;
669 hw->irq_callback = &au1550_spi_pio_irq_callback;
670 }
671}
672
673static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
674{
675 u32 stat, cfg;
676
677 /* set up the PSC for SPI mode */
678 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
679 wmb(); /* drain writebuffer */
680 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
681 wmb(); /* drain writebuffer */
682
683 hw->regs->psc_spicfg = 0;
684 wmb(); /* drain writebuffer */
685
686 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
687 wmb(); /* drain writebuffer */
688
689 do {
690 stat = hw->regs->psc_spistat;
691 wmb(); /* drain writebuffer */
692 } while ((stat & PSC_SPISTAT_SR) == 0);
693
694
695 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
696 cfg |= PSC_SPICFG_SET_LEN(8);
697 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
698 /* use minimal allowed brg and div values as initial setting: */
699 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
700
701#ifdef AU1550_SPI_DEBUG_LOOPBACK
702 cfg |= PSC_SPICFG_LB;
703#endif
704
705 hw->regs->psc_spicfg = cfg;
706 wmb(); /* drain writebuffer */
707
708 au1550_spi_mask_ack_all(hw);
709
710 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
711 wmb(); /* drain writebuffer */
712
713 do {
714 stat = hw->regs->psc_spistat;
715 wmb(); /* drain writebuffer */
716 } while ((stat & PSC_SPISTAT_DR) == 0);
717
718 au1550_spi_reset_fifos(hw);
719}
720
721
722static int au1550_spi_probe(struct platform_device *pdev)
723{
724 struct au1550_spi *hw;
725 struct spi_master *master;
726 struct resource *r;
727 int err = 0;
728
729 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
730 if (master == NULL) {
731 dev_err(&pdev->dev, "No memory for spi_master\n");
732 err = -ENOMEM;
733 goto err_nomem;
734 }
735
736 /* the spi->mode bits understood by this driver: */
737 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
738 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
739
740 hw = spi_master_get_devdata(master);
741
742 hw->master = master;
743 hw->pdata = dev_get_platdata(&pdev->dev);
744 hw->dev = &pdev->dev;
745
746 if (hw->pdata == NULL) {
747 dev_err(&pdev->dev, "No platform data supplied\n");
748 err = -ENOENT;
749 goto err_no_pdata;
750 }
751
752 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
753 if (!r) {
754 dev_err(&pdev->dev, "no IRQ\n");
755 err = -ENODEV;
756 goto err_no_iores;
757 }
758 hw->irq = r->start;
759
760 hw->usedma = 0;
761 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
762 if (r) {
763 hw->dma_tx_id = r->start;
764 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
765 if (r) {
766 hw->dma_rx_id = r->start;
767 if (usedma && ddma_memid) {
768 if (pdev->dev.dma_mask == NULL)
769 dev_warn(&pdev->dev, "no dma mask\n");
770 else
771 hw->usedma = 1;
772 }
773 }
774 }
775
776 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
777 if (!r) {
778 dev_err(&pdev->dev, "no mmio resource\n");
779 err = -ENODEV;
780 goto err_no_iores;
781 }
782
783 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
784 pdev->name);
785 if (!hw->ioarea) {
786 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
787 err = -ENXIO;
788 goto err_no_iores;
789 }
790
791 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
792 if (!hw->regs) {
793 dev_err(&pdev->dev, "cannot ioremap\n");
794 err = -ENXIO;
795 goto err_ioremap;
796 }
797
798 platform_set_drvdata(pdev, hw);
799
800 init_completion(&hw->master_done);
801
802 hw->bitbang.master = hw->master;
803 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
804 hw->bitbang.chipselect = au1550_spi_chipsel;
805 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
806
807 if (hw->usedma) {
808 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
809 hw->dma_tx_id, NULL, (void *)hw);
810 if (hw->dma_tx_ch == 0) {
811 dev_err(&pdev->dev,
812 "Cannot allocate tx dma channel\n");
813 err = -ENXIO;
814 goto err_no_txdma;
815 }
816 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
817 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
818 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
819 dev_err(&pdev->dev,
820 "Cannot allocate tx dma descriptors\n");
821 err = -ENXIO;
822 goto err_no_txdma_descr;
823 }
824
825
826 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
827 ddma_memid, NULL, (void *)hw);
828 if (hw->dma_rx_ch == 0) {
829 dev_err(&pdev->dev,
830 "Cannot allocate rx dma channel\n");
831 err = -ENXIO;
832 goto err_no_rxdma;
833 }
834 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
835 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
836 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
837 dev_err(&pdev->dev,
838 "Cannot allocate rx dma descriptors\n");
839 err = -ENXIO;
840 goto err_no_rxdma_descr;
841 }
842
843 err = au1550_spi_dma_rxtmp_alloc(hw,
844 AU1550_SPI_DMA_RXTMP_MINSIZE);
845 if (err < 0) {
846 dev_err(&pdev->dev,
847 "Cannot allocate initial rx dma tmp buffer\n");
848 goto err_dma_rxtmp_alloc;
849 }
850 }
851
852 au1550_spi_bits_handlers_set(hw, 8);
853
854 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
855 if (err) {
856 dev_err(&pdev->dev, "Cannot claim IRQ\n");
857 goto err_no_irq;
858 }
859
860 master->bus_num = pdev->id;
861 master->num_chipselect = hw->pdata->num_chipselect;
862
863 /*
864 * precompute valid range for spi freq - from au1550 datasheet:
865 * psc_tempclk = psc_mainclk / (2 << DIV)
866 * spiclk = psc_tempclk / (2 * (BRG + 1))
867 * BRG valid range is 4..63
868 * DIV valid range is 0..3
869 * round the min and max frequencies to values that would still
870 * produce valid brg and div
871 */
872 {
873 int min_div = (2 << 0) * (2 * (4 + 1));
874 int max_div = (2 << 3) * (2 * (63 + 1));
875 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
876 master->min_speed_hz =
877 hw->pdata->mainclk_hz / (max_div + 1) + 1;
878 }
879
880 au1550_spi_setup_psc_as_spi(hw);
881
882 err = spi_bitbang_start(&hw->bitbang);
883 if (err) {
884 dev_err(&pdev->dev, "Failed to register SPI master\n");
885 goto err_register;
886 }
887
888 dev_info(&pdev->dev,
889 "spi master registered: bus_num=%d num_chipselect=%d\n",
890 master->bus_num, master->num_chipselect);
891
892 return 0;
893
894err_register:
895 free_irq(hw->irq, hw);
896
897err_no_irq:
898 au1550_spi_dma_rxtmp_free(hw);
899
900err_dma_rxtmp_alloc:
901err_no_rxdma_descr:
902 if (hw->usedma)
903 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
904
905err_no_rxdma:
906err_no_txdma_descr:
907 if (hw->usedma)
908 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
909
910err_no_txdma:
911 iounmap((void __iomem *)hw->regs);
912
913err_ioremap:
914 release_mem_region(r->start, sizeof(psc_spi_t));
915
916err_no_iores:
917err_no_pdata:
918 spi_master_put(hw->master);
919
920err_nomem:
921 return err;
922}
923
924static int au1550_spi_remove(struct platform_device *pdev)
925{
926 struct au1550_spi *hw = platform_get_drvdata(pdev);
927
928 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
929 hw->master->bus_num);
930
931 spi_bitbang_stop(&hw->bitbang);
932 free_irq(hw->irq, hw);
933 iounmap((void __iomem *)hw->regs);
934 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
935
936 if (hw->usedma) {
937 au1550_spi_dma_rxtmp_free(hw);
938 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
939 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
940 }
941
942 spi_master_put(hw->master);
943 return 0;
944}
945
946/* work with hotplug and coldplug */
947MODULE_ALIAS("platform:au1550-spi");
948
949static struct platform_driver au1550_spi_drv = {
950 .probe = au1550_spi_probe,
951 .remove = au1550_spi_remove,
952 .driver = {
953 .name = "au1550-spi",
954 },
955};
956
957static int __init au1550_spi_init(void)
958{
959 /*
960 * create memory device with 8 bits dev_devwidth
961 * needed for proper byte ordering to spi fifo
962 */
963 switch (alchemy_get_cputype()) {
964 case ALCHEMY_CPU_AU1550:
965 case ALCHEMY_CPU_AU1200:
966 case ALCHEMY_CPU_AU1300:
967 break;
968 default:
969 return -ENODEV;
970 }
971
972 if (usedma) {
973 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
974 if (!ddma_memid)
975 printk(KERN_ERR "au1550-spi: cannot add memory"
976 "dbdma device\n");
977 }
978 return platform_driver_register(&au1550_spi_drv);
979}
980module_init(au1550_spi_init);
981
982static void __exit au1550_spi_exit(void)
983{
984 if (usedma && ddma_memid)
985 au1xxx_ddma_del_device(ddma_memid);
986 platform_driver_unregister(&au1550_spi_drv);
987}
988module_exit(au1550_spi_exit);
989
990MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
991MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
992MODULE_LICENSE("GPL");