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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/clk.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <net/dsa.h>
24#include <linux/ethtool.h>
25#include <linux/if_bridge.h>
26#include <linux/brcmphy.h>
27#include <linux/etherdevice.h>
28#include <linux/platform_data/b53.h>
29
30#include "bcm_sf2.h"
31#include "bcm_sf2_regs.h"
32#include "b53/b53_priv.h"
33#include "b53/b53_regs.h"
34
35static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36{
37 switch (priv->type) {
38 case BCM4908_DEVICE_ID:
39 switch (port) {
40 case 7:
41 return REG_RGMII_11_CNTRL;
42 default:
43 break;
44 }
45 break;
46 default:
47 switch (port) {
48 case 0:
49 return REG_RGMII_0_CNTRL;
50 case 1:
51 return REG_RGMII_1_CNTRL;
52 case 2:
53 return REG_RGMII_2_CNTRL;
54 default:
55 break;
56 }
57 }
58
59 WARN_ONCE(1, "Unsupported port %d\n", port);
60
61 /* RO fallback reg */
62 return REG_SWITCH_STATUS;
63}
64
65static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
66{
67 switch (port) {
68 case 0:
69 return REG_LED_0_CNTRL;
70 case 1:
71 return REG_LED_1_CNTRL;
72 case 2:
73 return REG_LED_2_CNTRL;
74 }
75
76 switch (priv->type) {
77 case BCM4908_DEVICE_ID:
78 switch (port) {
79 case 3:
80 return REG_LED_3_CNTRL;
81 case 7:
82 return REG_LED_4_CNTRL;
83 default:
84 break;
85 }
86 break;
87 default:
88 break;
89 }
90
91 WARN_ONCE(1, "Unsupported port %d\n", port);
92
93 /* RO fallback reg */
94 return REG_SWITCH_STATUS;
95}
96
97static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port)
98{
99 switch (priv->type) {
100 case BCM4908_DEVICE_ID:
101 case BCM7445_DEVICE_ID:
102 return port == 8 ? CORE_STS_OVERRIDE_IMP :
103 CORE_STS_OVERRIDE_GMIIP_PORT(port);
104 case BCM7278_DEVICE_ID:
105 return port == 8 ? CORE_STS_OVERRIDE_IMP2 :
106 CORE_STS_OVERRIDE_GMIIP2_PORT(port);
107 default:
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type);
109 }
110
111 /* RO fallback register */
112 return REG_SWITCH_STATUS;
113}
114
115/* Return the number of active ports, not counting the IMP (CPU) port */
116static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
117{
118 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
119 unsigned int port, count = 0;
120
121 for (port = 0; port < ds->num_ports; port++) {
122 if (dsa_is_cpu_port(ds, port))
123 continue;
124 if (priv->port_sts[port].enabled)
125 count++;
126 }
127
128 return count;
129}
130
131static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
132{
133 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
134 unsigned long new_rate;
135 unsigned int ports_active;
136 /* Frequenty in Mhz */
137 static const unsigned long rate_table[] = {
138 59220000,
139 60820000,
140 62500000,
141 62500000,
142 };
143
144 ports_active = bcm_sf2_num_active_ports(ds);
145 if (ports_active == 0 || !priv->clk_mdiv)
146 return;
147
148 /* If we overflow our table, just use the recommended operational
149 * frequency
150 */
151 if (ports_active > ARRAY_SIZE(rate_table))
152 new_rate = 90000000;
153 else
154 new_rate = rate_table[ports_active - 1];
155 clk_set_rate(priv->clk_mdiv, new_rate);
156}
157
158static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
159{
160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 unsigned int i;
162 u32 reg;
163
164 /* Enable the port memories */
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
168
169 /* Enable forwarding */
170 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
171
172 /* Enable IMP port in dumb mode */
173 reg = core_readl(priv, CORE_SWITCH_CTRL);
174 reg |= MII_DUMB_FWDG_EN;
175 core_writel(priv, reg, CORE_SWITCH_CTRL);
176
177 /* Configure Traffic Class to QoS mapping, allow each priority to map
178 * to a different queue number
179 */
180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
182 reg |= i << (PRT_TO_QID_SHIFT * i);
183 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
184
185 b53_brcm_hdr_setup(ds, port);
186
187 if (port == 8) {
188 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
189 reg = core_readl(priv, CORE_IMP_CTL);
190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
191 reg &= ~(RX_DIS | TX_DIS);
192 core_writel(priv, reg, CORE_IMP_CTL);
193 } else {
194 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
195 reg &= ~(RX_DIS | TX_DIS);
196 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
197 }
198
199 priv->port_sts[port].enabled = true;
200}
201
202static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
203{
204 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
205 u32 reg;
206
207 reg = reg_readl(priv, REG_SPHY_CNTRL);
208 if (enable) {
209 reg |= PHY_RESET;
210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
211 reg_writel(priv, reg, REG_SPHY_CNTRL);
212 udelay(21);
213 reg = reg_readl(priv, REG_SPHY_CNTRL);
214 reg &= ~PHY_RESET;
215 } else {
216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
217 reg_writel(priv, reg, REG_SPHY_CNTRL);
218 mdelay(1);
219 reg |= CK25_DIS;
220 }
221 reg_writel(priv, reg, REG_SPHY_CNTRL);
222
223 /* Use PHY-driven LED signaling */
224 if (!enable) {
225 u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
226
227 if (priv->type == BCM7278_DEVICE_ID ||
228 priv->type == BCM7445_DEVICE_ID) {
229 reg = reg_led_readl(priv, led_ctrl, 0);
230 reg |= LED_CNTRL_SPDLNK_SRC_SEL;
231 reg_led_writel(priv, reg, led_ctrl, 0);
232 }
233 }
234}
235
236static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
237 int port)
238{
239 unsigned int off;
240
241 switch (port) {
242 case 7:
243 off = P7_IRQ_OFF;
244 break;
245 case 0:
246 /* Port 0 interrupts are located on the first bank */
247 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
248 return;
249 default:
250 off = P_IRQ_OFF(port);
251 break;
252 }
253
254 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
255}
256
257static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
258 int port)
259{
260 unsigned int off;
261
262 switch (port) {
263 case 7:
264 off = P7_IRQ_OFF;
265 break;
266 case 0:
267 /* Port 0 interrupts are located on the first bank */
268 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
269 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
270 return;
271 default:
272 off = P_IRQ_OFF(port);
273 break;
274 }
275
276 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
277 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
278}
279
280static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
281 struct phy_device *phy)
282{
283 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
284 unsigned int i;
285 u32 reg;
286
287 if (!dsa_is_user_port(ds, port))
288 return 0;
289
290 priv->port_sts[port].enabled = true;
291
292 bcm_sf2_recalc_clock(ds);
293
294 /* Clear the memory power down */
295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
296 reg &= ~P_TXQ_PSM_VDD(port);
297 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
298
299 /* Enable Broadcom tags for that port if requested */
300 if (priv->brcm_tag_mask & BIT(port))
301 b53_brcm_hdr_setup(ds, port);
302
303 /* Configure Traffic Class to QoS mapping, allow each priority to map
304 * to a different queue number
305 */
306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
307 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
308 reg |= i << (PRT_TO_QID_SHIFT * i);
309 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
310
311 /* Re-enable the GPHY and re-apply workarounds */
312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
313 bcm_sf2_gphy_enable_set(ds, true);
314 if (phy) {
315 /* if phy_stop() has been called before, phy
316 * will be in halted state, and phy_start()
317 * will call resume.
318 *
319 * the resume path does not configure back
320 * autoneg settings, and since we hard reset
321 * the phy manually here, we need to reset the
322 * state machine also.
323 */
324 phy->state = PHY_READY;
325 phy_init_hw(phy);
326 }
327 }
328
329 /* Enable MoCA port interrupts to get notified */
330 if (port == priv->moca_port)
331 bcm_sf2_port_intr_enable(priv, port);
332
333 /* Set per-queue pause threshold to 32 */
334 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
335
336 /* Set ACB threshold to 24 */
337 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
338 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
339 SF2_NUM_EGRESS_QUEUES + i));
340 reg &= ~XOFF_THRESHOLD_MASK;
341 reg |= 24;
342 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
343 SF2_NUM_EGRESS_QUEUES + i));
344 }
345
346 return b53_enable_port(ds, port, phy);
347}
348
349static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
350{
351 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
352 u32 reg;
353
354 /* Disable learning while in WoL mode */
355 if (priv->wol_ports_mask & (1 << port)) {
356 reg = core_readl(priv, CORE_DIS_LEARN);
357 reg |= BIT(port);
358 core_writel(priv, reg, CORE_DIS_LEARN);
359 return;
360 }
361
362 if (port == priv->moca_port)
363 bcm_sf2_port_intr_disable(priv, port);
364
365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
366 bcm_sf2_gphy_enable_set(ds, false);
367
368 b53_disable_port(ds, port);
369
370 /* Power down the port memory */
371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
372 reg |= P_TXQ_PSM_VDD(port);
373 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
374
375 priv->port_sts[port].enabled = false;
376
377 bcm_sf2_recalc_clock(ds);
378}
379
380
381static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
382 int regnum, u16 val)
383{
384 int ret = 0;
385 u32 reg;
386
387 reg = reg_readl(priv, REG_SWITCH_CNTRL);
388 reg |= MDIO_MASTER_SEL;
389 reg_writel(priv, reg, REG_SWITCH_CNTRL);
390
391 /* Page << 8 | offset */
392 reg = 0x70;
393 reg <<= 2;
394 core_writel(priv, addr, reg);
395
396 /* Page << 8 | offset */
397 reg = 0x80 << 8 | regnum << 1;
398 reg <<= 2;
399
400 if (op)
401 ret = core_readl(priv, reg);
402 else
403 core_writel(priv, val, reg);
404
405 reg = reg_readl(priv, REG_SWITCH_CNTRL);
406 reg &= ~MDIO_MASTER_SEL;
407 reg_writel(priv, reg, REG_SWITCH_CNTRL);
408
409 return ret & 0xffff;
410}
411
412static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
413{
414 struct bcm_sf2_priv *priv = bus->priv;
415
416 /* Intercept reads from Broadcom pseudo-PHY address, else, send
417 * them to our master MDIO bus controller
418 */
419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
420 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
421 else
422 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
423}
424
425static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
426 u16 val)
427{
428 struct bcm_sf2_priv *priv = bus->priv;
429
430 /* Intercept writes to the Broadcom pseudo-PHY address, else,
431 * send them to our master MDIO bus controller
432 */
433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
434 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
435 else
436 return mdiobus_write_nested(priv->master_mii_bus, addr,
437 regnum, val);
438}
439
440static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
441{
442 struct dsa_switch *ds = dev_id;
443 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
444
445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
446 ~priv->irq0_mask;
447 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
448
449 return IRQ_HANDLED;
450}
451
452static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
453{
454 struct dsa_switch *ds = dev_id;
455 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
456
457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
458 ~priv->irq1_mask;
459 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
460
461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
462 priv->port_sts[7].link = true;
463 dsa_port_phylink_mac_change(ds, 7, true);
464 }
465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
466 priv->port_sts[7].link = false;
467 dsa_port_phylink_mac_change(ds, 7, false);
468 }
469
470 return IRQ_HANDLED;
471}
472
473static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
474{
475 unsigned int timeout = 1000;
476 u32 reg;
477 int ret;
478
479 /* The watchdog reset does not work on 7278, we need to hit the
480 * "external" reset line through the reset controller.
481 */
482 if (priv->type == BCM7278_DEVICE_ID) {
483 ret = reset_control_assert(priv->rcdev);
484 if (ret)
485 return ret;
486
487 return reset_control_deassert(priv->rcdev);
488 }
489
490 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
492 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
493
494 do {
495 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
496 if (!(reg & SOFTWARE_RESET))
497 break;
498
499 usleep_range(1000, 2000);
500 } while (timeout-- > 0);
501
502 if (timeout == 0)
503 return -ETIMEDOUT;
504
505 return 0;
506}
507
508static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
509{
510 struct device *dev = priv->dev->ds->dev;
511 int shift;
512 u32 mask;
513 u32 reg;
514 int i;
515
516 mask = BIT(priv->num_crossbar_int_ports) - 1;
517
518 reg = reg_readl(priv, REG_CROSSBAR);
519 switch (priv->type) {
520 case BCM4908_DEVICE_ID:
521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
522 reg &= ~(mask << shift);
523 if (0) /* FIXME */
524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
525 else if (priv->int_phy_mask & BIT(7))
526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
527 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
529 else if (WARN(1, "Invalid port mode\n"))
530 return;
531 break;
532 default:
533 return;
534 }
535 reg_writel(priv, reg, REG_CROSSBAR);
536
537 reg = reg_readl(priv, REG_CROSSBAR);
538 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
539 shift = i * priv->num_crossbar_int_ports;
540
541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
542 (reg >> shift) & mask);
543 }
544}
545
546static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
547{
548 intrl2_0_mask_set(priv, 0xffffffff);
549 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
550 intrl2_1_mask_set(priv, 0xffffffff);
551 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
552}
553
554static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
555 struct device_node *dn)
556{
557 struct device *dev = priv->dev->ds->dev;
558 struct bcm_sf2_port_status *port_st;
559 struct device_node *port;
560 unsigned int port_num;
561 struct property *prop;
562 int err;
563
564 priv->moca_port = -1;
565
566 for_each_available_child_of_node(dn, port) {
567 if (of_property_read_u32(port, "reg", &port_num))
568 continue;
569
570 if (port_num >= DSA_MAX_PORTS) {
571 dev_err(dev, "Invalid port number %d\n", port_num);
572 continue;
573 }
574
575 port_st = &priv->port_sts[port_num];
576
577 /* Internal PHYs get assigned a specific 'phy-mode' property
578 * value: "internal" to help flag them before MDIO probing
579 * has completed, since they might be turned off at that
580 * time
581 */
582 err = of_get_phy_mode(port, &port_st->mode);
583 if (err)
584 continue;
585
586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
587 priv->int_phy_mask |= 1 << port_num;
588
589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
590 priv->moca_port = port_num;
591
592 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
593 priv->brcm_tag_mask |= 1 << port_num;
594
595 /* Ensure that port 5 is not picked up as a DSA CPU port
596 * flavour but a regular port instead. We should be using
597 * devlink to be able to set the port flavour.
598 */
599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
600 prop = of_find_property(port, "ethernet", NULL);
601 if (prop)
602 of_remove_property(port, prop);
603 }
604 }
605}
606
607static int bcm_sf2_mdio_register(struct dsa_switch *ds)
608{
609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
610 struct device_node *dn, *child;
611 struct phy_device *phydev;
612 struct property *prop;
613 static int index;
614 int err, reg;
615
616 /* Find our integrated MDIO bus node */
617 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
618 priv->master_mii_bus = of_mdio_find_bus(dn);
619 if (!priv->master_mii_bus) {
620 of_node_put(dn);
621 return -EPROBE_DEFER;
622 }
623
624 get_device(&priv->master_mii_bus->dev);
625 priv->master_mii_dn = dn;
626
627 priv->slave_mii_bus = mdiobus_alloc();
628 if (!priv->slave_mii_bus) {
629 of_node_put(dn);
630 return -ENOMEM;
631 }
632
633 priv->slave_mii_bus->priv = priv;
634 priv->slave_mii_bus->name = "sf2 slave mii";
635 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
636 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
637 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
638 index++);
639 priv->slave_mii_bus->dev.of_node = dn;
640
641 /* Include the pseudo-PHY address to divert reads towards our
642 * workaround. This is only required for 7445D0, since 7445E0
643 * disconnects the internal switch pseudo-PHY such that we can use the
644 * regular SWITCH_MDIO master controller instead.
645 *
646 * Here we flag the pseudo PHY as needing special treatment and would
647 * otherwise make all other PHY read/writes go to the master MDIO bus
648 * controller that comes with this switch backed by the "mdio-unimac"
649 * driver.
650 */
651 if (of_machine_is_compatible("brcm,bcm7445d0"))
652 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
653 else
654 priv->indir_phy_mask = 0;
655
656 ds->phys_mii_mask = priv->indir_phy_mask;
657 ds->slave_mii_bus = priv->slave_mii_bus;
658 priv->slave_mii_bus->parent = ds->dev->parent;
659 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
660
661 /* We need to make sure that of_phy_connect() will not work by
662 * removing the 'phandle' and 'linux,phandle' properties and
663 * unregister the existing PHY device that was already registered.
664 */
665 for_each_available_child_of_node(dn, child) {
666 if (of_property_read_u32(child, "reg", ®) ||
667 reg >= PHY_MAX_ADDR)
668 continue;
669
670 if (!(priv->indir_phy_mask & BIT(reg)))
671 continue;
672
673 prop = of_find_property(child, "phandle", NULL);
674 if (prop)
675 of_remove_property(child, prop);
676
677 prop = of_find_property(child, "linux,phandle", NULL);
678 if (prop)
679 of_remove_property(child, prop);
680
681 phydev = of_phy_find_device(child);
682 if (phydev)
683 phy_device_remove(phydev);
684 }
685
686 err = mdiobus_register(priv->slave_mii_bus);
687 if (err && dn) {
688 mdiobus_free(priv->slave_mii_bus);
689 of_node_put(dn);
690 }
691
692 return err;
693}
694
695static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
696{
697 mdiobus_unregister(priv->slave_mii_bus);
698 mdiobus_free(priv->slave_mii_bus);
699 of_node_put(priv->master_mii_dn);
700}
701
702static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
703{
704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
705
706 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
707 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
708 * the REG_PHY_REVISION register layout is.
709 */
710 if (priv->int_phy_mask & BIT(port))
711 return priv->hw_params.gphy_rev;
712 else
713 return PHY_BRCM_AUTO_PWRDWN_ENABLE |
714 PHY_BRCM_DIS_TXCRXC_NOENRGY |
715 PHY_BRCM_IDDQ_SUSPEND;
716}
717
718static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
719 struct phylink_config *config)
720{
721 unsigned long *interfaces = config->supported_interfaces;
722 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
723
724 if (priv->int_phy_mask & BIT(port)) {
725 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
726 } else if (priv->moca_port == port) {
727 __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces);
728 } else {
729 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
730 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
731 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
732 phy_interface_set_rgmii(interfaces);
733 }
734
735 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
736 MAC_10 | MAC_100 | MAC_1000;
737}
738
739static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
740 unsigned int mode,
741 const struct phylink_link_state *state)
742{
743 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
744 u32 id_mode_dis = 0, port_mode;
745 u32 reg_rgmii_ctrl;
746 u32 reg;
747
748 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
749 return;
750
751 switch (state->interface) {
752 case PHY_INTERFACE_MODE_RGMII:
753 id_mode_dis = 1;
754 fallthrough;
755 case PHY_INTERFACE_MODE_RGMII_TXID:
756 port_mode = EXT_GPHY;
757 break;
758 case PHY_INTERFACE_MODE_MII:
759 port_mode = EXT_EPHY;
760 break;
761 case PHY_INTERFACE_MODE_REVMII:
762 port_mode = EXT_REVMII;
763 break;
764 default:
765 /* Nothing required for all other PHYs: internal and MoCA */
766 return;
767 }
768
769 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
770
771 /* Clear id_mode_dis bit, and the existing port mode, let
772 * RGMII_MODE_EN bet set by mac_link_{up,down}
773 */
774 reg = reg_readl(priv, reg_rgmii_ctrl);
775 reg &= ~ID_MODE_DIS;
776 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
777
778 reg |= port_mode;
779 if (id_mode_dis)
780 reg |= ID_MODE_DIS;
781
782 reg_writel(priv, reg, reg_rgmii_ctrl);
783}
784
785static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
786 phy_interface_t interface, bool link)
787{
788 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
789 u32 reg_rgmii_ctrl;
790 u32 reg;
791
792 if (!phy_interface_mode_is_rgmii(interface) &&
793 interface != PHY_INTERFACE_MODE_MII &&
794 interface != PHY_INTERFACE_MODE_REVMII)
795 return;
796
797 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
798
799 /* If the link is down, just disable the interface to conserve power */
800 reg = reg_readl(priv, reg_rgmii_ctrl);
801 if (link)
802 reg |= RGMII_MODE_EN;
803 else
804 reg &= ~RGMII_MODE_EN;
805 reg_writel(priv, reg, reg_rgmii_ctrl);
806}
807
808static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
809 unsigned int mode,
810 phy_interface_t interface)
811{
812 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
813 u32 reg, offset;
814
815 if (priv->wol_ports_mask & BIT(port))
816 return;
817
818 offset = bcm_sf2_port_override_offset(priv, port);
819 reg = core_readl(priv, offset);
820 reg &= ~LINK_STS;
821 core_writel(priv, reg, offset);
822
823 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
824}
825
826static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
827 unsigned int mode,
828 phy_interface_t interface,
829 struct phy_device *phydev,
830 int speed, int duplex,
831 bool tx_pause, bool rx_pause)
832{
833 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
834 struct ethtool_eee *p = &priv->dev->ports[port].eee;
835 u32 reg_rgmii_ctrl = 0;
836 u32 reg, offset;
837
838 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
839
840 offset = bcm_sf2_port_override_offset(priv, port);
841
842 if (phy_interface_mode_is_rgmii(interface) ||
843 interface == PHY_INTERFACE_MODE_MII ||
844 interface == PHY_INTERFACE_MODE_REVMII) {
845 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
846 reg = reg_readl(priv, reg_rgmii_ctrl);
847 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
848
849 if (tx_pause)
850 reg |= TX_PAUSE_EN;
851 if (rx_pause)
852 reg |= RX_PAUSE_EN;
853
854 reg_writel(priv, reg, reg_rgmii_ctrl);
855 }
856
857 reg = LINK_STS;
858 if (port == 8) {
859 if (priv->type == BCM4908_DEVICE_ID)
860 reg |= GMII_SPEED_UP_2G;
861 reg |= MII_SW_OR;
862 } else {
863 reg |= SW_OVERRIDE;
864 }
865
866 switch (speed) {
867 case SPEED_1000:
868 reg |= SPDSTS_1000 << SPEED_SHIFT;
869 break;
870 case SPEED_100:
871 reg |= SPDSTS_100 << SPEED_SHIFT;
872 break;
873 }
874
875 if (duplex == DUPLEX_FULL)
876 reg |= DUPLX_MODE;
877
878 if (tx_pause)
879 reg |= TXFLOW_CNTL;
880 if (rx_pause)
881 reg |= RXFLOW_CNTL;
882
883 core_writel(priv, reg, offset);
884
885 if (mode == MLO_AN_PHY && phydev)
886 p->eee_enabled = b53_eee_init(ds, port, phydev);
887}
888
889static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
890 struct phylink_link_state *status)
891{
892 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
893
894 status->link = false;
895
896 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
897 * which means that we need to force the link at the port override
898 * level to get the data to flow. We do use what the interrupt handler
899 * did determine before.
900 *
901 * For the other ports, we just force the link status, since this is
902 * a fixed PHY device.
903 */
904 if (port == priv->moca_port) {
905 status->link = priv->port_sts[port].link;
906 /* For MoCA interfaces, also force a link down notification
907 * since some version of the user-space daemon (mocad) use
908 * cmd->autoneg to force the link, which messes up the PHY
909 * state machine and make it go in PHY_FORCING state instead.
910 */
911 if (!status->link)
912 netif_carrier_off(dsa_to_port(ds, port)->slave);
913 status->duplex = DUPLEX_FULL;
914 } else {
915 status->link = true;
916 }
917}
918
919static void bcm_sf2_enable_acb(struct dsa_switch *ds)
920{
921 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
922 u32 reg;
923
924 /* Enable ACB globally */
925 reg = acb_readl(priv, ACB_CONTROL);
926 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
927 acb_writel(priv, reg, ACB_CONTROL);
928 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
929 reg |= ACB_EN | ACB_ALGORITHM;
930 acb_writel(priv, reg, ACB_CONTROL);
931}
932
933static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
934{
935 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
936 unsigned int port;
937
938 bcm_sf2_intr_disable(priv);
939
940 /* Disable all ports physically present including the IMP
941 * port, the other ones have already been disabled during
942 * bcm_sf2_sw_setup
943 */
944 for (port = 0; port < ds->num_ports; port++) {
945 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
946 bcm_sf2_port_disable(ds, port);
947 }
948
949 if (!priv->wol_ports_mask)
950 clk_disable_unprepare(priv->clk);
951
952 return 0;
953}
954
955static int bcm_sf2_sw_resume(struct dsa_switch *ds)
956{
957 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
958 int ret;
959
960 if (!priv->wol_ports_mask)
961 clk_prepare_enable(priv->clk);
962
963 ret = bcm_sf2_sw_rst(priv);
964 if (ret) {
965 pr_err("%s: failed to software reset switch\n", __func__);
966 return ret;
967 }
968
969 bcm_sf2_crossbar_setup(priv);
970
971 ret = bcm_sf2_cfp_resume(ds);
972 if (ret)
973 return ret;
974
975 if (priv->hw_params.num_gphy == 1)
976 bcm_sf2_gphy_enable_set(ds, true);
977
978 ds->ops->setup(ds);
979
980 return 0;
981}
982
983static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
984 struct ethtool_wolinfo *wol)
985{
986 struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
987 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
988 struct ethtool_wolinfo pwol = { };
989
990 /* Get the parent device WoL settings */
991 if (p->ethtool_ops->get_wol)
992 p->ethtool_ops->get_wol(p, &pwol);
993
994 /* Advertise the parent device supported settings */
995 wol->supported = pwol.supported;
996 memset(&wol->sopass, 0, sizeof(wol->sopass));
997
998 if (pwol.wolopts & WAKE_MAGICSECURE)
999 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1000
1001 if (priv->wol_ports_mask & (1 << port))
1002 wol->wolopts = pwol.wolopts;
1003 else
1004 wol->wolopts = 0;
1005}
1006
1007static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1008 struct ethtool_wolinfo *wol)
1009{
1010 struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
1011 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1012 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1013 struct ethtool_wolinfo pwol = { };
1014
1015 if (p->ethtool_ops->get_wol)
1016 p->ethtool_ops->get_wol(p, &pwol);
1017 if (wol->wolopts & ~pwol.supported)
1018 return -EINVAL;
1019
1020 if (wol->wolopts)
1021 priv->wol_ports_mask |= (1 << port);
1022 else
1023 priv->wol_ports_mask &= ~(1 << port);
1024
1025 /* If we have at least one port enabled, make sure the CPU port
1026 * is also enabled. If the CPU port is the last one enabled, we disable
1027 * it since this configuration does not make sense.
1028 */
1029 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1030 priv->wol_ports_mask |= (1 << cpu_port);
1031 else
1032 priv->wol_ports_mask &= ~(1 << cpu_port);
1033
1034 return p->ethtool_ops->set_wol(p, wol);
1035}
1036
1037static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1038{
1039 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1040 unsigned int port;
1041
1042 /* Enable all valid ports and disable those unused */
1043 for (port = 0; port < priv->hw_params.num_ports; port++) {
1044 /* IMP port receives special treatment */
1045 if (dsa_is_user_port(ds, port))
1046 bcm_sf2_port_setup(ds, port, NULL);
1047 else if (dsa_is_cpu_port(ds, port))
1048 bcm_sf2_imp_setup(ds, port);
1049 else
1050 bcm_sf2_port_disable(ds, port);
1051 }
1052
1053 b53_configure_vlan(ds);
1054 bcm_sf2_enable_acb(ds);
1055
1056 return b53_setup_devlink_resources(ds);
1057}
1058
1059static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1060{
1061 dsa_devlink_resources_unregister(ds);
1062}
1063
1064/* The SWITCH_CORE register space is managed by b53 but operates on a page +
1065 * register basis so we need to translate that into an address that the
1066 * bus-glue understands.
1067 */
1068#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1069
1070static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1071 u8 *val)
1072{
1073 struct bcm_sf2_priv *priv = dev->priv;
1074
1075 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1076
1077 return 0;
1078}
1079
1080static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1081 u16 *val)
1082{
1083 struct bcm_sf2_priv *priv = dev->priv;
1084
1085 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1086
1087 return 0;
1088}
1089
1090static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1091 u32 *val)
1092{
1093 struct bcm_sf2_priv *priv = dev->priv;
1094
1095 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1096
1097 return 0;
1098}
1099
1100static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1101 u64 *val)
1102{
1103 struct bcm_sf2_priv *priv = dev->priv;
1104
1105 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1106
1107 return 0;
1108}
1109
1110static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1111 u8 value)
1112{
1113 struct bcm_sf2_priv *priv = dev->priv;
1114
1115 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1116
1117 return 0;
1118}
1119
1120static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1121 u16 value)
1122{
1123 struct bcm_sf2_priv *priv = dev->priv;
1124
1125 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1126
1127 return 0;
1128}
1129
1130static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1131 u32 value)
1132{
1133 struct bcm_sf2_priv *priv = dev->priv;
1134
1135 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1136
1137 return 0;
1138}
1139
1140static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1141 u64 value)
1142{
1143 struct bcm_sf2_priv *priv = dev->priv;
1144
1145 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1146
1147 return 0;
1148}
1149
1150static const struct b53_io_ops bcm_sf2_io_ops = {
1151 .read8 = bcm_sf2_core_read8,
1152 .read16 = bcm_sf2_core_read16,
1153 .read32 = bcm_sf2_core_read32,
1154 .read48 = bcm_sf2_core_read64,
1155 .read64 = bcm_sf2_core_read64,
1156 .write8 = bcm_sf2_core_write8,
1157 .write16 = bcm_sf2_core_write16,
1158 .write32 = bcm_sf2_core_write32,
1159 .write48 = bcm_sf2_core_write64,
1160 .write64 = bcm_sf2_core_write64,
1161};
1162
1163static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1164 u32 stringset, uint8_t *data)
1165{
1166 int cnt = b53_get_sset_count(ds, port, stringset);
1167
1168 b53_get_strings(ds, port, stringset, data);
1169 bcm_sf2_cfp_get_strings(ds, port, stringset,
1170 data + cnt * ETH_GSTRING_LEN);
1171}
1172
1173static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1174 uint64_t *data)
1175{
1176 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1177
1178 b53_get_ethtool_stats(ds, port, data);
1179 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1180}
1181
1182static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1183 int sset)
1184{
1185 int cnt = b53_get_sset_count(ds, port, sset);
1186
1187 if (cnt < 0)
1188 return cnt;
1189
1190 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1191
1192 return cnt;
1193}
1194
1195static const struct dsa_switch_ops bcm_sf2_ops = {
1196 .get_tag_protocol = b53_get_tag_protocol,
1197 .setup = bcm_sf2_sw_setup,
1198 .teardown = bcm_sf2_sw_teardown,
1199 .get_strings = bcm_sf2_sw_get_strings,
1200 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1201 .get_sset_count = bcm_sf2_sw_get_sset_count,
1202 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1203 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1204 .phylink_get_caps = bcm_sf2_sw_get_caps,
1205 .phylink_mac_config = bcm_sf2_sw_mac_config,
1206 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1207 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1208 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1209 .suspend = bcm_sf2_sw_suspend,
1210 .resume = bcm_sf2_sw_resume,
1211 .get_wol = bcm_sf2_sw_get_wol,
1212 .set_wol = bcm_sf2_sw_set_wol,
1213 .port_enable = bcm_sf2_port_setup,
1214 .port_disable = bcm_sf2_port_disable,
1215 .get_mac_eee = b53_get_mac_eee,
1216 .set_mac_eee = b53_set_mac_eee,
1217 .port_bridge_join = b53_br_join,
1218 .port_bridge_leave = b53_br_leave,
1219 .port_pre_bridge_flags = b53_br_flags_pre,
1220 .port_bridge_flags = b53_br_flags,
1221 .port_stp_state_set = b53_br_set_stp_state,
1222 .port_fast_age = b53_br_fast_age,
1223 .port_vlan_filtering = b53_vlan_filtering,
1224 .port_vlan_add = b53_vlan_add,
1225 .port_vlan_del = b53_vlan_del,
1226 .port_fdb_dump = b53_fdb_dump,
1227 .port_fdb_add = b53_fdb_add,
1228 .port_fdb_del = b53_fdb_del,
1229 .get_rxnfc = bcm_sf2_get_rxnfc,
1230 .set_rxnfc = bcm_sf2_set_rxnfc,
1231 .port_mirror_add = b53_mirror_add,
1232 .port_mirror_del = b53_mirror_del,
1233 .port_mdb_add = b53_mdb_add,
1234 .port_mdb_del = b53_mdb_del,
1235};
1236
1237struct bcm_sf2_of_data {
1238 u32 type;
1239 const u16 *reg_offsets;
1240 unsigned int core_reg_align;
1241 unsigned int num_cfp_rules;
1242 unsigned int num_crossbar_int_ports;
1243};
1244
1245static const u16 bcm_sf2_4908_reg_offsets[] = {
1246 [REG_SWITCH_CNTRL] = 0x00,
1247 [REG_SWITCH_STATUS] = 0x04,
1248 [REG_DIR_DATA_WRITE] = 0x08,
1249 [REG_DIR_DATA_READ] = 0x0c,
1250 [REG_SWITCH_REVISION] = 0x10,
1251 [REG_PHY_REVISION] = 0x14,
1252 [REG_SPHY_CNTRL] = 0x24,
1253 [REG_CROSSBAR] = 0xc8,
1254 [REG_RGMII_11_CNTRL] = 0x014c,
1255 [REG_LED_0_CNTRL] = 0x40,
1256 [REG_LED_1_CNTRL] = 0x4c,
1257 [REG_LED_2_CNTRL] = 0x58,
1258 [REG_LED_3_CNTRL] = 0x64,
1259 [REG_LED_4_CNTRL] = 0x88,
1260 [REG_LED_5_CNTRL] = 0xa0,
1261 [REG_LED_AGGREGATE_CTRL] = 0xb8,
1262
1263};
1264
1265static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1266 .type = BCM4908_DEVICE_ID,
1267 .core_reg_align = 0,
1268 .reg_offsets = bcm_sf2_4908_reg_offsets,
1269 .num_cfp_rules = 256,
1270 .num_crossbar_int_ports = 2,
1271};
1272
1273/* Register offsets for the SWITCH_REG_* block */
1274static const u16 bcm_sf2_7445_reg_offsets[] = {
1275 [REG_SWITCH_CNTRL] = 0x00,
1276 [REG_SWITCH_STATUS] = 0x04,
1277 [REG_DIR_DATA_WRITE] = 0x08,
1278 [REG_DIR_DATA_READ] = 0x0C,
1279 [REG_SWITCH_REVISION] = 0x18,
1280 [REG_PHY_REVISION] = 0x1C,
1281 [REG_SPHY_CNTRL] = 0x2C,
1282 [REG_RGMII_0_CNTRL] = 0x34,
1283 [REG_RGMII_1_CNTRL] = 0x40,
1284 [REG_RGMII_2_CNTRL] = 0x4c,
1285 [REG_LED_0_CNTRL] = 0x90,
1286 [REG_LED_1_CNTRL] = 0x94,
1287 [REG_LED_2_CNTRL] = 0x98,
1288};
1289
1290static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1291 .type = BCM7445_DEVICE_ID,
1292 .core_reg_align = 0,
1293 .reg_offsets = bcm_sf2_7445_reg_offsets,
1294 .num_cfp_rules = 256,
1295};
1296
1297static const u16 bcm_sf2_7278_reg_offsets[] = {
1298 [REG_SWITCH_CNTRL] = 0x00,
1299 [REG_SWITCH_STATUS] = 0x04,
1300 [REG_DIR_DATA_WRITE] = 0x08,
1301 [REG_DIR_DATA_READ] = 0x0c,
1302 [REG_SWITCH_REVISION] = 0x10,
1303 [REG_PHY_REVISION] = 0x14,
1304 [REG_SPHY_CNTRL] = 0x24,
1305 [REG_RGMII_0_CNTRL] = 0xe0,
1306 [REG_RGMII_1_CNTRL] = 0xec,
1307 [REG_RGMII_2_CNTRL] = 0xf8,
1308 [REG_LED_0_CNTRL] = 0x40,
1309 [REG_LED_1_CNTRL] = 0x4c,
1310 [REG_LED_2_CNTRL] = 0x58,
1311};
1312
1313static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1314 .type = BCM7278_DEVICE_ID,
1315 .core_reg_align = 1,
1316 .reg_offsets = bcm_sf2_7278_reg_offsets,
1317 .num_cfp_rules = 128,
1318};
1319
1320static const struct of_device_id bcm_sf2_of_match[] = {
1321 { .compatible = "brcm,bcm4908-switch",
1322 .data = &bcm_sf2_4908_data
1323 },
1324 { .compatible = "brcm,bcm7445-switch-v4.0",
1325 .data = &bcm_sf2_7445_data
1326 },
1327 { .compatible = "brcm,bcm7278-switch-v4.0",
1328 .data = &bcm_sf2_7278_data
1329 },
1330 { .compatible = "brcm,bcm7278-switch-v4.8",
1331 .data = &bcm_sf2_7278_data
1332 },
1333 { /* sentinel */ },
1334};
1335MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1336
1337static int bcm_sf2_sw_probe(struct platform_device *pdev)
1338{
1339 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1340 struct device_node *dn = pdev->dev.of_node;
1341 const struct of_device_id *of_id = NULL;
1342 const struct bcm_sf2_of_data *data;
1343 struct b53_platform_data *pdata;
1344 struct dsa_switch_ops *ops;
1345 struct device_node *ports;
1346 struct bcm_sf2_priv *priv;
1347 struct b53_device *dev;
1348 struct dsa_switch *ds;
1349 void __iomem **base;
1350 unsigned int i;
1351 u32 reg, rev;
1352 int ret;
1353
1354 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1355 if (!priv)
1356 return -ENOMEM;
1357
1358 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1359 if (!ops)
1360 return -ENOMEM;
1361
1362 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1363 if (!dev)
1364 return -ENOMEM;
1365
1366 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1367 if (!pdata)
1368 return -ENOMEM;
1369
1370 of_id = of_match_node(bcm_sf2_of_match, dn);
1371 if (!of_id || !of_id->data)
1372 return -EINVAL;
1373
1374 data = of_id->data;
1375
1376 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1377 priv->type = data->type;
1378 priv->reg_offsets = data->reg_offsets;
1379 priv->core_reg_align = data->core_reg_align;
1380 priv->num_cfp_rules = data->num_cfp_rules;
1381 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1382
1383 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1384 "switch");
1385 if (IS_ERR(priv->rcdev))
1386 return PTR_ERR(priv->rcdev);
1387
1388 /* Auto-detection using standard registers will not work, so
1389 * provide an indication of what kind of device we are for
1390 * b53_common to work with
1391 */
1392 pdata->chip_id = priv->type;
1393 dev->pdata = pdata;
1394
1395 priv->dev = dev;
1396 ds = dev->ds;
1397 ds->ops = &bcm_sf2_ops;
1398
1399 /* Advertise the 8 egress queues */
1400 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1401
1402 dev_set_drvdata(&pdev->dev, priv);
1403
1404 spin_lock_init(&priv->indir_lock);
1405 mutex_init(&priv->cfp.lock);
1406 INIT_LIST_HEAD(&priv->cfp.rules_list);
1407
1408 /* CFP rule #0 cannot be used for specific classifications, flag it as
1409 * permanently used
1410 */
1411 set_bit(0, priv->cfp.used);
1412 set_bit(0, priv->cfp.unique);
1413
1414 /* Balance of_node_put() done by of_find_node_by_name() */
1415 of_node_get(dn);
1416 ports = of_find_node_by_name(dn, "ports");
1417 if (ports) {
1418 bcm_sf2_identify_ports(priv, ports);
1419 of_node_put(ports);
1420 }
1421
1422 priv->irq0 = irq_of_parse_and_map(dn, 0);
1423 priv->irq1 = irq_of_parse_and_map(dn, 1);
1424
1425 base = &priv->core;
1426 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1427 *base = devm_platform_ioremap_resource(pdev, i);
1428 if (IS_ERR(*base)) {
1429 pr_err("unable to find register: %s\n", reg_names[i]);
1430 return PTR_ERR(*base);
1431 }
1432 base++;
1433 }
1434
1435 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1436 if (IS_ERR(priv->clk))
1437 return PTR_ERR(priv->clk);
1438
1439 clk_prepare_enable(priv->clk);
1440
1441 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1442 if (IS_ERR(priv->clk_mdiv)) {
1443 ret = PTR_ERR(priv->clk_mdiv);
1444 goto out_clk;
1445 }
1446
1447 clk_prepare_enable(priv->clk_mdiv);
1448
1449 ret = bcm_sf2_sw_rst(priv);
1450 if (ret) {
1451 pr_err("unable to software reset switch: %d\n", ret);
1452 goto out_clk_mdiv;
1453 }
1454
1455 bcm_sf2_crossbar_setup(priv);
1456
1457 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1458
1459 ret = bcm_sf2_mdio_register(ds);
1460 if (ret) {
1461 pr_err("failed to register MDIO bus\n");
1462 goto out_clk_mdiv;
1463 }
1464
1465 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1466
1467 ret = bcm_sf2_cfp_rst(priv);
1468 if (ret) {
1469 pr_err("failed to reset CFP\n");
1470 goto out_mdio;
1471 }
1472
1473 /* Disable all interrupts and request them */
1474 bcm_sf2_intr_disable(priv);
1475
1476 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1477 "switch_0", ds);
1478 if (ret < 0) {
1479 pr_err("failed to request switch_0 IRQ\n");
1480 goto out_mdio;
1481 }
1482
1483 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1484 "switch_1", ds);
1485 if (ret < 0) {
1486 pr_err("failed to request switch_1 IRQ\n");
1487 goto out_mdio;
1488 }
1489
1490 /* Reset the MIB counters */
1491 reg = core_readl(priv, CORE_GMNCFGCFG);
1492 reg |= RST_MIB_CNT;
1493 core_writel(priv, reg, CORE_GMNCFGCFG);
1494 reg &= ~RST_MIB_CNT;
1495 core_writel(priv, reg, CORE_GMNCFGCFG);
1496
1497 /* Get the maximum number of ports for this switch */
1498 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1499 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1500 priv->hw_params.num_ports = DSA_MAX_PORTS;
1501
1502 /* Assume a single GPHY setup if we can't read that property */
1503 if (of_property_read_u32(dn, "brcm,num-gphy",
1504 &priv->hw_params.num_gphy))
1505 priv->hw_params.num_gphy = 1;
1506
1507 rev = reg_readl(priv, REG_SWITCH_REVISION);
1508 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1509 SWITCH_TOP_REV_MASK;
1510 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1511
1512 rev = reg_readl(priv, REG_PHY_REVISION);
1513 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1514
1515 ret = b53_switch_register(dev);
1516 if (ret)
1517 goto out_mdio;
1518
1519 dev_info(&pdev->dev,
1520 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1521 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1522 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1523 priv->irq0, priv->irq1);
1524
1525 return 0;
1526
1527out_mdio:
1528 bcm_sf2_mdio_unregister(priv);
1529out_clk_mdiv:
1530 clk_disable_unprepare(priv->clk_mdiv);
1531out_clk:
1532 clk_disable_unprepare(priv->clk);
1533 return ret;
1534}
1535
1536static int bcm_sf2_sw_remove(struct platform_device *pdev)
1537{
1538 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1539
1540 if (!priv)
1541 return 0;
1542
1543 priv->wol_ports_mask = 0;
1544 /* Disable interrupts */
1545 bcm_sf2_intr_disable(priv);
1546 dsa_unregister_switch(priv->dev->ds);
1547 bcm_sf2_cfp_exit(priv->dev->ds);
1548 bcm_sf2_mdio_unregister(priv);
1549 clk_disable_unprepare(priv->clk_mdiv);
1550 clk_disable_unprepare(priv->clk);
1551 if (priv->type == BCM7278_DEVICE_ID)
1552 reset_control_assert(priv->rcdev);
1553
1554 return 0;
1555}
1556
1557static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1558{
1559 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1560
1561 if (!priv)
1562 return;
1563
1564 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1565 * successful MDIO bus scan to occur. If we did turn off the GPHY
1566 * before (e.g: port_disable), this will also power it back on.
1567 *
1568 * Do not rely on kexec_in_progress, just power the PHY on.
1569 */
1570 if (priv->hw_params.num_gphy == 1)
1571 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1572
1573 dsa_switch_shutdown(priv->dev->ds);
1574
1575 platform_set_drvdata(pdev, NULL);
1576}
1577
1578#ifdef CONFIG_PM_SLEEP
1579static int bcm_sf2_suspend(struct device *dev)
1580{
1581 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1582
1583 return dsa_switch_suspend(priv->dev->ds);
1584}
1585
1586static int bcm_sf2_resume(struct device *dev)
1587{
1588 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1589
1590 return dsa_switch_resume(priv->dev->ds);
1591}
1592#endif /* CONFIG_PM_SLEEP */
1593
1594static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1595 bcm_sf2_suspend, bcm_sf2_resume);
1596
1597
1598static struct platform_driver bcm_sf2_driver = {
1599 .probe = bcm_sf2_sw_probe,
1600 .remove = bcm_sf2_sw_remove,
1601 .shutdown = bcm_sf2_sw_shutdown,
1602 .driver = {
1603 .name = "brcm-sf2",
1604 .of_match_table = bcm_sf2_of_match,
1605 .pm = &bcm_sf2_pm_ops,
1606 },
1607};
1608module_platform_driver(bcm_sf2_driver);
1609
1610MODULE_AUTHOR("Broadcom Corporation");
1611MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1612MODULE_LICENSE("GPL");
1613MODULE_ALIAS("platform:brcm-sf2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/of_net.h>
21#include <linux/of_mdio.h>
22#include <net/dsa.h>
23#include <linux/ethtool.h>
24#include <linux/if_bridge.h>
25#include <linux/brcmphy.h>
26#include <linux/etherdevice.h>
27#include <linux/platform_data/b53.h>
28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
31#include "b53/b53_priv.h"
32#include "b53/b53_regs.h"
33
34static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35{
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
37 unsigned int i;
38 u32 reg, offset;
39
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
44
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
47
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
52
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
55 */
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
60
61 b53_brcm_hdr_setup(ds, port);
62
63 if (port == 8) {
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
66 else
67 offset = CORE_STS_OVERRIDE_IMP2;
68
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 core_writel(priv, reg, offset);
73
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
79 } else {
80 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
81 reg &= ~(RX_DIS | TX_DIS);
82 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
83 }
84}
85
86static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
87{
88 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
89 u32 reg;
90
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
92 if (enable) {
93 reg |= PHY_RESET;
94 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
96 udelay(21);
97 reg = reg_readl(priv, REG_SPHY_CNTRL);
98 reg &= ~PHY_RESET;
99 } else {
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
101 reg_writel(priv, reg, REG_SPHY_CNTRL);
102 mdelay(1);
103 reg |= CK25_DIS;
104 }
105 reg_writel(priv, reg, REG_SPHY_CNTRL);
106
107 /* Use PHY-driven LED signaling */
108 if (!enable) {
109 reg = reg_readl(priv, REG_LED_CNTRL(0));
110 reg |= SPDLNK_SRC_SEL;
111 reg_writel(priv, reg, REG_LED_CNTRL(0));
112 }
113}
114
115static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
116 int port)
117{
118 unsigned int off;
119
120 switch (port) {
121 case 7:
122 off = P7_IRQ_OFF;
123 break;
124 case 0:
125 /* Port 0 interrupts are located on the first bank */
126 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
127 return;
128 default:
129 off = P_IRQ_OFF(port);
130 break;
131 }
132
133 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
134}
135
136static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
137 int port)
138{
139 unsigned int off;
140
141 switch (port) {
142 case 7:
143 off = P7_IRQ_OFF;
144 break;
145 case 0:
146 /* Port 0 interrupts are located on the first bank */
147 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
148 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
149 return;
150 default:
151 off = P_IRQ_OFF(port);
152 break;
153 }
154
155 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
156 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
157}
158
159static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
160 struct phy_device *phy)
161{
162 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
163 unsigned int i;
164 u32 reg;
165
166 if (!dsa_is_user_port(ds, port))
167 return 0;
168
169 /* Clear the memory power down */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173
174 /* Enable learning */
175 reg = core_readl(priv, CORE_DIS_LEARN);
176 reg &= ~BIT(port);
177 core_writel(priv, reg, CORE_DIS_LEARN);
178
179 /* Enable Broadcom tags for that port if requested */
180 if (priv->brcm_tag_mask & BIT(port))
181 b53_brcm_hdr_setup(ds, port);
182
183 /* Configure Traffic Class to QoS mapping, allow each priority to map
184 * to a different queue number
185 */
186 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
187 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
188 reg |= i << (PRT_TO_QID_SHIFT * i);
189 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
190
191 /* Re-enable the GPHY and re-apply workarounds */
192 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
193 bcm_sf2_gphy_enable_set(ds, true);
194 if (phy) {
195 /* if phy_stop() has been called before, phy
196 * will be in halted state, and phy_start()
197 * will call resume.
198 *
199 * the resume path does not configure back
200 * autoneg settings, and since we hard reset
201 * the phy manually here, we need to reset the
202 * state machine also.
203 */
204 phy->state = PHY_READY;
205 phy_init_hw(phy);
206 }
207 }
208
209 /* Enable MoCA port interrupts to get notified */
210 if (port == priv->moca_port)
211 bcm_sf2_port_intr_enable(priv, port);
212
213 /* Set per-queue pause threshold to 32 */
214 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
215
216 /* Set ACB threshold to 24 */
217 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
218 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
219 SF2_NUM_EGRESS_QUEUES + i));
220 reg &= ~XOFF_THRESHOLD_MASK;
221 reg |= 24;
222 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
223 SF2_NUM_EGRESS_QUEUES + i));
224 }
225
226 return b53_enable_port(ds, port, phy);
227}
228
229static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
230{
231 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
232 u32 reg;
233
234 /* Disable learning while in WoL mode */
235 if (priv->wol_ports_mask & (1 << port)) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
237 reg |= BIT(port);
238 core_writel(priv, reg, CORE_DIS_LEARN);
239 return;
240 }
241
242 if (port == priv->moca_port)
243 bcm_sf2_port_intr_disable(priv, port);
244
245 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
246 bcm_sf2_gphy_enable_set(ds, false);
247
248 b53_disable_port(ds, port);
249
250 /* Power down the port memory */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg |= P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
254}
255
256
257static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
258 int regnum, u16 val)
259{
260 int ret = 0;
261 u32 reg;
262
263 reg = reg_readl(priv, REG_SWITCH_CNTRL);
264 reg |= MDIO_MASTER_SEL;
265 reg_writel(priv, reg, REG_SWITCH_CNTRL);
266
267 /* Page << 8 | offset */
268 reg = 0x70;
269 reg <<= 2;
270 core_writel(priv, addr, reg);
271
272 /* Page << 8 | offset */
273 reg = 0x80 << 8 | regnum << 1;
274 reg <<= 2;
275
276 if (op)
277 ret = core_readl(priv, reg);
278 else
279 core_writel(priv, val, reg);
280
281 reg = reg_readl(priv, REG_SWITCH_CNTRL);
282 reg &= ~MDIO_MASTER_SEL;
283 reg_writel(priv, reg, REG_SWITCH_CNTRL);
284
285 return ret & 0xffff;
286}
287
288static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
289{
290 struct bcm_sf2_priv *priv = bus->priv;
291
292 /* Intercept reads from Broadcom pseudo-PHY address, else, send
293 * them to our master MDIO bus controller
294 */
295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
296 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
297 else
298 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
299}
300
301static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
302 u16 val)
303{
304 struct bcm_sf2_priv *priv = bus->priv;
305
306 /* Intercept writes to the Broadcom pseudo-PHY address, else,
307 * send them to our master MDIO bus controller
308 */
309 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
310 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
311 else
312 return mdiobus_write_nested(priv->master_mii_bus, addr,
313 regnum, val);
314}
315
316static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
317{
318 struct dsa_switch *ds = dev_id;
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
320
321 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
322 ~priv->irq0_mask;
323 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
324
325 return IRQ_HANDLED;
326}
327
328static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
329{
330 struct dsa_switch *ds = dev_id;
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
332
333 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
334 ~priv->irq1_mask;
335 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
336
337 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
338 priv->port_sts[7].link = true;
339 dsa_port_phylink_mac_change(ds, 7, true);
340 }
341 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
342 priv->port_sts[7].link = false;
343 dsa_port_phylink_mac_change(ds, 7, false);
344 }
345
346 return IRQ_HANDLED;
347}
348
349static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
350{
351 unsigned int timeout = 1000;
352 u32 reg;
353
354 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
355 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
356 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
357
358 do {
359 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
360 if (!(reg & SOFTWARE_RESET))
361 break;
362
363 usleep_range(1000, 2000);
364 } while (timeout-- > 0);
365
366 if (timeout == 0)
367 return -ETIMEDOUT;
368
369 return 0;
370}
371
372static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
373{
374 intrl2_0_mask_set(priv, 0xffffffff);
375 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
376 intrl2_1_mask_set(priv, 0xffffffff);
377 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
378}
379
380static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
381 struct device_node *dn)
382{
383 struct device_node *port;
384 int mode;
385 unsigned int port_num;
386
387 priv->moca_port = -1;
388
389 for_each_available_child_of_node(dn, port) {
390 if (of_property_read_u32(port, "reg", &port_num))
391 continue;
392
393 /* Internal PHYs get assigned a specific 'phy-mode' property
394 * value: "internal" to help flag them before MDIO probing
395 * has completed, since they might be turned off at that
396 * time
397 */
398 mode = of_get_phy_mode(port);
399 if (mode < 0)
400 continue;
401
402 if (mode == PHY_INTERFACE_MODE_INTERNAL)
403 priv->int_phy_mask |= 1 << port_num;
404
405 if (mode == PHY_INTERFACE_MODE_MOCA)
406 priv->moca_port = port_num;
407
408 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
409 priv->brcm_tag_mask |= 1 << port_num;
410 }
411}
412
413static int bcm_sf2_mdio_register(struct dsa_switch *ds)
414{
415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
416 struct device_node *dn;
417 static int index;
418 int err;
419
420 /* Find our integrated MDIO bus node */
421 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
422 priv->master_mii_bus = of_mdio_find_bus(dn);
423 if (!priv->master_mii_bus)
424 return -EPROBE_DEFER;
425
426 get_device(&priv->master_mii_bus->dev);
427 priv->master_mii_dn = dn;
428
429 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
430 if (!priv->slave_mii_bus)
431 return -ENOMEM;
432
433 priv->slave_mii_bus->priv = priv;
434 priv->slave_mii_bus->name = "sf2 slave mii";
435 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
436 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
437 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
438 index++);
439 priv->slave_mii_bus->dev.of_node = dn;
440
441 /* Include the pseudo-PHY address to divert reads towards our
442 * workaround. This is only required for 7445D0, since 7445E0
443 * disconnects the internal switch pseudo-PHY such that we can use the
444 * regular SWITCH_MDIO master controller instead.
445 *
446 * Here we flag the pseudo PHY as needing special treatment and would
447 * otherwise make all other PHY read/writes go to the master MDIO bus
448 * controller that comes with this switch backed by the "mdio-unimac"
449 * driver.
450 */
451 if (of_machine_is_compatible("brcm,bcm7445d0"))
452 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
453 else
454 priv->indir_phy_mask = 0;
455
456 ds->phys_mii_mask = priv->indir_phy_mask;
457 ds->slave_mii_bus = priv->slave_mii_bus;
458 priv->slave_mii_bus->parent = ds->dev->parent;
459 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
460
461 err = of_mdiobus_register(priv->slave_mii_bus, dn);
462 if (err && dn)
463 of_node_put(dn);
464
465 return err;
466}
467
468static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
469{
470 mdiobus_unregister(priv->slave_mii_bus);
471 of_node_put(priv->master_mii_dn);
472}
473
474static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
475{
476 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
477
478 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
479 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
480 * the REG_PHY_REVISION register layout is.
481 */
482
483 return priv->hw_params.gphy_rev;
484}
485
486static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
487 unsigned long *supported,
488 struct phylink_link_state *state)
489{
490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
491 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
492
493 if (!phy_interface_mode_is_rgmii(state->interface) &&
494 state->interface != PHY_INTERFACE_MODE_MII &&
495 state->interface != PHY_INTERFACE_MODE_REVMII &&
496 state->interface != PHY_INTERFACE_MODE_GMII &&
497 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
498 state->interface != PHY_INTERFACE_MODE_MOCA) {
499 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
500 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
501 dev_err(ds->dev,
502 "Unsupported interface: %d for port %d\n",
503 state->interface, port);
504 return;
505 }
506
507 /* Allow all the expected bits */
508 phylink_set(mask, Autoneg);
509 phylink_set_port_modes(mask);
510 phylink_set(mask, Pause);
511 phylink_set(mask, Asym_Pause);
512
513 /* With the exclusion of MII and Reverse MII, we support Gigabit,
514 * including Half duplex
515 */
516 if (state->interface != PHY_INTERFACE_MODE_MII &&
517 state->interface != PHY_INTERFACE_MODE_REVMII) {
518 phylink_set(mask, 1000baseT_Full);
519 phylink_set(mask, 1000baseT_Half);
520 }
521
522 phylink_set(mask, 10baseT_Half);
523 phylink_set(mask, 10baseT_Full);
524 phylink_set(mask, 100baseT_Half);
525 phylink_set(mask, 100baseT_Full);
526
527 bitmap_and(supported, supported, mask,
528 __ETHTOOL_LINK_MODE_MASK_NBITS);
529 bitmap_and(state->advertising, state->advertising, mask,
530 __ETHTOOL_LINK_MODE_MASK_NBITS);
531}
532
533static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
534 unsigned int mode,
535 const struct phylink_link_state *state)
536{
537 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
538 u32 id_mode_dis = 0, port_mode;
539 u32 reg, offset;
540
541 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
542 return;
543
544 if (priv->type == BCM7445_DEVICE_ID)
545 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
546 else
547 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
548
549 switch (state->interface) {
550 case PHY_INTERFACE_MODE_RGMII:
551 id_mode_dis = 1;
552 /* fallthrough */
553 case PHY_INTERFACE_MODE_RGMII_TXID:
554 port_mode = EXT_GPHY;
555 break;
556 case PHY_INTERFACE_MODE_MII:
557 port_mode = EXT_EPHY;
558 break;
559 case PHY_INTERFACE_MODE_REVMII:
560 port_mode = EXT_REVMII;
561 break;
562 default:
563 /* all other PHYs: internal and MoCA */
564 goto force_link;
565 }
566
567 /* Clear id_mode_dis bit, and the existing port mode, let
568 * RGMII_MODE_EN bet set by mac_link_{up,down}
569 */
570 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
571 reg &= ~ID_MODE_DIS;
572 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
573 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
574
575 reg |= port_mode;
576 if (id_mode_dis)
577 reg |= ID_MODE_DIS;
578
579 if (state->pause & MLO_PAUSE_TXRX_MASK) {
580 if (state->pause & MLO_PAUSE_TX)
581 reg |= TX_PAUSE_EN;
582 reg |= RX_PAUSE_EN;
583 }
584
585 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
586
587force_link:
588 /* Force link settings detected from the PHY */
589 reg = SW_OVERRIDE;
590 switch (state->speed) {
591 case SPEED_1000:
592 reg |= SPDSTS_1000 << SPEED_SHIFT;
593 break;
594 case SPEED_100:
595 reg |= SPDSTS_100 << SPEED_SHIFT;
596 break;
597 }
598
599 if (state->link)
600 reg |= LINK_STS;
601 if (state->duplex == DUPLEX_FULL)
602 reg |= DUPLX_MODE;
603
604 core_writel(priv, reg, offset);
605}
606
607static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
608 phy_interface_t interface, bool link)
609{
610 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
611 u32 reg;
612
613 if (!phy_interface_mode_is_rgmii(interface) &&
614 interface != PHY_INTERFACE_MODE_MII &&
615 interface != PHY_INTERFACE_MODE_REVMII)
616 return;
617
618 /* If the link is down, just disable the interface to conserve power */
619 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
620 if (link)
621 reg |= RGMII_MODE_EN;
622 else
623 reg &= ~RGMII_MODE_EN;
624 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
625}
626
627static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
628 unsigned int mode,
629 phy_interface_t interface)
630{
631 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
632}
633
634static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
635 unsigned int mode,
636 phy_interface_t interface,
637 struct phy_device *phydev)
638{
639 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
640 struct ethtool_eee *p = &priv->dev->ports[port].eee;
641
642 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
643
644 if (mode == MLO_AN_PHY && phydev)
645 p->eee_enabled = b53_eee_init(ds, port, phydev);
646}
647
648static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
649 struct phylink_link_state *status)
650{
651 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
652
653 status->link = false;
654
655 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
656 * which means that we need to force the link at the port override
657 * level to get the data to flow. We do use what the interrupt handler
658 * did determine before.
659 *
660 * For the other ports, we just force the link status, since this is
661 * a fixed PHY device.
662 */
663 if (port == priv->moca_port) {
664 status->link = priv->port_sts[port].link;
665 /* For MoCA interfaces, also force a link down notification
666 * since some version of the user-space daemon (mocad) use
667 * cmd->autoneg to force the link, which messes up the PHY
668 * state machine and make it go in PHY_FORCING state instead.
669 */
670 if (!status->link)
671 netif_carrier_off(ds->ports[port].slave);
672 status->duplex = DUPLEX_FULL;
673 } else {
674 status->link = true;
675 }
676}
677
678static void bcm_sf2_enable_acb(struct dsa_switch *ds)
679{
680 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
681 u32 reg;
682
683 /* Enable ACB globally */
684 reg = acb_readl(priv, ACB_CONTROL);
685 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
686 acb_writel(priv, reg, ACB_CONTROL);
687 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
688 reg |= ACB_EN | ACB_ALGORITHM;
689 acb_writel(priv, reg, ACB_CONTROL);
690}
691
692static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
693{
694 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
695 unsigned int port;
696
697 bcm_sf2_intr_disable(priv);
698
699 /* Disable all ports physically present including the IMP
700 * port, the other ones have already been disabled during
701 * bcm_sf2_sw_setup
702 */
703 for (port = 0; port < ds->num_ports; port++) {
704 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
705 bcm_sf2_port_disable(ds, port);
706 }
707
708 return 0;
709}
710
711static int bcm_sf2_sw_resume(struct dsa_switch *ds)
712{
713 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
714 int ret;
715
716 ret = bcm_sf2_sw_rst(priv);
717 if (ret) {
718 pr_err("%s: failed to software reset switch\n", __func__);
719 return ret;
720 }
721
722 ret = bcm_sf2_cfp_resume(ds);
723 if (ret)
724 return ret;
725
726 if (priv->hw_params.num_gphy == 1)
727 bcm_sf2_gphy_enable_set(ds, true);
728
729 ds->ops->setup(ds);
730
731 return 0;
732}
733
734static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
735 struct ethtool_wolinfo *wol)
736{
737 struct net_device *p = ds->ports[port].cpu_dp->master;
738 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
739 struct ethtool_wolinfo pwol = { };
740
741 /* Get the parent device WoL settings */
742 if (p->ethtool_ops->get_wol)
743 p->ethtool_ops->get_wol(p, &pwol);
744
745 /* Advertise the parent device supported settings */
746 wol->supported = pwol.supported;
747 memset(&wol->sopass, 0, sizeof(wol->sopass));
748
749 if (pwol.wolopts & WAKE_MAGICSECURE)
750 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
751
752 if (priv->wol_ports_mask & (1 << port))
753 wol->wolopts = pwol.wolopts;
754 else
755 wol->wolopts = 0;
756}
757
758static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
759 struct ethtool_wolinfo *wol)
760{
761 struct net_device *p = ds->ports[port].cpu_dp->master;
762 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
763 s8 cpu_port = ds->ports[port].cpu_dp->index;
764 struct ethtool_wolinfo pwol = { };
765
766 if (p->ethtool_ops->get_wol)
767 p->ethtool_ops->get_wol(p, &pwol);
768 if (wol->wolopts & ~pwol.supported)
769 return -EINVAL;
770
771 if (wol->wolopts)
772 priv->wol_ports_mask |= (1 << port);
773 else
774 priv->wol_ports_mask &= ~(1 << port);
775
776 /* If we have at least one port enabled, make sure the CPU port
777 * is also enabled. If the CPU port is the last one enabled, we disable
778 * it since this configuration does not make sense.
779 */
780 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
781 priv->wol_ports_mask |= (1 << cpu_port);
782 else
783 priv->wol_ports_mask &= ~(1 << cpu_port);
784
785 return p->ethtool_ops->set_wol(p, wol);
786}
787
788static int bcm_sf2_sw_setup(struct dsa_switch *ds)
789{
790 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
791 unsigned int port;
792
793 /* Enable all valid ports and disable those unused */
794 for (port = 0; port < priv->hw_params.num_ports; port++) {
795 /* IMP port receives special treatment */
796 if (dsa_is_user_port(ds, port))
797 bcm_sf2_port_setup(ds, port, NULL);
798 else if (dsa_is_cpu_port(ds, port))
799 bcm_sf2_imp_setup(ds, port);
800 else
801 bcm_sf2_port_disable(ds, port);
802 }
803
804 b53_configure_vlan(ds);
805 bcm_sf2_enable_acb(ds);
806
807 return 0;
808}
809
810/* The SWITCH_CORE register space is managed by b53 but operates on a page +
811 * register basis so we need to translate that into an address that the
812 * bus-glue understands.
813 */
814#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
815
816static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
817 u8 *val)
818{
819 struct bcm_sf2_priv *priv = dev->priv;
820
821 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
822
823 return 0;
824}
825
826static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
827 u16 *val)
828{
829 struct bcm_sf2_priv *priv = dev->priv;
830
831 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
832
833 return 0;
834}
835
836static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
837 u32 *val)
838{
839 struct bcm_sf2_priv *priv = dev->priv;
840
841 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
842
843 return 0;
844}
845
846static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
847 u64 *val)
848{
849 struct bcm_sf2_priv *priv = dev->priv;
850
851 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
852
853 return 0;
854}
855
856static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
857 u8 value)
858{
859 struct bcm_sf2_priv *priv = dev->priv;
860
861 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
862
863 return 0;
864}
865
866static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
867 u16 value)
868{
869 struct bcm_sf2_priv *priv = dev->priv;
870
871 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
872
873 return 0;
874}
875
876static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
877 u32 value)
878{
879 struct bcm_sf2_priv *priv = dev->priv;
880
881 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
882
883 return 0;
884}
885
886static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
887 u64 value)
888{
889 struct bcm_sf2_priv *priv = dev->priv;
890
891 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
892
893 return 0;
894}
895
896static const struct b53_io_ops bcm_sf2_io_ops = {
897 .read8 = bcm_sf2_core_read8,
898 .read16 = bcm_sf2_core_read16,
899 .read32 = bcm_sf2_core_read32,
900 .read48 = bcm_sf2_core_read64,
901 .read64 = bcm_sf2_core_read64,
902 .write8 = bcm_sf2_core_write8,
903 .write16 = bcm_sf2_core_write16,
904 .write32 = bcm_sf2_core_write32,
905 .write48 = bcm_sf2_core_write64,
906 .write64 = bcm_sf2_core_write64,
907};
908
909static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
910 u32 stringset, uint8_t *data)
911{
912 int cnt = b53_get_sset_count(ds, port, stringset);
913
914 b53_get_strings(ds, port, stringset, data);
915 bcm_sf2_cfp_get_strings(ds, port, stringset,
916 data + cnt * ETH_GSTRING_LEN);
917}
918
919static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
920 uint64_t *data)
921{
922 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
923
924 b53_get_ethtool_stats(ds, port, data);
925 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
926}
927
928static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
929 int sset)
930{
931 int cnt = b53_get_sset_count(ds, port, sset);
932
933 if (cnt < 0)
934 return cnt;
935
936 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
937
938 return cnt;
939}
940
941static const struct dsa_switch_ops bcm_sf2_ops = {
942 .get_tag_protocol = b53_get_tag_protocol,
943 .setup = bcm_sf2_sw_setup,
944 .get_strings = bcm_sf2_sw_get_strings,
945 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
946 .get_sset_count = bcm_sf2_sw_get_sset_count,
947 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
948 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
949 .phylink_validate = bcm_sf2_sw_validate,
950 .phylink_mac_config = bcm_sf2_sw_mac_config,
951 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
952 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
953 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
954 .suspend = bcm_sf2_sw_suspend,
955 .resume = bcm_sf2_sw_resume,
956 .get_wol = bcm_sf2_sw_get_wol,
957 .set_wol = bcm_sf2_sw_set_wol,
958 .port_enable = bcm_sf2_port_setup,
959 .port_disable = bcm_sf2_port_disable,
960 .get_mac_eee = b53_get_mac_eee,
961 .set_mac_eee = b53_set_mac_eee,
962 .port_bridge_join = b53_br_join,
963 .port_bridge_leave = b53_br_leave,
964 .port_stp_state_set = b53_br_set_stp_state,
965 .port_fast_age = b53_br_fast_age,
966 .port_vlan_filtering = b53_vlan_filtering,
967 .port_vlan_prepare = b53_vlan_prepare,
968 .port_vlan_add = b53_vlan_add,
969 .port_vlan_del = b53_vlan_del,
970 .port_fdb_dump = b53_fdb_dump,
971 .port_fdb_add = b53_fdb_add,
972 .port_fdb_del = b53_fdb_del,
973 .get_rxnfc = bcm_sf2_get_rxnfc,
974 .set_rxnfc = bcm_sf2_set_rxnfc,
975 .port_mirror_add = b53_mirror_add,
976 .port_mirror_del = b53_mirror_del,
977};
978
979struct bcm_sf2_of_data {
980 u32 type;
981 const u16 *reg_offsets;
982 unsigned int core_reg_align;
983 unsigned int num_cfp_rules;
984};
985
986/* Register offsets for the SWITCH_REG_* block */
987static const u16 bcm_sf2_7445_reg_offsets[] = {
988 [REG_SWITCH_CNTRL] = 0x00,
989 [REG_SWITCH_STATUS] = 0x04,
990 [REG_DIR_DATA_WRITE] = 0x08,
991 [REG_DIR_DATA_READ] = 0x0C,
992 [REG_SWITCH_REVISION] = 0x18,
993 [REG_PHY_REVISION] = 0x1C,
994 [REG_SPHY_CNTRL] = 0x2C,
995 [REG_RGMII_0_CNTRL] = 0x34,
996 [REG_RGMII_1_CNTRL] = 0x40,
997 [REG_RGMII_2_CNTRL] = 0x4c,
998 [REG_LED_0_CNTRL] = 0x90,
999 [REG_LED_1_CNTRL] = 0x94,
1000 [REG_LED_2_CNTRL] = 0x98,
1001};
1002
1003static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1004 .type = BCM7445_DEVICE_ID,
1005 .core_reg_align = 0,
1006 .reg_offsets = bcm_sf2_7445_reg_offsets,
1007 .num_cfp_rules = 256,
1008};
1009
1010static const u16 bcm_sf2_7278_reg_offsets[] = {
1011 [REG_SWITCH_CNTRL] = 0x00,
1012 [REG_SWITCH_STATUS] = 0x04,
1013 [REG_DIR_DATA_WRITE] = 0x08,
1014 [REG_DIR_DATA_READ] = 0x0c,
1015 [REG_SWITCH_REVISION] = 0x10,
1016 [REG_PHY_REVISION] = 0x14,
1017 [REG_SPHY_CNTRL] = 0x24,
1018 [REG_RGMII_0_CNTRL] = 0xe0,
1019 [REG_RGMII_1_CNTRL] = 0xec,
1020 [REG_RGMII_2_CNTRL] = 0xf8,
1021 [REG_LED_0_CNTRL] = 0x40,
1022 [REG_LED_1_CNTRL] = 0x4c,
1023 [REG_LED_2_CNTRL] = 0x58,
1024};
1025
1026static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1027 .type = BCM7278_DEVICE_ID,
1028 .core_reg_align = 1,
1029 .reg_offsets = bcm_sf2_7278_reg_offsets,
1030 .num_cfp_rules = 128,
1031};
1032
1033static const struct of_device_id bcm_sf2_of_match[] = {
1034 { .compatible = "brcm,bcm7445-switch-v4.0",
1035 .data = &bcm_sf2_7445_data
1036 },
1037 { .compatible = "brcm,bcm7278-switch-v4.0",
1038 .data = &bcm_sf2_7278_data
1039 },
1040 { .compatible = "brcm,bcm7278-switch-v4.8",
1041 .data = &bcm_sf2_7278_data
1042 },
1043 { /* sentinel */ },
1044};
1045MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1046
1047static int bcm_sf2_sw_probe(struct platform_device *pdev)
1048{
1049 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1050 struct device_node *dn = pdev->dev.of_node;
1051 const struct of_device_id *of_id = NULL;
1052 const struct bcm_sf2_of_data *data;
1053 struct b53_platform_data *pdata;
1054 struct dsa_switch_ops *ops;
1055 struct bcm_sf2_priv *priv;
1056 struct b53_device *dev;
1057 struct dsa_switch *ds;
1058 void __iomem **base;
1059 unsigned int i;
1060 u32 reg, rev;
1061 int ret;
1062
1063 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1064 if (!priv)
1065 return -ENOMEM;
1066
1067 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1068 if (!ops)
1069 return -ENOMEM;
1070
1071 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1072 if (!dev)
1073 return -ENOMEM;
1074
1075 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1076 if (!pdata)
1077 return -ENOMEM;
1078
1079 of_id = of_match_node(bcm_sf2_of_match, dn);
1080 if (!of_id || !of_id->data)
1081 return -EINVAL;
1082
1083 data = of_id->data;
1084
1085 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1086 priv->type = data->type;
1087 priv->reg_offsets = data->reg_offsets;
1088 priv->core_reg_align = data->core_reg_align;
1089 priv->num_cfp_rules = data->num_cfp_rules;
1090
1091 /* Auto-detection using standard registers will not work, so
1092 * provide an indication of what kind of device we are for
1093 * b53_common to work with
1094 */
1095 pdata->chip_id = priv->type;
1096 dev->pdata = pdata;
1097
1098 priv->dev = dev;
1099 ds = dev->ds;
1100 ds->ops = &bcm_sf2_ops;
1101
1102 /* Advertise the 8 egress queues */
1103 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1104
1105 dev_set_drvdata(&pdev->dev, priv);
1106
1107 spin_lock_init(&priv->indir_lock);
1108 mutex_init(&priv->cfp.lock);
1109 INIT_LIST_HEAD(&priv->cfp.rules_list);
1110
1111 /* CFP rule #0 cannot be used for specific classifications, flag it as
1112 * permanently used
1113 */
1114 set_bit(0, priv->cfp.used);
1115 set_bit(0, priv->cfp.unique);
1116
1117 bcm_sf2_identify_ports(priv, dn->child);
1118
1119 priv->irq0 = irq_of_parse_and_map(dn, 0);
1120 priv->irq1 = irq_of_parse_and_map(dn, 1);
1121
1122 base = &priv->core;
1123 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1124 *base = devm_platform_ioremap_resource(pdev, i);
1125 if (IS_ERR(*base)) {
1126 pr_err("unable to find register: %s\n", reg_names[i]);
1127 return PTR_ERR(*base);
1128 }
1129 base++;
1130 }
1131
1132 ret = bcm_sf2_sw_rst(priv);
1133 if (ret) {
1134 pr_err("unable to software reset switch: %d\n", ret);
1135 return ret;
1136 }
1137
1138 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1139
1140 ret = bcm_sf2_mdio_register(ds);
1141 if (ret) {
1142 pr_err("failed to register MDIO bus\n");
1143 return ret;
1144 }
1145
1146 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1147
1148 ret = bcm_sf2_cfp_rst(priv);
1149 if (ret) {
1150 pr_err("failed to reset CFP\n");
1151 goto out_mdio;
1152 }
1153
1154 /* Disable all interrupts and request them */
1155 bcm_sf2_intr_disable(priv);
1156
1157 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1158 "switch_0", ds);
1159 if (ret < 0) {
1160 pr_err("failed to request switch_0 IRQ\n");
1161 goto out_mdio;
1162 }
1163
1164 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1165 "switch_1", ds);
1166 if (ret < 0) {
1167 pr_err("failed to request switch_1 IRQ\n");
1168 goto out_mdio;
1169 }
1170
1171 /* Reset the MIB counters */
1172 reg = core_readl(priv, CORE_GMNCFGCFG);
1173 reg |= RST_MIB_CNT;
1174 core_writel(priv, reg, CORE_GMNCFGCFG);
1175 reg &= ~RST_MIB_CNT;
1176 core_writel(priv, reg, CORE_GMNCFGCFG);
1177
1178 /* Get the maximum number of ports for this switch */
1179 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1180 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1181 priv->hw_params.num_ports = DSA_MAX_PORTS;
1182
1183 /* Assume a single GPHY setup if we can't read that property */
1184 if (of_property_read_u32(dn, "brcm,num-gphy",
1185 &priv->hw_params.num_gphy))
1186 priv->hw_params.num_gphy = 1;
1187
1188 rev = reg_readl(priv, REG_SWITCH_REVISION);
1189 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1190 SWITCH_TOP_REV_MASK;
1191 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1192
1193 rev = reg_readl(priv, REG_PHY_REVISION);
1194 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1195
1196 ret = b53_switch_register(dev);
1197 if (ret)
1198 goto out_mdio;
1199
1200 dev_info(&pdev->dev,
1201 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1202 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1203 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1204 priv->irq0, priv->irq1);
1205
1206 return 0;
1207
1208out_mdio:
1209 bcm_sf2_mdio_unregister(priv);
1210 return ret;
1211}
1212
1213static int bcm_sf2_sw_remove(struct platform_device *pdev)
1214{
1215 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1216
1217 priv->wol_ports_mask = 0;
1218 /* Disable interrupts */
1219 bcm_sf2_intr_disable(priv);
1220 dsa_unregister_switch(priv->dev->ds);
1221 bcm_sf2_cfp_exit(priv->dev->ds);
1222 bcm_sf2_mdio_unregister(priv);
1223
1224 return 0;
1225}
1226
1227static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1228{
1229 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1230
1231 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1232 * successful MDIO bus scan to occur. If we did turn off the GPHY
1233 * before (e.g: port_disable), this will also power it back on.
1234 *
1235 * Do not rely on kexec_in_progress, just power the PHY on.
1236 */
1237 if (priv->hw_params.num_gphy == 1)
1238 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1239}
1240
1241#ifdef CONFIG_PM_SLEEP
1242static int bcm_sf2_suspend(struct device *dev)
1243{
1244 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1245
1246 return dsa_switch_suspend(priv->dev->ds);
1247}
1248
1249static int bcm_sf2_resume(struct device *dev)
1250{
1251 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1252
1253 return dsa_switch_resume(priv->dev->ds);
1254}
1255#endif /* CONFIG_PM_SLEEP */
1256
1257static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1258 bcm_sf2_suspend, bcm_sf2_resume);
1259
1260
1261static struct platform_driver bcm_sf2_driver = {
1262 .probe = bcm_sf2_sw_probe,
1263 .remove = bcm_sf2_sw_remove,
1264 .shutdown = bcm_sf2_sw_shutdown,
1265 .driver = {
1266 .name = "brcm-sf2",
1267 .of_match_table = bcm_sf2_of_match,
1268 .pm = &bcm_sf2_pm_ops,
1269 },
1270};
1271module_platform_driver(bcm_sf2_driver);
1272
1273MODULE_AUTHOR("Broadcom Corporation");
1274MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1275MODULE_LICENSE("GPL");
1276MODULE_ALIAS("platform:brcm-sf2");