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1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * This driver adds support for perf events to use the Performance
5 * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
6 * to monitor that node.
7 *
8 * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
9 * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
10 * to 4K boundary. For example, the PMCG at 0xff88840000 is named
11 * smmuv3_pmcg_ff88840
12 *
13 * Filtering by stream id is done by specifying filtering parameters
14 * with the event. options are:
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
17 * filter_stream_id - pattern to filter against
18 *
19 * To match a partial StreamID where the X most-significant bits must match
20 * but the Y least-significant bits might differ, STREAMID is programmed
21 * with a value that contains:
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
24 * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
25 * contain a value to match from the corresponding bits of event StreamID.
26 *
27 * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
28 * filter_span=1,filter_stream_id=0x42/ -a netperf
29 * Applies filter pattern 0x42 to transaction events, which means events
30 * matching stream ids 0x42 and 0x43 are counted. Further filtering
31 * information is available in the SMMU documentation.
32 *
33 * SMMU events are not attributable to a CPU, so task mode and sampling
34 * are not supported.
35 */
36
37#include <linux/acpi.h>
38#include <linux/acpi_iort.h>
39#include <linux/bitfield.h>
40#include <linux/bitops.h>
41#include <linux/cpuhotplug.h>
42#include <linux/cpumask.h>
43#include <linux/device.h>
44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/irq.h>
47#include <linux/kernel.h>
48#include <linux/list.h>
49#include <linux/msi.h>
50#include <linux/of.h>
51#include <linux/perf_event.h>
52#include <linux/platform_device.h>
53#include <linux/smp.h>
54#include <linux/sysfs.h>
55#include <linux/types.h>
56
57#define SMMU_PMCG_EVCNTR0 0x0
58#define SMMU_PMCG_EVCNTR(n, stride) (SMMU_PMCG_EVCNTR0 + (n) * (stride))
59#define SMMU_PMCG_EVTYPER0 0x400
60#define SMMU_PMCG_EVTYPER(n) (SMMU_PMCG_EVTYPER0 + (n) * 4)
61#define SMMU_PMCG_SID_SPAN_SHIFT 29
62#define SMMU_PMCG_SMR0 0xA00
63#define SMMU_PMCG_SMR(n) (SMMU_PMCG_SMR0 + (n) * 4)
64#define SMMU_PMCG_CNTENSET0 0xC00
65#define SMMU_PMCG_CNTENCLR0 0xC20
66#define SMMU_PMCG_INTENSET0 0xC40
67#define SMMU_PMCG_INTENCLR0 0xC60
68#define SMMU_PMCG_OVSCLR0 0xC80
69#define SMMU_PMCG_OVSSET0 0xCC0
70#define SMMU_PMCG_CFGR 0xE00
71#define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23)
72#define SMMU_PMCG_CFGR_MSI BIT(21)
73#define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20)
74#define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8)
75#define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0)
76#define SMMU_PMCG_CR 0xE04
77#define SMMU_PMCG_CR_ENABLE BIT(0)
78#define SMMU_PMCG_IIDR 0xE08
79#define SMMU_PMCG_IIDR_PRODUCTID GENMASK(31, 20)
80#define SMMU_PMCG_IIDR_VARIANT GENMASK(19, 16)
81#define SMMU_PMCG_IIDR_REVISION GENMASK(15, 12)
82#define SMMU_PMCG_IIDR_IMPLEMENTER GENMASK(11, 0)
83#define SMMU_PMCG_CEID0 0xE20
84#define SMMU_PMCG_CEID1 0xE28
85#define SMMU_PMCG_IRQ_CTRL 0xE50
86#define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0)
87#define SMMU_PMCG_IRQ_CFG0 0xE58
88#define SMMU_PMCG_IRQ_CFG1 0xE60
89#define SMMU_PMCG_IRQ_CFG2 0xE64
90
91/* IMP-DEF ID registers */
92#define SMMU_PMCG_PIDR0 0xFE0
93#define SMMU_PMCG_PIDR0_PART_0 GENMASK(7, 0)
94#define SMMU_PMCG_PIDR1 0xFE4
95#define SMMU_PMCG_PIDR1_DES_0 GENMASK(7, 4)
96#define SMMU_PMCG_PIDR1_PART_1 GENMASK(3, 0)
97#define SMMU_PMCG_PIDR2 0xFE8
98#define SMMU_PMCG_PIDR2_REVISION GENMASK(7, 4)
99#define SMMU_PMCG_PIDR2_DES_1 GENMASK(2, 0)
100#define SMMU_PMCG_PIDR3 0xFEC
101#define SMMU_PMCG_PIDR3_REVAND GENMASK(7, 4)
102#define SMMU_PMCG_PIDR4 0xFD0
103#define SMMU_PMCG_PIDR4_DES_2 GENMASK(3, 0)
104
105/* MSI config fields */
106#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
107#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1
108
109#define SMMU_PMCG_DEFAULT_FILTER_SPAN 1
110#define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0)
111
112#define SMMU_PMCG_MAX_COUNTERS 64
113#define SMMU_PMCG_ARCH_MAX_EVENTS 128
114
115#define SMMU_PMCG_PA_SHIFT 12
116
117#define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
118
119static int cpuhp_state_num;
120
121struct smmu_pmu {
122 struct hlist_node node;
123 struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
124 DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
125 DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
126 unsigned int irq;
127 unsigned int on_cpu;
128 struct pmu pmu;
129 unsigned int num_counters;
130 struct device *dev;
131 void __iomem *reg_base;
132 void __iomem *reloc_base;
133 u64 counter_mask;
134 u32 options;
135 u32 iidr;
136 bool global_filter;
137};
138
139#define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
140
141#define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
142 static inline u32 get_##_name(struct perf_event *event) \
143 { \
144 return FIELD_GET(GENMASK_ULL(_end, _start), \
145 event->attr._config); \
146 } \
147
148SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
149SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
150SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
151SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
152
153static inline void smmu_pmu_enable(struct pmu *pmu)
154{
155 struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
156
157 writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
158 smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
159 writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
160}
161
162static inline void smmu_pmu_disable(struct pmu *pmu)
163{
164 struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
165
166 writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
167 writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
168}
169
170static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
171 u32 idx, u64 value)
172{
173 if (smmu_pmu->counter_mask & BIT(32))
174 writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
175 else
176 writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
177}
178
179static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
180{
181 u64 value;
182
183 if (smmu_pmu->counter_mask & BIT(32))
184 value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
185 else
186 value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
187
188 return value;
189}
190
191static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
192{
193 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
194}
195
196static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
197{
198 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
199}
200
201static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
202{
203 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
204}
205
206static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
207 u32 idx)
208{
209 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
210}
211
212static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
213 u32 val)
214{
215 writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
216}
217
218static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
219{
220 writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
221}
222
223static void smmu_pmu_event_update(struct perf_event *event)
224{
225 struct hw_perf_event *hwc = &event->hw;
226 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
227 u64 delta, prev, now;
228 u32 idx = hwc->idx;
229
230 do {
231 prev = local64_read(&hwc->prev_count);
232 now = smmu_pmu_counter_get_value(smmu_pmu, idx);
233 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
234
235 /* handle overflow. */
236 delta = now - prev;
237 delta &= smmu_pmu->counter_mask;
238
239 local64_add(delta, &event->count);
240}
241
242static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
243 struct hw_perf_event *hwc)
244{
245 u32 idx = hwc->idx;
246 u64 new;
247
248 if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
249 /*
250 * On platforms that require this quirk, if the counter starts
251 * at < half_counter value and wraps, the current logic of
252 * handling the overflow may not work. It is expected that,
253 * those platforms will have full 64 counter bits implemented
254 * so that such a possibility is remote(eg: HiSilicon HIP08).
255 */
256 new = smmu_pmu_counter_get_value(smmu_pmu, idx);
257 } else {
258 /*
259 * We limit the max period to half the max counter value
260 * of the counter size, so that even in the case of extreme
261 * interrupt latency the counter will (hopefully) not wrap
262 * past its initial value.
263 */
264 new = smmu_pmu->counter_mask >> 1;
265 smmu_pmu_counter_set_value(smmu_pmu, idx, new);
266 }
267
268 local64_set(&hwc->prev_count, new);
269}
270
271static void smmu_pmu_set_event_filter(struct perf_event *event,
272 int idx, u32 span, u32 sid)
273{
274 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
275 u32 evtyper;
276
277 evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
278 smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
279 smmu_pmu_set_smr(smmu_pmu, idx, sid);
280}
281
282static bool smmu_pmu_check_global_filter(struct perf_event *curr,
283 struct perf_event *new)
284{
285 if (get_filter_enable(new) != get_filter_enable(curr))
286 return false;
287
288 if (!get_filter_enable(new))
289 return true;
290
291 return get_filter_span(new) == get_filter_span(curr) &&
292 get_filter_stream_id(new) == get_filter_stream_id(curr);
293}
294
295static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
296 struct perf_event *event, int idx)
297{
298 u32 span, sid;
299 unsigned int cur_idx, num_ctrs = smmu_pmu->num_counters;
300 bool filter_en = !!get_filter_enable(event);
301
302 span = filter_en ? get_filter_span(event) :
303 SMMU_PMCG_DEFAULT_FILTER_SPAN;
304 sid = filter_en ? get_filter_stream_id(event) :
305 SMMU_PMCG_DEFAULT_FILTER_SID;
306
307 cur_idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
308 /*
309 * Per-counter filtering, or scheduling the first globally-filtered
310 * event into an empty PMU so idx == 0 and it works out equivalent.
311 */
312 if (!smmu_pmu->global_filter || cur_idx == num_ctrs) {
313 smmu_pmu_set_event_filter(event, idx, span, sid);
314 return 0;
315 }
316
317 /* Otherwise, must match whatever's currently scheduled */
318 if (smmu_pmu_check_global_filter(smmu_pmu->events[cur_idx], event)) {
319 smmu_pmu_set_evtyper(smmu_pmu, idx, get_event(event));
320 return 0;
321 }
322
323 return -EAGAIN;
324}
325
326static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
327 struct perf_event *event)
328{
329 int idx, err;
330 unsigned int num_ctrs = smmu_pmu->num_counters;
331
332 idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
333 if (idx == num_ctrs)
334 /* The counters are all in use. */
335 return -EAGAIN;
336
337 err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
338 if (err)
339 return err;
340
341 set_bit(idx, smmu_pmu->used_counters);
342
343 return idx;
344}
345
346static bool smmu_pmu_events_compatible(struct perf_event *curr,
347 struct perf_event *new)
348{
349 if (new->pmu != curr->pmu)
350 return false;
351
352 if (to_smmu_pmu(new->pmu)->global_filter &&
353 !smmu_pmu_check_global_filter(curr, new))
354 return false;
355
356 return true;
357}
358
359/*
360 * Implementation of abstract pmu functionality required by
361 * the core perf events code.
362 */
363
364static int smmu_pmu_event_init(struct perf_event *event)
365{
366 struct hw_perf_event *hwc = &event->hw;
367 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
368 struct device *dev = smmu_pmu->dev;
369 struct perf_event *sibling;
370 int group_num_events = 1;
371 u16 event_id;
372
373 if (event->attr.type != event->pmu->type)
374 return -ENOENT;
375
376 if (hwc->sample_period) {
377 dev_dbg(dev, "Sampling not supported\n");
378 return -EOPNOTSUPP;
379 }
380
381 if (event->cpu < 0) {
382 dev_dbg(dev, "Per-task mode not supported\n");
383 return -EOPNOTSUPP;
384 }
385
386 /* Verify specified event is supported on this PMU */
387 event_id = get_event(event);
388 if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
389 (!test_bit(event_id, smmu_pmu->supported_events))) {
390 dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
391 return -EINVAL;
392 }
393
394 /* Don't allow groups with mixed PMUs, except for s/w events */
395 if (!is_software_event(event->group_leader)) {
396 if (!smmu_pmu_events_compatible(event->group_leader, event))
397 return -EINVAL;
398
399 if (++group_num_events > smmu_pmu->num_counters)
400 return -EINVAL;
401 }
402
403 for_each_sibling_event(sibling, event->group_leader) {
404 if (is_software_event(sibling))
405 continue;
406
407 if (!smmu_pmu_events_compatible(sibling, event))
408 return -EINVAL;
409
410 if (++group_num_events > smmu_pmu->num_counters)
411 return -EINVAL;
412 }
413
414 hwc->idx = -1;
415
416 /*
417 * Ensure all events are on the same cpu so all events are in the
418 * same cpu context, to avoid races on pmu_enable etc.
419 */
420 event->cpu = smmu_pmu->on_cpu;
421
422 return 0;
423}
424
425static void smmu_pmu_event_start(struct perf_event *event, int flags)
426{
427 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
428 struct hw_perf_event *hwc = &event->hw;
429 int idx = hwc->idx;
430
431 hwc->state = 0;
432
433 smmu_pmu_set_period(smmu_pmu, hwc);
434
435 smmu_pmu_counter_enable(smmu_pmu, idx);
436}
437
438static void smmu_pmu_event_stop(struct perf_event *event, int flags)
439{
440 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
441 struct hw_perf_event *hwc = &event->hw;
442 int idx = hwc->idx;
443
444 if (hwc->state & PERF_HES_STOPPED)
445 return;
446
447 smmu_pmu_counter_disable(smmu_pmu, idx);
448 /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
449 smmu_pmu_event_update(event);
450 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
451}
452
453static int smmu_pmu_event_add(struct perf_event *event, int flags)
454{
455 struct hw_perf_event *hwc = &event->hw;
456 int idx;
457 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
458
459 idx = smmu_pmu_get_event_idx(smmu_pmu, event);
460 if (idx < 0)
461 return idx;
462
463 hwc->idx = idx;
464 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
465 smmu_pmu->events[idx] = event;
466 local64_set(&hwc->prev_count, 0);
467
468 smmu_pmu_interrupt_enable(smmu_pmu, idx);
469
470 if (flags & PERF_EF_START)
471 smmu_pmu_event_start(event, flags);
472
473 /* Propagate changes to the userspace mapping. */
474 perf_event_update_userpage(event);
475
476 return 0;
477}
478
479static void smmu_pmu_event_del(struct perf_event *event, int flags)
480{
481 struct hw_perf_event *hwc = &event->hw;
482 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
483 int idx = hwc->idx;
484
485 smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
486 smmu_pmu_interrupt_disable(smmu_pmu, idx);
487 smmu_pmu->events[idx] = NULL;
488 clear_bit(idx, smmu_pmu->used_counters);
489
490 perf_event_update_userpage(event);
491}
492
493static void smmu_pmu_event_read(struct perf_event *event)
494{
495 smmu_pmu_event_update(event);
496}
497
498/* cpumask */
499
500static ssize_t smmu_pmu_cpumask_show(struct device *dev,
501 struct device_attribute *attr,
502 char *buf)
503{
504 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
505
506 return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
507}
508
509static struct device_attribute smmu_pmu_cpumask_attr =
510 __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
511
512static struct attribute *smmu_pmu_cpumask_attrs[] = {
513 &smmu_pmu_cpumask_attr.attr,
514 NULL
515};
516
517static const struct attribute_group smmu_pmu_cpumask_group = {
518 .attrs = smmu_pmu_cpumask_attrs,
519};
520
521/* Events */
522
523static ssize_t smmu_pmu_event_show(struct device *dev,
524 struct device_attribute *attr, char *page)
525{
526 struct perf_pmu_events_attr *pmu_attr;
527
528 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
529
530 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
531}
532
533#define SMMU_EVENT_ATTR(name, config) \
534 PMU_EVENT_ATTR_ID(name, smmu_pmu_event_show, config)
535
536static struct attribute *smmu_pmu_events[] = {
537 SMMU_EVENT_ATTR(cycles, 0),
538 SMMU_EVENT_ATTR(transaction, 1),
539 SMMU_EVENT_ATTR(tlb_miss, 2),
540 SMMU_EVENT_ATTR(config_cache_miss, 3),
541 SMMU_EVENT_ATTR(trans_table_walk_access, 4),
542 SMMU_EVENT_ATTR(config_struct_access, 5),
543 SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6),
544 SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7),
545 NULL
546};
547
548static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
549 struct attribute *attr, int unused)
550{
551 struct device *dev = kobj_to_dev(kobj);
552 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
553 struct perf_pmu_events_attr *pmu_attr;
554
555 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
556
557 if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
558 return attr->mode;
559
560 return 0;
561}
562
563static const struct attribute_group smmu_pmu_events_group = {
564 .name = "events",
565 .attrs = smmu_pmu_events,
566 .is_visible = smmu_pmu_event_is_visible,
567};
568
569static ssize_t smmu_pmu_identifier_attr_show(struct device *dev,
570 struct device_attribute *attr,
571 char *page)
572{
573 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
574
575 return sysfs_emit(page, "0x%08x\n", smmu_pmu->iidr);
576}
577
578static umode_t smmu_pmu_identifier_attr_visible(struct kobject *kobj,
579 struct attribute *attr,
580 int n)
581{
582 struct device *dev = kobj_to_dev(kobj);
583 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
584
585 if (!smmu_pmu->iidr)
586 return 0;
587 return attr->mode;
588}
589
590static struct device_attribute smmu_pmu_identifier_attr =
591 __ATTR(identifier, 0444, smmu_pmu_identifier_attr_show, NULL);
592
593static struct attribute *smmu_pmu_identifier_attrs[] = {
594 &smmu_pmu_identifier_attr.attr,
595 NULL
596};
597
598static const struct attribute_group smmu_pmu_identifier_group = {
599 .attrs = smmu_pmu_identifier_attrs,
600 .is_visible = smmu_pmu_identifier_attr_visible,
601};
602
603/* Formats */
604PMU_FORMAT_ATTR(event, "config:0-15");
605PMU_FORMAT_ATTR(filter_stream_id, "config1:0-31");
606PMU_FORMAT_ATTR(filter_span, "config1:32");
607PMU_FORMAT_ATTR(filter_enable, "config1:33");
608
609static struct attribute *smmu_pmu_formats[] = {
610 &format_attr_event.attr,
611 &format_attr_filter_stream_id.attr,
612 &format_attr_filter_span.attr,
613 &format_attr_filter_enable.attr,
614 NULL
615};
616
617static const struct attribute_group smmu_pmu_format_group = {
618 .name = "format",
619 .attrs = smmu_pmu_formats,
620};
621
622static const struct attribute_group *smmu_pmu_attr_grps[] = {
623 &smmu_pmu_cpumask_group,
624 &smmu_pmu_events_group,
625 &smmu_pmu_format_group,
626 &smmu_pmu_identifier_group,
627 NULL
628};
629
630/*
631 * Generic device handlers
632 */
633
634static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
635{
636 struct smmu_pmu *smmu_pmu;
637 unsigned int target;
638
639 smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
640 if (cpu != smmu_pmu->on_cpu)
641 return 0;
642
643 target = cpumask_any_but(cpu_online_mask, cpu);
644 if (target >= nr_cpu_ids)
645 return 0;
646
647 perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
648 smmu_pmu->on_cpu = target;
649 WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(target)));
650
651 return 0;
652}
653
654static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
655{
656 struct smmu_pmu *smmu_pmu = data;
657 DECLARE_BITMAP(ovs, BITS_PER_TYPE(u64));
658 u64 ovsr;
659 unsigned int idx;
660
661 ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
662 if (!ovsr)
663 return IRQ_NONE;
664
665 writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
666
667 bitmap_from_u64(ovs, ovsr);
668 for_each_set_bit(idx, ovs, smmu_pmu->num_counters) {
669 struct perf_event *event = smmu_pmu->events[idx];
670 struct hw_perf_event *hwc;
671
672 if (WARN_ON_ONCE(!event))
673 continue;
674
675 smmu_pmu_event_update(event);
676 hwc = &event->hw;
677
678 smmu_pmu_set_period(smmu_pmu, hwc);
679 }
680
681 return IRQ_HANDLED;
682}
683
684static void smmu_pmu_free_msis(void *data)
685{
686 struct device *dev = data;
687
688 platform_msi_domain_free_irqs(dev);
689}
690
691static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
692{
693 phys_addr_t doorbell;
694 struct device *dev = msi_desc_to_dev(desc);
695 struct smmu_pmu *pmu = dev_get_drvdata(dev);
696
697 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
698 doorbell &= MSI_CFG0_ADDR_MASK;
699
700 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
701 writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
702 writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
703 pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
704}
705
706static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
707{
708 struct device *dev = pmu->dev;
709 int ret;
710
711 /* Clear MSI address reg */
712 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
713
714 /* MSI supported or not */
715 if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
716 return;
717
718 ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
719 if (ret) {
720 dev_warn(dev, "failed to allocate MSIs\n");
721 return;
722 }
723
724 pmu->irq = msi_get_virq(dev, 0);
725
726 /* Add callback to free MSIs on teardown */
727 devm_add_action(dev, smmu_pmu_free_msis, dev);
728}
729
730static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
731{
732 unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
733 int irq, ret = -ENXIO;
734
735 smmu_pmu_setup_msi(pmu);
736
737 irq = pmu->irq;
738 if (irq)
739 ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
740 flags, "smmuv3-pmu", pmu);
741 return ret;
742}
743
744static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
745{
746 u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
747
748 smmu_pmu_disable(&smmu_pmu->pmu);
749
750 /* Disable counter and interrupt */
751 writeq_relaxed(counter_present_mask,
752 smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
753 writeq_relaxed(counter_present_mask,
754 smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
755 writeq_relaxed(counter_present_mask,
756 smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
757}
758
759static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
760{
761 u32 model;
762
763 model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
764
765 switch (model) {
766 case IORT_SMMU_V3_PMCG_HISI_HIP08:
767 /* HiSilicon Erratum 162001800 */
768 smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
769 break;
770 }
771
772 dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
773}
774
775static bool smmu_pmu_coresight_id_regs(struct smmu_pmu *smmu_pmu)
776{
777 return of_device_is_compatible(smmu_pmu->dev->of_node,
778 "arm,mmu-600-pmcg");
779}
780
781static void smmu_pmu_get_iidr(struct smmu_pmu *smmu_pmu)
782{
783 u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
784
785 if (!iidr && smmu_pmu_coresight_id_regs(smmu_pmu)) {
786 u32 pidr0 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR0);
787 u32 pidr1 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR1);
788 u32 pidr2 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR2);
789 u32 pidr3 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR3);
790 u32 pidr4 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR4);
791
792 u32 productid = FIELD_GET(SMMU_PMCG_PIDR0_PART_0, pidr0) |
793 (FIELD_GET(SMMU_PMCG_PIDR1_PART_1, pidr1) << 8);
794 u32 variant = FIELD_GET(SMMU_PMCG_PIDR2_REVISION, pidr2);
795 u32 revision = FIELD_GET(SMMU_PMCG_PIDR3_REVAND, pidr3);
796 u32 implementer =
797 FIELD_GET(SMMU_PMCG_PIDR1_DES_0, pidr1) |
798 (FIELD_GET(SMMU_PMCG_PIDR2_DES_1, pidr2) << 4) |
799 (FIELD_GET(SMMU_PMCG_PIDR4_DES_2, pidr4) << 8);
800
801 iidr = FIELD_PREP(SMMU_PMCG_IIDR_PRODUCTID, productid) |
802 FIELD_PREP(SMMU_PMCG_IIDR_VARIANT, variant) |
803 FIELD_PREP(SMMU_PMCG_IIDR_REVISION, revision) |
804 FIELD_PREP(SMMU_PMCG_IIDR_IMPLEMENTER, implementer);
805 }
806
807 smmu_pmu->iidr = iidr;
808}
809
810static int smmu_pmu_probe(struct platform_device *pdev)
811{
812 struct smmu_pmu *smmu_pmu;
813 struct resource *res_0;
814 u32 cfgr, reg_size;
815 u64 ceid_64[2];
816 int irq, err;
817 char *name;
818 struct device *dev = &pdev->dev;
819
820 smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
821 if (!smmu_pmu)
822 return -ENOMEM;
823
824 smmu_pmu->dev = dev;
825 platform_set_drvdata(pdev, smmu_pmu);
826
827 smmu_pmu->pmu = (struct pmu) {
828 .module = THIS_MODULE,
829 .task_ctx_nr = perf_invalid_context,
830 .pmu_enable = smmu_pmu_enable,
831 .pmu_disable = smmu_pmu_disable,
832 .event_init = smmu_pmu_event_init,
833 .add = smmu_pmu_event_add,
834 .del = smmu_pmu_event_del,
835 .start = smmu_pmu_event_start,
836 .stop = smmu_pmu_event_stop,
837 .read = smmu_pmu_event_read,
838 .attr_groups = smmu_pmu_attr_grps,
839 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
840 };
841
842 smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
843 if (IS_ERR(smmu_pmu->reg_base))
844 return PTR_ERR(smmu_pmu->reg_base);
845
846 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
847
848 /* Determine if page 1 is present */
849 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
850 smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
851 if (IS_ERR(smmu_pmu->reloc_base))
852 return PTR_ERR(smmu_pmu->reloc_base);
853 } else {
854 smmu_pmu->reloc_base = smmu_pmu->reg_base;
855 }
856
857 irq = platform_get_irq_optional(pdev, 0);
858 if (irq > 0)
859 smmu_pmu->irq = irq;
860
861 ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
862 ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
863 bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
864 SMMU_PMCG_ARCH_MAX_EVENTS);
865
866 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
867
868 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
869
870 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
871 smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
872
873 smmu_pmu_reset(smmu_pmu);
874
875 err = smmu_pmu_setup_irq(smmu_pmu);
876 if (err) {
877 dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
878 return err;
879 }
880
881 smmu_pmu_get_iidr(smmu_pmu);
882
883 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
884 (res_0->start) >> SMMU_PMCG_PA_SHIFT);
885 if (!name) {
886 dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
887 return -EINVAL;
888 }
889
890 if (!dev->of_node)
891 smmu_pmu_get_acpi_options(smmu_pmu);
892
893 /* Pick one CPU to be the preferred one to use */
894 smmu_pmu->on_cpu = raw_smp_processor_id();
895 WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu)));
896
897 err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
898 &smmu_pmu->node);
899 if (err) {
900 dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
901 err, &res_0->start);
902 return err;
903 }
904
905 err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
906 if (err) {
907 dev_err(dev, "Error %d registering PMU @%pa\n",
908 err, &res_0->start);
909 goto out_unregister;
910 }
911
912 dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
913 &res_0->start, smmu_pmu->num_counters,
914 smmu_pmu->global_filter ? "Global(Counter0)" :
915 "Individual");
916
917 return 0;
918
919out_unregister:
920 cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
921 return err;
922}
923
924static int smmu_pmu_remove(struct platform_device *pdev)
925{
926 struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
927
928 perf_pmu_unregister(&smmu_pmu->pmu);
929 cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
930
931 return 0;
932}
933
934static void smmu_pmu_shutdown(struct platform_device *pdev)
935{
936 struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
937
938 smmu_pmu_disable(&smmu_pmu->pmu);
939}
940
941#ifdef CONFIG_OF
942static const struct of_device_id smmu_pmu_of_match[] = {
943 { .compatible = "arm,smmu-v3-pmcg" },
944 {}
945};
946MODULE_DEVICE_TABLE(of, smmu_pmu_of_match);
947#endif
948
949static struct platform_driver smmu_pmu_driver = {
950 .driver = {
951 .name = "arm-smmu-v3-pmcg",
952 .of_match_table = of_match_ptr(smmu_pmu_of_match),
953 .suppress_bind_attrs = true,
954 },
955 .probe = smmu_pmu_probe,
956 .remove = smmu_pmu_remove,
957 .shutdown = smmu_pmu_shutdown,
958};
959
960static int __init arm_smmu_pmu_init(void)
961{
962 int ret;
963
964 cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
965 "perf/arm/pmcg:online",
966 NULL,
967 smmu_pmu_offline_cpu);
968 if (cpuhp_state_num < 0)
969 return cpuhp_state_num;
970
971 ret = platform_driver_register(&smmu_pmu_driver);
972 if (ret)
973 cpuhp_remove_multi_state(cpuhp_state_num);
974
975 return ret;
976}
977module_init(arm_smmu_pmu_init);
978
979static void __exit arm_smmu_pmu_exit(void)
980{
981 platform_driver_unregister(&smmu_pmu_driver);
982 cpuhp_remove_multi_state(cpuhp_state_num);
983}
984
985module_exit(arm_smmu_pmu_exit);
986
987MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
988MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
989MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
990MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * This driver adds support for perf events to use the Performance
5 * Monitor Counter Groups (PMCG) associated with an SMMUv3 node
6 * to monitor that node.
7 *
8 * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
9 * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
10 * to 4K boundary. For example, the PMCG at 0xff88840000 is named
11 * smmuv3_pmcg_ff88840
12 *
13 * Filtering by stream id is done by specifying filtering parameters
14 * with the event. options are:
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
17 * filter_stream_id - pattern to filter against
18 *
19 * To match a partial StreamID where the X most-significant bits must match
20 * but the Y least-significant bits might differ, STREAMID is programmed
21 * with a value that contains:
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
24 * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
25 * contain a value to match from the corresponding bits of event StreamID.
26 *
27 * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
28 * filter_span=1,filter_stream_id=0x42/ -a netperf
29 * Applies filter pattern 0x42 to transaction events, which means events
30 * matching stream ids 0x42 and 0x43 are counted. Further filtering
31 * information is available in the SMMU documentation.
32 *
33 * SMMU events are not attributable to a CPU, so task mode and sampling
34 * are not supported.
35 */
36
37#include <linux/acpi.h>
38#include <linux/acpi_iort.h>
39#include <linux/bitfield.h>
40#include <linux/bitops.h>
41#include <linux/cpuhotplug.h>
42#include <linux/cpumask.h>
43#include <linux/device.h>
44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/irq.h>
47#include <linux/kernel.h>
48#include <linux/list.h>
49#include <linux/msi.h>
50#include <linux/perf_event.h>
51#include <linux/platform_device.h>
52#include <linux/smp.h>
53#include <linux/sysfs.h>
54#include <linux/types.h>
55
56#define SMMU_PMCG_EVCNTR0 0x0
57#define SMMU_PMCG_EVCNTR(n, stride) (SMMU_PMCG_EVCNTR0 + (n) * (stride))
58#define SMMU_PMCG_EVTYPER0 0x400
59#define SMMU_PMCG_EVTYPER(n) (SMMU_PMCG_EVTYPER0 + (n) * 4)
60#define SMMU_PMCG_SID_SPAN_SHIFT 29
61#define SMMU_PMCG_SMR0 0xA00
62#define SMMU_PMCG_SMR(n) (SMMU_PMCG_SMR0 + (n) * 4)
63#define SMMU_PMCG_CNTENSET0 0xC00
64#define SMMU_PMCG_CNTENCLR0 0xC20
65#define SMMU_PMCG_INTENSET0 0xC40
66#define SMMU_PMCG_INTENCLR0 0xC60
67#define SMMU_PMCG_OVSCLR0 0xC80
68#define SMMU_PMCG_OVSSET0 0xCC0
69#define SMMU_PMCG_CFGR 0xE00
70#define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23)
71#define SMMU_PMCG_CFGR_MSI BIT(21)
72#define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20)
73#define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8)
74#define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0)
75#define SMMU_PMCG_CR 0xE04
76#define SMMU_PMCG_CR_ENABLE BIT(0)
77#define SMMU_PMCG_IIDR 0xE08
78#define SMMU_PMCG_CEID0 0xE20
79#define SMMU_PMCG_CEID1 0xE28
80#define SMMU_PMCG_IRQ_CTRL 0xE50
81#define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0)
82#define SMMU_PMCG_IRQ_CFG0 0xE58
83#define SMMU_PMCG_IRQ_CFG1 0xE60
84#define SMMU_PMCG_IRQ_CFG2 0xE64
85
86/* MSI config fields */
87#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
88#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1
89
90#define SMMU_PMCG_DEFAULT_FILTER_SPAN 1
91#define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0)
92
93#define SMMU_PMCG_MAX_COUNTERS 64
94#define SMMU_PMCG_ARCH_MAX_EVENTS 128
95
96#define SMMU_PMCG_PA_SHIFT 12
97
98#define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
99
100static int cpuhp_state_num;
101
102struct smmu_pmu {
103 struct hlist_node node;
104 struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
105 DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
106 DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
107 unsigned int irq;
108 unsigned int on_cpu;
109 struct pmu pmu;
110 unsigned int num_counters;
111 struct device *dev;
112 void __iomem *reg_base;
113 void __iomem *reloc_base;
114 u64 counter_mask;
115 u32 options;
116 u32 iidr;
117 bool global_filter;
118};
119
120#define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
121
122#define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
123 static inline u32 get_##_name(struct perf_event *event) \
124 { \
125 return FIELD_GET(GENMASK_ULL(_end, _start), \
126 event->attr._config); \
127 } \
128
129SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
130SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
131SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
132SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
133
134static inline void smmu_pmu_enable(struct pmu *pmu)
135{
136 struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
137
138 writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
139 smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
140 writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
141}
142
143static inline void smmu_pmu_disable(struct pmu *pmu)
144{
145 struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
146
147 writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
148 writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
149}
150
151static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
152 u32 idx, u64 value)
153{
154 if (smmu_pmu->counter_mask & BIT(32))
155 writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
156 else
157 writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
158}
159
160static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
161{
162 u64 value;
163
164 if (smmu_pmu->counter_mask & BIT(32))
165 value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
166 else
167 value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
168
169 return value;
170}
171
172static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
173{
174 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
175}
176
177static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
178{
179 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
180}
181
182static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
183{
184 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
185}
186
187static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
188 u32 idx)
189{
190 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
191}
192
193static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
194 u32 val)
195{
196 writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
197}
198
199static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
200{
201 writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
202}
203
204static void smmu_pmu_event_update(struct perf_event *event)
205{
206 struct hw_perf_event *hwc = &event->hw;
207 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
208 u64 delta, prev, now;
209 u32 idx = hwc->idx;
210
211 do {
212 prev = local64_read(&hwc->prev_count);
213 now = smmu_pmu_counter_get_value(smmu_pmu, idx);
214 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
215
216 /* handle overflow. */
217 delta = now - prev;
218 delta &= smmu_pmu->counter_mask;
219
220 local64_add(delta, &event->count);
221}
222
223static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
224 struct hw_perf_event *hwc)
225{
226 u32 idx = hwc->idx;
227 u64 new;
228
229 if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
230 /*
231 * On platforms that require this quirk, if the counter starts
232 * at < half_counter value and wraps, the current logic of
233 * handling the overflow may not work. It is expected that,
234 * those platforms will have full 64 counter bits implemented
235 * so that such a possibility is remote(eg: HiSilicon HIP08).
236 */
237 new = smmu_pmu_counter_get_value(smmu_pmu, idx);
238 } else {
239 /*
240 * We limit the max period to half the max counter value
241 * of the counter size, so that even in the case of extreme
242 * interrupt latency the counter will (hopefully) not wrap
243 * past its initial value.
244 */
245 new = smmu_pmu->counter_mask >> 1;
246 smmu_pmu_counter_set_value(smmu_pmu, idx, new);
247 }
248
249 local64_set(&hwc->prev_count, new);
250}
251
252static void smmu_pmu_set_event_filter(struct perf_event *event,
253 int idx, u32 span, u32 sid)
254{
255 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
256 u32 evtyper;
257
258 evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
259 smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
260 smmu_pmu_set_smr(smmu_pmu, idx, sid);
261}
262
263static bool smmu_pmu_check_global_filter(struct perf_event *curr,
264 struct perf_event *new)
265{
266 if (get_filter_enable(new) != get_filter_enable(curr))
267 return false;
268
269 if (!get_filter_enable(new))
270 return true;
271
272 return get_filter_span(new) == get_filter_span(curr) &&
273 get_filter_stream_id(new) == get_filter_stream_id(curr);
274}
275
276static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
277 struct perf_event *event, int idx)
278{
279 u32 span, sid;
280 unsigned int cur_idx, num_ctrs = smmu_pmu->num_counters;
281 bool filter_en = !!get_filter_enable(event);
282
283 span = filter_en ? get_filter_span(event) :
284 SMMU_PMCG_DEFAULT_FILTER_SPAN;
285 sid = filter_en ? get_filter_stream_id(event) :
286 SMMU_PMCG_DEFAULT_FILTER_SID;
287
288 cur_idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
289 /*
290 * Per-counter filtering, or scheduling the first globally-filtered
291 * event into an empty PMU so idx == 0 and it works out equivalent.
292 */
293 if (!smmu_pmu->global_filter || cur_idx == num_ctrs) {
294 smmu_pmu_set_event_filter(event, idx, span, sid);
295 return 0;
296 }
297
298 /* Otherwise, must match whatever's currently scheduled */
299 if (smmu_pmu_check_global_filter(smmu_pmu->events[cur_idx], event)) {
300 smmu_pmu_set_evtyper(smmu_pmu, idx, get_event(event));
301 return 0;
302 }
303
304 return -EAGAIN;
305}
306
307static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
308 struct perf_event *event)
309{
310 int idx, err;
311 unsigned int num_ctrs = smmu_pmu->num_counters;
312
313 idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
314 if (idx == num_ctrs)
315 /* The counters are all in use. */
316 return -EAGAIN;
317
318 err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
319 if (err)
320 return err;
321
322 set_bit(idx, smmu_pmu->used_counters);
323
324 return idx;
325}
326
327static bool smmu_pmu_events_compatible(struct perf_event *curr,
328 struct perf_event *new)
329{
330 if (new->pmu != curr->pmu)
331 return false;
332
333 if (to_smmu_pmu(new->pmu)->global_filter &&
334 !smmu_pmu_check_global_filter(curr, new))
335 return false;
336
337 return true;
338}
339
340/*
341 * Implementation of abstract pmu functionality required by
342 * the core perf events code.
343 */
344
345static int smmu_pmu_event_init(struct perf_event *event)
346{
347 struct hw_perf_event *hwc = &event->hw;
348 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
349 struct device *dev = smmu_pmu->dev;
350 struct perf_event *sibling;
351 int group_num_events = 1;
352 u16 event_id;
353
354 if (event->attr.type != event->pmu->type)
355 return -ENOENT;
356
357 if (hwc->sample_period) {
358 dev_dbg(dev, "Sampling not supported\n");
359 return -EOPNOTSUPP;
360 }
361
362 if (event->cpu < 0) {
363 dev_dbg(dev, "Per-task mode not supported\n");
364 return -EOPNOTSUPP;
365 }
366
367 /* Verify specified event is supported on this PMU */
368 event_id = get_event(event);
369 if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
370 (!test_bit(event_id, smmu_pmu->supported_events))) {
371 dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
372 return -EINVAL;
373 }
374
375 /* Don't allow groups with mixed PMUs, except for s/w events */
376 if (!is_software_event(event->group_leader)) {
377 if (!smmu_pmu_events_compatible(event->group_leader, event))
378 return -EINVAL;
379
380 if (++group_num_events > smmu_pmu->num_counters)
381 return -EINVAL;
382 }
383
384 for_each_sibling_event(sibling, event->group_leader) {
385 if (is_software_event(sibling))
386 continue;
387
388 if (!smmu_pmu_events_compatible(sibling, event))
389 return -EINVAL;
390
391 if (++group_num_events > smmu_pmu->num_counters)
392 return -EINVAL;
393 }
394
395 hwc->idx = -1;
396
397 /*
398 * Ensure all events are on the same cpu so all events are in the
399 * same cpu context, to avoid races on pmu_enable etc.
400 */
401 event->cpu = smmu_pmu->on_cpu;
402
403 return 0;
404}
405
406static void smmu_pmu_event_start(struct perf_event *event, int flags)
407{
408 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
409 struct hw_perf_event *hwc = &event->hw;
410 int idx = hwc->idx;
411
412 hwc->state = 0;
413
414 smmu_pmu_set_period(smmu_pmu, hwc);
415
416 smmu_pmu_counter_enable(smmu_pmu, idx);
417}
418
419static void smmu_pmu_event_stop(struct perf_event *event, int flags)
420{
421 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
422 struct hw_perf_event *hwc = &event->hw;
423 int idx = hwc->idx;
424
425 if (hwc->state & PERF_HES_STOPPED)
426 return;
427
428 smmu_pmu_counter_disable(smmu_pmu, idx);
429 /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
430 smmu_pmu_event_update(event);
431 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
432}
433
434static int smmu_pmu_event_add(struct perf_event *event, int flags)
435{
436 struct hw_perf_event *hwc = &event->hw;
437 int idx;
438 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
439
440 idx = smmu_pmu_get_event_idx(smmu_pmu, event);
441 if (idx < 0)
442 return idx;
443
444 hwc->idx = idx;
445 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
446 smmu_pmu->events[idx] = event;
447 local64_set(&hwc->prev_count, 0);
448
449 smmu_pmu_interrupt_enable(smmu_pmu, idx);
450
451 if (flags & PERF_EF_START)
452 smmu_pmu_event_start(event, flags);
453
454 /* Propagate changes to the userspace mapping. */
455 perf_event_update_userpage(event);
456
457 return 0;
458}
459
460static void smmu_pmu_event_del(struct perf_event *event, int flags)
461{
462 struct hw_perf_event *hwc = &event->hw;
463 struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
464 int idx = hwc->idx;
465
466 smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
467 smmu_pmu_interrupt_disable(smmu_pmu, idx);
468 smmu_pmu->events[idx] = NULL;
469 clear_bit(idx, smmu_pmu->used_counters);
470
471 perf_event_update_userpage(event);
472}
473
474static void smmu_pmu_event_read(struct perf_event *event)
475{
476 smmu_pmu_event_update(event);
477}
478
479/* cpumask */
480
481static ssize_t smmu_pmu_cpumask_show(struct device *dev,
482 struct device_attribute *attr,
483 char *buf)
484{
485 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
486
487 return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
488}
489
490static struct device_attribute smmu_pmu_cpumask_attr =
491 __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
492
493static struct attribute *smmu_pmu_cpumask_attrs[] = {
494 &smmu_pmu_cpumask_attr.attr,
495 NULL
496};
497
498static const struct attribute_group smmu_pmu_cpumask_group = {
499 .attrs = smmu_pmu_cpumask_attrs,
500};
501
502/* Events */
503
504static ssize_t smmu_pmu_event_show(struct device *dev,
505 struct device_attribute *attr, char *page)
506{
507 struct perf_pmu_events_attr *pmu_attr;
508
509 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
510
511 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
512}
513
514#define SMMU_EVENT_ATTR(name, config) \
515 PMU_EVENT_ATTR_ID(name, smmu_pmu_event_show, config)
516
517static struct attribute *smmu_pmu_events[] = {
518 SMMU_EVENT_ATTR(cycles, 0),
519 SMMU_EVENT_ATTR(transaction, 1),
520 SMMU_EVENT_ATTR(tlb_miss, 2),
521 SMMU_EVENT_ATTR(config_cache_miss, 3),
522 SMMU_EVENT_ATTR(trans_table_walk_access, 4),
523 SMMU_EVENT_ATTR(config_struct_access, 5),
524 SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6),
525 SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7),
526 NULL
527};
528
529static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
530 struct attribute *attr, int unused)
531{
532 struct device *dev = kobj_to_dev(kobj);
533 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
534 struct perf_pmu_events_attr *pmu_attr;
535
536 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
537
538 if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
539 return attr->mode;
540
541 return 0;
542}
543
544static const struct attribute_group smmu_pmu_events_group = {
545 .name = "events",
546 .attrs = smmu_pmu_events,
547 .is_visible = smmu_pmu_event_is_visible,
548};
549
550static ssize_t smmu_pmu_identifier_attr_show(struct device *dev,
551 struct device_attribute *attr,
552 char *page)
553{
554 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
555
556 return sysfs_emit(page, "0x%08x\n", smmu_pmu->iidr);
557}
558
559static umode_t smmu_pmu_identifier_attr_visible(struct kobject *kobj,
560 struct attribute *attr,
561 int n)
562{
563 struct device *dev = kobj_to_dev(kobj);
564 struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
565
566 if (!smmu_pmu->iidr)
567 return 0;
568 return attr->mode;
569}
570
571static struct device_attribute smmu_pmu_identifier_attr =
572 __ATTR(identifier, 0444, smmu_pmu_identifier_attr_show, NULL);
573
574static struct attribute *smmu_pmu_identifier_attrs[] = {
575 &smmu_pmu_identifier_attr.attr,
576 NULL
577};
578
579static const struct attribute_group smmu_pmu_identifier_group = {
580 .attrs = smmu_pmu_identifier_attrs,
581 .is_visible = smmu_pmu_identifier_attr_visible,
582};
583
584/* Formats */
585PMU_FORMAT_ATTR(event, "config:0-15");
586PMU_FORMAT_ATTR(filter_stream_id, "config1:0-31");
587PMU_FORMAT_ATTR(filter_span, "config1:32");
588PMU_FORMAT_ATTR(filter_enable, "config1:33");
589
590static struct attribute *smmu_pmu_formats[] = {
591 &format_attr_event.attr,
592 &format_attr_filter_stream_id.attr,
593 &format_attr_filter_span.attr,
594 &format_attr_filter_enable.attr,
595 NULL
596};
597
598static const struct attribute_group smmu_pmu_format_group = {
599 .name = "format",
600 .attrs = smmu_pmu_formats,
601};
602
603static const struct attribute_group *smmu_pmu_attr_grps[] = {
604 &smmu_pmu_cpumask_group,
605 &smmu_pmu_events_group,
606 &smmu_pmu_format_group,
607 &smmu_pmu_identifier_group,
608 NULL
609};
610
611/*
612 * Generic device handlers
613 */
614
615static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
616{
617 struct smmu_pmu *smmu_pmu;
618 unsigned int target;
619
620 smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
621 if (cpu != smmu_pmu->on_cpu)
622 return 0;
623
624 target = cpumask_any_but(cpu_online_mask, cpu);
625 if (target >= nr_cpu_ids)
626 return 0;
627
628 perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
629 smmu_pmu->on_cpu = target;
630 WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(target)));
631
632 return 0;
633}
634
635static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
636{
637 struct smmu_pmu *smmu_pmu = data;
638 u64 ovsr;
639 unsigned int idx;
640
641 ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
642 if (!ovsr)
643 return IRQ_NONE;
644
645 writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
646
647 for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
648 struct perf_event *event = smmu_pmu->events[idx];
649 struct hw_perf_event *hwc;
650
651 if (WARN_ON_ONCE(!event))
652 continue;
653
654 smmu_pmu_event_update(event);
655 hwc = &event->hw;
656
657 smmu_pmu_set_period(smmu_pmu, hwc);
658 }
659
660 return IRQ_HANDLED;
661}
662
663static void smmu_pmu_free_msis(void *data)
664{
665 struct device *dev = data;
666
667 platform_msi_domain_free_irqs(dev);
668}
669
670static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
671{
672 phys_addr_t doorbell;
673 struct device *dev = msi_desc_to_dev(desc);
674 struct smmu_pmu *pmu = dev_get_drvdata(dev);
675
676 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
677 doorbell &= MSI_CFG0_ADDR_MASK;
678
679 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
680 writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
681 writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
682 pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
683}
684
685static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
686{
687 struct msi_desc *desc;
688 struct device *dev = pmu->dev;
689 int ret;
690
691 /* Clear MSI address reg */
692 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
693
694 /* MSI supported or not */
695 if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
696 return;
697
698 ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
699 if (ret) {
700 dev_warn(dev, "failed to allocate MSIs\n");
701 return;
702 }
703
704 desc = first_msi_entry(dev);
705 if (desc)
706 pmu->irq = desc->irq;
707
708 /* Add callback to free MSIs on teardown */
709 devm_add_action(dev, smmu_pmu_free_msis, dev);
710}
711
712static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
713{
714 unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
715 int irq, ret = -ENXIO;
716
717 smmu_pmu_setup_msi(pmu);
718
719 irq = pmu->irq;
720 if (irq)
721 ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
722 flags, "smmuv3-pmu", pmu);
723 return ret;
724}
725
726static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
727{
728 u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
729
730 smmu_pmu_disable(&smmu_pmu->pmu);
731
732 /* Disable counter and interrupt */
733 writeq_relaxed(counter_present_mask,
734 smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
735 writeq_relaxed(counter_present_mask,
736 smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
737 writeq_relaxed(counter_present_mask,
738 smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
739}
740
741static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
742{
743 u32 model;
744
745 model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
746
747 switch (model) {
748 case IORT_SMMU_V3_PMCG_HISI_HIP08:
749 /* HiSilicon Erratum 162001800 */
750 smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
751 break;
752 }
753
754 dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
755}
756
757static int smmu_pmu_probe(struct platform_device *pdev)
758{
759 struct smmu_pmu *smmu_pmu;
760 struct resource *res_0;
761 u32 cfgr, reg_size;
762 u64 ceid_64[2];
763 int irq, err;
764 char *name;
765 struct device *dev = &pdev->dev;
766
767 smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
768 if (!smmu_pmu)
769 return -ENOMEM;
770
771 smmu_pmu->dev = dev;
772 platform_set_drvdata(pdev, smmu_pmu);
773
774 smmu_pmu->pmu = (struct pmu) {
775 .module = THIS_MODULE,
776 .task_ctx_nr = perf_invalid_context,
777 .pmu_enable = smmu_pmu_enable,
778 .pmu_disable = smmu_pmu_disable,
779 .event_init = smmu_pmu_event_init,
780 .add = smmu_pmu_event_add,
781 .del = smmu_pmu_event_del,
782 .start = smmu_pmu_event_start,
783 .stop = smmu_pmu_event_stop,
784 .read = smmu_pmu_event_read,
785 .attr_groups = smmu_pmu_attr_grps,
786 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
787 };
788
789 smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
790 if (IS_ERR(smmu_pmu->reg_base))
791 return PTR_ERR(smmu_pmu->reg_base);
792
793 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
794
795 /* Determine if page 1 is present */
796 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
797 smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
798 if (IS_ERR(smmu_pmu->reloc_base))
799 return PTR_ERR(smmu_pmu->reloc_base);
800 } else {
801 smmu_pmu->reloc_base = smmu_pmu->reg_base;
802 }
803
804 irq = platform_get_irq_optional(pdev, 0);
805 if (irq > 0)
806 smmu_pmu->irq = irq;
807
808 ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
809 ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
810 bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
811 SMMU_PMCG_ARCH_MAX_EVENTS);
812
813 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
814
815 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
816
817 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
818 smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
819
820 smmu_pmu_reset(smmu_pmu);
821
822 err = smmu_pmu_setup_irq(smmu_pmu);
823 if (err) {
824 dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
825 return err;
826 }
827
828 smmu_pmu->iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
829
830 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
831 (res_0->start) >> SMMU_PMCG_PA_SHIFT);
832 if (!name) {
833 dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
834 return -EINVAL;
835 }
836
837 smmu_pmu_get_acpi_options(smmu_pmu);
838
839 /* Pick one CPU to be the preferred one to use */
840 smmu_pmu->on_cpu = raw_smp_processor_id();
841 WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu)));
842
843 err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
844 &smmu_pmu->node);
845 if (err) {
846 dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
847 err, &res_0->start);
848 return err;
849 }
850
851 err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
852 if (err) {
853 dev_err(dev, "Error %d registering PMU @%pa\n",
854 err, &res_0->start);
855 goto out_unregister;
856 }
857
858 dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
859 &res_0->start, smmu_pmu->num_counters,
860 smmu_pmu->global_filter ? "Global(Counter0)" :
861 "Individual");
862
863 return 0;
864
865out_unregister:
866 cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
867 return err;
868}
869
870static int smmu_pmu_remove(struct platform_device *pdev)
871{
872 struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
873
874 perf_pmu_unregister(&smmu_pmu->pmu);
875 cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
876
877 return 0;
878}
879
880static void smmu_pmu_shutdown(struct platform_device *pdev)
881{
882 struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
883
884 smmu_pmu_disable(&smmu_pmu->pmu);
885}
886
887static struct platform_driver smmu_pmu_driver = {
888 .driver = {
889 .name = "arm-smmu-v3-pmcg",
890 .suppress_bind_attrs = true,
891 },
892 .probe = smmu_pmu_probe,
893 .remove = smmu_pmu_remove,
894 .shutdown = smmu_pmu_shutdown,
895};
896
897static int __init arm_smmu_pmu_init(void)
898{
899 cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
900 "perf/arm/pmcg:online",
901 NULL,
902 smmu_pmu_offline_cpu);
903 if (cpuhp_state_num < 0)
904 return cpuhp_state_num;
905
906 return platform_driver_register(&smmu_pmu_driver);
907}
908module_init(arm_smmu_pmu_init);
909
910static void __exit arm_smmu_pmu_exit(void)
911{
912 platform_driver_unregister(&smmu_pmu_driver);
913 cpuhp_remove_multi_state(cpuhp_state_num);
914}
915
916module_exit(arm_smmu_pmu_exit);
917
918MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
919MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
920MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
921MODULE_LICENSE("GPL v2");