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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/acpi.h>
12#include <linux/bitmap.h>
13#include <linux/gpio/consumer.h>
14#include <linux/gpio/driver.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/pca953x.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/seq_file.h>
24#include <linux/slab.h>
25
26#include <asm/unaligned.h>
27
28#define PCA953X_INPUT 0x00
29#define PCA953X_OUTPUT 0x01
30#define PCA953X_INVERT 0x02
31#define PCA953X_DIRECTION 0x03
32
33#define REG_ADDR_MASK GENMASK(5, 0)
34#define REG_ADDR_EXT BIT(6)
35#define REG_ADDR_AI BIT(7)
36
37#define PCA957X_IN 0x00
38#define PCA957X_INVRT 0x01
39#define PCA957X_BKEN 0x02
40#define PCA957X_PUPD 0x03
41#define PCA957X_CFG 0x04
42#define PCA957X_OUT 0x05
43#define PCA957X_MSK 0x06
44#define PCA957X_INTS 0x07
45
46#define PCAL953X_OUT_STRENGTH 0x20
47#define PCAL953X_IN_LATCH 0x22
48#define PCAL953X_PULL_EN 0x23
49#define PCAL953X_PULL_SEL 0x24
50#define PCAL953X_INT_MASK 0x25
51#define PCAL953X_INT_STAT 0x26
52#define PCAL953X_OUT_CONF 0x27
53
54#define PCAL6524_INT_EDGE 0x28
55#define PCAL6524_INT_CLR 0x2a
56#define PCAL6524_IN_STATUS 0x2b
57#define PCAL6524_OUT_INDCONF 0x2c
58#define PCAL6524_DEBOUNCE 0x2d
59
60#define PCA_GPIO_MASK GENMASK(7, 0)
61
62#define PCAL_GPIO_MASK GENMASK(4, 0)
63#define PCAL_PINCTRL_MASK GENMASK(6, 5)
64
65#define PCA_INT BIT(8)
66#define PCA_PCAL BIT(9)
67#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
68#define PCA953X_TYPE BIT(12)
69#define PCA957X_TYPE BIT(13)
70#define PCAL653X_TYPE BIT(14)
71#define PCA_TYPE_MASK GENMASK(15, 12)
72
73#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
74
75static const struct i2c_device_id pca953x_id[] = {
76 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
77 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
78 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
79 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
80 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
81 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
82 { "pca9536", 4 | PCA953X_TYPE, },
83 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
84 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
85 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
86 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
87 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
88 { "pca9556", 8 | PCA953X_TYPE, },
89 { "pca9557", 8 | PCA953X_TYPE, },
90 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
91 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
92 { "pca9698", 40 | PCA953X_TYPE, },
93
94 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
95 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
96 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
97 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
98 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
99 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
100 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
101
102 { "max7310", 8 | PCA953X_TYPE, },
103 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
104 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
105 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
106 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
107 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
108 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
109 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
110 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
111 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
112 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
113 { "xra1202", 8 | PCA953X_TYPE },
114 { }
115};
116MODULE_DEVICE_TABLE(i2c, pca953x_id);
117
118#ifdef CONFIG_GPIO_PCA953X_IRQ
119
120#include <linux/dmi.h>
121
122static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
123
124static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
125 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
126 { }
127};
128
129static int pca953x_acpi_get_irq(struct device *dev)
130{
131 int ret;
132
133 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
134 if (ret)
135 dev_warn(dev, "can't add GPIO ACPI mapping\n");
136
137 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
138 if (ret < 0)
139 return ret;
140
141 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
142 return ret;
143}
144
145static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
146 {
147 /*
148 * On Intel Galileo Gen 2 board the IRQ pin of one of
149 * the I²C GPIO expanders, which has GpioInt() resource,
150 * is provided as an absolute number instead of being
151 * relative. Since first controller (gpio-sch.c) and
152 * second (gpio-dwapb.c) are at the fixed bases, we may
153 * safely refer to the number in the global space to get
154 * an IRQ out of it.
155 */
156 .matches = {
157 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
158 },
159 },
160 {}
161};
162#endif
163
164static const struct acpi_device_id pca953x_acpi_ids[] = {
165 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
166 { }
167};
168MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
169
170#define MAX_BANK 5
171#define BANK_SZ 8
172#define MAX_LINE (MAX_BANK * BANK_SZ)
173
174#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
175
176struct pca953x_reg_config {
177 int direction;
178 int output;
179 int input;
180 int invert;
181};
182
183static const struct pca953x_reg_config pca953x_regs = {
184 .direction = PCA953X_DIRECTION,
185 .output = PCA953X_OUTPUT,
186 .input = PCA953X_INPUT,
187 .invert = PCA953X_INVERT,
188};
189
190static const struct pca953x_reg_config pca957x_regs = {
191 .direction = PCA957X_CFG,
192 .output = PCA957X_OUT,
193 .input = PCA957X_IN,
194 .invert = PCA957X_INVRT,
195};
196
197struct pca953x_chip {
198 unsigned gpio_start;
199 struct mutex i2c_lock;
200 struct regmap *regmap;
201
202#ifdef CONFIG_GPIO_PCA953X_IRQ
203 struct mutex irq_lock;
204 DECLARE_BITMAP(irq_mask, MAX_LINE);
205 DECLARE_BITMAP(irq_stat, MAX_LINE);
206 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
207 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
208#endif
209 atomic_t wakeup_path;
210
211 struct i2c_client *client;
212 struct gpio_chip gpio_chip;
213 const char *const *names;
214 unsigned long driver_data;
215 struct regulator *regulator;
216
217 const struct pca953x_reg_config *regs;
218
219 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
220 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
221 u32 checkbank);
222};
223
224static int pca953x_bank_shift(struct pca953x_chip *chip)
225{
226 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
227}
228
229#define PCA953x_BANK_INPUT BIT(0)
230#define PCA953x_BANK_OUTPUT BIT(1)
231#define PCA953x_BANK_POLARITY BIT(2)
232#define PCA953x_BANK_CONFIG BIT(3)
233
234#define PCA957x_BANK_INPUT BIT(0)
235#define PCA957x_BANK_POLARITY BIT(1)
236#define PCA957x_BANK_BUSHOLD BIT(2)
237#define PCA957x_BANK_CONFIG BIT(4)
238#define PCA957x_BANK_OUTPUT BIT(5)
239
240#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
241#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
242#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
243#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
244#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
245
246/*
247 * We care about the following registers:
248 * - Standard set, below 0x40, each port can be replicated up to 8 times
249 * - PCA953x standard
250 * Input port 0x00 + 0 * bank_size R
251 * Output port 0x00 + 1 * bank_size RW
252 * Polarity Inversion port 0x00 + 2 * bank_size RW
253 * Configuration port 0x00 + 3 * bank_size RW
254 * - PCA957x with mixed up registers
255 * Input port 0x00 + 0 * bank_size R
256 * Polarity Inversion port 0x00 + 1 * bank_size RW
257 * Bus hold port 0x00 + 2 * bank_size RW
258 * Configuration port 0x00 + 4 * bank_size RW
259 * Output port 0x00 + 5 * bank_size RW
260 *
261 * - Extended set, above 0x40, often chip specific.
262 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
263 * Input latch register 0x40 + 2 * bank_size RW
264 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
265 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
266 * Interrupt mask register 0x40 + 5 * bank_size RW
267 * Interrupt status register 0x40 + 6 * bank_size R
268 *
269 * - Registers with bit 0x80 set, the AI bit
270 * The bit is cleared and the registers fall into one of the
271 * categories above.
272 */
273
274static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
275 u32 checkbank)
276{
277 int bank_shift = pca953x_bank_shift(chip);
278 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
279 int offset = reg & (BIT(bank_shift) - 1);
280
281 /* Special PCAL extended register check. */
282 if (reg & REG_ADDR_EXT) {
283 if (!(chip->driver_data & PCA_PCAL))
284 return false;
285 bank += 8;
286 }
287
288 /* Register is not in the matching bank. */
289 if (!(BIT(bank) & checkbank))
290 return false;
291
292 /* Register is not within allowed range of bank. */
293 if (offset >= NBANK(chip))
294 return false;
295
296 return true;
297}
298
299/*
300 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
301 * same register layout as the PCAL6524, the spacing of the registers has been
302 * fundamentally altered by compacting them and thus does not obey the same
303 * rules, including being able to use bit shifting to determine bank. These
304 * chips hence need special handling here.
305 */
306static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
307 u32 checkbank)
308{
309 int bank;
310 int offset;
311
312 if (reg >= 0x30) {
313 /*
314 * Reserved block between 14h and 2Fh does not align on
315 * expected bank boundaries like other devices.
316 */
317 int temp = reg - 0x30;
318
319 bank = temp / NBANK(chip);
320 offset = temp - (bank * NBANK(chip));
321 bank += 8;
322 } else if (reg >= 0x54) {
323 /*
324 * Handle lack of reserved registers after output port
325 * configuration register to form a bank.
326 */
327 int temp = reg - 0x54;
328
329 bank = temp / NBANK(chip);
330 offset = temp - (bank * NBANK(chip));
331 bank += 16;
332 } else {
333 bank = reg / NBANK(chip);
334 offset = reg - (bank * NBANK(chip));
335 }
336
337 /* Register is not in the matching bank. */
338 if (!(BIT(bank) & checkbank))
339 return false;
340
341 /* Register is not within allowed range of bank. */
342 if (offset >= NBANK(chip))
343 return false;
344
345 return true;
346}
347
348static bool pca953x_readable_register(struct device *dev, unsigned int reg)
349{
350 struct pca953x_chip *chip = dev_get_drvdata(dev);
351 u32 bank;
352
353 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
354 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
355 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
356 PCA957x_BANK_BUSHOLD;
357 } else {
358 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
359 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
360 }
361
362 if (chip->driver_data & PCA_PCAL) {
363 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
364 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
365 PCAL9xxx_BANK_IRQ_STAT;
366 }
367
368 return chip->check_reg(chip, reg, bank);
369}
370
371static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
372{
373 struct pca953x_chip *chip = dev_get_drvdata(dev);
374 u32 bank;
375
376 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
377 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
378 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
379 } else {
380 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
381 PCA953x_BANK_CONFIG;
382 }
383
384 if (chip->driver_data & PCA_PCAL)
385 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
386 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
387
388 return chip->check_reg(chip, reg, bank);
389}
390
391static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
392{
393 struct pca953x_chip *chip = dev_get_drvdata(dev);
394 u32 bank;
395
396 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
397 bank = PCA957x_BANK_INPUT;
398 else
399 bank = PCA953x_BANK_INPUT;
400
401 if (chip->driver_data & PCA_PCAL)
402 bank |= PCAL9xxx_BANK_IRQ_STAT;
403
404 return chip->check_reg(chip, reg, bank);
405}
406
407static const struct regmap_config pca953x_i2c_regmap = {
408 .reg_bits = 8,
409 .val_bits = 8,
410
411 .use_single_read = true,
412 .use_single_write = true,
413
414 .readable_reg = pca953x_readable_register,
415 .writeable_reg = pca953x_writeable_register,
416 .volatile_reg = pca953x_volatile_register,
417
418 .disable_locking = true,
419 .cache_type = REGCACHE_RBTREE,
420 .max_register = 0x7f,
421};
422
423static const struct regmap_config pca953x_ai_i2c_regmap = {
424 .reg_bits = 8,
425 .val_bits = 8,
426
427 .read_flag_mask = REG_ADDR_AI,
428 .write_flag_mask = REG_ADDR_AI,
429
430 .readable_reg = pca953x_readable_register,
431 .writeable_reg = pca953x_writeable_register,
432 .volatile_reg = pca953x_volatile_register,
433
434 .disable_locking = true,
435 .cache_type = REGCACHE_RBTREE,
436 .max_register = 0x7f,
437};
438
439static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
440{
441 int bank_shift = pca953x_bank_shift(chip);
442 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
443 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
444 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
445
446 return regaddr;
447}
448
449/*
450 * The PCAL6534 and compatible chips have altered bank alignment that doesn't
451 * fit within the bit shifting scheme used for other devices.
452 */
453static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
454{
455 int addr;
456 int pinctrl;
457
458 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
459
460 switch (reg) {
461 case PCAL953X_OUT_STRENGTH:
462 case PCAL953X_IN_LATCH:
463 case PCAL953X_PULL_EN:
464 case PCAL953X_PULL_SEL:
465 case PCAL953X_INT_MASK:
466 case PCAL953X_INT_STAT:
467 case PCAL953X_OUT_CONF:
468 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
469 break;
470 case PCAL6524_INT_EDGE:
471 case PCAL6524_INT_CLR:
472 case PCAL6524_IN_STATUS:
473 case PCAL6524_OUT_INDCONF:
474 case PCAL6524_DEBOUNCE:
475 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
476 break;
477 default:
478 pinctrl = 0;
479 break;
480 }
481
482 return pinctrl + addr + (off / BANK_SZ);
483}
484
485static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
486{
487 u8 regaddr = chip->recalc_addr(chip, reg, 0);
488 u8 value[MAX_BANK];
489 int i, ret;
490
491 for (i = 0; i < NBANK(chip); i++)
492 value[i] = bitmap_get_value8(val, i * BANK_SZ);
493
494 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
495 if (ret < 0) {
496 dev_err(&chip->client->dev, "failed writing register\n");
497 return ret;
498 }
499
500 return 0;
501}
502
503static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
504{
505 u8 regaddr = chip->recalc_addr(chip, reg, 0);
506 u8 value[MAX_BANK];
507 int i, ret;
508
509 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
510 if (ret < 0) {
511 dev_err(&chip->client->dev, "failed reading register\n");
512 return ret;
513 }
514
515 for (i = 0; i < NBANK(chip); i++)
516 bitmap_set_value8(val, value[i], i * BANK_SZ);
517
518 return 0;
519}
520
521static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
522{
523 struct pca953x_chip *chip = gpiochip_get_data(gc);
524 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
525 u8 bit = BIT(off % BANK_SZ);
526 int ret;
527
528 mutex_lock(&chip->i2c_lock);
529 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
530 mutex_unlock(&chip->i2c_lock);
531 return ret;
532}
533
534static int pca953x_gpio_direction_output(struct gpio_chip *gc,
535 unsigned off, int val)
536{
537 struct pca953x_chip *chip = gpiochip_get_data(gc);
538 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
539 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
540 u8 bit = BIT(off % BANK_SZ);
541 int ret;
542
543 mutex_lock(&chip->i2c_lock);
544 /* set output level */
545 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
546 if (ret)
547 goto exit;
548
549 /* then direction */
550 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
551exit:
552 mutex_unlock(&chip->i2c_lock);
553 return ret;
554}
555
556static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
557{
558 struct pca953x_chip *chip = gpiochip_get_data(gc);
559 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
560 u8 bit = BIT(off % BANK_SZ);
561 u32 reg_val;
562 int ret;
563
564 mutex_lock(&chip->i2c_lock);
565 ret = regmap_read(chip->regmap, inreg, ®_val);
566 mutex_unlock(&chip->i2c_lock);
567 if (ret < 0)
568 return ret;
569
570 return !!(reg_val & bit);
571}
572
573static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
574{
575 struct pca953x_chip *chip = gpiochip_get_data(gc);
576 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
577 u8 bit = BIT(off % BANK_SZ);
578
579 mutex_lock(&chip->i2c_lock);
580 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
581 mutex_unlock(&chip->i2c_lock);
582}
583
584static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
585{
586 struct pca953x_chip *chip = gpiochip_get_data(gc);
587 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
588 u8 bit = BIT(off % BANK_SZ);
589 u32 reg_val;
590 int ret;
591
592 mutex_lock(&chip->i2c_lock);
593 ret = regmap_read(chip->regmap, dirreg, ®_val);
594 mutex_unlock(&chip->i2c_lock);
595 if (ret < 0)
596 return ret;
597
598 if (reg_val & bit)
599 return GPIO_LINE_DIRECTION_IN;
600
601 return GPIO_LINE_DIRECTION_OUT;
602}
603
604static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
605 unsigned long *mask, unsigned long *bits)
606{
607 struct pca953x_chip *chip = gpiochip_get_data(gc);
608 DECLARE_BITMAP(reg_val, MAX_LINE);
609 int ret;
610
611 mutex_lock(&chip->i2c_lock);
612 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
613 mutex_unlock(&chip->i2c_lock);
614 if (ret)
615 return ret;
616
617 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
618 return 0;
619}
620
621static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
622 unsigned long *mask, unsigned long *bits)
623{
624 struct pca953x_chip *chip = gpiochip_get_data(gc);
625 DECLARE_BITMAP(reg_val, MAX_LINE);
626 int ret;
627
628 mutex_lock(&chip->i2c_lock);
629 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
630 if (ret)
631 goto exit;
632
633 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
634
635 pca953x_write_regs(chip, chip->regs->output, reg_val);
636exit:
637 mutex_unlock(&chip->i2c_lock);
638}
639
640static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
641 unsigned int offset,
642 unsigned long config)
643{
644 enum pin_config_param param = pinconf_to_config_param(config);
645
646 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
647 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
648 u8 bit = BIT(offset % BANK_SZ);
649 int ret;
650
651 /*
652 * pull-up/pull-down configuration requires PCAL extended
653 * registers
654 */
655 if (!(chip->driver_data & PCA_PCAL))
656 return -ENOTSUPP;
657
658 mutex_lock(&chip->i2c_lock);
659
660 /* Configure pull-up/pull-down */
661 if (param == PIN_CONFIG_BIAS_PULL_UP)
662 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
663 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
664 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
665 else
666 ret = 0;
667 if (ret)
668 goto exit;
669
670 /* Disable/Enable pull-up/pull-down */
671 if (param == PIN_CONFIG_BIAS_DISABLE)
672 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
673 else
674 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
675
676exit:
677 mutex_unlock(&chip->i2c_lock);
678 return ret;
679}
680
681static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
682 unsigned long config)
683{
684 struct pca953x_chip *chip = gpiochip_get_data(gc);
685
686 switch (pinconf_to_config_param(config)) {
687 case PIN_CONFIG_BIAS_PULL_UP:
688 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
689 case PIN_CONFIG_BIAS_PULL_DOWN:
690 case PIN_CONFIG_BIAS_DISABLE:
691 return pca953x_gpio_set_pull_up_down(chip, offset, config);
692 default:
693 return -ENOTSUPP;
694 }
695}
696
697static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
698{
699 struct gpio_chip *gc;
700
701 gc = &chip->gpio_chip;
702
703 gc->direction_input = pca953x_gpio_direction_input;
704 gc->direction_output = pca953x_gpio_direction_output;
705 gc->get = pca953x_gpio_get_value;
706 gc->set = pca953x_gpio_set_value;
707 gc->get_direction = pca953x_gpio_get_direction;
708 gc->get_multiple = pca953x_gpio_get_multiple;
709 gc->set_multiple = pca953x_gpio_set_multiple;
710 gc->set_config = pca953x_gpio_set_config;
711 gc->can_sleep = true;
712
713 gc->base = chip->gpio_start;
714 gc->ngpio = gpios;
715 gc->label = dev_name(&chip->client->dev);
716 gc->parent = &chip->client->dev;
717 gc->owner = THIS_MODULE;
718 gc->names = chip->names;
719}
720
721#ifdef CONFIG_GPIO_PCA953X_IRQ
722static void pca953x_irq_mask(struct irq_data *d)
723{
724 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
725 struct pca953x_chip *chip = gpiochip_get_data(gc);
726 irq_hw_number_t hwirq = irqd_to_hwirq(d);
727
728 clear_bit(hwirq, chip->irq_mask);
729 gpiochip_disable_irq(gc, hwirq);
730}
731
732static void pca953x_irq_unmask(struct irq_data *d)
733{
734 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
735 struct pca953x_chip *chip = gpiochip_get_data(gc);
736 irq_hw_number_t hwirq = irqd_to_hwirq(d);
737
738 gpiochip_enable_irq(gc, hwirq);
739 set_bit(hwirq, chip->irq_mask);
740}
741
742static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
743{
744 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
745 struct pca953x_chip *chip = gpiochip_get_data(gc);
746
747 if (on)
748 atomic_inc(&chip->wakeup_path);
749 else
750 atomic_dec(&chip->wakeup_path);
751
752 return irq_set_irq_wake(chip->client->irq, on);
753}
754
755static void pca953x_irq_bus_lock(struct irq_data *d)
756{
757 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
758 struct pca953x_chip *chip = gpiochip_get_data(gc);
759
760 mutex_lock(&chip->irq_lock);
761}
762
763static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
764{
765 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
766 struct pca953x_chip *chip = gpiochip_get_data(gc);
767 DECLARE_BITMAP(irq_mask, MAX_LINE);
768 DECLARE_BITMAP(reg_direction, MAX_LINE);
769 int level;
770
771 if (chip->driver_data & PCA_PCAL) {
772 /* Enable latch on interrupt-enabled inputs */
773 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
774
775 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
776
777 /* Unmask enabled interrupts */
778 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
779 }
780
781 /* Switch direction to input if needed */
782 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
783
784 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
785 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
786 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
787
788 /* Look for any newly setup interrupt */
789 for_each_set_bit(level, irq_mask, gc->ngpio)
790 pca953x_gpio_direction_input(&chip->gpio_chip, level);
791
792 mutex_unlock(&chip->irq_lock);
793}
794
795static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
796{
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
798 struct pca953x_chip *chip = gpiochip_get_data(gc);
799 irq_hw_number_t hwirq = irqd_to_hwirq(d);
800
801 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
802 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
803 d->irq, type);
804 return -EINVAL;
805 }
806
807 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
808 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
809
810 return 0;
811}
812
813static void pca953x_irq_shutdown(struct irq_data *d)
814{
815 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
816 struct pca953x_chip *chip = gpiochip_get_data(gc);
817 irq_hw_number_t hwirq = irqd_to_hwirq(d);
818
819 clear_bit(hwirq, chip->irq_trig_raise);
820 clear_bit(hwirq, chip->irq_trig_fall);
821}
822
823static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
824{
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
826
827 seq_printf(p, dev_name(gc->parent));
828}
829
830static const struct irq_chip pca953x_irq_chip = {
831 .irq_mask = pca953x_irq_mask,
832 .irq_unmask = pca953x_irq_unmask,
833 .irq_set_wake = pca953x_irq_set_wake,
834 .irq_bus_lock = pca953x_irq_bus_lock,
835 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
836 .irq_set_type = pca953x_irq_set_type,
837 .irq_shutdown = pca953x_irq_shutdown,
838 .irq_print_chip = pca953x_irq_print_chip,
839 .flags = IRQCHIP_IMMUTABLE,
840 GPIOCHIP_IRQ_RESOURCE_HELPERS,
841};
842
843static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
844{
845 struct gpio_chip *gc = &chip->gpio_chip;
846 DECLARE_BITMAP(reg_direction, MAX_LINE);
847 DECLARE_BITMAP(old_stat, MAX_LINE);
848 DECLARE_BITMAP(cur_stat, MAX_LINE);
849 DECLARE_BITMAP(new_stat, MAX_LINE);
850 DECLARE_BITMAP(trigger, MAX_LINE);
851 int ret;
852
853 if (chip->driver_data & PCA_PCAL) {
854 /* Read the current interrupt status from the device */
855 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
856 if (ret)
857 return false;
858
859 /* Check latched inputs and clear interrupt status */
860 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
861 if (ret)
862 return false;
863
864 /* Apply filter for rising/falling edge selection */
865 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
866
867 bitmap_and(pending, new_stat, trigger, gc->ngpio);
868
869 return !bitmap_empty(pending, gc->ngpio);
870 }
871
872 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
873 if (ret)
874 return false;
875
876 /* Remove output pins from the equation */
877 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
878
879 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
880
881 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
882 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
883 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
884
885 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
886
887 if (bitmap_empty(trigger, gc->ngpio))
888 return false;
889
890 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
891 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
892 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
893 bitmap_and(pending, new_stat, trigger, gc->ngpio);
894
895 return !bitmap_empty(pending, gc->ngpio);
896}
897
898static irqreturn_t pca953x_irq_handler(int irq, void *devid)
899{
900 struct pca953x_chip *chip = devid;
901 struct gpio_chip *gc = &chip->gpio_chip;
902 DECLARE_BITMAP(pending, MAX_LINE);
903 int level;
904 bool ret;
905
906 bitmap_zero(pending, MAX_LINE);
907
908 mutex_lock(&chip->i2c_lock);
909 ret = pca953x_irq_pending(chip, pending);
910 mutex_unlock(&chip->i2c_lock);
911
912 if (ret) {
913 ret = 0;
914
915 for_each_set_bit(level, pending, gc->ngpio) {
916 int nested_irq = irq_find_mapping(gc->irq.domain, level);
917
918 if (unlikely(nested_irq <= 0)) {
919 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
920 continue;
921 }
922
923 handle_nested_irq(nested_irq);
924 ret = 1;
925 }
926 }
927
928 return IRQ_RETVAL(ret);
929}
930
931static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
932{
933 struct i2c_client *client = chip->client;
934 DECLARE_BITMAP(reg_direction, MAX_LINE);
935 DECLARE_BITMAP(irq_stat, MAX_LINE);
936 struct gpio_irq_chip *girq;
937 int ret;
938
939 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
940 ret = pca953x_acpi_get_irq(&client->dev);
941 if (ret > 0)
942 client->irq = ret;
943 }
944
945 if (!client->irq)
946 return 0;
947
948 if (irq_base == -1)
949 return 0;
950
951 if (!(chip->driver_data & PCA_INT))
952 return 0;
953
954 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
955 if (ret)
956 return ret;
957
958 /*
959 * There is no way to know which GPIO line generated the
960 * interrupt. We have to rely on the previous read for
961 * this purpose.
962 */
963 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
964 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
965 mutex_init(&chip->irq_lock);
966
967 girq = &chip->gpio_chip.irq;
968 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
969 /* This will let us handle the parent IRQ in the driver */
970 girq->parent_handler = NULL;
971 girq->num_parents = 0;
972 girq->parents = NULL;
973 girq->default_type = IRQ_TYPE_NONE;
974 girq->handler = handle_simple_irq;
975 girq->threaded = true;
976 girq->first = irq_base; /* FIXME: get rid of this */
977
978 ret = devm_request_threaded_irq(&client->dev, client->irq,
979 NULL, pca953x_irq_handler,
980 IRQF_ONESHOT | IRQF_SHARED,
981 dev_name(&client->dev), chip);
982 if (ret) {
983 dev_err(&client->dev, "failed to request irq %d\n",
984 client->irq);
985 return ret;
986 }
987
988 return 0;
989}
990
991#else /* CONFIG_GPIO_PCA953X_IRQ */
992static int pca953x_irq_setup(struct pca953x_chip *chip,
993 int irq_base)
994{
995 struct i2c_client *client = chip->client;
996
997 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
998 dev_warn(&client->dev, "interrupt support not compiled in\n");
999
1000 return 0;
1001}
1002#endif
1003
1004static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
1005{
1006 DECLARE_BITMAP(val, MAX_LINE);
1007 u8 regaddr;
1008 int ret;
1009
1010 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1011 ret = regcache_sync_region(chip->regmap, regaddr,
1012 regaddr + NBANK(chip) - 1);
1013 if (ret)
1014 goto out;
1015
1016 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1017 ret = regcache_sync_region(chip->regmap, regaddr,
1018 regaddr + NBANK(chip) - 1);
1019 if (ret)
1020 goto out;
1021
1022 /* set platform specific polarity inversion */
1023 if (invert)
1024 bitmap_fill(val, MAX_LINE);
1025 else
1026 bitmap_zero(val, MAX_LINE);
1027
1028 ret = pca953x_write_regs(chip, chip->regs->invert, val);
1029out:
1030 return ret;
1031}
1032
1033static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
1034{
1035 DECLARE_BITMAP(val, MAX_LINE);
1036 unsigned int i;
1037 int ret;
1038
1039 ret = device_pca95xx_init(chip, invert);
1040 if (ret)
1041 goto out;
1042
1043 /* To enable register 6, 7 to control pull up and pull down */
1044 for (i = 0; i < NBANK(chip); i++)
1045 bitmap_set_value8(val, 0x02, i * BANK_SZ);
1046
1047 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
1048 if (ret)
1049 goto out;
1050
1051 return 0;
1052out:
1053 return ret;
1054}
1055
1056static int pca953x_probe(struct i2c_client *client)
1057{
1058 const struct i2c_device_id *i2c_id = i2c_client_get_device_id(client);
1059 struct pca953x_platform_data *pdata;
1060 struct pca953x_chip *chip;
1061 int irq_base = 0;
1062 int ret;
1063 u32 invert = 0;
1064 struct regulator *reg;
1065 const struct regmap_config *regmap_config;
1066
1067 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1068 if (chip == NULL)
1069 return -ENOMEM;
1070
1071 pdata = dev_get_platdata(&client->dev);
1072 if (pdata) {
1073 irq_base = pdata->irq_base;
1074 chip->gpio_start = pdata->gpio_base;
1075 invert = pdata->invert;
1076 chip->names = pdata->names;
1077 } else {
1078 struct gpio_desc *reset_gpio;
1079
1080 chip->gpio_start = -1;
1081 irq_base = 0;
1082
1083 /*
1084 * See if we need to de-assert a reset pin.
1085 *
1086 * There is no known ACPI-enabled platforms that are
1087 * using "reset" GPIO. Otherwise any of those platform
1088 * must use _DSD method with corresponding property.
1089 */
1090 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1091 GPIOD_OUT_LOW);
1092 if (IS_ERR(reset_gpio))
1093 return PTR_ERR(reset_gpio);
1094 }
1095
1096 chip->client = client;
1097
1098 reg = devm_regulator_get(&client->dev, "vcc");
1099 if (IS_ERR(reg))
1100 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
1101
1102 ret = regulator_enable(reg);
1103 if (ret) {
1104 dev_err(&client->dev, "reg en err: %d\n", ret);
1105 return ret;
1106 }
1107 chip->regulator = reg;
1108
1109 if (i2c_id) {
1110 chip->driver_data = i2c_id->driver_data;
1111 } else {
1112 const void *match;
1113
1114 match = device_get_match_data(&client->dev);
1115 if (!match) {
1116 ret = -ENODEV;
1117 goto err_exit;
1118 }
1119
1120 chip->driver_data = (uintptr_t)match;
1121 }
1122
1123 i2c_set_clientdata(client, chip);
1124
1125 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1126
1127 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1128 dev_info(&client->dev, "using AI\n");
1129 regmap_config = &pca953x_ai_i2c_regmap;
1130 } else {
1131 dev_info(&client->dev, "using no AI\n");
1132 regmap_config = &pca953x_i2c_regmap;
1133 }
1134
1135 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1136 chip->recalc_addr = pcal6534_recalc_addr;
1137 chip->check_reg = pcal6534_check_register;
1138 } else {
1139 chip->recalc_addr = pca953x_recalc_addr;
1140 chip->check_reg = pca953x_check_register;
1141 }
1142
1143 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1144 if (IS_ERR(chip->regmap)) {
1145 ret = PTR_ERR(chip->regmap);
1146 goto err_exit;
1147 }
1148
1149 regcache_mark_dirty(chip->regmap);
1150
1151 mutex_init(&chip->i2c_lock);
1152 /*
1153 * In case we have an i2c-mux controlled by a GPIO provided by an
1154 * expander using the same driver higher on the device tree, read the
1155 * i2c adapter nesting depth and use the retrieved value as lockdep
1156 * subclass for chip->i2c_lock.
1157 *
1158 * REVISIT: This solution is not complete. It protects us from lockdep
1159 * false positives when the expander controlling the i2c-mux is on
1160 * a different level on the device tree, but not when it's on the same
1161 * level on a different branch (in which case the subclass number
1162 * would be the same).
1163 *
1164 * TODO: Once a correct solution is developed, a similar fix should be
1165 * applied to all other i2c-controlled GPIO expanders (and potentially
1166 * regmap-i2c).
1167 */
1168 lockdep_set_subclass(&chip->i2c_lock,
1169 i2c_adapter_depth(client->adapter));
1170
1171 /* initialize cached registers from their original values.
1172 * we can't share this chip with another i2c master.
1173 */
1174 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1175 chip->regs = &pca957x_regs;
1176 ret = device_pca957x_init(chip, invert);
1177 } else {
1178 chip->regs = &pca953x_regs;
1179 ret = device_pca95xx_init(chip, invert);
1180 }
1181 if (ret)
1182 goto err_exit;
1183
1184 ret = pca953x_irq_setup(chip, irq_base);
1185 if (ret)
1186 goto err_exit;
1187
1188 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1189 if (ret)
1190 goto err_exit;
1191
1192 if (pdata && pdata->setup) {
1193 ret = pdata->setup(client, chip->gpio_chip.base,
1194 chip->gpio_chip.ngpio, pdata->context);
1195 if (ret < 0)
1196 dev_warn(&client->dev, "setup failed, %d\n", ret);
1197 }
1198
1199 return 0;
1200
1201err_exit:
1202 regulator_disable(chip->regulator);
1203 return ret;
1204}
1205
1206static void pca953x_remove(struct i2c_client *client)
1207{
1208 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1209 struct pca953x_chip *chip = i2c_get_clientdata(client);
1210
1211 if (pdata && pdata->teardown) {
1212 pdata->teardown(client, chip->gpio_chip.base,
1213 chip->gpio_chip.ngpio, pdata->context);
1214 }
1215
1216 regulator_disable(chip->regulator);
1217}
1218
1219#ifdef CONFIG_PM_SLEEP
1220static int pca953x_regcache_sync(struct device *dev)
1221{
1222 struct pca953x_chip *chip = dev_get_drvdata(dev);
1223 int ret;
1224 u8 regaddr;
1225
1226 /*
1227 * The ordering between direction and output is important,
1228 * sync these registers first and only then sync the rest.
1229 */
1230 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1231 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1232 if (ret) {
1233 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1234 return ret;
1235 }
1236
1237 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1238 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1239 if (ret) {
1240 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1241 return ret;
1242 }
1243
1244#ifdef CONFIG_GPIO_PCA953X_IRQ
1245 if (chip->driver_data & PCA_PCAL) {
1246 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
1247 ret = regcache_sync_region(chip->regmap, regaddr,
1248 regaddr + NBANK(chip) - 1);
1249 if (ret) {
1250 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1251 ret);
1252 return ret;
1253 }
1254
1255 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
1256 ret = regcache_sync_region(chip->regmap, regaddr,
1257 regaddr + NBANK(chip) - 1);
1258 if (ret) {
1259 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1260 ret);
1261 return ret;
1262 }
1263 }
1264#endif
1265
1266 return 0;
1267}
1268
1269static int pca953x_suspend(struct device *dev)
1270{
1271 struct pca953x_chip *chip = dev_get_drvdata(dev);
1272
1273 mutex_lock(&chip->i2c_lock);
1274 regcache_cache_only(chip->regmap, true);
1275 mutex_unlock(&chip->i2c_lock);
1276
1277 if (atomic_read(&chip->wakeup_path))
1278 device_set_wakeup_path(dev);
1279 else
1280 regulator_disable(chip->regulator);
1281
1282 return 0;
1283}
1284
1285static int pca953x_resume(struct device *dev)
1286{
1287 struct pca953x_chip *chip = dev_get_drvdata(dev);
1288 int ret;
1289
1290 if (!atomic_read(&chip->wakeup_path)) {
1291 ret = regulator_enable(chip->regulator);
1292 if (ret) {
1293 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1294 return 0;
1295 }
1296 }
1297
1298 mutex_lock(&chip->i2c_lock);
1299 regcache_cache_only(chip->regmap, false);
1300 regcache_mark_dirty(chip->regmap);
1301 ret = pca953x_regcache_sync(dev);
1302 if (ret) {
1303 mutex_unlock(&chip->i2c_lock);
1304 return ret;
1305 }
1306
1307 ret = regcache_sync(chip->regmap);
1308 mutex_unlock(&chip->i2c_lock);
1309 if (ret) {
1310 dev_err(dev, "Failed to restore register map: %d\n", ret);
1311 return ret;
1312 }
1313
1314 return 0;
1315}
1316#endif
1317
1318/* convenience to stop overlong match-table lines */
1319#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
1320#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1321#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1322
1323static const struct of_device_id pca953x_dt_ids[] = {
1324 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
1325 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1326 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1327 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1328 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1329 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1330 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1331 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1332 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1333 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1334 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1335 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1336 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1337 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1338 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1339 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1340 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1341
1342 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
1343 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1344 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1345 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
1346 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1347 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1348 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1349
1350 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1351 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1352 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1353 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1354 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1355
1356 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1357 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1358 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1359 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1360 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1361 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1362
1363 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1364 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1365 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1366
1367 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1368 { }
1369};
1370
1371MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1372
1373static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1374
1375static struct i2c_driver pca953x_driver = {
1376 .driver = {
1377 .name = "pca953x",
1378 .pm = &pca953x_pm_ops,
1379 .of_match_table = pca953x_dt_ids,
1380 .acpi_match_table = pca953x_acpi_ids,
1381 },
1382 .probe_new = pca953x_probe,
1383 .remove = pca953x_remove,
1384 .id_table = pca953x_id,
1385};
1386
1387static int __init pca953x_init(void)
1388{
1389 return i2c_add_driver(&pca953x_driver);
1390}
1391/* register after i2c postcore initcall and before
1392 * subsys initcalls that may rely on these GPIOs
1393 */
1394subsys_initcall(pca953x_init);
1395
1396static void __exit pca953x_exit(void)
1397{
1398 i2c_del_driver(&pca953x_driver);
1399}
1400module_exit(pca953x_exit);
1401
1402MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1403MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1404MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/acpi.h>
12#include <linux/bitmap.h>
13#include <linux/gpio/driver.h>
14#include <linux/gpio/consumer.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/pca953x.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25#include <asm/unaligned.h>
26
27#define PCA953X_INPUT 0x00
28#define PCA953X_OUTPUT 0x01
29#define PCA953X_INVERT 0x02
30#define PCA953X_DIRECTION 0x03
31
32#define REG_ADDR_MASK GENMASK(5, 0)
33#define REG_ADDR_EXT BIT(6)
34#define REG_ADDR_AI BIT(7)
35
36#define PCA957X_IN 0x00
37#define PCA957X_INVRT 0x01
38#define PCA957X_BKEN 0x02
39#define PCA957X_PUPD 0x03
40#define PCA957X_CFG 0x04
41#define PCA957X_OUT 0x05
42#define PCA957X_MSK 0x06
43#define PCA957X_INTS 0x07
44
45#define PCAL953X_OUT_STRENGTH 0x20
46#define PCAL953X_IN_LATCH 0x22
47#define PCAL953X_PULL_EN 0x23
48#define PCAL953X_PULL_SEL 0x24
49#define PCAL953X_INT_MASK 0x25
50#define PCAL953X_INT_STAT 0x26
51#define PCAL953X_OUT_CONF 0x27
52
53#define PCAL6524_INT_EDGE 0x28
54#define PCAL6524_INT_CLR 0x2a
55#define PCAL6524_IN_STATUS 0x2b
56#define PCAL6524_OUT_INDCONF 0x2c
57#define PCAL6524_DEBOUNCE 0x2d
58
59#define PCA_GPIO_MASK GENMASK(7, 0)
60
61#define PCAL_GPIO_MASK GENMASK(4, 0)
62#define PCAL_PINCTRL_MASK GENMASK(6, 5)
63
64#define PCA_INT BIT(8)
65#define PCA_PCAL BIT(9)
66#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
67#define PCA953X_TYPE BIT(12)
68#define PCA957X_TYPE BIT(13)
69#define PCA_TYPE_MASK GENMASK(15, 12)
70
71#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
72
73static const struct i2c_device_id pca953x_id[] = {
74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
76 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
77 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
78 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
79 { "pca9536", 4 | PCA953X_TYPE, },
80 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
81 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
82 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
83 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
84 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
85 { "pca9556", 8 | PCA953X_TYPE, },
86 { "pca9557", 8 | PCA953X_TYPE, },
87 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
88 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
89 { "pca9698", 40 | PCA953X_TYPE, },
90
91 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
93 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
94 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
95 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
96
97 { "max7310", 8 | PCA953X_TYPE, },
98 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
99 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
100 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
101 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
102 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
103 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
104 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
105 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
106 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
107 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
108 { "xra1202", 8 | PCA953X_TYPE },
109 { }
110};
111MODULE_DEVICE_TABLE(i2c, pca953x_id);
112
113#ifdef CONFIG_GPIO_PCA953X_IRQ
114
115#include <linux/dmi.h>
116
117static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
118
119static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
120 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
121 { }
122};
123
124static int pca953x_acpi_get_irq(struct device *dev)
125{
126 int ret;
127
128 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
129 if (ret)
130 dev_warn(dev, "can't add GPIO ACPI mapping\n");
131
132 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
133 if (ret < 0)
134 return ret;
135
136 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
137 return ret;
138}
139
140static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
141 {
142 /*
143 * On Intel Galileo Gen 2 board the IRQ pin of one of
144 * the I²C GPIO expanders, which has GpioInt() resource,
145 * is provided as an absolute number instead of being
146 * relative. Since first controller (gpio-sch.c) and
147 * second (gpio-dwapb.c) are at the fixed bases, we may
148 * safely refer to the number in the global space to get
149 * an IRQ out of it.
150 */
151 .matches = {
152 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
153 },
154 },
155 {}
156};
157#endif
158
159static const struct acpi_device_id pca953x_acpi_ids[] = {
160 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
161 { }
162};
163MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
164
165#define MAX_BANK 5
166#define BANK_SZ 8
167#define MAX_LINE (MAX_BANK * BANK_SZ)
168
169#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
170
171struct pca953x_reg_config {
172 int direction;
173 int output;
174 int input;
175 int invert;
176};
177
178static const struct pca953x_reg_config pca953x_regs = {
179 .direction = PCA953X_DIRECTION,
180 .output = PCA953X_OUTPUT,
181 .input = PCA953X_INPUT,
182 .invert = PCA953X_INVERT,
183};
184
185static const struct pca953x_reg_config pca957x_regs = {
186 .direction = PCA957X_CFG,
187 .output = PCA957X_OUT,
188 .input = PCA957X_IN,
189 .invert = PCA957X_INVRT,
190};
191
192struct pca953x_chip {
193 unsigned gpio_start;
194 struct mutex i2c_lock;
195 struct regmap *regmap;
196
197#ifdef CONFIG_GPIO_PCA953X_IRQ
198 struct mutex irq_lock;
199 DECLARE_BITMAP(irq_mask, MAX_LINE);
200 DECLARE_BITMAP(irq_stat, MAX_LINE);
201 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
202 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
203 struct irq_chip irq_chip;
204#endif
205 atomic_t wakeup_path;
206
207 struct i2c_client *client;
208 struct gpio_chip gpio_chip;
209 const char *const *names;
210 unsigned long driver_data;
211 struct regulator *regulator;
212
213 const struct pca953x_reg_config *regs;
214};
215
216static int pca953x_bank_shift(struct pca953x_chip *chip)
217{
218 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
219}
220
221#define PCA953x_BANK_INPUT BIT(0)
222#define PCA953x_BANK_OUTPUT BIT(1)
223#define PCA953x_BANK_POLARITY BIT(2)
224#define PCA953x_BANK_CONFIG BIT(3)
225
226#define PCA957x_BANK_INPUT BIT(0)
227#define PCA957x_BANK_POLARITY BIT(1)
228#define PCA957x_BANK_BUSHOLD BIT(2)
229#define PCA957x_BANK_CONFIG BIT(4)
230#define PCA957x_BANK_OUTPUT BIT(5)
231
232#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
233#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
234#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
235#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
236#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
237
238/*
239 * We care about the following registers:
240 * - Standard set, below 0x40, each port can be replicated up to 8 times
241 * - PCA953x standard
242 * Input port 0x00 + 0 * bank_size R
243 * Output port 0x00 + 1 * bank_size RW
244 * Polarity Inversion port 0x00 + 2 * bank_size RW
245 * Configuration port 0x00 + 3 * bank_size RW
246 * - PCA957x with mixed up registers
247 * Input port 0x00 + 0 * bank_size R
248 * Polarity Inversion port 0x00 + 1 * bank_size RW
249 * Bus hold port 0x00 + 2 * bank_size RW
250 * Configuration port 0x00 + 4 * bank_size RW
251 * Output port 0x00 + 5 * bank_size RW
252 *
253 * - Extended set, above 0x40, often chip specific.
254 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
255 * Input latch register 0x40 + 2 * bank_size RW
256 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
257 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
258 * Interrupt mask register 0x40 + 5 * bank_size RW
259 * Interrupt status register 0x40 + 6 * bank_size R
260 *
261 * - Registers with bit 0x80 set, the AI bit
262 * The bit is cleared and the registers fall into one of the
263 * categories above.
264 */
265
266static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
267 u32 checkbank)
268{
269 int bank_shift = pca953x_bank_shift(chip);
270 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
271 int offset = reg & (BIT(bank_shift) - 1);
272
273 /* Special PCAL extended register check. */
274 if (reg & REG_ADDR_EXT) {
275 if (!(chip->driver_data & PCA_PCAL))
276 return false;
277 bank += 8;
278 }
279
280 /* Register is not in the matching bank. */
281 if (!(BIT(bank) & checkbank))
282 return false;
283
284 /* Register is not within allowed range of bank. */
285 if (offset >= NBANK(chip))
286 return false;
287
288 return true;
289}
290
291static bool pca953x_readable_register(struct device *dev, unsigned int reg)
292{
293 struct pca953x_chip *chip = dev_get_drvdata(dev);
294 u32 bank;
295
296 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
297 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
298 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
299 } else {
300 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
301 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
302 PCA957x_BANK_BUSHOLD;
303 }
304
305 if (chip->driver_data & PCA_PCAL) {
306 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
307 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
308 PCAL9xxx_BANK_IRQ_STAT;
309 }
310
311 return pca953x_check_register(chip, reg, bank);
312}
313
314static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
315{
316 struct pca953x_chip *chip = dev_get_drvdata(dev);
317 u32 bank;
318
319 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
320 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
321 PCA953x_BANK_CONFIG;
322 } else {
323 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
324 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
325 }
326
327 if (chip->driver_data & PCA_PCAL)
328 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
329 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
330
331 return pca953x_check_register(chip, reg, bank);
332}
333
334static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
335{
336 struct pca953x_chip *chip = dev_get_drvdata(dev);
337 u32 bank;
338
339 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
340 bank = PCA953x_BANK_INPUT;
341 else
342 bank = PCA957x_BANK_INPUT;
343
344 if (chip->driver_data & PCA_PCAL)
345 bank |= PCAL9xxx_BANK_IRQ_STAT;
346
347 return pca953x_check_register(chip, reg, bank);
348}
349
350static const struct regmap_config pca953x_i2c_regmap = {
351 .reg_bits = 8,
352 .val_bits = 8,
353
354 .readable_reg = pca953x_readable_register,
355 .writeable_reg = pca953x_writeable_register,
356 .volatile_reg = pca953x_volatile_register,
357
358 .disable_locking = true,
359 .cache_type = REGCACHE_RBTREE,
360 .max_register = 0x7f,
361};
362
363static const struct regmap_config pca953x_ai_i2c_regmap = {
364 .reg_bits = 8,
365 .val_bits = 8,
366
367 .read_flag_mask = REG_ADDR_AI,
368 .write_flag_mask = REG_ADDR_AI,
369
370 .readable_reg = pca953x_readable_register,
371 .writeable_reg = pca953x_writeable_register,
372 .volatile_reg = pca953x_volatile_register,
373
374 .disable_locking = true,
375 .cache_type = REGCACHE_RBTREE,
376 .max_register = 0x7f,
377};
378
379static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
380{
381 int bank_shift = pca953x_bank_shift(chip);
382 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
383 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
384 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
385
386 return regaddr;
387}
388
389static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
390{
391 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
392 u8 value[MAX_BANK];
393 int i, ret;
394
395 for (i = 0; i < NBANK(chip); i++)
396 value[i] = bitmap_get_value8(val, i * BANK_SZ);
397
398 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
399 if (ret < 0) {
400 dev_err(&chip->client->dev, "failed writing register\n");
401 return ret;
402 }
403
404 return 0;
405}
406
407static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
408{
409 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
410 u8 value[MAX_BANK];
411 int i, ret;
412
413 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
414 if (ret < 0) {
415 dev_err(&chip->client->dev, "failed reading register\n");
416 return ret;
417 }
418
419 for (i = 0; i < NBANK(chip); i++)
420 bitmap_set_value8(val, value[i], i * BANK_SZ);
421
422 return 0;
423}
424
425static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
426{
427 struct pca953x_chip *chip = gpiochip_get_data(gc);
428 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
429 u8 bit = BIT(off % BANK_SZ);
430 int ret;
431
432 mutex_lock(&chip->i2c_lock);
433 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
434 mutex_unlock(&chip->i2c_lock);
435 return ret;
436}
437
438static int pca953x_gpio_direction_output(struct gpio_chip *gc,
439 unsigned off, int val)
440{
441 struct pca953x_chip *chip = gpiochip_get_data(gc);
442 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
443 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
444 u8 bit = BIT(off % BANK_SZ);
445 int ret;
446
447 mutex_lock(&chip->i2c_lock);
448 /* set output level */
449 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
450 if (ret)
451 goto exit;
452
453 /* then direction */
454 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
455exit:
456 mutex_unlock(&chip->i2c_lock);
457 return ret;
458}
459
460static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
461{
462 struct pca953x_chip *chip = gpiochip_get_data(gc);
463 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off);
464 u8 bit = BIT(off % BANK_SZ);
465 u32 reg_val;
466 int ret;
467
468 mutex_lock(&chip->i2c_lock);
469 ret = regmap_read(chip->regmap, inreg, ®_val);
470 mutex_unlock(&chip->i2c_lock);
471 if (ret < 0)
472 return ret;
473
474 return !!(reg_val & bit);
475}
476
477static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
478{
479 struct pca953x_chip *chip = gpiochip_get_data(gc);
480 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
481 u8 bit = BIT(off % BANK_SZ);
482
483 mutex_lock(&chip->i2c_lock);
484 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
485 mutex_unlock(&chip->i2c_lock);
486}
487
488static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
489{
490 struct pca953x_chip *chip = gpiochip_get_data(gc);
491 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
492 u8 bit = BIT(off % BANK_SZ);
493 u32 reg_val;
494 int ret;
495
496 mutex_lock(&chip->i2c_lock);
497 ret = regmap_read(chip->regmap, dirreg, ®_val);
498 mutex_unlock(&chip->i2c_lock);
499 if (ret < 0)
500 return ret;
501
502 if (reg_val & bit)
503 return GPIO_LINE_DIRECTION_IN;
504
505 return GPIO_LINE_DIRECTION_OUT;
506}
507
508static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
509 unsigned long *mask, unsigned long *bits)
510{
511 struct pca953x_chip *chip = gpiochip_get_data(gc);
512 DECLARE_BITMAP(reg_val, MAX_LINE);
513 int ret;
514
515 mutex_lock(&chip->i2c_lock);
516 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
517 mutex_unlock(&chip->i2c_lock);
518 if (ret)
519 return ret;
520
521 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
522 return 0;
523}
524
525static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
526 unsigned long *mask, unsigned long *bits)
527{
528 struct pca953x_chip *chip = gpiochip_get_data(gc);
529 DECLARE_BITMAP(reg_val, MAX_LINE);
530 int ret;
531
532 mutex_lock(&chip->i2c_lock);
533 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
534 if (ret)
535 goto exit;
536
537 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
538
539 pca953x_write_regs(chip, chip->regs->output, reg_val);
540exit:
541 mutex_unlock(&chip->i2c_lock);
542}
543
544static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
545 unsigned int offset,
546 unsigned long config)
547{
548 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset);
549 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset);
550 u8 bit = BIT(offset % BANK_SZ);
551 int ret;
552
553 /*
554 * pull-up/pull-down configuration requires PCAL extended
555 * registers
556 */
557 if (!(chip->driver_data & PCA_PCAL))
558 return -ENOTSUPP;
559
560 mutex_lock(&chip->i2c_lock);
561
562 /* Configure pull-up/pull-down */
563 if (config == PIN_CONFIG_BIAS_PULL_UP)
564 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
565 else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
566 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
567 else
568 ret = 0;
569 if (ret)
570 goto exit;
571
572 /* Disable/Enable pull-up/pull-down */
573 if (config == PIN_CONFIG_BIAS_DISABLE)
574 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
575 else
576 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
577
578exit:
579 mutex_unlock(&chip->i2c_lock);
580 return ret;
581}
582
583static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
584 unsigned long config)
585{
586 struct pca953x_chip *chip = gpiochip_get_data(gc);
587
588 switch (pinconf_to_config_param(config)) {
589 case PIN_CONFIG_BIAS_PULL_UP:
590 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
591 case PIN_CONFIG_BIAS_PULL_DOWN:
592 case PIN_CONFIG_BIAS_DISABLE:
593 return pca953x_gpio_set_pull_up_down(chip, offset, config);
594 default:
595 return -ENOTSUPP;
596 }
597}
598
599static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
600{
601 struct gpio_chip *gc;
602
603 gc = &chip->gpio_chip;
604
605 gc->direction_input = pca953x_gpio_direction_input;
606 gc->direction_output = pca953x_gpio_direction_output;
607 gc->get = pca953x_gpio_get_value;
608 gc->set = pca953x_gpio_set_value;
609 gc->get_direction = pca953x_gpio_get_direction;
610 gc->get_multiple = pca953x_gpio_get_multiple;
611 gc->set_multiple = pca953x_gpio_set_multiple;
612 gc->set_config = pca953x_gpio_set_config;
613 gc->can_sleep = true;
614
615 gc->base = chip->gpio_start;
616 gc->ngpio = gpios;
617 gc->label = dev_name(&chip->client->dev);
618 gc->parent = &chip->client->dev;
619 gc->owner = THIS_MODULE;
620 gc->names = chip->names;
621}
622
623#ifdef CONFIG_GPIO_PCA953X_IRQ
624static void pca953x_irq_mask(struct irq_data *d)
625{
626 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
627 struct pca953x_chip *chip = gpiochip_get_data(gc);
628 irq_hw_number_t hwirq = irqd_to_hwirq(d);
629
630 clear_bit(hwirq, chip->irq_mask);
631}
632
633static void pca953x_irq_unmask(struct irq_data *d)
634{
635 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
636 struct pca953x_chip *chip = gpiochip_get_data(gc);
637 irq_hw_number_t hwirq = irqd_to_hwirq(d);
638
639 set_bit(hwirq, chip->irq_mask);
640}
641
642static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
643{
644 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
645 struct pca953x_chip *chip = gpiochip_get_data(gc);
646
647 if (on)
648 atomic_inc(&chip->wakeup_path);
649 else
650 atomic_dec(&chip->wakeup_path);
651
652 return irq_set_irq_wake(chip->client->irq, on);
653}
654
655static void pca953x_irq_bus_lock(struct irq_data *d)
656{
657 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
658 struct pca953x_chip *chip = gpiochip_get_data(gc);
659
660 mutex_lock(&chip->irq_lock);
661}
662
663static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
664{
665 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
666 struct pca953x_chip *chip = gpiochip_get_data(gc);
667 DECLARE_BITMAP(irq_mask, MAX_LINE);
668 DECLARE_BITMAP(reg_direction, MAX_LINE);
669 int level;
670
671 if (chip->driver_data & PCA_PCAL) {
672 /* Enable latch on interrupt-enabled inputs */
673 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
674
675 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
676
677 /* Unmask enabled interrupts */
678 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
679 }
680
681 /* Switch direction to input if needed */
682 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
683
684 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
685 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
686 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
687
688 /* Look for any newly setup interrupt */
689 for_each_set_bit(level, irq_mask, gc->ngpio)
690 pca953x_gpio_direction_input(&chip->gpio_chip, level);
691
692 mutex_unlock(&chip->irq_lock);
693}
694
695static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
696{
697 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
698 struct pca953x_chip *chip = gpiochip_get_data(gc);
699 irq_hw_number_t hwirq = irqd_to_hwirq(d);
700
701 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
702 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
703 d->irq, type);
704 return -EINVAL;
705 }
706
707 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
708 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
709
710 return 0;
711}
712
713static void pca953x_irq_shutdown(struct irq_data *d)
714{
715 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
716 struct pca953x_chip *chip = gpiochip_get_data(gc);
717 irq_hw_number_t hwirq = irqd_to_hwirq(d);
718
719 clear_bit(hwirq, chip->irq_trig_raise);
720 clear_bit(hwirq, chip->irq_trig_fall);
721}
722
723static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
724{
725 struct gpio_chip *gc = &chip->gpio_chip;
726 DECLARE_BITMAP(reg_direction, MAX_LINE);
727 DECLARE_BITMAP(old_stat, MAX_LINE);
728 DECLARE_BITMAP(cur_stat, MAX_LINE);
729 DECLARE_BITMAP(new_stat, MAX_LINE);
730 DECLARE_BITMAP(trigger, MAX_LINE);
731 int ret;
732
733 if (chip->driver_data & PCA_PCAL) {
734 /* Read the current interrupt status from the device */
735 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
736 if (ret)
737 return false;
738
739 /* Check latched inputs and clear interrupt status */
740 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
741 if (ret)
742 return false;
743
744 /* Apply filter for rising/falling edge selection */
745 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
746
747 bitmap_and(pending, new_stat, trigger, gc->ngpio);
748
749 return !bitmap_empty(pending, gc->ngpio);
750 }
751
752 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
753 if (ret)
754 return false;
755
756 /* Remove output pins from the equation */
757 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
758
759 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
760
761 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
762 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
763 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
764
765 if (bitmap_empty(trigger, gc->ngpio))
766 return false;
767
768 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
769
770 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
771 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
772 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
773 bitmap_and(pending, new_stat, trigger, gc->ngpio);
774
775 return !bitmap_empty(pending, gc->ngpio);
776}
777
778static irqreturn_t pca953x_irq_handler(int irq, void *devid)
779{
780 struct pca953x_chip *chip = devid;
781 struct gpio_chip *gc = &chip->gpio_chip;
782 DECLARE_BITMAP(pending, MAX_LINE);
783 int level;
784 bool ret;
785
786 bitmap_zero(pending, MAX_LINE);
787
788 mutex_lock(&chip->i2c_lock);
789 ret = pca953x_irq_pending(chip, pending);
790 mutex_unlock(&chip->i2c_lock);
791
792 if (ret) {
793 ret = 0;
794
795 for_each_set_bit(level, pending, gc->ngpio) {
796 int nested_irq = irq_find_mapping(gc->irq.domain, level);
797
798 if (unlikely(nested_irq <= 0)) {
799 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
800 continue;
801 }
802
803 handle_nested_irq(nested_irq);
804 ret = 1;
805 }
806 }
807
808 return IRQ_RETVAL(ret);
809}
810
811static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
812{
813 struct i2c_client *client = chip->client;
814 struct irq_chip *irq_chip = &chip->irq_chip;
815 DECLARE_BITMAP(reg_direction, MAX_LINE);
816 DECLARE_BITMAP(irq_stat, MAX_LINE);
817 struct gpio_irq_chip *girq;
818 int ret;
819
820 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
821 ret = pca953x_acpi_get_irq(&client->dev);
822 if (ret > 0)
823 client->irq = ret;
824 }
825
826 if (!client->irq)
827 return 0;
828
829 if (irq_base == -1)
830 return 0;
831
832 if (!(chip->driver_data & PCA_INT))
833 return 0;
834
835 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
836 if (ret)
837 return ret;
838
839 /*
840 * There is no way to know which GPIO line generated the
841 * interrupt. We have to rely on the previous read for
842 * this purpose.
843 */
844 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
845 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
846 mutex_init(&chip->irq_lock);
847
848 irq_chip->name = dev_name(&client->dev);
849 irq_chip->irq_mask = pca953x_irq_mask;
850 irq_chip->irq_unmask = pca953x_irq_unmask;
851 irq_chip->irq_set_wake = pca953x_irq_set_wake;
852 irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
853 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
854 irq_chip->irq_set_type = pca953x_irq_set_type;
855 irq_chip->irq_shutdown = pca953x_irq_shutdown;
856
857 girq = &chip->gpio_chip.irq;
858 girq->chip = irq_chip;
859 /* This will let us handle the parent IRQ in the driver */
860 girq->parent_handler = NULL;
861 girq->num_parents = 0;
862 girq->parents = NULL;
863 girq->default_type = IRQ_TYPE_NONE;
864 girq->handler = handle_simple_irq;
865 girq->threaded = true;
866 girq->first = irq_base; /* FIXME: get rid of this */
867
868 ret = devm_request_threaded_irq(&client->dev, client->irq,
869 NULL, pca953x_irq_handler,
870 IRQF_ONESHOT | IRQF_SHARED,
871 dev_name(&client->dev), chip);
872 if (ret) {
873 dev_err(&client->dev, "failed to request irq %d\n",
874 client->irq);
875 return ret;
876 }
877
878 return 0;
879}
880
881#else /* CONFIG_GPIO_PCA953X_IRQ */
882static int pca953x_irq_setup(struct pca953x_chip *chip,
883 int irq_base)
884{
885 struct i2c_client *client = chip->client;
886
887 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
888 dev_warn(&client->dev, "interrupt support not compiled in\n");
889
890 return 0;
891}
892#endif
893
894static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
895{
896 DECLARE_BITMAP(val, MAX_LINE);
897 int ret;
898
899 ret = regcache_sync_region(chip->regmap, chip->regs->output,
900 chip->regs->output + NBANK(chip));
901 if (ret)
902 goto out;
903
904 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
905 chip->regs->direction + NBANK(chip));
906 if (ret)
907 goto out;
908
909 /* set platform specific polarity inversion */
910 if (invert)
911 bitmap_fill(val, MAX_LINE);
912 else
913 bitmap_zero(val, MAX_LINE);
914
915 ret = pca953x_write_regs(chip, chip->regs->invert, val);
916out:
917 return ret;
918}
919
920static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
921{
922 DECLARE_BITMAP(val, MAX_LINE);
923 unsigned int i;
924 int ret;
925
926 ret = device_pca95xx_init(chip, invert);
927 if (ret)
928 goto out;
929
930 /* To enable register 6, 7 to control pull up and pull down */
931 for (i = 0; i < NBANK(chip); i++)
932 bitmap_set_value8(val, 0x02, i * BANK_SZ);
933
934 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
935 if (ret)
936 goto out;
937
938 return 0;
939out:
940 return ret;
941}
942
943static int pca953x_probe(struct i2c_client *client,
944 const struct i2c_device_id *i2c_id)
945{
946 struct pca953x_platform_data *pdata;
947 struct pca953x_chip *chip;
948 int irq_base = 0;
949 int ret;
950 u32 invert = 0;
951 struct regulator *reg;
952 const struct regmap_config *regmap_config;
953
954 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
955 if (chip == NULL)
956 return -ENOMEM;
957
958 pdata = dev_get_platdata(&client->dev);
959 if (pdata) {
960 irq_base = pdata->irq_base;
961 chip->gpio_start = pdata->gpio_base;
962 invert = pdata->invert;
963 chip->names = pdata->names;
964 } else {
965 struct gpio_desc *reset_gpio;
966
967 chip->gpio_start = -1;
968 irq_base = 0;
969
970 /*
971 * See if we need to de-assert a reset pin.
972 *
973 * There is no known ACPI-enabled platforms that are
974 * using "reset" GPIO. Otherwise any of those platform
975 * must use _DSD method with corresponding property.
976 */
977 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
978 GPIOD_OUT_LOW);
979 if (IS_ERR(reset_gpio))
980 return PTR_ERR(reset_gpio);
981 }
982
983 chip->client = client;
984
985 reg = devm_regulator_get(&client->dev, "vcc");
986 if (IS_ERR(reg))
987 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
988
989 ret = regulator_enable(reg);
990 if (ret) {
991 dev_err(&client->dev, "reg en err: %d\n", ret);
992 return ret;
993 }
994 chip->regulator = reg;
995
996 if (i2c_id) {
997 chip->driver_data = i2c_id->driver_data;
998 } else {
999 const void *match;
1000
1001 match = device_get_match_data(&client->dev);
1002 if (!match) {
1003 ret = -ENODEV;
1004 goto err_exit;
1005 }
1006
1007 chip->driver_data = (uintptr_t)match;
1008 }
1009
1010 i2c_set_clientdata(client, chip);
1011
1012 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1013
1014 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1015 dev_info(&client->dev, "using AI\n");
1016 regmap_config = &pca953x_ai_i2c_regmap;
1017 } else {
1018 dev_info(&client->dev, "using no AI\n");
1019 regmap_config = &pca953x_i2c_regmap;
1020 }
1021
1022 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1023 if (IS_ERR(chip->regmap)) {
1024 ret = PTR_ERR(chip->regmap);
1025 goto err_exit;
1026 }
1027
1028 regcache_mark_dirty(chip->regmap);
1029
1030 mutex_init(&chip->i2c_lock);
1031 /*
1032 * In case we have an i2c-mux controlled by a GPIO provided by an
1033 * expander using the same driver higher on the device tree, read the
1034 * i2c adapter nesting depth and use the retrieved value as lockdep
1035 * subclass for chip->i2c_lock.
1036 *
1037 * REVISIT: This solution is not complete. It protects us from lockdep
1038 * false positives when the expander controlling the i2c-mux is on
1039 * a different level on the device tree, but not when it's on the same
1040 * level on a different branch (in which case the subclass number
1041 * would be the same).
1042 *
1043 * TODO: Once a correct solution is developed, a similar fix should be
1044 * applied to all other i2c-controlled GPIO expanders (and potentially
1045 * regmap-i2c).
1046 */
1047 lockdep_set_subclass(&chip->i2c_lock,
1048 i2c_adapter_depth(client->adapter));
1049
1050 /* initialize cached registers from their original values.
1051 * we can't share this chip with another i2c master.
1052 */
1053
1054 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
1055 chip->regs = &pca953x_regs;
1056 ret = device_pca95xx_init(chip, invert);
1057 } else {
1058 chip->regs = &pca957x_regs;
1059 ret = device_pca957x_init(chip, invert);
1060 }
1061 if (ret)
1062 goto err_exit;
1063
1064 ret = pca953x_irq_setup(chip, irq_base);
1065 if (ret)
1066 goto err_exit;
1067
1068 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1069 if (ret)
1070 goto err_exit;
1071
1072 if (pdata && pdata->setup) {
1073 ret = pdata->setup(client, chip->gpio_chip.base,
1074 chip->gpio_chip.ngpio, pdata->context);
1075 if (ret < 0)
1076 dev_warn(&client->dev, "setup failed, %d\n", ret);
1077 }
1078
1079 return 0;
1080
1081err_exit:
1082 regulator_disable(chip->regulator);
1083 return ret;
1084}
1085
1086static int pca953x_remove(struct i2c_client *client)
1087{
1088 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1089 struct pca953x_chip *chip = i2c_get_clientdata(client);
1090 int ret;
1091
1092 if (pdata && pdata->teardown) {
1093 ret = pdata->teardown(client, chip->gpio_chip.base,
1094 chip->gpio_chip.ngpio, pdata->context);
1095 if (ret < 0)
1096 dev_err(&client->dev, "teardown failed, %d\n", ret);
1097 } else {
1098 ret = 0;
1099 }
1100
1101 regulator_disable(chip->regulator);
1102
1103 return ret;
1104}
1105
1106#ifdef CONFIG_PM_SLEEP
1107static int pca953x_regcache_sync(struct device *dev)
1108{
1109 struct pca953x_chip *chip = dev_get_drvdata(dev);
1110 int ret;
1111
1112 /*
1113 * The ordering between direction and output is important,
1114 * sync these registers first and only then sync the rest.
1115 */
1116 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
1117 chip->regs->direction + NBANK(chip));
1118 if (ret) {
1119 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1120 return ret;
1121 }
1122
1123 ret = regcache_sync_region(chip->regmap, chip->regs->output,
1124 chip->regs->output + NBANK(chip));
1125 if (ret) {
1126 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1127 return ret;
1128 }
1129
1130#ifdef CONFIG_GPIO_PCA953X_IRQ
1131 if (chip->driver_data & PCA_PCAL) {
1132 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
1133 PCAL953X_IN_LATCH + NBANK(chip));
1134 if (ret) {
1135 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1136 ret);
1137 return ret;
1138 }
1139
1140 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
1141 PCAL953X_INT_MASK + NBANK(chip));
1142 if (ret) {
1143 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1144 ret);
1145 return ret;
1146 }
1147 }
1148#endif
1149
1150 return 0;
1151}
1152
1153static int pca953x_suspend(struct device *dev)
1154{
1155 struct pca953x_chip *chip = dev_get_drvdata(dev);
1156
1157 regcache_cache_only(chip->regmap, true);
1158
1159 if (atomic_read(&chip->wakeup_path))
1160 device_set_wakeup_path(dev);
1161 else
1162 regulator_disable(chip->regulator);
1163
1164 return 0;
1165}
1166
1167static int pca953x_resume(struct device *dev)
1168{
1169 struct pca953x_chip *chip = dev_get_drvdata(dev);
1170 int ret;
1171
1172 if (!atomic_read(&chip->wakeup_path)) {
1173 ret = regulator_enable(chip->regulator);
1174 if (ret) {
1175 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1176 return 0;
1177 }
1178 }
1179
1180 regcache_cache_only(chip->regmap, false);
1181 regcache_mark_dirty(chip->regmap);
1182 ret = pca953x_regcache_sync(dev);
1183 if (ret)
1184 return ret;
1185
1186 ret = regcache_sync(chip->regmap);
1187 if (ret) {
1188 dev_err(dev, "Failed to restore register map: %d\n", ret);
1189 return ret;
1190 }
1191
1192 return 0;
1193}
1194#endif
1195
1196/* convenience to stop overlong match-table lines */
1197#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1198#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1199
1200static const struct of_device_id pca953x_dt_ids[] = {
1201 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1202 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1203 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1204 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1205 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1206 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1207 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1208 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1209 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1210 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1211 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1212 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1213 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1214 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1215 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1216 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1217
1218 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1219 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1220 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1221 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1222 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1223
1224 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1225 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1226 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1227 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1228 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1229
1230 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1231 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1232 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1233 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1234 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1235 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1236
1237 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1238 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1239 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1240
1241 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1242 { }
1243};
1244
1245MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1246
1247static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1248
1249static struct i2c_driver pca953x_driver = {
1250 .driver = {
1251 .name = "pca953x",
1252 .pm = &pca953x_pm_ops,
1253 .of_match_table = pca953x_dt_ids,
1254 .acpi_match_table = pca953x_acpi_ids,
1255 },
1256 .probe = pca953x_probe,
1257 .remove = pca953x_remove,
1258 .id_table = pca953x_id,
1259};
1260
1261static int __init pca953x_init(void)
1262{
1263 return i2c_add_driver(&pca953x_driver);
1264}
1265/* register after i2c postcore initcall and before
1266 * subsys initcalls that may rely on these GPIOs
1267 */
1268subsys_initcall(pca953x_init);
1269
1270static void __exit pca953x_exit(void)
1271{
1272 i2c_del_driver(&pca953x_driver);
1273}
1274module_exit(pca953x_exit);
1275
1276MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1277MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1278MODULE_LICENSE("GPL");