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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H
4
5/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs.
8 *
9 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
10 */
11
12#define pte_ERROR(e) \
13 pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \
14 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15#define pmd_ERROR(e) \
16 pr_err("%s:%d: bad pmd %p(%016Lx)\n", \
17 __FILE__, __LINE__, &(e), pmd_val(e))
18#define pgd_ERROR(e) \
19 pr_err("%s:%d: bad pgd %p(%016Lx)\n", \
20 __FILE__, __LINE__, &(e), pgd_val(e))
21
22#define pxx_xchg64(_pxx, _ptr, _val) ({ \
23 _pxx##val_t *_p = (_pxx##val_t *)_ptr; \
24 _pxx##val_t _o = *_p; \
25 do { } while (!try_cmpxchg64(_p, &_o, (_val))); \
26 native_make_##_pxx(_o); \
27})
28
29/*
30 * Rules for using set_pte: the pte being assigned *must* be
31 * either not present or in a state where the hardware will
32 * not attempt to update the pte. In places where this is
33 * not possible, use pte_get_and_clear to obtain the old pte
34 * value and then use set_pte to update it. -ben
35 */
36static inline void native_set_pte(pte_t *ptep, pte_t pte)
37{
38 WRITE_ONCE(ptep->pte_high, pte.pte_high);
39 smp_wmb();
40 WRITE_ONCE(ptep->pte_low, pte.pte_low);
41}
42
43static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
44{
45 pxx_xchg64(pte, ptep, native_pte_val(pte));
46}
47
48static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
49{
50 pxx_xchg64(pmd, pmdp, native_pmd_val(pmd));
51}
52
53static inline void native_set_pud(pud_t *pudp, pud_t pud)
54{
55#ifdef CONFIG_PAGE_TABLE_ISOLATION
56 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
57#endif
58 pxx_xchg64(pud, pudp, native_pud_val(pud));
59}
60
61/*
62 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
63 * entry, so clear the bottom half first and enforce ordering with a compiler
64 * barrier.
65 */
66static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
67 pte_t *ptep)
68{
69 WRITE_ONCE(ptep->pte_low, 0);
70 smp_wmb();
71 WRITE_ONCE(ptep->pte_high, 0);
72}
73
74static inline void native_pmd_clear(pmd_t *pmdp)
75{
76 WRITE_ONCE(pmdp->pmd_low, 0);
77 smp_wmb();
78 WRITE_ONCE(pmdp->pmd_high, 0);
79}
80
81static inline void native_pud_clear(pud_t *pudp)
82{
83}
84
85static inline void pud_clear(pud_t *pudp)
86{
87 set_pud(pudp, __pud(0));
88
89 /*
90 * According to Intel App note "TLBs, Paging-Structure Caches,
91 * and Their Invalidation", April 2007, document 317080-001,
92 * section 8.1: in PAE mode we explicitly have to flush the
93 * TLB via cr3 if the top-level pgd is changed...
94 *
95 * Currently all places where pud_clear() is called either have
96 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
97 * pud_clear_bad()), so we don't need TLB flush here.
98 */
99}
100
101
102#ifdef CONFIG_SMP
103static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
104{
105 return pxx_xchg64(pte, ptep, 0ULL);
106}
107
108static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
109{
110 return pxx_xchg64(pmd, pmdp, 0ULL);
111}
112
113static inline pud_t native_pudp_get_and_clear(pud_t *pudp)
114{
115 return pxx_xchg64(pud, pudp, 0ULL);
116}
117#else
118#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
119#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
120#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
121#endif
122
123#ifndef pmdp_establish
124#define pmdp_establish pmdp_establish
125static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
126 unsigned long address, pmd_t *pmdp, pmd_t pmd)
127{
128 pmd_t old;
129
130 /*
131 * If pmd has present bit cleared we can get away without expensive
132 * cmpxchg64: we can update pmdp half-by-half without racing with
133 * anybody.
134 */
135 if (!(pmd_val(pmd) & _PAGE_PRESENT)) {
136 /* xchg acts as a barrier before setting of the high bits */
137 old.pmd_low = xchg(&pmdp->pmd_low, pmd.pmd_low);
138 old.pmd_high = READ_ONCE(pmdp->pmd_high);
139 WRITE_ONCE(pmdp->pmd_high, pmd.pmd_high);
140
141 return old;
142 }
143
144 return pxx_xchg64(pmd, pmdp, pmd.pmd);
145}
146#endif
147
148/* Encode and de-code a swap entry */
149#define SWP_TYPE_BITS 5
150
151#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
152
153/* We always extract/encode the offset by shifting it all the way up, and then down again */
154#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS)
155
156#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
157#define __swp_type(x) (((x).val) & ((1UL << SWP_TYPE_BITS) - 1))
158#define __swp_offset(x) ((x).val >> SWP_TYPE_BITS)
159#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << SWP_TYPE_BITS})
160
161/*
162 * Normally, __swp_entry() converts from arch-independent swp_entry_t to
163 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result
164 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the
165 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to
166 * __swp_entry_to_pte() through the following helper macro based on 64bit
167 * __swp_entry().
168 */
169#define __swp_pteval_entry(type, offset) ((pteval_t) { \
170 (~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
171 | ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) })
172
173#define __swp_entry_to_pte(x) ((pte_t){ .pte = \
174 __swp_pteval_entry(__swp_type(x), __swp_offset(x)) })
175/*
176 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent
177 * swp_entry_t, but also has to convert it from 64bit to the 32bit
178 * intermediate representation, using the following macros based on 64bit
179 * __swp_type() and __swp_offset().
180 */
181#define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS)))
182#define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT))
183
184#define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \
185 __pteval_swp_offset(pte)))
186
187#include <asm/pgtable-invert.h>
188
189#endif /* _ASM_X86_PGTABLE_3LEVEL_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H
4
5#include <asm/atomic64_32.h>
6
7/*
8 * Intel Physical Address Extension (PAE) Mode - three-level page
9 * tables on PPro+ CPUs.
10 *
11 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
12 */
13
14#define pte_ERROR(e) \
15 pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \
16 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
17#define pmd_ERROR(e) \
18 pr_err("%s:%d: bad pmd %p(%016Lx)\n", \
19 __FILE__, __LINE__, &(e), pmd_val(e))
20#define pgd_ERROR(e) \
21 pr_err("%s:%d: bad pgd %p(%016Lx)\n", \
22 __FILE__, __LINE__, &(e), pgd_val(e))
23
24/* Rules for using set_pte: the pte being assigned *must* be
25 * either not present or in a state where the hardware will
26 * not attempt to update the pte. In places where this is
27 * not possible, use pte_get_and_clear to obtain the old pte
28 * value and then use set_pte to update it. -ben
29 */
30static inline void native_set_pte(pte_t *ptep, pte_t pte)
31{
32 ptep->pte_high = pte.pte_high;
33 smp_wmb();
34 ptep->pte_low = pte.pte_low;
35}
36
37#define pmd_read_atomic pmd_read_atomic
38/*
39 * pte_offset_map_lock() on 32-bit PAE kernels was reading the pmd_t with
40 * a "*pmdp" dereference done by GCC. Problem is, in certain places
41 * where pte_offset_map_lock() is called, concurrent page faults are
42 * allowed, if the mmap_lock is hold for reading. An example is mincore
43 * vs page faults vs MADV_DONTNEED. On the page fault side
44 * pmd_populate() rightfully does a set_64bit(), but if we're reading the
45 * pmd_t with a "*pmdp" on the mincore side, a SMP race can happen
46 * because GCC will not read the 64-bit value of the pmd atomically.
47 *
48 * To fix this all places running pte_offset_map_lock() while holding the
49 * mmap_lock in read mode, shall read the pmdp pointer using this
50 * function to know if the pmd is null or not, and in turn to know if
51 * they can run pte_offset_map_lock() or pmd_trans_huge() or other pmd
52 * operations.
53 *
54 * Without THP if the mmap_lock is held for reading, the pmd can only
55 * transition from null to not null while pmd_read_atomic() runs. So
56 * we can always return atomic pmd values with this function.
57 *
58 * With THP if the mmap_lock is held for reading, the pmd can become
59 * trans_huge or none or point to a pte (and in turn become "stable")
60 * at any time under pmd_read_atomic(). We could read it truly
61 * atomically here with an atomic64_read() for the THP enabled case (and
62 * it would be a whole lot simpler), but to avoid using cmpxchg8b we
63 * only return an atomic pmdval if the low part of the pmdval is later
64 * found to be stable (i.e. pointing to a pte). We are also returning a
65 * 'none' (zero) pmdval if the low part of the pmd is zero.
66 *
67 * In some cases the high and low part of the pmdval returned may not be
68 * consistent if THP is enabled (the low part may point to previously
69 * mapped hugepage, while the high part may point to a more recently
70 * mapped hugepage), but pmd_none_or_trans_huge_or_clear_bad() only
71 * needs the low part of the pmd to be read atomically to decide if the
72 * pmd is unstable or not, with the only exception when the low part
73 * of the pmd is zero, in which case we return a 'none' pmd.
74 */
75static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
76{
77 pmdval_t ret;
78 u32 *tmp = (u32 *)pmdp;
79
80 ret = (pmdval_t) (*tmp);
81 if (ret) {
82 /*
83 * If the low part is null, we must not read the high part
84 * or we can end up with a partial pmd.
85 */
86 smp_rmb();
87 ret |= ((pmdval_t)*(tmp + 1)) << 32;
88 }
89
90 return (pmd_t) { ret };
91}
92
93static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
94{
95 set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
96}
97
98static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
99{
100 set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
101}
102
103static inline void native_set_pud(pud_t *pudp, pud_t pud)
104{
105#ifdef CONFIG_PAGE_TABLE_ISOLATION
106 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
107#endif
108 set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
109}
110
111/*
112 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
113 * entry, so clear the bottom half first and enforce ordering with a compiler
114 * barrier.
115 */
116static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
117 pte_t *ptep)
118{
119 ptep->pte_low = 0;
120 smp_wmb();
121 ptep->pte_high = 0;
122}
123
124static inline void native_pmd_clear(pmd_t *pmd)
125{
126 u32 *tmp = (u32 *)pmd;
127 *tmp = 0;
128 smp_wmb();
129 *(tmp + 1) = 0;
130}
131
132static inline void native_pud_clear(pud_t *pudp)
133{
134}
135
136static inline void pud_clear(pud_t *pudp)
137{
138 set_pud(pudp, __pud(0));
139
140 /*
141 * According to Intel App note "TLBs, Paging-Structure Caches,
142 * and Their Invalidation", April 2007, document 317080-001,
143 * section 8.1: in PAE mode we explicitly have to flush the
144 * TLB via cr3 if the top-level pgd is changed...
145 *
146 * Currently all places where pud_clear() is called either have
147 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
148 * pud_clear_bad()), so we don't need TLB flush here.
149 */
150}
151
152#ifdef CONFIG_SMP
153static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
154{
155 pte_t res;
156
157 res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
158
159 return res;
160}
161#else
162#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
163#endif
164
165union split_pmd {
166 struct {
167 u32 pmd_low;
168 u32 pmd_high;
169 };
170 pmd_t pmd;
171};
172
173#ifdef CONFIG_SMP
174static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
175{
176 union split_pmd res, *orig = (union split_pmd *)pmdp;
177
178 /* xchg acts as a barrier before setting of the high bits */
179 res.pmd_low = xchg(&orig->pmd_low, 0);
180 res.pmd_high = orig->pmd_high;
181 orig->pmd_high = 0;
182
183 return res.pmd;
184}
185#else
186#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
187#endif
188
189#ifndef pmdp_establish
190#define pmdp_establish pmdp_establish
191static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
192 unsigned long address, pmd_t *pmdp, pmd_t pmd)
193{
194 pmd_t old;
195
196 /*
197 * If pmd has present bit cleared we can get away without expensive
198 * cmpxchg64: we can update pmdp half-by-half without racing with
199 * anybody.
200 */
201 if (!(pmd_val(pmd) & _PAGE_PRESENT)) {
202 union split_pmd old, new, *ptr;
203
204 ptr = (union split_pmd *)pmdp;
205
206 new.pmd = pmd;
207
208 /* xchg acts as a barrier before setting of the high bits */
209 old.pmd_low = xchg(&ptr->pmd_low, new.pmd_low);
210 old.pmd_high = ptr->pmd_high;
211 ptr->pmd_high = new.pmd_high;
212 return old.pmd;
213 }
214
215 do {
216 old = *pmdp;
217 } while (cmpxchg64(&pmdp->pmd, old.pmd, pmd.pmd) != old.pmd);
218
219 return old;
220}
221#endif
222
223#ifdef CONFIG_SMP
224union split_pud {
225 struct {
226 u32 pud_low;
227 u32 pud_high;
228 };
229 pud_t pud;
230};
231
232static inline pud_t native_pudp_get_and_clear(pud_t *pudp)
233{
234 union split_pud res, *orig = (union split_pud *)pudp;
235
236#ifdef CONFIG_PAGE_TABLE_ISOLATION
237 pti_set_user_pgtbl(&pudp->p4d.pgd, __pgd(0));
238#endif
239
240 /* xchg acts as a barrier before setting of the high bits */
241 res.pud_low = xchg(&orig->pud_low, 0);
242 res.pud_high = orig->pud_high;
243 orig->pud_high = 0;
244
245 return res.pud;
246}
247#else
248#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
249#endif
250
251/* Encode and de-code a swap entry */
252#define SWP_TYPE_BITS 5
253
254#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
255
256/* We always extract/encode the offset by shifting it all the way up, and then down again */
257#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS)
258
259#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
260#define __swp_type(x) (((x).val) & 0x1f)
261#define __swp_offset(x) ((x).val >> 5)
262#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
263
264/*
265 * Normally, __swp_entry() converts from arch-independent swp_entry_t to
266 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result
267 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the
268 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to
269 * __swp_entry_to_pte() through the following helper macro based on 64bit
270 * __swp_entry().
271 */
272#define __swp_pteval_entry(type, offset) ((pteval_t) { \
273 (~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
274 | ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) })
275
276#define __swp_entry_to_pte(x) ((pte_t){ .pte = \
277 __swp_pteval_entry(__swp_type(x), __swp_offset(x)) })
278/*
279 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent
280 * swp_entry_t, but also has to convert it from 64bit to the 32bit
281 * intermediate representation, using the following macros based on 64bit
282 * __swp_type() and __swp_offset().
283 */
284#define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS)))
285#define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT))
286
287#define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \
288 __pteval_swp_offset(pte)))
289
290#include <asm/pgtable-invert.h>
291
292#endif /* _ASM_X86_PGTABLE_3LEVEL_H */