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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H
4
5/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs.
8 *
9 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
10 */
11
12#define pte_ERROR(e) \
13 pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \
14 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15#define pmd_ERROR(e) \
16 pr_err("%s:%d: bad pmd %p(%016Lx)\n", \
17 __FILE__, __LINE__, &(e), pmd_val(e))
18#define pgd_ERROR(e) \
19 pr_err("%s:%d: bad pgd %p(%016Lx)\n", \
20 __FILE__, __LINE__, &(e), pgd_val(e))
21
22#define pxx_xchg64(_pxx, _ptr, _val) ({ \
23 _pxx##val_t *_p = (_pxx##val_t *)_ptr; \
24 _pxx##val_t _o = *_p; \
25 do { } while (!try_cmpxchg64(_p, &_o, (_val))); \
26 native_make_##_pxx(_o); \
27})
28
29/*
30 * Rules for using set_pte: the pte being assigned *must* be
31 * either not present or in a state where the hardware will
32 * not attempt to update the pte. In places where this is
33 * not possible, use pte_get_and_clear to obtain the old pte
34 * value and then use set_pte to update it. -ben
35 */
36static inline void native_set_pte(pte_t *ptep, pte_t pte)
37{
38 WRITE_ONCE(ptep->pte_high, pte.pte_high);
39 smp_wmb();
40 WRITE_ONCE(ptep->pte_low, pte.pte_low);
41}
42
43static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
44{
45 pxx_xchg64(pte, ptep, native_pte_val(pte));
46}
47
48static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
49{
50 pxx_xchg64(pmd, pmdp, native_pmd_val(pmd));
51}
52
53static inline void native_set_pud(pud_t *pudp, pud_t pud)
54{
55#ifdef CONFIG_PAGE_TABLE_ISOLATION
56 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
57#endif
58 pxx_xchg64(pud, pudp, native_pud_val(pud));
59}
60
61/*
62 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
63 * entry, so clear the bottom half first and enforce ordering with a compiler
64 * barrier.
65 */
66static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
67 pte_t *ptep)
68{
69 WRITE_ONCE(ptep->pte_low, 0);
70 smp_wmb();
71 WRITE_ONCE(ptep->pte_high, 0);
72}
73
74static inline void native_pmd_clear(pmd_t *pmdp)
75{
76 WRITE_ONCE(pmdp->pmd_low, 0);
77 smp_wmb();
78 WRITE_ONCE(pmdp->pmd_high, 0);
79}
80
81static inline void native_pud_clear(pud_t *pudp)
82{
83}
84
85static inline void pud_clear(pud_t *pudp)
86{
87 set_pud(pudp, __pud(0));
88
89 /*
90 * According to Intel App note "TLBs, Paging-Structure Caches,
91 * and Their Invalidation", April 2007, document 317080-001,
92 * section 8.1: in PAE mode we explicitly have to flush the
93 * TLB via cr3 if the top-level pgd is changed...
94 *
95 * Currently all places where pud_clear() is called either have
96 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
97 * pud_clear_bad()), so we don't need TLB flush here.
98 */
99}
100
101
102#ifdef CONFIG_SMP
103static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
104{
105 return pxx_xchg64(pte, ptep, 0ULL);
106}
107
108static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
109{
110 return pxx_xchg64(pmd, pmdp, 0ULL);
111}
112
113static inline pud_t native_pudp_get_and_clear(pud_t *pudp)
114{
115 return pxx_xchg64(pud, pudp, 0ULL);
116}
117#else
118#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
119#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
120#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
121#endif
122
123#ifndef pmdp_establish
124#define pmdp_establish pmdp_establish
125static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
126 unsigned long address, pmd_t *pmdp, pmd_t pmd)
127{
128 pmd_t old;
129
130 /*
131 * If pmd has present bit cleared we can get away without expensive
132 * cmpxchg64: we can update pmdp half-by-half without racing with
133 * anybody.
134 */
135 if (!(pmd_val(pmd) & _PAGE_PRESENT)) {
136 /* xchg acts as a barrier before setting of the high bits */
137 old.pmd_low = xchg(&pmdp->pmd_low, pmd.pmd_low);
138 old.pmd_high = READ_ONCE(pmdp->pmd_high);
139 WRITE_ONCE(pmdp->pmd_high, pmd.pmd_high);
140
141 return old;
142 }
143
144 return pxx_xchg64(pmd, pmdp, pmd.pmd);
145}
146#endif
147
148/* Encode and de-code a swap entry */
149#define SWP_TYPE_BITS 5
150
151#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
152
153/* We always extract/encode the offset by shifting it all the way up, and then down again */
154#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS)
155
156#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
157#define __swp_type(x) (((x).val) & ((1UL << SWP_TYPE_BITS) - 1))
158#define __swp_offset(x) ((x).val >> SWP_TYPE_BITS)
159#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << SWP_TYPE_BITS})
160
161/*
162 * Normally, __swp_entry() converts from arch-independent swp_entry_t to
163 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result
164 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the
165 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to
166 * __swp_entry_to_pte() through the following helper macro based on 64bit
167 * __swp_entry().
168 */
169#define __swp_pteval_entry(type, offset) ((pteval_t) { \
170 (~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
171 | ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) })
172
173#define __swp_entry_to_pte(x) ((pte_t){ .pte = \
174 __swp_pteval_entry(__swp_type(x), __swp_offset(x)) })
175/*
176 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent
177 * swp_entry_t, but also has to convert it from 64bit to the 32bit
178 * intermediate representation, using the following macros based on 64bit
179 * __swp_type() and __swp_offset().
180 */
181#define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS)))
182#define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT))
183
184#define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \
185 __pteval_swp_offset(pte)))
186
187#include <asm/pgtable-invert.h>
188
189#endif /* _ASM_X86_PGTABLE_3LEVEL_H */
1#ifndef _ASM_X86_PGTABLE_3LEVEL_H
2#define _ASM_X86_PGTABLE_3LEVEL_H
3
4/*
5 * Intel Physical Address Extension (PAE) Mode - three-level page
6 * tables on PPro+ CPUs.
7 *
8 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
9 */
10
11#define pte_ERROR(e) \
12 printk("%s:%d: bad pte %p(%08lx%08lx).\n", \
13 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
14#define pmd_ERROR(e) \
15 printk("%s:%d: bad pmd %p(%016Lx).\n", \
16 __FILE__, __LINE__, &(e), pmd_val(e))
17#define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", \
19 __FILE__, __LINE__, &(e), pgd_val(e))
20
21/* Rules for using set_pte: the pte being assigned *must* be
22 * either not present or in a state where the hardware will
23 * not attempt to update the pte. In places where this is
24 * not possible, use pte_get_and_clear to obtain the old pte
25 * value and then use set_pte to update it. -ben
26 */
27static inline void native_set_pte(pte_t *ptep, pte_t pte)
28{
29 ptep->pte_high = pte.pte_high;
30 smp_wmb();
31 ptep->pte_low = pte.pte_low;
32}
33
34static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
35{
36 set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
37}
38
39static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
40{
41 set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
42}
43
44static inline void native_set_pud(pud_t *pudp, pud_t pud)
45{
46 set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
47}
48
49/*
50 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
51 * entry, so clear the bottom half first and enforce ordering with a compiler
52 * barrier.
53 */
54static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
55 pte_t *ptep)
56{
57 ptep->pte_low = 0;
58 smp_wmb();
59 ptep->pte_high = 0;
60}
61
62static inline void native_pmd_clear(pmd_t *pmd)
63{
64 u32 *tmp = (u32 *)pmd;
65 *tmp = 0;
66 smp_wmb();
67 *(tmp + 1) = 0;
68}
69
70static inline void pud_clear(pud_t *pudp)
71{
72 set_pud(pudp, __pud(0));
73
74 /*
75 * According to Intel App note "TLBs, Paging-Structure Caches,
76 * and Their Invalidation", April 2007, document 317080-001,
77 * section 8.1: in PAE mode we explicitly have to flush the
78 * TLB via cr3 if the top-level pgd is changed...
79 *
80 * Currently all places where pud_clear() is called either have
81 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
82 * pud_clear_bad()), so we don't need TLB flush here.
83 */
84}
85
86#ifdef CONFIG_SMP
87static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
88{
89 pte_t res;
90
91 /* xchg acts as a barrier before the setting of the high bits */
92 res.pte_low = xchg(&ptep->pte_low, 0);
93 res.pte_high = ptep->pte_high;
94 ptep->pte_high = 0;
95
96 return res;
97}
98#else
99#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
100#endif
101
102#ifdef CONFIG_SMP
103union split_pmd {
104 struct {
105 u32 pmd_low;
106 u32 pmd_high;
107 };
108 pmd_t pmd;
109};
110static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
111{
112 union split_pmd res, *orig = (union split_pmd *)pmdp;
113
114 /* xchg acts as a barrier before setting of the high bits */
115 res.pmd_low = xchg(&orig->pmd_low, 0);
116 res.pmd_high = orig->pmd_high;
117 orig->pmd_high = 0;
118
119 return res.pmd;
120}
121#else
122#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
123#endif
124
125/*
126 * Bits 0, 6 and 7 are taken in the low part of the pte,
127 * put the 32 bits of offset into the high part.
128 */
129#define pte_to_pgoff(pte) ((pte).pte_high)
130#define pgoff_to_pte(off) \
131 ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
132#define PTE_FILE_MAX_BITS 32
133
134/* Encode and de-code a swap entry */
135#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
136#define __swp_type(x) (((x).val) & 0x1f)
137#define __swp_offset(x) ((x).val >> 5)
138#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
139#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
140#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
141
142#endif /* _ASM_X86_PGTABLE_3LEVEL_H */