Loading...
1# SPDX-License-Identifier: GPL-2.0-only
2menu "Platform options"
3
4comment "Memory settings"
5
6config NIOS2_MEM_BASE
7 hex "Memory base address"
8 default "0x00000000"
9 help
10 This is the physical address of the memory that the kernel will run
11 from. This address is used to link the kernel and setup initial memory
12 management. You should take the raw memory address without any MMU
13 or cache bits set.
14 Please not that this address is used directly so you have to manually
15 do address translation if it's connected to a bridge.
16
17comment "Device tree"
18
19config NIOS2_DTB_AT_PHYS_ADDR
20 bool "DTB at physical address"
21 help
22 When enabled you can select a physical address to load the dtb from.
23 Normally this address is passed by a bootloader such as u-boot but
24 using this you can use a devicetree without a bootloader.
25 This way you can store a devicetree in NOR flash or an onchip rom.
26 Please note that this address is used directly so you have to manually
27 do address translation if it's connected to a bridge. Also take into
28 account that when using an MMU you'd have to ad 0xC0000000 to your
29 address
30
31config NIOS2_DTB_PHYS_ADDR
32 hex "DTB Address"
33 depends on NIOS2_DTB_AT_PHYS_ADDR
34 default "0xC0000000"
35 help
36 Physical address of a dtb blob.
37
38config NIOS2_DTB_SOURCE_BOOL
39 bool "Compile and link device tree into kernel image"
40 depends on !COMPILE_TEST
41 help
42 This allows you to specify a dts (device tree source) file
43 which will be compiled and linked into the kernel image.
44
45config NIOS2_DTB_SOURCE
46 string "Device tree source file"
47 depends on NIOS2_DTB_SOURCE_BOOL
48 default ""
49 help
50 Absolute path to the device tree source (dts) file describing your
51 system.
52
53comment "Nios II instructions"
54
55config NIOS2_ARCH_REVISION
56 int "Select Nios II architecture revision"
57 range 1 2
58 default 1
59 help
60 Select between Nios II R1 and Nios II R2 . The architectures
61 are binary incompatible. Default is R1 .
62
63config NIOS2_HW_MUL_SUPPORT
64 bool "Enable MUL instruction"
65 help
66 Set to true if you configured the Nios II to include the MUL
67 instruction. This will enable the -mhw-mul compiler flag.
68
69config NIOS2_HW_MULX_SUPPORT
70 bool "Enable MULX instruction"
71 help
72 Set to true if you configured the Nios II to include the MULX
73 instruction. Enables the -mhw-mulx compiler flag.
74
75config NIOS2_HW_DIV_SUPPORT
76 bool "Enable DIV instruction"
77 help
78 Set to true if you configured the Nios II to include the DIV
79 instruction. Enables the -mhw-div compiler flag.
80
81config NIOS2_BMX_SUPPORT
82 bool "Enable BMX instructions"
83 depends on NIOS2_ARCH_REVISION = 2
84 help
85 Set to true if you configured the Nios II R2 to include
86 the BMX Bit Manipulation Extension instructions. Enables
87 the -mbmx compiler flag.
88
89config NIOS2_CDX_SUPPORT
90 bool "Enable CDX instructions"
91 depends on NIOS2_ARCH_REVISION = 2
92 help
93 Set to true if you configured the Nios II R2 to include
94 the CDX Bit Manipulation Extension instructions. Enables
95 the -mcdx compiler flag.
96
97config NIOS2_FPU_SUPPORT
98 bool "Custom floating point instr support"
99 help
100 Enables the -mcustom-fpu-cfg=60-1 compiler flag.
101
102config NIOS2_CI_SWAB_SUPPORT
103 bool "Byteswap custom instruction"
104 help
105 Use the byteswap (endian converter) Nios II custom instruction provided
106 by Altera and which can be enabled in QSYS builder. This accelerates
107 endian conversions in the kernel (e.g. ntohs).
108
109config NIOS2_CI_SWAB_NO
110 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
111 default 0
112 help
113 Number of the instruction as configured in QSYS Builder.
114
115comment "Cache settings"
116
117config CUSTOM_CACHE_SETTINGS
118 bool "Custom cache settings"
119 help
120 This option allows you to tweak the cache settings used during early
121 boot (where the information from device tree is not yet available).
122 There should be no reason to change these values. Linux will work
123 perfectly fine, even if the Nios II is configured with smaller caches.
124
125 Say N here unless you know what you are doing.
126
127config NIOS2_DCACHE_SIZE
128 hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
129 range 0x200 0x10000
130 default "0x800"
131 help
132 Maximum possible data cache size.
133
134config NIOS2_DCACHE_LINE_SIZE
135 hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
136 range 0x10 0x20
137 default "0x20"
138 help
139 Minimum possible data cache line size.
140
141config NIOS2_ICACHE_SIZE
142 hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
143 range 0x200 0x10000
144 default "0x1000"
145 help
146 Maximum possible instruction cache size.
147
148endmenu
1# SPDX-License-Identifier: GPL-2.0-only
2menu "Platform options"
3
4comment "Memory settings"
5
6config NIOS2_MEM_BASE
7 hex "Memory base address"
8 default "0x00000000"
9 help
10 This is the physical address of the memory that the kernel will run
11 from. This address is used to link the kernel and setup initial memory
12 management. You should take the raw memory address without any MMU
13 or cache bits set.
14 Please not that this address is used directly so you have to manually
15 do address translation if it's connected to a bridge.
16
17comment "Device tree"
18
19config NIOS2_DTB_AT_PHYS_ADDR
20 bool "DTB at physical address"
21 help
22 When enabled you can select a physical address to load the dtb from.
23 Normally this address is passed by a bootloader such as u-boot but
24 using this you can use a devicetree without a bootloader.
25 This way you can store a devicetree in NOR flash or an onchip rom.
26 Please note that this address is used directly so you have to manually
27 do address translation if it's connected to a bridge. Also take into
28 account that when using an MMU you'd have to ad 0xC0000000 to your
29 address
30
31config NIOS2_DTB_PHYS_ADDR
32 hex "DTB Address"
33 depends on NIOS2_DTB_AT_PHYS_ADDR
34 default "0xC0000000"
35 help
36 Physical address of a dtb blob.
37
38config NIOS2_DTB_SOURCE_BOOL
39 bool "Compile and link device tree into kernel image"
40 help
41 This allows you to specify a dts (device tree source) file
42 which will be compiled and linked into the kernel image.
43
44config NIOS2_DTB_SOURCE
45 string "Device tree source file"
46 depends on NIOS2_DTB_SOURCE_BOOL
47 default ""
48 help
49 Absolute path to the device tree source (dts) file describing your
50 system.
51
52comment "Nios II instructions"
53
54config NIOS2_ARCH_REVISION
55 int "Select Nios II architecture revision"
56 range 1 2
57 default 1
58 help
59 Select between Nios II R1 and Nios II R2 . The architectures
60 are binary incompatible. Default is R1 .
61
62config NIOS2_HW_MUL_SUPPORT
63 bool "Enable MUL instruction"
64 help
65 Set to true if you configured the Nios II to include the MUL
66 instruction. This will enable the -mhw-mul compiler flag.
67
68config NIOS2_HW_MULX_SUPPORT
69 bool "Enable MULX instruction"
70 help
71 Set to true if you configured the Nios II to include the MULX
72 instruction. Enables the -mhw-mulx compiler flag.
73
74config NIOS2_HW_DIV_SUPPORT
75 bool "Enable DIV instruction"
76 help
77 Set to true if you configured the Nios II to include the DIV
78 instruction. Enables the -mhw-div compiler flag.
79
80config NIOS2_BMX_SUPPORT
81 bool "Enable BMX instructions"
82 depends on NIOS2_ARCH_REVISION = 2
83 help
84 Set to true if you configured the Nios II R2 to include
85 the BMX Bit Manipulation Extension instructions. Enables
86 the -mbmx compiler flag.
87
88config NIOS2_CDX_SUPPORT
89 bool "Enable CDX instructions"
90 depends on NIOS2_ARCH_REVISION = 2
91 help
92 Set to true if you configured the Nios II R2 to include
93 the CDX Bit Manipulation Extension instructions. Enables
94 the -mcdx compiler flag.
95
96config NIOS2_FPU_SUPPORT
97 bool "Custom floating point instr support"
98 help
99 Enables the -mcustom-fpu-cfg=60-1 compiler flag.
100
101config NIOS2_CI_SWAB_SUPPORT
102 bool "Byteswap custom instruction"
103 help
104 Use the byteswap (endian converter) Nios II custom instruction provided
105 by Altera and which can be enabled in QSYS builder. This accelerates
106 endian conversions in the kernel (e.g. ntohs).
107
108config NIOS2_CI_SWAB_NO
109 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
110 default 0
111 help
112 Number of the instruction as configured in QSYS Builder.
113
114comment "Cache settings"
115
116config CUSTOM_CACHE_SETTINGS
117 bool "Custom cache settings"
118 help
119 This option allows you to tweak the cache settings used during early
120 boot (where the information from device tree is not yet available).
121 There should be no reason to change these values. Linux will work
122 perfectly fine, even if the Nios II is configured with smaller caches.
123
124 Say N here unless you know what you are doing.
125
126config NIOS2_DCACHE_SIZE
127 hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
128 range 0x200 0x10000
129 default "0x800"
130 help
131 Maximum possible data cache size.
132
133config NIOS2_DCACHE_LINE_SIZE
134 hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
135 range 0x10 0x20
136 default "0x20"
137 help
138 Minimum possible data cache line size.
139
140config NIOS2_ICACHE_SIZE
141 hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
142 range 0x200 0x10000
143 default "0x1000"
144 help
145 Maximum possible instruction cache size.
146
147endmenu