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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018 NXP
5 */
6
7/dts-v1/;
8#include "ls1021a.dtsi"
9
10/ {
11 model = "LS1021A TWR Board";
12 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
13
14 aliases {
15 enet2_rgmii_phy = &rgmii_phy1;
16 enet0_sgmii_phy = &sgmii_phy2;
17 enet1_sgmii_phy = &sgmii_phy0;
18 };
19
20 sys_mclk: clock-mclk {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24576000>;
24 };
25
26 reg_3p3v: regulator {
27 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-always-on;
32 };
33
34 sound {
35 compatible = "simple-audio-card";
36 simple-audio-card,format = "i2s";
37 simple-audio-card,widgets =
38 "Microphone", "Microphone Jack",
39 "Headphone", "Headphone Jack",
40 "Speaker", "Speaker Ext",
41 "Line", "Line In Jack";
42 simple-audio-card,routing =
43 "MIC_IN", "Microphone Jack",
44 "Microphone Jack", "Mic Bias",
45 "LINE_IN", "Line In Jack",
46 "Headphone Jack", "HP_OUT",
47 "Speaker Ext", "LINE_OUT";
48
49 simple-audio-card,cpu {
50 sound-dai = <&sai1>;
51 frame-master;
52 bitclock-master;
53 };
54
55 simple-audio-card,codec {
56 sound-dai = <&codec>;
57 frame-master;
58 bitclock-master;
59 };
60 };
61
62 panel: panel {
63 compatible = "nec,nl4827hc19-05b";
64
65 port {
66 panel_in: endpoint {
67 remote-endpoint = <&dcu_out>;
68 };
69 };
70 };
71};
72
73&dcu {
74 status = "okay";
75
76 port {
77 dcu_out: endpoint {
78 remote-endpoint = <&panel_in>;
79 };
80 };
81};
82
83&dspi1 {
84 bus-num = <0>;
85 status = "okay";
86
87 dspiflash: s25fl064k@0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "spansion,s25fl064k";
91 spi-max-frequency = <16000000>;
92 spi-cpol;
93 spi-cpha;
94 reg = <0>;
95 };
96};
97
98&enet0 {
99 tbi-handle = <&tbi0>;
100 phy-handle = <&sgmii_phy2>;
101 phy-connection-type = "sgmii";
102 status = "okay";
103};
104
105&enet1 {
106 tbi-handle = <&tbi1>;
107 phy-handle = <&sgmii_phy0>;
108 phy-connection-type = "sgmii";
109 status = "okay";
110};
111
112&enet2 {
113 phy-handle = <&rgmii_phy1>;
114 phy-connection-type = "rgmii-id";
115 status = "okay";
116};
117
118&i2c0 {
119 status = "okay";
120
121 ina220@40 {
122 compatible = "ti,ina220";
123 reg = <0x40>;
124 shunt-resistor = <1000>;
125 };
126
127 ina220@41 {
128 compatible = "ti,ina220";
129 reg = <0x41>;
130 shunt-resistor = <1000>;
131 };
132
133};
134
135&i2c1 {
136 status = "okay";
137 codec: sgtl5000@a {
138 #sound-dai-cells = <0>;
139 compatible = "fsl,sgtl5000";
140 reg = <0x0a>;
141 VDDA-supply = <®_3p3v>;
142 VDDIO-supply = <®_3p3v>;
143 clocks = <&sys_mclk>;
144 };
145};
146
147&ifc {
148 #address-cells = <2>;
149 #size-cells = <1>;
150 /* NOR Flash on board */
151 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
152 status = "okay";
153
154 nor@0,0 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "cfi-flash";
158 reg = <0x0 0x0 0x8000000>;
159 big-endian;
160 bank-width = <2>;
161 device-width = <1>;
162 };
163};
164
165&lpuart0 {
166 status = "okay";
167};
168
169&mdio0 {
170 sgmii_phy0: ethernet-phy@0 {
171 reg = <0x0>;
172 };
173 rgmii_phy1: ethernet-phy@1 {
174 reg = <0x1>;
175 };
176 sgmii_phy2: ethernet-phy@2 {
177 reg = <0x2>;
178 };
179 tbi0: tbi-phy@1f {
180 reg = <0x1f>;
181 device_type = "tbi-phy";
182 };
183};
184
185&mdio1 {
186 tbi1: tbi-phy@1f {
187 reg = <0x1f>;
188 device_type = "tbi-phy";
189 };
190};
191
192&esdhc {
193 status = "okay";
194};
195
196&qspi {
197 status = "okay";
198
199 n25q128a130: flash@0 {
200 compatible = "jedec,spi-nor";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 spi-max-frequency = <50000000>;
204 reg = <0>;
205 spi-rx-bus-width = <4>;
206 spi-tx-bus-width = <4>;
207 };
208};
209
210&sai1 {
211 status = "okay";
212};
213
214&sata {
215 status = "okay";
216};
217
218&uart0 {
219 status = "okay";
220};
221
222&uart1 {
223 status = "okay";
224};
225
226&can0 {
227 status = "okay";
228};
229
230&can1 {
231 status = "okay";
232};
233
234&can2 {
235 status = "disabled";
236};
237
238&can3 {
239 status = "disabled";
240};
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 * Copyright 2018 NXP
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include "ls1021a.dtsi"
51
52/ {
53 model = "LS1021A TWR Board";
54 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
55
56 aliases {
57 enet2_rgmii_phy = &rgmii_phy1;
58 enet0_sgmii_phy = &sgmii_phy2;
59 enet1_sgmii_phy = &sgmii_phy0;
60 };
61
62 sys_mclk: clock-mclk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <24576000>;
66 };
67
68 regulators {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 reg_3p3v: regulator@0 {
74 compatible = "regulator-fixed";
75 reg = <0>;
76 regulator-name = "3P3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-always-on;
80 };
81 };
82
83 sound {
84 compatible = "simple-audio-card";
85 simple-audio-card,format = "i2s";
86 simple-audio-card,widgets =
87 "Microphone", "Microphone Jack",
88 "Headphone", "Headphone Jack",
89 "Speaker", "Speaker Ext",
90 "Line", "Line In Jack";
91 simple-audio-card,routing =
92 "MIC_IN", "Microphone Jack",
93 "Microphone Jack", "Mic Bias",
94 "LINE_IN", "Line In Jack",
95 "Headphone Jack", "HP_OUT",
96 "Speaker Ext", "LINE_OUT";
97
98 simple-audio-card,cpu {
99 sound-dai = <&sai1>;
100 frame-master;
101 bitclock-master;
102 };
103
104 simple-audio-card,codec {
105 sound-dai = <&codec>;
106 frame-master;
107 bitclock-master;
108 };
109 };
110
111 panel: panel {
112 compatible = "nec,nl4827hc19-05b";
113
114 port {
115 panel_in: endpoint {
116 remote-endpoint = <&dcu_out>;
117 };
118 };
119 };
120};
121
122&dcu {
123 status = "okay";
124
125 port {
126 dcu_out: endpoint {
127 remote-endpoint = <&panel_in>;
128 };
129 };
130};
131
132&dspi1 {
133 bus-num = <0>;
134 status = "okay";
135
136 dspiflash: s25fl064k@0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "spansion,s25fl064k";
140 spi-max-frequency = <16000000>;
141 spi-cpol;
142 spi-cpha;
143 reg = <0>;
144 };
145};
146
147&enet0 {
148 tbi-handle = <&tbi0>;
149 phy-handle = <&sgmii_phy2>;
150 phy-connection-type = "sgmii";
151 status = "okay";
152};
153
154&enet1 {
155 tbi-handle = <&tbi1>;
156 phy-handle = <&sgmii_phy0>;
157 phy-connection-type = "sgmii";
158 status = "okay";
159};
160
161&enet2 {
162 phy-handle = <&rgmii_phy1>;
163 phy-connection-type = "rgmii-id";
164 status = "okay";
165};
166
167&i2c0 {
168 status = "okay";
169
170 ina220@40 {
171 compatible = "ti,ina220";
172 reg = <0x40>;
173 shunt-resistor = <1000>;
174 };
175
176 ina220@41 {
177 compatible = "ti,ina220";
178 reg = <0x41>;
179 shunt-resistor = <1000>;
180 };
181
182};
183
184&i2c1 {
185 status = "okay";
186 codec: sgtl5000@a {
187 #sound-dai-cells = <0>;
188 compatible = "fsl,sgtl5000";
189 reg = <0x0a>;
190 VDDA-supply = <®_3p3v>;
191 VDDIO-supply = <®_3p3v>;
192 clocks = <&sys_mclk>;
193 };
194};
195
196&ifc {
197 #address-cells = <2>;
198 #size-cells = <1>;
199 /* NOR Flash on board */
200 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
201 status = "okay";
202
203 nor@0,0 {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 compatible = "cfi-flash";
207 reg = <0x0 0x0 0x8000000>;
208 big-endian;
209 bank-width = <2>;
210 device-width = <1>;
211 };
212};
213
214&lpuart0 {
215 status = "okay";
216};
217
218&mdio0 {
219 sgmii_phy0: ethernet-phy@0 {
220 reg = <0x0>;
221 };
222 rgmii_phy1: ethernet-phy@1 {
223 reg = <0x1>;
224 };
225 sgmii_phy2: ethernet-phy@2 {
226 reg = <0x2>;
227 };
228 tbi0: tbi-phy@1f {
229 reg = <0x1f>;
230 device_type = "tbi-phy";
231 };
232};
233
234&mdio1 {
235 tbi1: tbi-phy@1f {
236 reg = <0x1f>;
237 device_type = "tbi-phy";
238 };
239};
240
241&esdhc {
242 status = "okay";
243};
244
245&qspi {
246 status = "okay";
247
248 n25q128a130: flash@0 {
249 compatible = "jedec,spi-nor";
250 #address-cells = <1>;
251 #size-cells = <1>;
252 spi-max-frequency = <50000000>;
253 reg = <0>;
254 spi-rx-bus-width = <4>;
255 spi-tx-bus-width = <4>;
256 };
257};
258
259&sai1 {
260 status = "okay";
261};
262
263&sata {
264 status = "okay";
265};
266
267&uart0 {
268 status = "okay";
269};
270
271&uart1 {
272 status = "okay";
273};
274
275&can0 {
276 status = "okay";
277};
278
279&can1 {
280 status = "okay";
281};
282
283&can2 {
284 status = "disabled";
285};
286
287&can3 {
288 status = "disabled";
289};