Loading...
Note: File does not exist in v4.6.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RISC-V performance counter support.
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 *
7 * This code is based on ARM perf event code which is in turn based on
8 * sparc64 and x86 code.
9 */
10
11#define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
12
13#include <linux/mod_devicetable.h>
14#include <linux/perf/riscv_pmu.h>
15#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/of_irq.h>
19#include <linux/of.h>
20#include <linux/cpu_pm.h>
21#include <linux/sched/clock.h>
22
23#include <asm/errata_list.h>
24#include <asm/sbi.h>
25#include <asm/hwcap.h>
26
27PMU_FORMAT_ATTR(event, "config:0-47");
28PMU_FORMAT_ATTR(firmware, "config:63");
29
30static struct attribute *riscv_arch_formats_attr[] = {
31 &format_attr_event.attr,
32 &format_attr_firmware.attr,
33 NULL,
34};
35
36static struct attribute_group riscv_pmu_format_group = {
37 .name = "format",
38 .attrs = riscv_arch_formats_attr,
39};
40
41static const struct attribute_group *riscv_pmu_attr_groups[] = {
42 &riscv_pmu_format_group,
43 NULL,
44};
45
46/*
47 * RISC-V doesn't have hetergenous harts yet. This need to be part of
48 * per_cpu in case of harts with different pmu counters
49 */
50static union sbi_pmu_ctr_info *pmu_ctr_list;
51static bool riscv_pmu_use_irq;
52static unsigned int riscv_pmu_irq_num;
53static unsigned int riscv_pmu_irq;
54
55struct sbi_pmu_event_data {
56 union {
57 union {
58 struct hw_gen_event {
59 uint32_t event_code:16;
60 uint32_t event_type:4;
61 uint32_t reserved:12;
62 } hw_gen_event;
63 struct hw_cache_event {
64 uint32_t result_id:1;
65 uint32_t op_id:2;
66 uint32_t cache_id:13;
67 uint32_t event_type:4;
68 uint32_t reserved:12;
69 } hw_cache_event;
70 };
71 uint32_t event_idx;
72 };
73};
74
75static const struct sbi_pmu_event_data pmu_hw_event_map[] = {
76 [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = {
77 SBI_PMU_HW_CPU_CYCLES,
78 SBI_PMU_EVENT_TYPE_HW, 0}},
79 [PERF_COUNT_HW_INSTRUCTIONS] = {.hw_gen_event = {
80 SBI_PMU_HW_INSTRUCTIONS,
81 SBI_PMU_EVENT_TYPE_HW, 0}},
82 [PERF_COUNT_HW_CACHE_REFERENCES] = {.hw_gen_event = {
83 SBI_PMU_HW_CACHE_REFERENCES,
84 SBI_PMU_EVENT_TYPE_HW, 0}},
85 [PERF_COUNT_HW_CACHE_MISSES] = {.hw_gen_event = {
86 SBI_PMU_HW_CACHE_MISSES,
87 SBI_PMU_EVENT_TYPE_HW, 0}},
88 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = {.hw_gen_event = {
89 SBI_PMU_HW_BRANCH_INSTRUCTIONS,
90 SBI_PMU_EVENT_TYPE_HW, 0}},
91 [PERF_COUNT_HW_BRANCH_MISSES] = {.hw_gen_event = {
92 SBI_PMU_HW_BRANCH_MISSES,
93 SBI_PMU_EVENT_TYPE_HW, 0}},
94 [PERF_COUNT_HW_BUS_CYCLES] = {.hw_gen_event = {
95 SBI_PMU_HW_BUS_CYCLES,
96 SBI_PMU_EVENT_TYPE_HW, 0}},
97 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = {
98 SBI_PMU_HW_STALLED_CYCLES_FRONTEND,
99 SBI_PMU_EVENT_TYPE_HW, 0}},
100 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = {
101 SBI_PMU_HW_STALLED_CYCLES_BACKEND,
102 SBI_PMU_EVENT_TYPE_HW, 0}},
103 [PERF_COUNT_HW_REF_CPU_CYCLES] = {.hw_gen_event = {
104 SBI_PMU_HW_REF_CPU_CYCLES,
105 SBI_PMU_EVENT_TYPE_HW, 0}},
106};
107
108#define C(x) PERF_COUNT_HW_CACHE_##x
109static const struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
110[PERF_COUNT_HW_CACHE_OP_MAX]
111[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
112 [C(L1D)] = {
113 [C(OP_READ)] = {
114 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
115 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
116 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
117 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
118 },
119 [C(OP_WRITE)] = {
120 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
121 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
122 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
123 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
124 },
125 [C(OP_PREFETCH)] = {
126 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
127 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
128 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
129 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
130 },
131 },
132 [C(L1I)] = {
133 [C(OP_READ)] = {
134 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
135 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
136 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
137 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
138 },
139 [C(OP_WRITE)] = {
140 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
141 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
142 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
143 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
144 },
145 [C(OP_PREFETCH)] = {
146 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
147 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
148 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
149 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
150 },
151 },
152 [C(LL)] = {
153 [C(OP_READ)] = {
154 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
155 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
156 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
157 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
158 },
159 [C(OP_WRITE)] = {
160 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
161 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
162 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
163 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
164 },
165 [C(OP_PREFETCH)] = {
166 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
167 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
168 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
169 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
170 },
171 },
172 [C(DTLB)] = {
173 [C(OP_READ)] = {
174 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
175 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
176 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
177 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
178 },
179 [C(OP_WRITE)] = {
180 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
181 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
182 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
183 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
184 },
185 [C(OP_PREFETCH)] = {
186 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
187 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
188 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
189 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
190 },
191 },
192 [C(ITLB)] = {
193 [C(OP_READ)] = {
194 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
195 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
196 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
197 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
198 },
199 [C(OP_WRITE)] = {
200 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
201 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
202 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
203 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
204 },
205 [C(OP_PREFETCH)] = {
206 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
207 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
208 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
209 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
210 },
211 },
212 [C(BPU)] = {
213 [C(OP_READ)] = {
214 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
215 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
216 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
217 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
218 },
219 [C(OP_WRITE)] = {
220 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
221 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
222 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
223 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
224 },
225 [C(OP_PREFETCH)] = {
226 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
227 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
228 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
229 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
230 },
231 },
232 [C(NODE)] = {
233 [C(OP_READ)] = {
234 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
235 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
236 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
237 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
238 },
239 [C(OP_WRITE)] = {
240 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
241 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
242 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
243 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
244 },
245 [C(OP_PREFETCH)] = {
246 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
247 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
248 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
249 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
250 },
251 },
252};
253
254static int pmu_sbi_ctr_get_width(int idx)
255{
256 return pmu_ctr_list[idx].width;
257}
258
259static bool pmu_sbi_ctr_is_fw(int cidx)
260{
261 union sbi_pmu_ctr_info *info;
262
263 info = &pmu_ctr_list[cidx];
264 if (!info)
265 return false;
266
267 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
268}
269
270static int pmu_sbi_ctr_get_idx(struct perf_event *event)
271{
272 struct hw_perf_event *hwc = &event->hw;
273 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
274 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
275 struct sbiret ret;
276 int idx;
277 uint64_t cbase = 0;
278 unsigned long cflags = 0;
279
280 if (event->attr.exclude_kernel)
281 cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
282 if (event->attr.exclude_user)
283 cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
284
285 /* retrieve the available counter index */
286#if defined(CONFIG_32BIT)
287 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
288 rvpmu->cmask, cflags, hwc->event_base, hwc->config,
289 hwc->config >> 32);
290#else
291 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
292 rvpmu->cmask, cflags, hwc->event_base, hwc->config, 0);
293#endif
294 if (ret.error) {
295 pr_debug("Not able to find a counter for event %lx config %llx\n",
296 hwc->event_base, hwc->config);
297 return sbi_err_map_linux_errno(ret.error);
298 }
299
300 idx = ret.value;
301 if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
302 return -ENOENT;
303
304 /* Additional sanity check for the counter id */
305 if (pmu_sbi_ctr_is_fw(idx)) {
306 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs))
307 return idx;
308 } else {
309 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs))
310 return idx;
311 }
312
313 return -ENOENT;
314}
315
316static void pmu_sbi_ctr_clear_idx(struct perf_event *event)
317{
318
319 struct hw_perf_event *hwc = &event->hw;
320 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
321 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
322 int idx = hwc->idx;
323
324 if (pmu_sbi_ctr_is_fw(idx))
325 clear_bit(idx, cpuc->used_fw_ctrs);
326 else
327 clear_bit(idx, cpuc->used_hw_ctrs);
328}
329
330static int pmu_event_find_cache(u64 config)
331{
332 unsigned int cache_type, cache_op, cache_result, ret;
333
334 cache_type = (config >> 0) & 0xff;
335 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
336 return -EINVAL;
337
338 cache_op = (config >> 8) & 0xff;
339 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
340 return -EINVAL;
341
342 cache_result = (config >> 16) & 0xff;
343 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
344 return -EINVAL;
345
346 ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;
347
348 return ret;
349}
350
351static bool pmu_sbi_is_fw_event(struct perf_event *event)
352{
353 u32 type = event->attr.type;
354 u64 config = event->attr.config;
355
356 if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1))
357 return true;
358 else
359 return false;
360}
361
362static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
363{
364 u32 type = event->attr.type;
365 u64 config = event->attr.config;
366 int bSoftware;
367 u64 raw_config_val;
368 int ret;
369
370 switch (type) {
371 case PERF_TYPE_HARDWARE:
372 if (config >= PERF_COUNT_HW_MAX)
373 return -EINVAL;
374 ret = pmu_hw_event_map[event->attr.config].event_idx;
375 break;
376 case PERF_TYPE_HW_CACHE:
377 ret = pmu_event_find_cache(config);
378 break;
379 case PERF_TYPE_RAW:
380 /*
381 * As per SBI specification, the upper 16 bits must be unused for
382 * a raw event. Use the MSB (63b) to distinguish between hardware
383 * raw event and firmware events.
384 */
385 bSoftware = config >> 63;
386 raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
387 if (bSoftware) {
388 if (raw_config_val < SBI_PMU_FW_MAX)
389 ret = (raw_config_val & 0xFFFF) |
390 (SBI_PMU_EVENT_TYPE_FW << 16);
391 else
392 return -EINVAL;
393 } else {
394 ret = RISCV_PMU_RAW_EVENT_IDX;
395 *econfig = raw_config_val;
396 }
397 break;
398 default:
399 ret = -EINVAL;
400 break;
401 }
402
403 return ret;
404}
405
406static u64 pmu_sbi_ctr_read(struct perf_event *event)
407{
408 struct hw_perf_event *hwc = &event->hw;
409 int idx = hwc->idx;
410 struct sbiret ret;
411 union sbi_pmu_ctr_info info;
412 u64 val = 0;
413
414 if (pmu_sbi_is_fw_event(event)) {
415 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
416 hwc->idx, 0, 0, 0, 0, 0);
417 if (!ret.error)
418 val = ret.value;
419 } else {
420 info = pmu_ctr_list[idx];
421 val = riscv_pmu_ctr_read_csr(info.csr);
422 if (IS_ENABLED(CONFIG_32BIT))
423 val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val;
424 }
425
426 return val;
427}
428
429static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
430{
431 struct sbiret ret;
432 struct hw_perf_event *hwc = &event->hw;
433 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
434
435#if defined(CONFIG_32BIT)
436 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
437 1, flag, ival, ival >> 32, 0);
438#else
439 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
440 1, flag, ival, 0, 0);
441#endif
442 if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
443 pr_err("Starting counter idx %d failed with error %d\n",
444 hwc->idx, sbi_err_map_linux_errno(ret.error));
445}
446
447static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
448{
449 struct sbiret ret;
450 struct hw_perf_event *hwc = &event->hw;
451
452 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
453 if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
454 flag != SBI_PMU_STOP_FLAG_RESET)
455 pr_err("Stopping counter idx %d failed with error %d\n",
456 hwc->idx, sbi_err_map_linux_errno(ret.error));
457}
458
459static int pmu_sbi_find_num_ctrs(void)
460{
461 struct sbiret ret;
462
463 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);
464 if (!ret.error)
465 return ret.value;
466 else
467 return sbi_err_map_linux_errno(ret.error);
468}
469
470static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
471{
472 struct sbiret ret;
473 int i, num_hw_ctr = 0, num_fw_ctr = 0;
474 union sbi_pmu_ctr_info cinfo;
475
476 pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
477 if (!pmu_ctr_list)
478 return -ENOMEM;
479
480 for (i = 0; i < nctr; i++) {
481 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
482 if (ret.error)
483 /* The logical counter ids are not expected to be contiguous */
484 continue;
485
486 *mask |= BIT(i);
487
488 cinfo.value = ret.value;
489 if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
490 num_fw_ctr++;
491 else
492 num_hw_ctr++;
493 pmu_ctr_list[i].value = cinfo.value;
494 }
495
496 pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr);
497
498 return 0;
499}
500
501static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
502{
503 /*
504 * No need to check the error because we are disabling all the counters
505 * which may include counters that are not enabled yet.
506 */
507 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
508 0, pmu->cmask, 0, 0, 0, 0);
509}
510
511static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
512{
513 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
514
515 /* No need to check the error here as we can't do anything about the error */
516 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0,
517 cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0);
518}
519
520/*
521 * This function starts all the used counters in two step approach.
522 * Any counter that did not overflow can be start in a single step
523 * while the overflowed counters need to be started with updated initialization
524 * value.
525 */
526static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
527 unsigned long ctr_ovf_mask)
528{
529 int idx = 0;
530 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
531 struct perf_event *event;
532 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
533 unsigned long ctr_start_mask = 0;
534 uint64_t max_period;
535 struct hw_perf_event *hwc;
536 u64 init_val = 0;
537
538 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask;
539
540 /* Start all the counters that did not overflow in a single shot */
541 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask,
542 0, 0, 0, 0);
543
544 /* Reinitialize and start all the counter that overflowed */
545 while (ctr_ovf_mask) {
546 if (ctr_ovf_mask & 0x01) {
547 event = cpu_hw_evt->events[idx];
548 hwc = &event->hw;
549 max_period = riscv_pmu_ctr_get_width_mask(event);
550 init_val = local64_read(&hwc->prev_count) & max_period;
551#if defined(CONFIG_32BIT)
552 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
553 flag, init_val, init_val >> 32, 0);
554#else
555 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
556 flag, init_val, 0, 0);
557#endif
558 perf_event_update_userpage(event);
559 }
560 ctr_ovf_mask = ctr_ovf_mask >> 1;
561 idx++;
562 }
563}
564
565static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
566{
567 struct perf_sample_data data;
568 struct pt_regs *regs;
569 struct hw_perf_event *hw_evt;
570 union sbi_pmu_ctr_info *info;
571 int lidx, hidx, fidx;
572 struct riscv_pmu *pmu;
573 struct perf_event *event;
574 unsigned long overflow;
575 unsigned long overflowed_ctrs = 0;
576 struct cpu_hw_events *cpu_hw_evt = dev;
577 u64 start_clock = sched_clock();
578
579 if (WARN_ON_ONCE(!cpu_hw_evt))
580 return IRQ_NONE;
581
582 /* Firmware counter don't support overflow yet */
583 fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
584 event = cpu_hw_evt->events[fidx];
585 if (!event) {
586 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
587 return IRQ_NONE;
588 }
589
590 pmu = to_riscv_pmu(event->pmu);
591 pmu_sbi_stop_hw_ctrs(pmu);
592
593 /* Overflow status register should only be read after counter are stopped */
594 ALT_SBI_PMU_OVERFLOW(overflow);
595
596 /*
597 * Overflow interrupt pending bit should only be cleared after stopping
598 * all the counters to avoid any race condition.
599 */
600 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
601
602 /* No overflow bit is set */
603 if (!overflow)
604 return IRQ_NONE;
605
606 regs = get_irq_regs();
607
608 for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
609 struct perf_event *event = cpu_hw_evt->events[lidx];
610
611 /* Skip if invalid event or user did not request a sampling */
612 if (!event || !is_sampling_event(event))
613 continue;
614
615 info = &pmu_ctr_list[lidx];
616 /* Do a sanity check */
617 if (!info || info->type != SBI_PMU_CTR_TYPE_HW)
618 continue;
619
620 /* compute hardware counter index */
621 hidx = info->csr - CSR_CYCLE;
622 /* check if the corresponding bit is set in sscountovf */
623 if (!(overflow & (1 << hidx)))
624 continue;
625
626 /*
627 * Keep a track of overflowed counters so that they can be started
628 * with updated initial value.
629 */
630 overflowed_ctrs |= 1 << lidx;
631 hw_evt = &event->hw;
632 riscv_pmu_event_update(event);
633 perf_sample_data_init(&data, 0, hw_evt->last_period);
634 if (riscv_pmu_event_set_period(event)) {
635 /*
636 * Unlike other ISAs, RISC-V don't have to disable interrupts
637 * to avoid throttling here. As per the specification, the
638 * interrupt remains disabled until the OF bit is set.
639 * Interrupts are enabled again only during the start.
640 * TODO: We will need to stop the guest counters once
641 * virtualization support is added.
642 */
643 perf_event_overflow(event, &data, regs);
644 }
645 }
646
647 pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
648 perf_sample_event_took(sched_clock() - start_clock);
649
650 return IRQ_HANDLED;
651}
652
653static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
654{
655 struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
656 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
657
658 /*
659 * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
660 * as is necessary to maintain uABI compatibility.
661 */
662 csr_write(CSR_SCOUNTEREN, 0x7);
663
664 /* Stop all the counters so that they can be enabled from perf */
665 pmu_sbi_stop_all(pmu);
666
667 if (riscv_pmu_use_irq) {
668 cpu_hw_evt->irq = riscv_pmu_irq;
669 csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
670 csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
671 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
672 }
673
674 return 0;
675}
676
677static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
678{
679 if (riscv_pmu_use_irq) {
680 disable_percpu_irq(riscv_pmu_irq);
681 csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
682 }
683
684 /* Disable all counters access for user mode now */
685 csr_write(CSR_SCOUNTEREN, 0x0);
686
687 return 0;
688}
689
690static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
691{
692 int ret;
693 struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
694 struct device_node *cpu, *child;
695 struct irq_domain *domain = NULL;
696
697 if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
698 riscv_pmu_irq_num = RV_IRQ_PMU;
699 riscv_pmu_use_irq = true;
700 } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
701 riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
702 riscv_cached_marchid(0) == 0 &&
703 riscv_cached_mimpid(0) == 0) {
704 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
705 riscv_pmu_use_irq = true;
706 }
707
708 if (!riscv_pmu_use_irq)
709 return -EOPNOTSUPP;
710
711 for_each_of_cpu_node(cpu) {
712 child = of_get_compatible_child(cpu, "riscv,cpu-intc");
713 if (!child) {
714 pr_err("Failed to find INTC node\n");
715 of_node_put(cpu);
716 return -ENODEV;
717 }
718 domain = irq_find_host(child);
719 of_node_put(child);
720 if (domain) {
721 of_node_put(cpu);
722 break;
723 }
724 }
725 if (!domain) {
726 pr_err("Failed to find INTC IRQ root domain\n");
727 return -ENODEV;
728 }
729
730 riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
731 if (!riscv_pmu_irq) {
732 pr_err("Failed to map PMU interrupt for node\n");
733 return -ENODEV;
734 }
735
736 ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
737 if (ret) {
738 pr_err("registering percpu irq failed [%d]\n", ret);
739 return ret;
740 }
741
742 return 0;
743}
744
745#ifdef CONFIG_CPU_PM
746static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
747 void *v)
748{
749 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb);
750 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
751 int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS);
752 struct perf_event *event;
753 int idx;
754
755 if (!enabled)
756 return NOTIFY_OK;
757
758 for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) {
759 event = cpuc->events[idx];
760 if (!event)
761 continue;
762
763 switch (cmd) {
764 case CPU_PM_ENTER:
765 /*
766 * Stop and update the counter
767 */
768 riscv_pmu_stop(event, PERF_EF_UPDATE);
769 break;
770 case CPU_PM_EXIT:
771 case CPU_PM_ENTER_FAILED:
772 /*
773 * Restore and enable the counter.
774 *
775 * Requires RCU read locking to be functional,
776 * wrap the call within RCU_NONIDLE to make the
777 * RCU subsystem aware this cpu is not idle from
778 * an RCU perspective for the riscv_pmu_start() call
779 * duration.
780 */
781 RCU_NONIDLE(riscv_pmu_start(event, PERF_EF_RELOAD));
782 break;
783 default:
784 break;
785 }
786 }
787
788 return NOTIFY_OK;
789}
790
791static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
792{
793 pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
794 return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
795}
796
797static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
798{
799 cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
800}
801#else
802static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
803static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
804#endif
805
806static void riscv_pmu_destroy(struct riscv_pmu *pmu)
807{
808 riscv_pm_pmu_unregister(pmu);
809 cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
810}
811
812static int pmu_sbi_device_probe(struct platform_device *pdev)
813{
814 struct riscv_pmu *pmu = NULL;
815 unsigned long cmask = 0;
816 int ret = -ENODEV;
817 int num_counters;
818
819 pr_info("SBI PMU extension is available\n");
820 pmu = riscv_pmu_alloc();
821 if (!pmu)
822 return -ENOMEM;
823
824 num_counters = pmu_sbi_find_num_ctrs();
825 if (num_counters < 0) {
826 pr_err("SBI PMU extension doesn't provide any counters\n");
827 goto out_free;
828 }
829
830 /* cache all the information about counters now */
831 if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
832 goto out_free;
833
834 ret = pmu_sbi_setup_irqs(pmu, pdev);
835 if (ret < 0) {
836 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n");
837 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
838 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
839 }
840
841 pmu->pmu.attr_groups = riscv_pmu_attr_groups;
842 pmu->cmask = cmask;
843 pmu->ctr_start = pmu_sbi_ctr_start;
844 pmu->ctr_stop = pmu_sbi_ctr_stop;
845 pmu->event_map = pmu_sbi_event_map;
846 pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
847 pmu->ctr_get_width = pmu_sbi_ctr_get_width;
848 pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
849 pmu->ctr_read = pmu_sbi_ctr_read;
850
851 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
852 if (ret)
853 return ret;
854
855 ret = riscv_pm_pmu_register(pmu);
856 if (ret)
857 goto out_unregister;
858
859 ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
860 if (ret)
861 goto out_unregister;
862
863 return 0;
864
865out_unregister:
866 riscv_pmu_destroy(pmu);
867
868out_free:
869 kfree(pmu);
870 return ret;
871}
872
873static struct platform_driver pmu_sbi_driver = {
874 .probe = pmu_sbi_device_probe,
875 .driver = {
876 .name = RISCV_PMU_PDEV_NAME,
877 },
878};
879
880static int __init pmu_sbi_devinit(void)
881{
882 int ret;
883 struct platform_device *pdev;
884
885 if (sbi_spec_version < sbi_mk_version(0, 3) ||
886 sbi_probe_extension(SBI_EXT_PMU) <= 0) {
887 return 0;
888 }
889
890 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
891 "perf/riscv/pmu:starting",
892 pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
893 if (ret) {
894 pr_err("CPU hotplug notifier could not be registered: %d\n",
895 ret);
896 return ret;
897 }
898
899 ret = platform_driver_register(&pmu_sbi_driver);
900 if (ret)
901 return ret;
902
903 pdev = platform_device_register_simple(RISCV_PMU_PDEV_NAME, -1, NULL, 0);
904 if (IS_ERR(pdev)) {
905 platform_driver_unregister(&pmu_sbi_driver);
906 return PTR_ERR(pdev);
907 }
908
909 /* Notify legacy implementation that SBI pmu is available*/
910 riscv_pmu_legacy_skip_init();
911
912 return ret;
913}
914device_initcall(pmu_sbi_devinit)