1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/*
  3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef ATH11K_CE_H
  7#define ATH11K_CE_H
  8
  9#define CE_COUNT_MAX 12
 10
 11/* Byte swap data words */
 12#define CE_ATTR_BYTE_SWAP_DATA 2
 13
 14/* no interrupt on copy completion */
 15#define CE_ATTR_DIS_INTR		8
 16
 17/* Host software's Copy Engine configuration. */
 18#ifdef __BIG_ENDIAN
 19#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
 20#else
 21#define CE_ATTR_FLAGS 0
 22#endif
 23
 24/* Threshold to poll for tx completion in case of Interrupt disabled CE's */
 25#define ATH11K_CE_USAGE_THRESHOLD 32
 26
 27void ath11k_ce_byte_swap(void *mem, u32 len);
 28
 29/*
 30 * Directions for interconnect pipe configuration.
 31 * These definitions may be used during configuration and are shared
 32 * between Host and Target.
 33 *
 34 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
 35 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
 36 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
 37 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
 38 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
 39 * over the interconnect.
 40 */
 41#define PIPEDIR_NONE		0
 42#define PIPEDIR_IN		1 /* Target-->Host, WiFi Rx direction */
 43#define PIPEDIR_OUT		2 /* Host->Target, WiFi Tx direction */
 44#define PIPEDIR_INOUT		3 /* bidirectional */
 45#define PIPEDIR_INOUT_H2H	4 /* bidirectional, host to host */
 46
 47/* CE address/mask */
 48#define CE_HOST_IE_ADDRESS	0x00A1803C
 49#define CE_HOST_IE_2_ADDRESS	0x00A18040
 50#define CE_HOST_IE_3_ADDRESS	CE_HOST_IE_ADDRESS
 51
 52#define CE_HOST_IE_3_SHIFT	0xC
 53
 54#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
 55
 56#define ATH11K_CE_RX_POST_RETRY_JIFFIES 50
 57
 58struct ath11k_base;
 59
 60/*
 61 * Establish a mapping between a service/direction and a pipe.
 62 * Configuration information for a Copy Engine pipe and services.
 63 * Passed from Host to Target through QMI message and must be in
 64 * little endian format.
 65 */
 66struct service_to_pipe {
 67	__le32 service_id;
 68	__le32 pipedir;
 69	__le32 pipenum;
 70};
 71
 72/*
 73 * Configuration information for a Copy Engine pipe.
 74 * Passed from Host to Target through QMI message during startup (one per CE).
 75 *
 76 * NOTE: Structure is shared between Host software and Target firmware!
 77 */
 78struct ce_pipe_config {
 79	__le32 pipenum;
 80	__le32 pipedir;
 81	__le32 nentries;
 82	__le32 nbytes_max;
 83	__le32 flags;
 84	__le32 reserved;
 85};
 86
 87struct ce_attr {
 88	/* CE_ATTR_* values */
 89	unsigned int flags;
 90
 91	/* #entries in source ring - Must be a power of 2 */
 92	unsigned int src_nentries;
 93
 94	/*
 95	 * Max source send size for this CE.
 96	 * This is also the minimum size of a destination buffer.
 97	 */
 98	unsigned int src_sz_max;
 99
100	/* #entries in destination ring - Must be a power of 2 */
101	unsigned int dest_nentries;
102
103	void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
104	void (*send_cb)(struct ath11k_base *, struct sk_buff *);
105};
106
107#define CE_DESC_RING_ALIGN 8
108
109struct ath11k_ce_ring {
110	/* Number of entries in this ring; must be power of 2 */
111	unsigned int nentries;
112	unsigned int nentries_mask;
113
114	/* For dest ring, this is the next index to be processed
115	 * by software after it was/is received into.
116	 *
117	 * For src ring, this is the last descriptor that was sent
118	 * and completion processed by software.
119	 *
120	 * Regardless of src or dest ring, this is an invariant
121	 * (modulo ring size):
122	 *     write index >= read index >= sw_index
123	 */
124	unsigned int sw_index;
125	/* cached copy */
126	unsigned int write_index;
127
128	/* Start of DMA-coherent area reserved for descriptors */
129	/* Host address space */
130	void *base_addr_owner_space_unaligned;
131	/* CE address space */
132	u32 base_addr_ce_space_unaligned;
133
134	/* Actual start of descriptors.
135	 * Aligned to descriptor-size boundary.
136	 * Points into reserved DMA-coherent area, above.
137	 */
138	/* Host address space */
139	void *base_addr_owner_space;
140
141	/* CE address space */
142	u32 base_addr_ce_space;
143
144	/* HAL ring id */
145	u32 hal_ring_id;
146
147	/* keep last */
148	struct sk_buff *skb[];
149};
150
151struct ath11k_ce_pipe {
152	struct ath11k_base *ab;
153	u16 pipe_num;
154	unsigned int attr_flags;
155	unsigned int buf_sz;
156	unsigned int rx_buf_needed;
157
158	void (*send_cb)(struct ath11k_base *, struct sk_buff *);
159	void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
160
161	struct tasklet_struct intr_tq;
162	struct ath11k_ce_ring *src_ring;
163	struct ath11k_ce_ring *dest_ring;
164	struct ath11k_ce_ring *status_ring;
165	u64 timestamp;
166};
167
168struct ath11k_ce {
169	struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX];
170	/* Protects rings of all ce pipes */
171	spinlock_t ce_lock;
172	struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX];
173};
174
175extern const struct ce_attr ath11k_host_ce_config_ipq8074[];
176extern const struct ce_attr ath11k_host_ce_config_qca6390[];
177extern const struct ce_attr ath11k_host_ce_config_qcn9074[];
178
179void ath11k_ce_cleanup_pipes(struct ath11k_base *ab);
180void ath11k_ce_rx_replenish_retry(struct timer_list *t);
181void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id);
182int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
183		   u16 transfer_id);
184void ath11k_ce_rx_post_buf(struct ath11k_base *ab);
185int ath11k_ce_init_pipes(struct ath11k_base *ab);
186int ath11k_ce_alloc_pipes(struct ath11k_base *ab);
187void ath11k_ce_free_pipes(struct ath11k_base *ab);
188int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id);
189void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id);
190int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
191				  u8 *ul_pipe, u8 *dl_pipe);
192int ath11k_ce_attr_attach(struct ath11k_base *ab);
193void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
194				 u32 **shadow_cfg, u32 *shadow_cfg_len);
195void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab);
196
197#endif