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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH11K_CE_H
8#define ATH11K_CE_H
9
10#define CE_COUNT_MAX 12
11
12/* Byte swap data words */
13#define CE_ATTR_BYTE_SWAP_DATA 2
14
15/* no interrupt on copy completion */
16#define CE_ATTR_DIS_INTR 8
17
18/* Host software's Copy Engine configuration. */
19#ifdef __BIG_ENDIAN
20#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
21#else
22#define CE_ATTR_FLAGS 0
23#endif
24
25/* Threshold to poll for tx completion in case of Interrupt disabled CE's */
26#define ATH11K_CE_USAGE_THRESHOLD 32
27
28void ath11k_ce_byte_swap(void *mem, u32 len);
29
30/*
31 * Directions for interconnect pipe configuration.
32 * These definitions may be used during configuration and are shared
33 * between Host and Target.
34 *
35 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
36 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
37 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
38 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
39 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
40 * over the interconnect.
41 */
42#define PIPEDIR_NONE 0
43#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
44#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
45#define PIPEDIR_INOUT 3 /* bidirectional */
46#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
47
48/* CE address/mask */
49#define CE_HOST_IE_ADDRESS 0x00A1803C
50#define CE_HOST_IE_2_ADDRESS 0x00A18040
51#define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS
52
53/* CE IE registers are different for IPQ5018 */
54#define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C
55#define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050
56#define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS
57
58#define CE_HOST_IE_3_SHIFT 0xC
59
60#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
61
62#define ATH11K_CE_RX_POST_RETRY_JIFFIES 50
63
64struct ath11k_base;
65
66/*
67 * Establish a mapping between a service/direction and a pipe.
68 * Configuration information for a Copy Engine pipe and services.
69 * Passed from Host to Target through QMI message and must be in
70 * little endian format.
71 */
72struct service_to_pipe {
73 __le32 service_id;
74 __le32 pipedir;
75 __le32 pipenum;
76};
77
78/*
79 * Configuration information for a Copy Engine pipe.
80 * Passed from Host to Target through QMI message during startup (one per CE).
81 *
82 * NOTE: Structure is shared between Host software and Target firmware!
83 */
84struct ce_pipe_config {
85 __le32 pipenum;
86 __le32 pipedir;
87 __le32 nentries;
88 __le32 nbytes_max;
89 __le32 flags;
90 __le32 reserved;
91};
92
93struct ce_ie_addr {
94 u32 ie1_reg_addr;
95 u32 ie2_reg_addr;
96 u32 ie3_reg_addr;
97};
98
99struct ce_remap {
100 u32 base;
101 u32 size;
102};
103
104struct ce_attr {
105 /* CE_ATTR_* values */
106 unsigned int flags;
107
108 /* #entries in source ring - Must be a power of 2 */
109 unsigned int src_nentries;
110
111 /*
112 * Max source send size for this CE.
113 * This is also the minimum size of a destination buffer.
114 */
115 unsigned int src_sz_max;
116
117 /* #entries in destination ring - Must be a power of 2 */
118 unsigned int dest_nentries;
119
120 void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
121 void (*send_cb)(struct ath11k_base *, struct sk_buff *);
122};
123
124#define CE_DESC_RING_ALIGN 8
125
126struct ath11k_ce_ring {
127 /* Number of entries in this ring; must be power of 2 */
128 unsigned int nentries;
129 unsigned int nentries_mask;
130
131 /* For dest ring, this is the next index to be processed
132 * by software after it was/is received into.
133 *
134 * For src ring, this is the last descriptor that was sent
135 * and completion processed by software.
136 *
137 * Regardless of src or dest ring, this is an invariant
138 * (modulo ring size):
139 * write index >= read index >= sw_index
140 */
141 unsigned int sw_index;
142 /* cached copy */
143 unsigned int write_index;
144
145 /* Start of DMA-coherent area reserved for descriptors */
146 /* Host address space */
147 void *base_addr_owner_space_unaligned;
148 /* CE address space */
149 u32 base_addr_ce_space_unaligned;
150
151 /* Actual start of descriptors.
152 * Aligned to descriptor-size boundary.
153 * Points into reserved DMA-coherent area, above.
154 */
155 /* Host address space */
156 void *base_addr_owner_space;
157
158 /* CE address space */
159 u32 base_addr_ce_space;
160
161 /* HAL ring id */
162 u32 hal_ring_id;
163
164 /* keep last */
165 struct sk_buff *skb[];
166};
167
168struct ath11k_ce_pipe {
169 struct ath11k_base *ab;
170 u16 pipe_num;
171 unsigned int attr_flags;
172 unsigned int buf_sz;
173 unsigned int rx_buf_needed;
174
175 void (*send_cb)(struct ath11k_base *, struct sk_buff *);
176 void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
177
178 struct tasklet_struct intr_tq;
179 struct ath11k_ce_ring *src_ring;
180 struct ath11k_ce_ring *dest_ring;
181 struct ath11k_ce_ring *status_ring;
182 u64 timestamp;
183};
184
185struct ath11k_ce {
186 struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX];
187 /* Protects rings of all ce pipes */
188 spinlock_t ce_lock;
189 struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX];
190};
191
192extern const struct ce_attr ath11k_host_ce_config_ipq8074[];
193extern const struct ce_attr ath11k_host_ce_config_qca6390[];
194extern const struct ce_attr ath11k_host_ce_config_qcn9074[];
195
196void ath11k_ce_cleanup_pipes(struct ath11k_base *ab);
197void ath11k_ce_rx_replenish_retry(struct timer_list *t);
198void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id);
199int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
200 u16 transfer_id);
201void ath11k_ce_rx_post_buf(struct ath11k_base *ab);
202int ath11k_ce_init_pipes(struct ath11k_base *ab);
203int ath11k_ce_alloc_pipes(struct ath11k_base *ab);
204void ath11k_ce_free_pipes(struct ath11k_base *ab);
205int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id);
206void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id);
207void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
208 u32 **shadow_cfg, u32 *shadow_cfg_len);
209void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab);
210
211#endif