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1// SPDX-License-Identifier: GPL-2.0
2//
3// Register cache access API
4//
5// Copyright 2011 Wolfson Microelectronics plc
6//
7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8
9#include <linux/bsearch.h>
10#include <linux/device.h>
11#include <linux/export.h>
12#include <linux/slab.h>
13#include <linux/sort.h>
14
15#include "trace.h"
16#include "internal.h"
17
18static const struct regcache_ops *cache_types[] = {
19 ®cache_rbtree_ops,
20#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
21 ®cache_lzo_ops,
22#endif
23 ®cache_flat_ops,
24};
25
26static int regcache_hw_init(struct regmap *map)
27{
28 int i, j;
29 int ret;
30 int count;
31 unsigned int reg, val;
32 void *tmp_buf;
33
34 if (!map->num_reg_defaults_raw)
35 return -EINVAL;
36
37 /* calculate the size of reg_defaults */
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
39 if (regmap_readable(map, i * map->reg_stride) &&
40 !regmap_volatile(map, i * map->reg_stride))
41 count++;
42
43 /* all registers are unreadable or volatile, so just bypass */
44 if (!count) {
45 map->cache_bypass = true;
46 return 0;
47 }
48
49 map->num_reg_defaults = count;
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
51 GFP_KERNEL);
52 if (!map->reg_defaults)
53 return -ENOMEM;
54
55 if (!map->reg_defaults_raw) {
56 bool cache_bypass = map->cache_bypass;
57 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
58
59 /* Bypass the cache access till data read from HW */
60 map->cache_bypass = true;
61 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
62 if (!tmp_buf) {
63 ret = -ENOMEM;
64 goto err_free;
65 }
66 ret = regmap_raw_read(map, 0, tmp_buf,
67 map->cache_size_raw);
68 map->cache_bypass = cache_bypass;
69 if (ret == 0) {
70 map->reg_defaults_raw = tmp_buf;
71 map->cache_free = true;
72 } else {
73 kfree(tmp_buf);
74 }
75 }
76
77 /* fill the reg_defaults */
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
79 reg = i * map->reg_stride;
80
81 if (!regmap_readable(map, reg))
82 continue;
83
84 if (regmap_volatile(map, reg))
85 continue;
86
87 if (map->reg_defaults_raw) {
88 val = regcache_get_val(map, map->reg_defaults_raw, i);
89 } else {
90 bool cache_bypass = map->cache_bypass;
91
92 map->cache_bypass = true;
93 ret = regmap_read(map, reg, &val);
94 map->cache_bypass = cache_bypass;
95 if (ret != 0) {
96 dev_err(map->dev, "Failed to read %d: %d\n",
97 reg, ret);
98 goto err_free;
99 }
100 }
101
102 map->reg_defaults[j].reg = reg;
103 map->reg_defaults[j].def = val;
104 j++;
105 }
106
107 return 0;
108
109err_free:
110 kfree(map->reg_defaults);
111
112 return ret;
113}
114
115int regcache_init(struct regmap *map, const struct regmap_config *config)
116{
117 int ret;
118 int i;
119 void *tmp_buf;
120
121 if (map->cache_type == REGCACHE_NONE) {
122 if (config->reg_defaults || config->num_reg_defaults_raw)
123 dev_warn(map->dev,
124 "No cache used with register defaults set!\n");
125
126 map->cache_bypass = true;
127 return 0;
128 }
129
130 if (config->reg_defaults && !config->num_reg_defaults) {
131 dev_err(map->dev,
132 "Register defaults are set without the number!\n");
133 return -EINVAL;
134 }
135
136 if (config->num_reg_defaults && !config->reg_defaults) {
137 dev_err(map->dev,
138 "Register defaults number are set without the reg!\n");
139 return -EINVAL;
140 }
141
142 for (i = 0; i < config->num_reg_defaults; i++)
143 if (config->reg_defaults[i].reg % map->reg_stride)
144 return -EINVAL;
145
146 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
147 if (cache_types[i]->type == map->cache_type)
148 break;
149
150 if (i == ARRAY_SIZE(cache_types)) {
151 dev_err(map->dev, "Could not match compress type: %d\n",
152 map->cache_type);
153 return -EINVAL;
154 }
155
156 map->num_reg_defaults = config->num_reg_defaults;
157 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
158 map->reg_defaults_raw = config->reg_defaults_raw;
159 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
160 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
161
162 map->cache = NULL;
163 map->cache_ops = cache_types[i];
164
165 if (!map->cache_ops->read ||
166 !map->cache_ops->write ||
167 !map->cache_ops->name)
168 return -EINVAL;
169
170 /* We still need to ensure that the reg_defaults
171 * won't vanish from under us. We'll need to make
172 * a copy of it.
173 */
174 if (config->reg_defaults) {
175 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
176 sizeof(struct reg_default), GFP_KERNEL);
177 if (!tmp_buf)
178 return -ENOMEM;
179 map->reg_defaults = tmp_buf;
180 } else if (map->num_reg_defaults_raw) {
181 /* Some devices such as PMICs don't have cache defaults,
182 * we cope with this by reading back the HW registers and
183 * crafting the cache defaults by hand.
184 */
185 ret = regcache_hw_init(map);
186 if (ret < 0)
187 return ret;
188 if (map->cache_bypass)
189 return 0;
190 }
191
192 if (!map->max_register && map->num_reg_defaults_raw)
193 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
194
195 if (map->cache_ops->init) {
196 dev_dbg(map->dev, "Initializing %s cache\n",
197 map->cache_ops->name);
198 ret = map->cache_ops->init(map);
199 if (ret)
200 goto err_free;
201 }
202 return 0;
203
204err_free:
205 kfree(map->reg_defaults);
206 if (map->cache_free)
207 kfree(map->reg_defaults_raw);
208
209 return ret;
210}
211
212void regcache_exit(struct regmap *map)
213{
214 if (map->cache_type == REGCACHE_NONE)
215 return;
216
217 BUG_ON(!map->cache_ops);
218
219 kfree(map->reg_defaults);
220 if (map->cache_free)
221 kfree(map->reg_defaults_raw);
222
223 if (map->cache_ops->exit) {
224 dev_dbg(map->dev, "Destroying %s cache\n",
225 map->cache_ops->name);
226 map->cache_ops->exit(map);
227 }
228}
229
230/**
231 * regcache_read - Fetch the value of a given register from the cache.
232 *
233 * @map: map to configure.
234 * @reg: The register index.
235 * @value: The value to be returned.
236 *
237 * Return a negative value on failure, 0 on success.
238 */
239int regcache_read(struct regmap *map,
240 unsigned int reg, unsigned int *value)
241{
242 int ret;
243
244 if (map->cache_type == REGCACHE_NONE)
245 return -ENOSYS;
246
247 BUG_ON(!map->cache_ops);
248
249 if (!regmap_volatile(map, reg)) {
250 ret = map->cache_ops->read(map, reg, value);
251
252 if (ret == 0)
253 trace_regmap_reg_read_cache(map, reg, *value);
254
255 return ret;
256 }
257
258 return -EINVAL;
259}
260
261/**
262 * regcache_write - Set the value of a given register in the cache.
263 *
264 * @map: map to configure.
265 * @reg: The register index.
266 * @value: The new register value.
267 *
268 * Return a negative value on failure, 0 on success.
269 */
270int regcache_write(struct regmap *map,
271 unsigned int reg, unsigned int value)
272{
273 if (map->cache_type == REGCACHE_NONE)
274 return 0;
275
276 BUG_ON(!map->cache_ops);
277
278 if (!regmap_volatile(map, reg))
279 return map->cache_ops->write(map, reg, value);
280
281 return 0;
282}
283
284static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
285 unsigned int val)
286{
287 int ret;
288
289 /* If we don't know the chip just got reset, then sync everything. */
290 if (!map->no_sync_defaults)
291 return true;
292
293 /* Is this the hardware default? If so skip. */
294 ret = regcache_lookup_reg(map, reg);
295 if (ret >= 0 && val == map->reg_defaults[ret].def)
296 return false;
297 return true;
298}
299
300static int regcache_default_sync(struct regmap *map, unsigned int min,
301 unsigned int max)
302{
303 unsigned int reg;
304
305 for (reg = min; reg <= max; reg += map->reg_stride) {
306 unsigned int val;
307 int ret;
308
309 if (regmap_volatile(map, reg) ||
310 !regmap_writeable(map, reg))
311 continue;
312
313 ret = regcache_read(map, reg, &val);
314 if (ret)
315 return ret;
316
317 if (!regcache_reg_needs_sync(map, reg, val))
318 continue;
319
320 map->cache_bypass = true;
321 ret = _regmap_write(map, reg, val);
322 map->cache_bypass = false;
323 if (ret) {
324 dev_err(map->dev, "Unable to sync register %#x. %d\n",
325 reg, ret);
326 return ret;
327 }
328 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
329 }
330
331 return 0;
332}
333
334/**
335 * regcache_sync - Sync the register cache with the hardware.
336 *
337 * @map: map to configure.
338 *
339 * Any registers that should not be synced should be marked as
340 * volatile. In general drivers can choose not to use the provided
341 * syncing functionality if they so require.
342 *
343 * Return a negative value on failure, 0 on success.
344 */
345int regcache_sync(struct regmap *map)
346{
347 int ret = 0;
348 unsigned int i;
349 const char *name;
350 bool bypass;
351
352 BUG_ON(!map->cache_ops);
353
354 map->lock(map->lock_arg);
355 /* Remember the initial bypass state */
356 bypass = map->cache_bypass;
357 dev_dbg(map->dev, "Syncing %s cache\n",
358 map->cache_ops->name);
359 name = map->cache_ops->name;
360 trace_regcache_sync(map, name, "start");
361
362 if (!map->cache_dirty)
363 goto out;
364
365 map->async = true;
366
367 /* Apply any patch first */
368 map->cache_bypass = true;
369 for (i = 0; i < map->patch_regs; i++) {
370 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
371 if (ret != 0) {
372 dev_err(map->dev, "Failed to write %x = %x: %d\n",
373 map->patch[i].reg, map->patch[i].def, ret);
374 goto out;
375 }
376 }
377 map->cache_bypass = false;
378
379 if (map->cache_ops->sync)
380 ret = map->cache_ops->sync(map, 0, map->max_register);
381 else
382 ret = regcache_default_sync(map, 0, map->max_register);
383
384 if (ret == 0)
385 map->cache_dirty = false;
386
387out:
388 /* Restore the bypass state */
389 map->async = false;
390 map->cache_bypass = bypass;
391 map->no_sync_defaults = false;
392 map->unlock(map->lock_arg);
393
394 regmap_async_complete(map);
395
396 trace_regcache_sync(map, name, "stop");
397
398 return ret;
399}
400EXPORT_SYMBOL_GPL(regcache_sync);
401
402/**
403 * regcache_sync_region - Sync part of the register cache with the hardware.
404 *
405 * @map: map to sync.
406 * @min: first register to sync
407 * @max: last register to sync
408 *
409 * Write all non-default register values in the specified region to
410 * the hardware.
411 *
412 * Return a negative value on failure, 0 on success.
413 */
414int regcache_sync_region(struct regmap *map, unsigned int min,
415 unsigned int max)
416{
417 int ret = 0;
418 const char *name;
419 bool bypass;
420
421 BUG_ON(!map->cache_ops);
422
423 map->lock(map->lock_arg);
424
425 /* Remember the initial bypass state */
426 bypass = map->cache_bypass;
427
428 name = map->cache_ops->name;
429 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
430
431 trace_regcache_sync(map, name, "start region");
432
433 if (!map->cache_dirty)
434 goto out;
435
436 map->async = true;
437
438 if (map->cache_ops->sync)
439 ret = map->cache_ops->sync(map, min, max);
440 else
441 ret = regcache_default_sync(map, min, max);
442
443out:
444 /* Restore the bypass state */
445 map->cache_bypass = bypass;
446 map->async = false;
447 map->no_sync_defaults = false;
448 map->unlock(map->lock_arg);
449
450 regmap_async_complete(map);
451
452 trace_regcache_sync(map, name, "stop region");
453
454 return ret;
455}
456EXPORT_SYMBOL_GPL(regcache_sync_region);
457
458/**
459 * regcache_drop_region - Discard part of the register cache
460 *
461 * @map: map to operate on
462 * @min: first register to discard
463 * @max: last register to discard
464 *
465 * Discard part of the register cache.
466 *
467 * Return a negative value on failure, 0 on success.
468 */
469int regcache_drop_region(struct regmap *map, unsigned int min,
470 unsigned int max)
471{
472 int ret = 0;
473
474 if (!map->cache_ops || !map->cache_ops->drop)
475 return -EINVAL;
476
477 map->lock(map->lock_arg);
478
479 trace_regcache_drop_region(map, min, max);
480
481 ret = map->cache_ops->drop(map, min, max);
482
483 map->unlock(map->lock_arg);
484
485 return ret;
486}
487EXPORT_SYMBOL_GPL(regcache_drop_region);
488
489/**
490 * regcache_cache_only - Put a register map into cache only mode
491 *
492 * @map: map to configure
493 * @enable: flag if changes should be written to the hardware
494 *
495 * When a register map is marked as cache only writes to the register
496 * map API will only update the register cache, they will not cause
497 * any hardware changes. This is useful for allowing portions of
498 * drivers to act as though the device were functioning as normal when
499 * it is disabled for power saving reasons.
500 */
501void regcache_cache_only(struct regmap *map, bool enable)
502{
503 map->lock(map->lock_arg);
504 WARN_ON(map->cache_type != REGCACHE_NONE &&
505 map->cache_bypass && enable);
506 map->cache_only = enable;
507 trace_regmap_cache_only(map, enable);
508 map->unlock(map->lock_arg);
509}
510EXPORT_SYMBOL_GPL(regcache_cache_only);
511
512/**
513 * regcache_mark_dirty - Indicate that HW registers were reset to default values
514 *
515 * @map: map to mark
516 *
517 * Inform regcache that the device has been powered down or reset, so that
518 * on resume, regcache_sync() knows to write out all non-default values
519 * stored in the cache.
520 *
521 * If this function is not called, regcache_sync() will assume that
522 * the hardware state still matches the cache state, modulo any writes that
523 * happened when cache_only was true.
524 */
525void regcache_mark_dirty(struct regmap *map)
526{
527 map->lock(map->lock_arg);
528 map->cache_dirty = true;
529 map->no_sync_defaults = true;
530 map->unlock(map->lock_arg);
531}
532EXPORT_SYMBOL_GPL(regcache_mark_dirty);
533
534/**
535 * regcache_cache_bypass - Put a register map into cache bypass mode
536 *
537 * @map: map to configure
538 * @enable: flag if changes should not be written to the cache
539 *
540 * When a register map is marked with the cache bypass option, writes
541 * to the register map API will only update the hardware and not
542 * the cache directly. This is useful when syncing the cache back to
543 * the hardware.
544 */
545void regcache_cache_bypass(struct regmap *map, bool enable)
546{
547 map->lock(map->lock_arg);
548 WARN_ON(map->cache_only && enable);
549 map->cache_bypass = enable;
550 trace_regmap_cache_bypass(map, enable);
551 map->unlock(map->lock_arg);
552}
553EXPORT_SYMBOL_GPL(regcache_cache_bypass);
554
555bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
556 unsigned int val)
557{
558 if (regcache_get_val(map, base, idx) == val)
559 return true;
560
561 /* Use device native format if possible */
562 if (map->format.format_val) {
563 map->format.format_val(base + (map->cache_word_size * idx),
564 val, 0);
565 return false;
566 }
567
568 switch (map->cache_word_size) {
569 case 1: {
570 u8 *cache = base;
571
572 cache[idx] = val;
573 break;
574 }
575 case 2: {
576 u16 *cache = base;
577
578 cache[idx] = val;
579 break;
580 }
581 case 4: {
582 u32 *cache = base;
583
584 cache[idx] = val;
585 break;
586 }
587#ifdef CONFIG_64BIT
588 case 8: {
589 u64 *cache = base;
590
591 cache[idx] = val;
592 break;
593 }
594#endif
595 default:
596 BUG();
597 }
598 return false;
599}
600
601unsigned int regcache_get_val(struct regmap *map, const void *base,
602 unsigned int idx)
603{
604 if (!base)
605 return -EINVAL;
606
607 /* Use device native format if possible */
608 if (map->format.parse_val)
609 return map->format.parse_val(regcache_get_val_addr(map, base,
610 idx));
611
612 switch (map->cache_word_size) {
613 case 1: {
614 const u8 *cache = base;
615
616 return cache[idx];
617 }
618 case 2: {
619 const u16 *cache = base;
620
621 return cache[idx];
622 }
623 case 4: {
624 const u32 *cache = base;
625
626 return cache[idx];
627 }
628#ifdef CONFIG_64BIT
629 case 8: {
630 const u64 *cache = base;
631
632 return cache[idx];
633 }
634#endif
635 default:
636 BUG();
637 }
638 /* unreachable */
639 return -1;
640}
641
642static int regcache_default_cmp(const void *a, const void *b)
643{
644 const struct reg_default *_a = a;
645 const struct reg_default *_b = b;
646
647 return _a->reg - _b->reg;
648}
649
650int regcache_lookup_reg(struct regmap *map, unsigned int reg)
651{
652 struct reg_default key;
653 struct reg_default *r;
654
655 key.reg = reg;
656 key.def = 0;
657
658 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
659 sizeof(struct reg_default), regcache_default_cmp);
660
661 if (r)
662 return r - map->reg_defaults;
663 else
664 return -ENOENT;
665}
666
667static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
668{
669 if (!cache_present)
670 return true;
671
672 return test_bit(idx, cache_present);
673}
674
675static int regcache_sync_block_single(struct regmap *map, void *block,
676 unsigned long *cache_present,
677 unsigned int block_base,
678 unsigned int start, unsigned int end)
679{
680 unsigned int i, regtmp, val;
681 int ret;
682
683 for (i = start; i < end; i++) {
684 regtmp = block_base + (i * map->reg_stride);
685
686 if (!regcache_reg_present(cache_present, i) ||
687 !regmap_writeable(map, regtmp))
688 continue;
689
690 val = regcache_get_val(map, block, i);
691 if (!regcache_reg_needs_sync(map, regtmp, val))
692 continue;
693
694 map->cache_bypass = true;
695
696 ret = _regmap_write(map, regtmp, val);
697
698 map->cache_bypass = false;
699 if (ret != 0) {
700 dev_err(map->dev, "Unable to sync register %#x. %d\n",
701 regtmp, ret);
702 return ret;
703 }
704 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
705 regtmp, val);
706 }
707
708 return 0;
709}
710
711static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
712 unsigned int base, unsigned int cur)
713{
714 size_t val_bytes = map->format.val_bytes;
715 int ret, count;
716
717 if (*data == NULL)
718 return 0;
719
720 count = (cur - base) / map->reg_stride;
721
722 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
723 count * val_bytes, count, base, cur - map->reg_stride);
724
725 map->cache_bypass = true;
726
727 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
728 if (ret)
729 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
730 base, cur - map->reg_stride, ret);
731
732 map->cache_bypass = false;
733
734 *data = NULL;
735
736 return ret;
737}
738
739static int regcache_sync_block_raw(struct regmap *map, void *block,
740 unsigned long *cache_present,
741 unsigned int block_base, unsigned int start,
742 unsigned int end)
743{
744 unsigned int i, val;
745 unsigned int regtmp = 0;
746 unsigned int base = 0;
747 const void *data = NULL;
748 int ret;
749
750 for (i = start; i < end; i++) {
751 regtmp = block_base + (i * map->reg_stride);
752
753 if (!regcache_reg_present(cache_present, i) ||
754 !regmap_writeable(map, regtmp)) {
755 ret = regcache_sync_block_raw_flush(map, &data,
756 base, regtmp);
757 if (ret != 0)
758 return ret;
759 continue;
760 }
761
762 val = regcache_get_val(map, block, i);
763 if (!regcache_reg_needs_sync(map, regtmp, val)) {
764 ret = regcache_sync_block_raw_flush(map, &data,
765 base, regtmp);
766 if (ret != 0)
767 return ret;
768 continue;
769 }
770
771 if (!data) {
772 data = regcache_get_val_addr(map, block, i);
773 base = regtmp;
774 }
775 }
776
777 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
778 map->reg_stride);
779}
780
781int regcache_sync_block(struct regmap *map, void *block,
782 unsigned long *cache_present,
783 unsigned int block_base, unsigned int start,
784 unsigned int end)
785{
786 if (regmap_can_raw_write(map) && !map->use_single_write)
787 return regcache_sync_block_raw(map, block, cache_present,
788 block_base, start, end);
789 else
790 return regcache_sync_block_single(map, block, cache_present,
791 block_base, start, end);
792}
1/*
2 * Register cache access API
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/bsearch.h>
14#include <linux/device.h>
15#include <linux/export.h>
16#include <linux/slab.h>
17#include <linux/sort.h>
18
19#include "trace.h"
20#include "internal.h"
21
22static const struct regcache_ops *cache_types[] = {
23 ®cache_rbtree_ops,
24 ®cache_lzo_ops,
25 ®cache_flat_ops,
26};
27
28static int regcache_hw_init(struct regmap *map)
29{
30 int i, j;
31 int ret;
32 int count;
33 unsigned int reg, val;
34 void *tmp_buf;
35
36 if (!map->num_reg_defaults_raw)
37 return -EINVAL;
38
39 /* calculate the size of reg_defaults */
40 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
41 if (!regmap_volatile(map, i * map->reg_stride))
42 count++;
43
44 /* all registers are volatile, so just bypass */
45 if (!count) {
46 map->cache_bypass = true;
47 return 0;
48 }
49
50 map->num_reg_defaults = count;
51 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
52 GFP_KERNEL);
53 if (!map->reg_defaults)
54 return -ENOMEM;
55
56 if (!map->reg_defaults_raw) {
57 bool cache_bypass = map->cache_bypass;
58 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
59
60 /* Bypass the cache access till data read from HW */
61 map->cache_bypass = true;
62 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
63 if (!tmp_buf) {
64 ret = -ENOMEM;
65 goto err_free;
66 }
67 ret = regmap_raw_read(map, 0, tmp_buf,
68 map->cache_size_raw);
69 map->cache_bypass = cache_bypass;
70 if (ret == 0) {
71 map->reg_defaults_raw = tmp_buf;
72 map->cache_free = 1;
73 } else {
74 kfree(tmp_buf);
75 }
76 }
77
78 /* fill the reg_defaults */
79 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
80 reg = i * map->reg_stride;
81
82 if (!regmap_readable(map, reg))
83 continue;
84
85 if (regmap_volatile(map, reg))
86 continue;
87
88 if (map->reg_defaults_raw) {
89 val = regcache_get_val(map, map->reg_defaults_raw, i);
90 } else {
91 bool cache_bypass = map->cache_bypass;
92
93 map->cache_bypass = true;
94 ret = regmap_read(map, reg, &val);
95 map->cache_bypass = cache_bypass;
96 if (ret != 0) {
97 dev_err(map->dev, "Failed to read %d: %d\n",
98 reg, ret);
99 goto err_free;
100 }
101 }
102
103 map->reg_defaults[j].reg = reg;
104 map->reg_defaults[j].def = val;
105 j++;
106 }
107
108 return 0;
109
110err_free:
111 kfree(map->reg_defaults);
112
113 return ret;
114}
115
116int regcache_init(struct regmap *map, const struct regmap_config *config)
117{
118 int ret;
119 int i;
120 void *tmp_buf;
121
122 if (map->cache_type == REGCACHE_NONE) {
123 if (config->reg_defaults || config->num_reg_defaults_raw)
124 dev_warn(map->dev,
125 "No cache used with register defaults set!\n");
126
127 map->cache_bypass = true;
128 return 0;
129 }
130
131 if (config->reg_defaults && !config->num_reg_defaults) {
132 dev_err(map->dev,
133 "Register defaults are set without the number!\n");
134 return -EINVAL;
135 }
136
137 for (i = 0; i < config->num_reg_defaults; i++)
138 if (config->reg_defaults[i].reg % map->reg_stride)
139 return -EINVAL;
140
141 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
142 if (cache_types[i]->type == map->cache_type)
143 break;
144
145 if (i == ARRAY_SIZE(cache_types)) {
146 dev_err(map->dev, "Could not match compress type: %d\n",
147 map->cache_type);
148 return -EINVAL;
149 }
150
151 map->num_reg_defaults = config->num_reg_defaults;
152 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
153 map->reg_defaults_raw = config->reg_defaults_raw;
154 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
155 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
156
157 map->cache = NULL;
158 map->cache_ops = cache_types[i];
159
160 if (!map->cache_ops->read ||
161 !map->cache_ops->write ||
162 !map->cache_ops->name)
163 return -EINVAL;
164
165 /* We still need to ensure that the reg_defaults
166 * won't vanish from under us. We'll need to make
167 * a copy of it.
168 */
169 if (config->reg_defaults) {
170 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
171 sizeof(struct reg_default), GFP_KERNEL);
172 if (!tmp_buf)
173 return -ENOMEM;
174 map->reg_defaults = tmp_buf;
175 } else if (map->num_reg_defaults_raw) {
176 /* Some devices such as PMICs don't have cache defaults,
177 * we cope with this by reading back the HW registers and
178 * crafting the cache defaults by hand.
179 */
180 ret = regcache_hw_init(map);
181 if (ret < 0)
182 return ret;
183 if (map->cache_bypass)
184 return 0;
185 }
186
187 if (!map->max_register)
188 map->max_register = map->num_reg_defaults_raw;
189
190 if (map->cache_ops->init) {
191 dev_dbg(map->dev, "Initializing %s cache\n",
192 map->cache_ops->name);
193 ret = map->cache_ops->init(map);
194 if (ret)
195 goto err_free;
196 }
197 return 0;
198
199err_free:
200 kfree(map->reg_defaults);
201 if (map->cache_free)
202 kfree(map->reg_defaults_raw);
203
204 return ret;
205}
206
207void regcache_exit(struct regmap *map)
208{
209 if (map->cache_type == REGCACHE_NONE)
210 return;
211
212 BUG_ON(!map->cache_ops);
213
214 kfree(map->reg_defaults);
215 if (map->cache_free)
216 kfree(map->reg_defaults_raw);
217
218 if (map->cache_ops->exit) {
219 dev_dbg(map->dev, "Destroying %s cache\n",
220 map->cache_ops->name);
221 map->cache_ops->exit(map);
222 }
223}
224
225/**
226 * regcache_read: Fetch the value of a given register from the cache.
227 *
228 * @map: map to configure.
229 * @reg: The register index.
230 * @value: The value to be returned.
231 *
232 * Return a negative value on failure, 0 on success.
233 */
234int regcache_read(struct regmap *map,
235 unsigned int reg, unsigned int *value)
236{
237 int ret;
238
239 if (map->cache_type == REGCACHE_NONE)
240 return -ENOSYS;
241
242 BUG_ON(!map->cache_ops);
243
244 if (!regmap_volatile(map, reg)) {
245 ret = map->cache_ops->read(map, reg, value);
246
247 if (ret == 0)
248 trace_regmap_reg_read_cache(map, reg, *value);
249
250 return ret;
251 }
252
253 return -EINVAL;
254}
255
256/**
257 * regcache_write: Set the value of a given register in the cache.
258 *
259 * @map: map to configure.
260 * @reg: The register index.
261 * @value: The new register value.
262 *
263 * Return a negative value on failure, 0 on success.
264 */
265int regcache_write(struct regmap *map,
266 unsigned int reg, unsigned int value)
267{
268 if (map->cache_type == REGCACHE_NONE)
269 return 0;
270
271 BUG_ON(!map->cache_ops);
272
273 if (!regmap_volatile(map, reg))
274 return map->cache_ops->write(map, reg, value);
275
276 return 0;
277}
278
279static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
280 unsigned int val)
281{
282 int ret;
283
284 /* If we don't know the chip just got reset, then sync everything. */
285 if (!map->no_sync_defaults)
286 return true;
287
288 /* Is this the hardware default? If so skip. */
289 ret = regcache_lookup_reg(map, reg);
290 if (ret >= 0 && val == map->reg_defaults[ret].def)
291 return false;
292 return true;
293}
294
295static int regcache_default_sync(struct regmap *map, unsigned int min,
296 unsigned int max)
297{
298 unsigned int reg;
299
300 for (reg = min; reg <= max; reg += map->reg_stride) {
301 unsigned int val;
302 int ret;
303
304 if (regmap_volatile(map, reg) ||
305 !regmap_writeable(map, reg))
306 continue;
307
308 ret = regcache_read(map, reg, &val);
309 if (ret)
310 return ret;
311
312 if (!regcache_reg_needs_sync(map, reg, val))
313 continue;
314
315 map->cache_bypass = true;
316 ret = _regmap_write(map, reg, val);
317 map->cache_bypass = false;
318 if (ret) {
319 dev_err(map->dev, "Unable to sync register %#x. %d\n",
320 reg, ret);
321 return ret;
322 }
323 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
324 }
325
326 return 0;
327}
328
329/**
330 * regcache_sync: Sync the register cache with the hardware.
331 *
332 * @map: map to configure.
333 *
334 * Any registers that should not be synced should be marked as
335 * volatile. In general drivers can choose not to use the provided
336 * syncing functionality if they so require.
337 *
338 * Return a negative value on failure, 0 on success.
339 */
340int regcache_sync(struct regmap *map)
341{
342 int ret = 0;
343 unsigned int i;
344 const char *name;
345 bool bypass;
346
347 BUG_ON(!map->cache_ops);
348
349 map->lock(map->lock_arg);
350 /* Remember the initial bypass state */
351 bypass = map->cache_bypass;
352 dev_dbg(map->dev, "Syncing %s cache\n",
353 map->cache_ops->name);
354 name = map->cache_ops->name;
355 trace_regcache_sync(map, name, "start");
356
357 if (!map->cache_dirty)
358 goto out;
359
360 map->async = true;
361
362 /* Apply any patch first */
363 map->cache_bypass = true;
364 for (i = 0; i < map->patch_regs; i++) {
365 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
366 if (ret != 0) {
367 dev_err(map->dev, "Failed to write %x = %x: %d\n",
368 map->patch[i].reg, map->patch[i].def, ret);
369 goto out;
370 }
371 }
372 map->cache_bypass = false;
373
374 if (map->cache_ops->sync)
375 ret = map->cache_ops->sync(map, 0, map->max_register);
376 else
377 ret = regcache_default_sync(map, 0, map->max_register);
378
379 if (ret == 0)
380 map->cache_dirty = false;
381
382out:
383 /* Restore the bypass state */
384 map->async = false;
385 map->cache_bypass = bypass;
386 map->no_sync_defaults = false;
387 map->unlock(map->lock_arg);
388
389 regmap_async_complete(map);
390
391 trace_regcache_sync(map, name, "stop");
392
393 return ret;
394}
395EXPORT_SYMBOL_GPL(regcache_sync);
396
397/**
398 * regcache_sync_region: Sync part of the register cache with the hardware.
399 *
400 * @map: map to sync.
401 * @min: first register to sync
402 * @max: last register to sync
403 *
404 * Write all non-default register values in the specified region to
405 * the hardware.
406 *
407 * Return a negative value on failure, 0 on success.
408 */
409int regcache_sync_region(struct regmap *map, unsigned int min,
410 unsigned int max)
411{
412 int ret = 0;
413 const char *name;
414 bool bypass;
415
416 BUG_ON(!map->cache_ops);
417
418 map->lock(map->lock_arg);
419
420 /* Remember the initial bypass state */
421 bypass = map->cache_bypass;
422
423 name = map->cache_ops->name;
424 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
425
426 trace_regcache_sync(map, name, "start region");
427
428 if (!map->cache_dirty)
429 goto out;
430
431 map->async = true;
432
433 if (map->cache_ops->sync)
434 ret = map->cache_ops->sync(map, min, max);
435 else
436 ret = regcache_default_sync(map, min, max);
437
438out:
439 /* Restore the bypass state */
440 map->cache_bypass = bypass;
441 map->async = false;
442 map->no_sync_defaults = false;
443 map->unlock(map->lock_arg);
444
445 regmap_async_complete(map);
446
447 trace_regcache_sync(map, name, "stop region");
448
449 return ret;
450}
451EXPORT_SYMBOL_GPL(regcache_sync_region);
452
453/**
454 * regcache_drop_region: Discard part of the register cache
455 *
456 * @map: map to operate on
457 * @min: first register to discard
458 * @max: last register to discard
459 *
460 * Discard part of the register cache.
461 *
462 * Return a negative value on failure, 0 on success.
463 */
464int regcache_drop_region(struct regmap *map, unsigned int min,
465 unsigned int max)
466{
467 int ret = 0;
468
469 if (!map->cache_ops || !map->cache_ops->drop)
470 return -EINVAL;
471
472 map->lock(map->lock_arg);
473
474 trace_regcache_drop_region(map, min, max);
475
476 ret = map->cache_ops->drop(map, min, max);
477
478 map->unlock(map->lock_arg);
479
480 return ret;
481}
482EXPORT_SYMBOL_GPL(regcache_drop_region);
483
484/**
485 * regcache_cache_only: Put a register map into cache only mode
486 *
487 * @map: map to configure
488 * @cache_only: flag if changes should be written to the hardware
489 *
490 * When a register map is marked as cache only writes to the register
491 * map API will only update the register cache, they will not cause
492 * any hardware changes. This is useful for allowing portions of
493 * drivers to act as though the device were functioning as normal when
494 * it is disabled for power saving reasons.
495 */
496void regcache_cache_only(struct regmap *map, bool enable)
497{
498 map->lock(map->lock_arg);
499 WARN_ON(map->cache_bypass && enable);
500 map->cache_only = enable;
501 trace_regmap_cache_only(map, enable);
502 map->unlock(map->lock_arg);
503}
504EXPORT_SYMBOL_GPL(regcache_cache_only);
505
506/**
507 * regcache_mark_dirty: Indicate that HW registers were reset to default values
508 *
509 * @map: map to mark
510 *
511 * Inform regcache that the device has been powered down or reset, so that
512 * on resume, regcache_sync() knows to write out all non-default values
513 * stored in the cache.
514 *
515 * If this function is not called, regcache_sync() will assume that
516 * the hardware state still matches the cache state, modulo any writes that
517 * happened when cache_only was true.
518 */
519void regcache_mark_dirty(struct regmap *map)
520{
521 map->lock(map->lock_arg);
522 map->cache_dirty = true;
523 map->no_sync_defaults = true;
524 map->unlock(map->lock_arg);
525}
526EXPORT_SYMBOL_GPL(regcache_mark_dirty);
527
528/**
529 * regcache_cache_bypass: Put a register map into cache bypass mode
530 *
531 * @map: map to configure
532 * @cache_bypass: flag if changes should not be written to the hardware
533 *
534 * When a register map is marked with the cache bypass option, writes
535 * to the register map API will only update the hardware and not the
536 * the cache directly. This is useful when syncing the cache back to
537 * the hardware.
538 */
539void regcache_cache_bypass(struct regmap *map, bool enable)
540{
541 map->lock(map->lock_arg);
542 WARN_ON(map->cache_only && enable);
543 map->cache_bypass = enable;
544 trace_regmap_cache_bypass(map, enable);
545 map->unlock(map->lock_arg);
546}
547EXPORT_SYMBOL_GPL(regcache_cache_bypass);
548
549bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
550 unsigned int val)
551{
552 if (regcache_get_val(map, base, idx) == val)
553 return true;
554
555 /* Use device native format if possible */
556 if (map->format.format_val) {
557 map->format.format_val(base + (map->cache_word_size * idx),
558 val, 0);
559 return false;
560 }
561
562 switch (map->cache_word_size) {
563 case 1: {
564 u8 *cache = base;
565
566 cache[idx] = val;
567 break;
568 }
569 case 2: {
570 u16 *cache = base;
571
572 cache[idx] = val;
573 break;
574 }
575 case 4: {
576 u32 *cache = base;
577
578 cache[idx] = val;
579 break;
580 }
581#ifdef CONFIG_64BIT
582 case 8: {
583 u64 *cache = base;
584
585 cache[idx] = val;
586 break;
587 }
588#endif
589 default:
590 BUG();
591 }
592 return false;
593}
594
595unsigned int regcache_get_val(struct regmap *map, const void *base,
596 unsigned int idx)
597{
598 if (!base)
599 return -EINVAL;
600
601 /* Use device native format if possible */
602 if (map->format.parse_val)
603 return map->format.parse_val(regcache_get_val_addr(map, base,
604 idx));
605
606 switch (map->cache_word_size) {
607 case 1: {
608 const u8 *cache = base;
609
610 return cache[idx];
611 }
612 case 2: {
613 const u16 *cache = base;
614
615 return cache[idx];
616 }
617 case 4: {
618 const u32 *cache = base;
619
620 return cache[idx];
621 }
622#ifdef CONFIG_64BIT
623 case 8: {
624 const u64 *cache = base;
625
626 return cache[idx];
627 }
628#endif
629 default:
630 BUG();
631 }
632 /* unreachable */
633 return -1;
634}
635
636static int regcache_default_cmp(const void *a, const void *b)
637{
638 const struct reg_default *_a = a;
639 const struct reg_default *_b = b;
640
641 return _a->reg - _b->reg;
642}
643
644int regcache_lookup_reg(struct regmap *map, unsigned int reg)
645{
646 struct reg_default key;
647 struct reg_default *r;
648
649 key.reg = reg;
650 key.def = 0;
651
652 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
653 sizeof(struct reg_default), regcache_default_cmp);
654
655 if (r)
656 return r - map->reg_defaults;
657 else
658 return -ENOENT;
659}
660
661static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
662{
663 if (!cache_present)
664 return true;
665
666 return test_bit(idx, cache_present);
667}
668
669static int regcache_sync_block_single(struct regmap *map, void *block,
670 unsigned long *cache_present,
671 unsigned int block_base,
672 unsigned int start, unsigned int end)
673{
674 unsigned int i, regtmp, val;
675 int ret;
676
677 for (i = start; i < end; i++) {
678 regtmp = block_base + (i * map->reg_stride);
679
680 if (!regcache_reg_present(cache_present, i) ||
681 !regmap_writeable(map, regtmp))
682 continue;
683
684 val = regcache_get_val(map, block, i);
685 if (!regcache_reg_needs_sync(map, regtmp, val))
686 continue;
687
688 map->cache_bypass = true;
689
690 ret = _regmap_write(map, regtmp, val);
691
692 map->cache_bypass = false;
693 if (ret != 0) {
694 dev_err(map->dev, "Unable to sync register %#x. %d\n",
695 regtmp, ret);
696 return ret;
697 }
698 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
699 regtmp, val);
700 }
701
702 return 0;
703}
704
705static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
706 unsigned int base, unsigned int cur)
707{
708 size_t val_bytes = map->format.val_bytes;
709 int ret, count;
710
711 if (*data == NULL)
712 return 0;
713
714 count = (cur - base) / map->reg_stride;
715
716 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
717 count * val_bytes, count, base, cur - map->reg_stride);
718
719 map->cache_bypass = true;
720
721 ret = _regmap_raw_write(map, base, *data, count * val_bytes);
722 if (ret)
723 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
724 base, cur - map->reg_stride, ret);
725
726 map->cache_bypass = false;
727
728 *data = NULL;
729
730 return ret;
731}
732
733static int regcache_sync_block_raw(struct regmap *map, void *block,
734 unsigned long *cache_present,
735 unsigned int block_base, unsigned int start,
736 unsigned int end)
737{
738 unsigned int i, val;
739 unsigned int regtmp = 0;
740 unsigned int base = 0;
741 const void *data = NULL;
742 int ret;
743
744 for (i = start; i < end; i++) {
745 regtmp = block_base + (i * map->reg_stride);
746
747 if (!regcache_reg_present(cache_present, i) ||
748 !regmap_writeable(map, regtmp)) {
749 ret = regcache_sync_block_raw_flush(map, &data,
750 base, regtmp);
751 if (ret != 0)
752 return ret;
753 continue;
754 }
755
756 val = regcache_get_val(map, block, i);
757 if (!regcache_reg_needs_sync(map, regtmp, val)) {
758 ret = regcache_sync_block_raw_flush(map, &data,
759 base, regtmp);
760 if (ret != 0)
761 return ret;
762 continue;
763 }
764
765 if (!data) {
766 data = regcache_get_val_addr(map, block, i);
767 base = regtmp;
768 }
769 }
770
771 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
772 map->reg_stride);
773}
774
775int regcache_sync_block(struct regmap *map, void *block,
776 unsigned long *cache_present,
777 unsigned int block_base, unsigned int start,
778 unsigned int end)
779{
780 if (regmap_can_raw_write(map) && !map->use_single_write)
781 return regcache_sync_block_raw(map, block, cache_present,
782 block_base, start, end);
783 else
784 return regcache_sync_block_single(map, block, cache_present,
785 block_base, start, end);
786}