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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H2 (R8A77900) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2014 Cogent Embedded Inc.
8 */
9
10#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/power/r8a7790-sysc.h>
14
15/ {
16 compatible = "renesas,r8a7790";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &iic0;
26 i2c5 = &iic1;
27 i2c6 = &iic2;
28 i2c7 = &iic3;
29 spi0 = &qspi;
30 spi1 = &msiof0;
31 spi2 = &msiof1;
32 spi3 = &msiof2;
33 spi4 = &msiof3;
34 vin0 = &vin0;
35 vin1 = &vin1;
36 vin2 = &vin2;
37 vin3 = &vin3;
38 };
39
40 /*
41 * The external audio clocks are configured as 0 Hz fixed frequency
42 * clocks by default.
43 * Boards that provide audio clocks should override them.
44 */
45 audio_clk_a: audio_clk_a {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <0>;
49 };
50 audio_clk_b: audio_clk_b {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <0>;
54 };
55 audio_clk_c: audio_clk_c {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 /* External CAN clock */
62 can_clk: can {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 /* This value must be overridden by the board. */
66 clock-frequency = <0>;
67 };
68
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu0: cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a15";
76 reg = <0>;
77 clock-frequency = <1300000000>;
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
79 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
80 enable-method = "renesas,apmu";
81 next-level-cache = <&L2_CA15>;
82 capacity-dmips-mhz = <1024>;
83 voltage-tolerance = <1>; /* 1% */
84 clock-latency = <300000>; /* 300 us */
85
86 /* kHz - uV - OPPs unknown yet */
87 operating-points = <1400000 1000000>,
88 <1225000 1000000>,
89 <1050000 1000000>,
90 < 875000 1000000>,
91 < 700000 1000000>,
92 < 350000 1000000>;
93 };
94
95 cpu1: cpu@1 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a15";
98 reg = <1>;
99 clock-frequency = <1300000000>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
101 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
102 enable-method = "renesas,apmu";
103 next-level-cache = <&L2_CA15>;
104 capacity-dmips-mhz = <1024>;
105 voltage-tolerance = <1>; /* 1% */
106 clock-latency = <300000>; /* 300 us */
107
108 /* kHz - uV - OPPs unknown yet */
109 operating-points = <1400000 1000000>,
110 <1225000 1000000>,
111 <1050000 1000000>,
112 < 875000 1000000>,
113 < 700000 1000000>,
114 < 350000 1000000>;
115 };
116
117 cpu2: cpu@2 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a15";
120 reg = <2>;
121 clock-frequency = <1300000000>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
123 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
124 enable-method = "renesas,apmu";
125 next-level-cache = <&L2_CA15>;
126 capacity-dmips-mhz = <1024>;
127 voltage-tolerance = <1>; /* 1% */
128 clock-latency = <300000>; /* 300 us */
129
130 /* kHz - uV - OPPs unknown yet */
131 operating-points = <1400000 1000000>,
132 <1225000 1000000>,
133 <1050000 1000000>,
134 < 875000 1000000>,
135 < 700000 1000000>,
136 < 350000 1000000>;
137 };
138
139 cpu3: cpu@3 {
140 device_type = "cpu";
141 compatible = "arm,cortex-a15";
142 reg = <3>;
143 clock-frequency = <1300000000>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
145 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
146 enable-method = "renesas,apmu";
147 next-level-cache = <&L2_CA15>;
148 capacity-dmips-mhz = <1024>;
149 voltage-tolerance = <1>; /* 1% */
150 clock-latency = <300000>; /* 300 us */
151
152 /* kHz - uV - OPPs unknown yet */
153 operating-points = <1400000 1000000>,
154 <1225000 1000000>,
155 <1050000 1000000>,
156 < 875000 1000000>,
157 < 700000 1000000>,
158 < 350000 1000000>;
159 };
160
161 cpu4: cpu@100 {
162 device_type = "cpu";
163 compatible = "arm,cortex-a7";
164 reg = <0x100>;
165 clock-frequency = <780000000>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
167 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
168 enable-method = "renesas,apmu";
169 next-level-cache = <&L2_CA7>;
170 capacity-dmips-mhz = <539>;
171 };
172
173 cpu5: cpu@101 {
174 device_type = "cpu";
175 compatible = "arm,cortex-a7";
176 reg = <0x101>;
177 clock-frequency = <780000000>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
179 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
180 enable-method = "renesas,apmu";
181 next-level-cache = <&L2_CA7>;
182 capacity-dmips-mhz = <539>;
183 };
184
185 cpu6: cpu@102 {
186 device_type = "cpu";
187 compatible = "arm,cortex-a7";
188 reg = <0x102>;
189 clock-frequency = <780000000>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
191 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
192 enable-method = "renesas,apmu";
193 next-level-cache = <&L2_CA7>;
194 capacity-dmips-mhz = <539>;
195 };
196
197 cpu7: cpu@103 {
198 device_type = "cpu";
199 compatible = "arm,cortex-a7";
200 reg = <0x103>;
201 clock-frequency = <780000000>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
203 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
204 enable-method = "renesas,apmu";
205 next-level-cache = <&L2_CA7>;
206 capacity-dmips-mhz = <539>;
207 };
208
209 L2_CA15: cache-controller-0 {
210 compatible = "cache";
211 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
212 cache-unified;
213 cache-level = <2>;
214 };
215
216 L2_CA7: cache-controller-1 {
217 compatible = "cache";
218 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
219 cache-unified;
220 cache-level = <2>;
221 };
222 };
223
224 /* External root clock */
225 extal_clk: extal {
226 compatible = "fixed-clock";
227 #clock-cells = <0>;
228 /* This value must be overridden by the board. */
229 clock-frequency = <0>;
230 };
231
232 /* External PCIe clock - can be overridden by the board */
233 pcie_bus_clk: pcie_bus {
234 compatible = "fixed-clock";
235 #clock-cells = <0>;
236 clock-frequency = <0>;
237 };
238
239 pmu-0 {
240 compatible = "arm,cortex-a15-pmu";
241 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
242 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
243 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
244 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
245 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
246 };
247
248 pmu-1 {
249 compatible = "arm,cortex-a7-pmu";
250 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
251 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
252 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
253 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
255 };
256
257 /* External SCIF clock */
258 scif_clk: scif {
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
261 /* This value must be overridden by the board. */
262 clock-frequency = <0>;
263 };
264
265 soc {
266 compatible = "simple-bus";
267 interrupt-parent = <&gic>;
268
269 #address-cells = <2>;
270 #size-cells = <2>;
271 ranges;
272
273 rwdt: watchdog@e6020000 {
274 compatible = "renesas,r8a7790-wdt",
275 "renesas,rcar-gen2-wdt";
276 reg = <0 0xe6020000 0 0x0c>;
277 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&cpg CPG_MOD 402>;
279 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
280 resets = <&cpg 402>;
281 status = "disabled";
282 };
283
284 gpio0: gpio@e6050000 {
285 compatible = "renesas,gpio-r8a7790",
286 "renesas,rcar-gen2-gpio";
287 reg = <0 0xe6050000 0 0x50>;
288 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 gpio-ranges = <&pfc 0 0 32>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
294 clocks = <&cpg CPG_MOD 912>;
295 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
296 resets = <&cpg 912>;
297 };
298
299 gpio1: gpio@e6051000 {
300 compatible = "renesas,gpio-r8a7790",
301 "renesas,rcar-gen2-gpio";
302 reg = <0 0xe6051000 0 0x50>;
303 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
304 #gpio-cells = <2>;
305 gpio-controller;
306 gpio-ranges = <&pfc 0 32 30>;
307 #interrupt-cells = <2>;
308 interrupt-controller;
309 clocks = <&cpg CPG_MOD 911>;
310 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
311 resets = <&cpg 911>;
312 };
313
314 gpio2: gpio@e6052000 {
315 compatible = "renesas,gpio-r8a7790",
316 "renesas,rcar-gen2-gpio";
317 reg = <0 0xe6052000 0 0x50>;
318 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
319 #gpio-cells = <2>;
320 gpio-controller;
321 gpio-ranges = <&pfc 0 64 30>;
322 #interrupt-cells = <2>;
323 interrupt-controller;
324 clocks = <&cpg CPG_MOD 910>;
325 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
326 resets = <&cpg 910>;
327 };
328
329 gpio3: gpio@e6053000 {
330 compatible = "renesas,gpio-r8a7790",
331 "renesas,rcar-gen2-gpio";
332 reg = <0 0xe6053000 0 0x50>;
333 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>;
335 gpio-controller;
336 gpio-ranges = <&pfc 0 96 32>;
337 #interrupt-cells = <2>;
338 interrupt-controller;
339 clocks = <&cpg CPG_MOD 909>;
340 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
341 resets = <&cpg 909>;
342 };
343
344 gpio4: gpio@e6054000 {
345 compatible = "renesas,gpio-r8a7790",
346 "renesas,rcar-gen2-gpio";
347 reg = <0 0xe6054000 0 0x50>;
348 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 gpio-ranges = <&pfc 0 128 32>;
352 #interrupt-cells = <2>;
353 interrupt-controller;
354 clocks = <&cpg CPG_MOD 908>;
355 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
356 resets = <&cpg 908>;
357 };
358
359 gpio5: gpio@e6055000 {
360 compatible = "renesas,gpio-r8a7790",
361 "renesas,rcar-gen2-gpio";
362 reg = <0 0xe6055000 0 0x50>;
363 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-ranges = <&pfc 0 160 32>;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 clocks = <&cpg CPG_MOD 907>;
370 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
371 resets = <&cpg 907>;
372 };
373
374 pfc: pinctrl@e6060000 {
375 compatible = "renesas,pfc-r8a7790";
376 reg = <0 0xe6060000 0 0x250>;
377 };
378
379 cpg: clock-controller@e6150000 {
380 compatible = "renesas,r8a7790-cpg-mssr";
381 reg = <0 0xe6150000 0 0x1000>;
382 clocks = <&extal_clk>, <&usb_extal_clk>;
383 clock-names = "extal", "usb_extal";
384 #clock-cells = <2>;
385 #power-domain-cells = <0>;
386 #reset-cells = <1>;
387 };
388
389 apmu@e6151000 {
390 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
391 reg = <0 0xe6151000 0 0x188>;
392 cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
393 };
394
395 apmu@e6152000 {
396 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
397 reg = <0 0xe6152000 0 0x188>;
398 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
399 };
400
401 rst: reset-controller@e6160000 {
402 compatible = "renesas,r8a7790-rst";
403 reg = <0 0xe6160000 0 0x0100>;
404 };
405
406 sysc: system-controller@e6180000 {
407 compatible = "renesas,r8a7790-sysc";
408 reg = <0 0xe6180000 0 0x0200>;
409 #power-domain-cells = <1>;
410 };
411
412 irqc0: interrupt-controller@e61c0000 {
413 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
414 #interrupt-cells = <2>;
415 interrupt-controller;
416 reg = <0 0xe61c0000 0 0x200>;
417 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 407>;
422 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
423 resets = <&cpg 407>;
424 };
425
426 thermal: thermal@e61f0000 {
427 compatible = "renesas,thermal-r8a7790",
428 "renesas,rcar-gen2-thermal",
429 "renesas,rcar-thermal";
430 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
431 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cpg CPG_MOD 522>;
433 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
434 resets = <&cpg 522>;
435 #thermal-sensor-cells = <0>;
436 };
437
438 ipmmu_sy0: iommu@e6280000 {
439 compatible = "renesas,ipmmu-r8a7790",
440 "renesas,ipmmu-vmsa";
441 reg = <0 0xe6280000 0 0x1000>;
442 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
444 #iommu-cells = <1>;
445 status = "disabled";
446 };
447
448 ipmmu_sy1: iommu@e6290000 {
449 compatible = "renesas,ipmmu-r8a7790",
450 "renesas,ipmmu-vmsa";
451 reg = <0 0xe6290000 0 0x1000>;
452 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
453 #iommu-cells = <1>;
454 status = "disabled";
455 };
456
457 ipmmu_ds: iommu@e6740000 {
458 compatible = "renesas,ipmmu-r8a7790",
459 "renesas,ipmmu-vmsa";
460 reg = <0 0xe6740000 0 0x1000>;
461 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
463 #iommu-cells = <1>;
464 status = "disabled";
465 };
466
467 ipmmu_mp: iommu@ec680000 {
468 compatible = "renesas,ipmmu-r8a7790",
469 "renesas,ipmmu-vmsa";
470 reg = <0 0xec680000 0 0x1000>;
471 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
472 #iommu-cells = <1>;
473 status = "disabled";
474 };
475
476 ipmmu_mx: iommu@fe951000 {
477 compatible = "renesas,ipmmu-r8a7790",
478 "renesas,ipmmu-vmsa";
479 reg = <0 0xfe951000 0 0x1000>;
480 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
482 #iommu-cells = <1>;
483 status = "disabled";
484 };
485
486 ipmmu_rt: iommu@ffc80000 {
487 compatible = "renesas,ipmmu-r8a7790",
488 "renesas,ipmmu-vmsa";
489 reg = <0 0xffc80000 0 0x1000>;
490 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
491 #iommu-cells = <1>;
492 status = "disabled";
493 };
494
495 icram0: sram@e63a0000 {
496 compatible = "mmio-sram";
497 reg = <0 0xe63a0000 0 0x12000>;
498 #address-cells = <1>;
499 #size-cells = <1>;
500 ranges = <0 0 0xe63a0000 0x12000>;
501 };
502
503 icram1: sram@e63c0000 {
504 compatible = "mmio-sram";
505 reg = <0 0xe63c0000 0 0x1000>;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0 0 0xe63c0000 0x1000>;
509
510 smp-sram@0 {
511 compatible = "renesas,smp-sram";
512 reg = <0 0x100>;
513 };
514 };
515
516 i2c0: i2c@e6508000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "renesas,i2c-r8a7790",
520 "renesas,rcar-gen2-i2c";
521 reg = <0 0xe6508000 0 0x40>;
522 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cpg CPG_MOD 931>;
524 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
525 resets = <&cpg 931>;
526 i2c-scl-internal-delay-ns = <110>;
527 status = "disabled";
528 };
529
530 i2c1: i2c@e6518000 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "renesas,i2c-r8a7790",
534 "renesas,rcar-gen2-i2c";
535 reg = <0 0xe6518000 0 0x40>;
536 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cpg CPG_MOD 930>;
538 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
539 resets = <&cpg 930>;
540 i2c-scl-internal-delay-ns = <6>;
541 status = "disabled";
542 };
543
544 i2c2: i2c@e6530000 {
545 #address-cells = <1>;
546 #size-cells = <0>;
547 compatible = "renesas,i2c-r8a7790",
548 "renesas,rcar-gen2-i2c";
549 reg = <0 0xe6530000 0 0x40>;
550 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cpg CPG_MOD 929>;
552 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
553 resets = <&cpg 929>;
554 i2c-scl-internal-delay-ns = <6>;
555 status = "disabled";
556 };
557
558 i2c3: i2c@e6540000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "renesas,i2c-r8a7790",
562 "renesas,rcar-gen2-i2c";
563 reg = <0 0xe6540000 0 0x40>;
564 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cpg CPG_MOD 928>;
566 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
567 resets = <&cpg 928>;
568 i2c-scl-internal-delay-ns = <110>;
569 status = "disabled";
570 };
571
572 iic0: i2c@e6500000 {
573 #address-cells = <1>;
574 #size-cells = <0>;
575 compatible = "renesas,iic-r8a7790",
576 "renesas,rcar-gen2-iic",
577 "renesas,rmobile-iic";
578 reg = <0 0xe6500000 0 0x425>;
579 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cpg CPG_MOD 318>;
581 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
582 <&dmac1 0x61>, <&dmac1 0x62>;
583 dma-names = "tx", "rx", "tx", "rx";
584 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
585 resets = <&cpg 318>;
586 status = "disabled";
587 };
588
589 iic1: i2c@e6510000 {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 compatible = "renesas,iic-r8a7790",
593 "renesas,rcar-gen2-iic",
594 "renesas,rmobile-iic";
595 reg = <0 0xe6510000 0 0x425>;
596 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cpg CPG_MOD 323>;
598 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
599 <&dmac1 0x65>, <&dmac1 0x66>;
600 dma-names = "tx", "rx", "tx", "rx";
601 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
602 resets = <&cpg 323>;
603 status = "disabled";
604 };
605
606 iic2: i2c@e6520000 {
607 #address-cells = <1>;
608 #size-cells = <0>;
609 compatible = "renesas,iic-r8a7790",
610 "renesas,rcar-gen2-iic",
611 "renesas,rmobile-iic";
612 reg = <0 0xe6520000 0 0x425>;
613 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cpg CPG_MOD 300>;
615 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
616 <&dmac1 0x69>, <&dmac1 0x6a>;
617 dma-names = "tx", "rx", "tx", "rx";
618 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
619 resets = <&cpg 300>;
620 status = "disabled";
621 };
622
623 iic3: i2c@e60b0000 {
624 #address-cells = <1>;
625 #size-cells = <0>;
626 compatible = "renesas,iic-r8a7790",
627 "renesas,rcar-gen2-iic",
628 "renesas,rmobile-iic";
629 reg = <0 0xe60b0000 0 0x425>;
630 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&cpg CPG_MOD 926>;
632 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
633 <&dmac1 0x77>, <&dmac1 0x78>;
634 dma-names = "tx", "rx", "tx", "rx";
635 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
636 resets = <&cpg 926>;
637 status = "disabled";
638 };
639
640 hsusb: usb@e6590000 {
641 compatible = "renesas,usbhs-r8a7790",
642 "renesas,rcar-gen2-usbhs";
643 reg = <0 0xe6590000 0 0x100>;
644 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cpg CPG_MOD 704>;
646 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
647 <&usb_dmac1 0>, <&usb_dmac1 1>;
648 dma-names = "ch0", "ch1", "ch2", "ch3";
649 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
650 resets = <&cpg 704>;
651 renesas,buswait = <4>;
652 phys = <&usb0 1>;
653 phy-names = "usb";
654 status = "disabled";
655 };
656
657 usbphy: usb-phy-controller@e6590100 {
658 compatible = "renesas,usb-phy-r8a7790",
659 "renesas,rcar-gen2-usb-phy";
660 reg = <0 0xe6590100 0 0x100>;
661 #address-cells = <1>;
662 #size-cells = <0>;
663 clocks = <&cpg CPG_MOD 704>;
664 clock-names = "usbhs";
665 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
666 resets = <&cpg 704>;
667 status = "disabled";
668
669 usb0: usb-phy@0 {
670 reg = <0>;
671 #phy-cells = <1>;
672 };
673 usb2: usb-phy@2 {
674 reg = <2>;
675 #phy-cells = <1>;
676 };
677 };
678
679 usb_dmac0: dma-controller@e65a0000 {
680 compatible = "renesas,r8a7790-usb-dmac",
681 "renesas,usb-dmac";
682 reg = <0 0xe65a0000 0 0x100>;
683 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
685 interrupt-names = "ch0", "ch1";
686 clocks = <&cpg CPG_MOD 330>;
687 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
688 resets = <&cpg 330>;
689 #dma-cells = <1>;
690 dma-channels = <2>;
691 };
692
693 usb_dmac1: dma-controller@e65b0000 {
694 compatible = "renesas,r8a7790-usb-dmac",
695 "renesas,usb-dmac";
696 reg = <0 0xe65b0000 0 0x100>;
697 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "ch0", "ch1";
700 clocks = <&cpg CPG_MOD 331>;
701 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
702 resets = <&cpg 331>;
703 #dma-cells = <1>;
704 dma-channels = <2>;
705 };
706
707 dmac0: dma-controller@e6700000 {
708 compatible = "renesas,dmac-r8a7790",
709 "renesas,rcar-dmac";
710 reg = <0 0xe6700000 0 0x20000>;
711 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
727 interrupt-names = "error",
728 "ch0", "ch1", "ch2", "ch3",
729 "ch4", "ch5", "ch6", "ch7",
730 "ch8", "ch9", "ch10", "ch11",
731 "ch12", "ch13", "ch14";
732 clocks = <&cpg CPG_MOD 219>;
733 clock-names = "fck";
734 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
735 resets = <&cpg 219>;
736 #dma-cells = <1>;
737 dma-channels = <15>;
738 };
739
740 dmac1: dma-controller@e6720000 {
741 compatible = "renesas,dmac-r8a7790",
742 "renesas,rcar-dmac";
743 reg = <0 0xe6720000 0 0x20000>;
744 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
760 interrupt-names = "error",
761 "ch0", "ch1", "ch2", "ch3",
762 "ch4", "ch5", "ch6", "ch7",
763 "ch8", "ch9", "ch10", "ch11",
764 "ch12", "ch13", "ch14";
765 clocks = <&cpg CPG_MOD 218>;
766 clock-names = "fck";
767 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
768 resets = <&cpg 218>;
769 #dma-cells = <1>;
770 dma-channels = <15>;
771 };
772
773 avb: ethernet@e6800000 {
774 compatible = "renesas,etheravb-r8a7790",
775 "renesas,etheravb-rcar-gen2";
776 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
777 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cpg CPG_MOD 812>;
779 clock-names = "fck";
780 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
781 resets = <&cpg 812>;
782 #address-cells = <1>;
783 #size-cells = <0>;
784 status = "disabled";
785 };
786
787 qspi: spi@e6b10000 {
788 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
789 reg = <0 0xe6b10000 0 0x2c>;
790 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 917>;
792 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
793 <&dmac1 0x17>, <&dmac1 0x18>;
794 dma-names = "tx", "rx", "tx", "rx";
795 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
796 resets = <&cpg 917>;
797 num-cs = <1>;
798 #address-cells = <1>;
799 #size-cells = <0>;
800 status = "disabled";
801 };
802
803 scifa0: serial@e6c40000 {
804 compatible = "renesas,scifa-r8a7790",
805 "renesas,rcar-gen2-scifa", "renesas,scifa";
806 reg = <0 0xe6c40000 0 64>;
807 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&cpg CPG_MOD 204>;
809 clock-names = "fck";
810 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
811 <&dmac1 0x21>, <&dmac1 0x22>;
812 dma-names = "tx", "rx", "tx", "rx";
813 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
814 resets = <&cpg 204>;
815 status = "disabled";
816 };
817
818 scifa1: serial@e6c50000 {
819 compatible = "renesas,scifa-r8a7790",
820 "renesas,rcar-gen2-scifa", "renesas,scifa";
821 reg = <0 0xe6c50000 0 64>;
822 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&cpg CPG_MOD 203>;
824 clock-names = "fck";
825 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
826 <&dmac1 0x25>, <&dmac1 0x26>;
827 dma-names = "tx", "rx", "tx", "rx";
828 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
829 resets = <&cpg 203>;
830 status = "disabled";
831 };
832
833 scifa2: serial@e6c60000 {
834 compatible = "renesas,scifa-r8a7790",
835 "renesas,rcar-gen2-scifa", "renesas,scifa";
836 reg = <0 0xe6c60000 0 64>;
837 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 202>;
839 clock-names = "fck";
840 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
841 <&dmac1 0x27>, <&dmac1 0x28>;
842 dma-names = "tx", "rx", "tx", "rx";
843 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
844 resets = <&cpg 202>;
845 status = "disabled";
846 };
847
848 scifb0: serial@e6c20000 {
849 compatible = "renesas,scifb-r8a7790",
850 "renesas,rcar-gen2-scifb", "renesas,scifb";
851 reg = <0 0xe6c20000 0 0x100>;
852 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&cpg CPG_MOD 206>;
854 clock-names = "fck";
855 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
856 <&dmac1 0x3d>, <&dmac1 0x3e>;
857 dma-names = "tx", "rx", "tx", "rx";
858 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
859 resets = <&cpg 206>;
860 status = "disabled";
861 };
862
863 scifb1: serial@e6c30000 {
864 compatible = "renesas,scifb-r8a7790",
865 "renesas,rcar-gen2-scifb", "renesas,scifb";
866 reg = <0 0xe6c30000 0 0x100>;
867 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&cpg CPG_MOD 207>;
869 clock-names = "fck";
870 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
871 <&dmac1 0x19>, <&dmac1 0x1a>;
872 dma-names = "tx", "rx", "tx", "rx";
873 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
874 resets = <&cpg 207>;
875 status = "disabled";
876 };
877
878 scifb2: serial@e6ce0000 {
879 compatible = "renesas,scifb-r8a7790",
880 "renesas,rcar-gen2-scifb", "renesas,scifb";
881 reg = <0 0xe6ce0000 0 0x100>;
882 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&cpg CPG_MOD 216>;
884 clock-names = "fck";
885 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
886 <&dmac1 0x1d>, <&dmac1 0x1e>;
887 dma-names = "tx", "rx", "tx", "rx";
888 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
889 resets = <&cpg 216>;
890 status = "disabled";
891 };
892
893 scif0: serial@e6e60000 {
894 compatible = "renesas,scif-r8a7790",
895 "renesas,rcar-gen2-scif",
896 "renesas,scif";
897 reg = <0 0xe6e60000 0 64>;
898 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cpg CPG_MOD 721>,
900 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
901 clock-names = "fck", "brg_int", "scif_clk";
902 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
903 <&dmac1 0x29>, <&dmac1 0x2a>;
904 dma-names = "tx", "rx", "tx", "rx";
905 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
906 resets = <&cpg 721>;
907 status = "disabled";
908 };
909
910 scif1: serial@e6e68000 {
911 compatible = "renesas,scif-r8a7790",
912 "renesas,rcar-gen2-scif",
913 "renesas,scif";
914 reg = <0 0xe6e68000 0 64>;
915 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&cpg CPG_MOD 720>,
917 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
918 clock-names = "fck", "brg_int", "scif_clk";
919 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
920 <&dmac1 0x2d>, <&dmac1 0x2e>;
921 dma-names = "tx", "rx", "tx", "rx";
922 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
923 resets = <&cpg 720>;
924 status = "disabled";
925 };
926
927 scif2: serial@e6e56000 {
928 compatible = "renesas,scif-r8a7790",
929 "renesas,rcar-gen2-scif",
930 "renesas,scif";
931 reg = <0 0xe6e56000 0 64>;
932 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cpg CPG_MOD 310>,
934 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
935 clock-names = "fck", "brg_int", "scif_clk";
936 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
937 <&dmac1 0x2b>, <&dmac1 0x2c>;
938 dma-names = "tx", "rx", "tx", "rx";
939 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
940 resets = <&cpg 310>;
941 status = "disabled";
942 };
943
944 hscif0: serial@e62c0000 {
945 compatible = "renesas,hscif-r8a7790",
946 "renesas,rcar-gen2-hscif", "renesas,hscif";
947 reg = <0 0xe62c0000 0 96>;
948 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cpg CPG_MOD 717>,
950 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
951 clock-names = "fck", "brg_int", "scif_clk";
952 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
953 <&dmac1 0x39>, <&dmac1 0x3a>;
954 dma-names = "tx", "rx", "tx", "rx";
955 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
956 resets = <&cpg 717>;
957 status = "disabled";
958 };
959
960 hscif1: serial@e62c8000 {
961 compatible = "renesas,hscif-r8a7790",
962 "renesas,rcar-gen2-hscif", "renesas,hscif";
963 reg = <0 0xe62c8000 0 96>;
964 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&cpg CPG_MOD 716>,
966 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
967 clock-names = "fck", "brg_int", "scif_clk";
968 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
969 <&dmac1 0x4d>, <&dmac1 0x4e>;
970 dma-names = "tx", "rx", "tx", "rx";
971 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
972 resets = <&cpg 716>;
973 status = "disabled";
974 };
975
976 msiof0: spi@e6e20000 {
977 compatible = "renesas,msiof-r8a7790",
978 "renesas,rcar-gen2-msiof";
979 reg = <0 0xe6e20000 0 0x0064>;
980 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cpg CPG_MOD 0>;
982 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
983 <&dmac1 0x51>, <&dmac1 0x52>;
984 dma-names = "tx", "rx", "tx", "rx";
985 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
986 resets = <&cpg 0>;
987 #address-cells = <1>;
988 #size-cells = <0>;
989 status = "disabled";
990 };
991
992 msiof1: spi@e6e10000 {
993 compatible = "renesas,msiof-r8a7790",
994 "renesas,rcar-gen2-msiof";
995 reg = <0 0xe6e10000 0 0x0064>;
996 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&cpg CPG_MOD 208>;
998 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
999 <&dmac1 0x55>, <&dmac1 0x56>;
1000 dma-names = "tx", "rx", "tx", "rx";
1001 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1002 resets = <&cpg 208>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 status = "disabled";
1006 };
1007
1008 msiof2: spi@e6e00000 {
1009 compatible = "renesas,msiof-r8a7790",
1010 "renesas,rcar-gen2-msiof";
1011 reg = <0 0xe6e00000 0 0x0064>;
1012 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cpg CPG_MOD 205>;
1014 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1015 <&dmac1 0x41>, <&dmac1 0x42>;
1016 dma-names = "tx", "rx", "tx", "rx";
1017 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1018 resets = <&cpg 205>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
1024 msiof3: spi@e6c90000 {
1025 compatible = "renesas,msiof-r8a7790",
1026 "renesas,rcar-gen2-msiof";
1027 reg = <0 0xe6c90000 0 0x0064>;
1028 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&cpg CPG_MOD 215>;
1030 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1031 <&dmac1 0x45>, <&dmac1 0x46>;
1032 dma-names = "tx", "rx", "tx", "rx";
1033 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1034 resets = <&cpg 215>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 status = "disabled";
1038 };
1039
1040 can0: can@e6e80000 {
1041 compatible = "renesas,can-r8a7790",
1042 "renesas,rcar-gen2-can";
1043 reg = <0 0xe6e80000 0 0x1000>;
1044 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&cpg CPG_MOD 916>,
1046 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
1047 clock-names = "clkp1", "clkp2", "can_clk";
1048 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1049 resets = <&cpg 916>;
1050 status = "disabled";
1051 };
1052
1053 can1: can@e6e88000 {
1054 compatible = "renesas,can-r8a7790",
1055 "renesas,rcar-gen2-can";
1056 reg = <0 0xe6e88000 0 0x1000>;
1057 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&cpg CPG_MOD 915>,
1059 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
1060 clock-names = "clkp1", "clkp2", "can_clk";
1061 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1062 resets = <&cpg 915>;
1063 status = "disabled";
1064 };
1065
1066 vin0: video@e6ef0000 {
1067 compatible = "renesas,vin-r8a7790",
1068 "renesas,rcar-gen2-vin";
1069 reg = <0 0xe6ef0000 0 0x1000>;
1070 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&cpg CPG_MOD 811>;
1072 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1073 resets = <&cpg 811>;
1074 status = "disabled";
1075 };
1076
1077 vin1: video@e6ef1000 {
1078 compatible = "renesas,vin-r8a7790",
1079 "renesas,rcar-gen2-vin";
1080 reg = <0 0xe6ef1000 0 0x1000>;
1081 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&cpg CPG_MOD 810>;
1083 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1084 resets = <&cpg 810>;
1085 status = "disabled";
1086 };
1087
1088 vin2: video@e6ef2000 {
1089 compatible = "renesas,vin-r8a7790",
1090 "renesas,rcar-gen2-vin";
1091 reg = <0 0xe6ef2000 0 0x1000>;
1092 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cpg CPG_MOD 809>;
1094 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1095 resets = <&cpg 809>;
1096 status = "disabled";
1097 };
1098
1099 vin3: video@e6ef3000 {
1100 compatible = "renesas,vin-r8a7790",
1101 "renesas,rcar-gen2-vin";
1102 reg = <0 0xe6ef3000 0 0x1000>;
1103 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&cpg CPG_MOD 808>;
1105 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1106 resets = <&cpg 808>;
1107 status = "disabled";
1108 };
1109
1110 rcar_sound: sound@ec500000 {
1111 /*
1112 * #sound-dai-cells is required
1113 *
1114 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1115 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1116 */
1117 compatible = "renesas,rcar_sound-r8a7790",
1118 "renesas,rcar_sound-gen2";
1119 reg = <0 0xec500000 0 0x1000>, /* SCU */
1120 <0 0xec5a0000 0 0x100>, /* ADG */
1121 <0 0xec540000 0 0x1000>, /* SSIU */
1122 <0 0xec541000 0 0x280>, /* SSI */
1123 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1124 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1125
1126 clocks = <&cpg CPG_MOD 1005>,
1127 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1128 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1129 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1130 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1131 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1132 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1133 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1134 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1135 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1136 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1137 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1138 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1139 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1140 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1141 <&cpg CPG_CORE R8A7790_CLK_M2>;
1142 clock-names = "ssi-all",
1143 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1144 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1145 "ssi.1", "ssi.0",
1146 "src.9", "src.8", "src.7", "src.6",
1147 "src.5", "src.4", "src.3", "src.2",
1148 "src.1", "src.0",
1149 "ctu.0", "ctu.1",
1150 "mix.0", "mix.1",
1151 "dvc.0", "dvc.1",
1152 "clk_a", "clk_b", "clk_c", "clk_i";
1153 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1154 resets = <&cpg 1005>,
1155 <&cpg 1006>, <&cpg 1007>,
1156 <&cpg 1008>, <&cpg 1009>,
1157 <&cpg 1010>, <&cpg 1011>,
1158 <&cpg 1012>, <&cpg 1013>,
1159 <&cpg 1014>, <&cpg 1015>;
1160 reset-names = "ssi-all",
1161 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1162 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1163 "ssi.1", "ssi.0";
1164
1165 status = "disabled";
1166
1167 rcar_sound,dvc {
1168 dvc0: dvc-0 {
1169 dmas = <&audma1 0xbc>;
1170 dma-names = "tx";
1171 };
1172 dvc1: dvc-1 {
1173 dmas = <&audma1 0xbe>;
1174 dma-names = "tx";
1175 };
1176 };
1177
1178 rcar_sound,mix {
1179 mix0: mix-0 { };
1180 mix1: mix-1 { };
1181 };
1182
1183 rcar_sound,ctu {
1184 ctu00: ctu-0 { };
1185 ctu01: ctu-1 { };
1186 ctu02: ctu-2 { };
1187 ctu03: ctu-3 { };
1188 ctu10: ctu-4 { };
1189 ctu11: ctu-5 { };
1190 ctu12: ctu-6 { };
1191 ctu13: ctu-7 { };
1192 };
1193
1194 rcar_sound,src {
1195 src0: src-0 {
1196 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1197 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1198 dma-names = "rx", "tx";
1199 };
1200 src1: src-1 {
1201 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1202 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1203 dma-names = "rx", "tx";
1204 };
1205 src2: src-2 {
1206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1207 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1208 dma-names = "rx", "tx";
1209 };
1210 src3: src-3 {
1211 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1212 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1213 dma-names = "rx", "tx";
1214 };
1215 src4: src-4 {
1216 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1217 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1218 dma-names = "rx", "tx";
1219 };
1220 src5: src-5 {
1221 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1222 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1223 dma-names = "rx", "tx";
1224 };
1225 src6: src-6 {
1226 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1227 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1228 dma-names = "rx", "tx";
1229 };
1230 src7: src-7 {
1231 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1232 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1233 dma-names = "rx", "tx";
1234 };
1235 src8: src-8 {
1236 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1237 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1238 dma-names = "rx", "tx";
1239 };
1240 src9: src-9 {
1241 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1242 dmas = <&audma0 0x97>, <&audma1 0xba>;
1243 dma-names = "rx", "tx";
1244 };
1245 };
1246
1247 rcar_sound,ssi {
1248 ssi0: ssi-0 {
1249 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1250 dmas = <&audma0 0x01>, <&audma1 0x02>,
1251 <&audma0 0x15>, <&audma1 0x16>;
1252 dma-names = "rx", "tx", "rxu", "txu";
1253 };
1254 ssi1: ssi-1 {
1255 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1256 dmas = <&audma0 0x03>, <&audma1 0x04>,
1257 <&audma0 0x49>, <&audma1 0x4a>;
1258 dma-names = "rx", "tx", "rxu", "txu";
1259 };
1260 ssi2: ssi-2 {
1261 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1262 dmas = <&audma0 0x05>, <&audma1 0x06>,
1263 <&audma0 0x63>, <&audma1 0x64>;
1264 dma-names = "rx", "tx", "rxu", "txu";
1265 };
1266 ssi3: ssi-3 {
1267 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1268 dmas = <&audma0 0x07>, <&audma1 0x08>,
1269 <&audma0 0x6f>, <&audma1 0x70>;
1270 dma-names = "rx", "tx", "rxu", "txu";
1271 };
1272 ssi4: ssi-4 {
1273 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1274 dmas = <&audma0 0x09>, <&audma1 0x0a>,
1275 <&audma0 0x71>, <&audma1 0x72>;
1276 dma-names = "rx", "tx", "rxu", "txu";
1277 };
1278 ssi5: ssi-5 {
1279 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1280 dmas = <&audma0 0x0b>, <&audma1 0x0c>,
1281 <&audma0 0x73>, <&audma1 0x74>;
1282 dma-names = "rx", "tx", "rxu", "txu";
1283 };
1284 ssi6: ssi-6 {
1285 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1286 dmas = <&audma0 0x0d>, <&audma1 0x0e>,
1287 <&audma0 0x75>, <&audma1 0x76>;
1288 dma-names = "rx", "tx", "rxu", "txu";
1289 };
1290 ssi7: ssi-7 {
1291 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1292 dmas = <&audma0 0x0f>, <&audma1 0x10>,
1293 <&audma0 0x79>, <&audma1 0x7a>;
1294 dma-names = "rx", "tx", "rxu", "txu";
1295 };
1296 ssi8: ssi-8 {
1297 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1298 dmas = <&audma0 0x11>, <&audma1 0x12>,
1299 <&audma0 0x7b>, <&audma1 0x7c>;
1300 dma-names = "rx", "tx", "rxu", "txu";
1301 };
1302 ssi9: ssi-9 {
1303 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1304 dmas = <&audma0 0x13>, <&audma1 0x14>,
1305 <&audma0 0x7d>, <&audma1 0x7e>;
1306 dma-names = "rx", "tx", "rxu", "txu";
1307 };
1308 };
1309 };
1310
1311 audma0: dma-controller@ec700000 {
1312 compatible = "renesas,dmac-r8a7790",
1313 "renesas,rcar-dmac";
1314 reg = <0 0xec700000 0 0x10000>;
1315 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1329 interrupt-names = "error",
1330 "ch0", "ch1", "ch2", "ch3",
1331 "ch4", "ch5", "ch6", "ch7",
1332 "ch8", "ch9", "ch10", "ch11",
1333 "ch12";
1334 clocks = <&cpg CPG_MOD 502>;
1335 clock-names = "fck";
1336 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1337 resets = <&cpg 502>;
1338 #dma-cells = <1>;
1339 dma-channels = <13>;
1340 };
1341
1342 audma1: dma-controller@ec720000 {
1343 compatible = "renesas,dmac-r8a7790",
1344 "renesas,rcar-dmac";
1345 reg = <0 0xec720000 0 0x10000>;
1346 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1360 interrupt-names = "error",
1361 "ch0", "ch1", "ch2", "ch3",
1362 "ch4", "ch5", "ch6", "ch7",
1363 "ch8", "ch9", "ch10", "ch11",
1364 "ch12";
1365 clocks = <&cpg CPG_MOD 501>;
1366 clock-names = "fck";
1367 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1368 resets = <&cpg 501>;
1369 #dma-cells = <1>;
1370 dma-channels = <13>;
1371 };
1372
1373 xhci: usb@ee000000 {
1374 compatible = "renesas,xhci-r8a7790",
1375 "renesas,rcar-gen2-xhci";
1376 reg = <0 0xee000000 0 0xc00>;
1377 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1378 clocks = <&cpg CPG_MOD 328>;
1379 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1380 resets = <&cpg 328>;
1381 phys = <&usb2 1>;
1382 phy-names = "usb";
1383 status = "disabled";
1384 };
1385
1386 pci0: pci@ee090000 {
1387 compatible = "renesas,pci-r8a7790",
1388 "renesas,pci-rcar-gen2";
1389 device_type = "pci";
1390 reg = <0 0xee090000 0 0xc00>,
1391 <0 0xee080000 0 0x1100>;
1392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&cpg CPG_MOD 703>;
1394 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1395 resets = <&cpg 703>;
1396 status = "disabled";
1397
1398 bus-range = <0 0>;
1399 #address-cells = <3>;
1400 #size-cells = <2>;
1401 #interrupt-cells = <1>;
1402 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1403 interrupt-map-mask = <0xf800 0 0 0x7>;
1404 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1405 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1406 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1407
1408 usb@1,0 {
1409 reg = <0x800 0 0 0 0>;
1410 phys = <&usb0 0>;
1411 phy-names = "usb";
1412 };
1413
1414 usb@2,0 {
1415 reg = <0x1000 0 0 0 0>;
1416 phys = <&usb0 0>;
1417 phy-names = "usb";
1418 };
1419 };
1420
1421 pci1: pci@ee0b0000 {
1422 compatible = "renesas,pci-r8a7790",
1423 "renesas,pci-rcar-gen2";
1424 device_type = "pci";
1425 reg = <0 0xee0b0000 0 0xc00>,
1426 <0 0xee0a0000 0 0x1100>;
1427 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1428 clocks = <&cpg CPG_MOD 703>;
1429 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1430 resets = <&cpg 703>;
1431 status = "disabled";
1432
1433 bus-range = <1 1>;
1434 #address-cells = <3>;
1435 #size-cells = <2>;
1436 #interrupt-cells = <1>;
1437 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1438 interrupt-map-mask = <0xf800 0 0 0x7>;
1439 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1440 <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1441 <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1442 };
1443
1444 pci2: pci@ee0d0000 {
1445 compatible = "renesas,pci-r8a7790",
1446 "renesas,pci-rcar-gen2";
1447 device_type = "pci";
1448 clocks = <&cpg CPG_MOD 703>;
1449 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1450 resets = <&cpg 703>;
1451 reg = <0 0xee0d0000 0 0xc00>,
1452 <0 0xee0c0000 0 0x1100>;
1453 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1454 status = "disabled";
1455
1456 bus-range = <2 2>;
1457 #address-cells = <3>;
1458 #size-cells = <2>;
1459 #interrupt-cells = <1>;
1460 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1461 interrupt-map-mask = <0xf800 0 0 0x7>;
1462 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1463 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1464 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1465
1466 usb@1,0 {
1467 reg = <0x20800 0 0 0 0>;
1468 phys = <&usb2 0>;
1469 phy-names = "usb";
1470 };
1471
1472 usb@2,0 {
1473 reg = <0x21000 0 0 0 0>;
1474 phys = <&usb2 0>;
1475 phy-names = "usb";
1476 };
1477 };
1478
1479 sdhi0: mmc@ee100000 {
1480 compatible = "renesas,sdhi-r8a7790",
1481 "renesas,rcar-gen2-sdhi";
1482 reg = <0 0xee100000 0 0x328>;
1483 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&cpg CPG_MOD 314>;
1485 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1486 <&dmac1 0xcd>, <&dmac1 0xce>;
1487 dma-names = "tx", "rx", "tx", "rx";
1488 max-frequency = <195000000>;
1489 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1490 resets = <&cpg 314>;
1491 status = "disabled";
1492 };
1493
1494 sdhi1: mmc@ee120000 {
1495 compatible = "renesas,sdhi-r8a7790",
1496 "renesas,rcar-gen2-sdhi";
1497 reg = <0 0xee120000 0 0x328>;
1498 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&cpg CPG_MOD 313>;
1500 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
1501 <&dmac1 0xc9>, <&dmac1 0xca>;
1502 dma-names = "tx", "rx", "tx", "rx";
1503 max-frequency = <195000000>;
1504 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1505 resets = <&cpg 313>;
1506 status = "disabled";
1507 };
1508
1509 sdhi2: mmc@ee140000 {
1510 compatible = "renesas,sdhi-r8a7790",
1511 "renesas,rcar-gen2-sdhi";
1512 reg = <0 0xee140000 0 0x100>;
1513 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1514 clocks = <&cpg CPG_MOD 312>;
1515 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1516 <&dmac1 0xc1>, <&dmac1 0xc2>;
1517 dma-names = "tx", "rx", "tx", "rx";
1518 max-frequency = <97500000>;
1519 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1520 resets = <&cpg 312>;
1521 status = "disabled";
1522 };
1523
1524 sdhi3: mmc@ee160000 {
1525 compatible = "renesas,sdhi-r8a7790",
1526 "renesas,rcar-gen2-sdhi";
1527 reg = <0 0xee160000 0 0x100>;
1528 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1529 clocks = <&cpg CPG_MOD 311>;
1530 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1531 <&dmac1 0xd3>, <&dmac1 0xd4>;
1532 dma-names = "tx", "rx", "tx", "rx";
1533 max-frequency = <97500000>;
1534 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1535 resets = <&cpg 311>;
1536 status = "disabled";
1537 };
1538
1539 mmcif0: mmc@ee200000 {
1540 compatible = "renesas,mmcif-r8a7790",
1541 "renesas,sh-mmcif";
1542 reg = <0 0xee200000 0 0x80>;
1543 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1544 clocks = <&cpg CPG_MOD 315>;
1545 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1546 <&dmac1 0xd1>, <&dmac1 0xd2>;
1547 dma-names = "tx", "rx", "tx", "rx";
1548 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1549 resets = <&cpg 315>;
1550 reg-io-width = <4>;
1551 status = "disabled";
1552 max-frequency = <97500000>;
1553 };
1554
1555 mmcif1: mmc@ee220000 {
1556 compatible = "renesas,mmcif-r8a7790",
1557 "renesas,sh-mmcif";
1558 reg = <0 0xee220000 0 0x80>;
1559 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1560 clocks = <&cpg CPG_MOD 305>;
1561 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
1562 <&dmac1 0xe1>, <&dmac1 0xe2>;
1563 dma-names = "tx", "rx", "tx", "rx";
1564 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1565 resets = <&cpg 305>;
1566 reg-io-width = <4>;
1567 status = "disabled";
1568 max-frequency = <97500000>;
1569 };
1570
1571 sata0: sata@ee300000 {
1572 compatible = "renesas,sata-r8a7790",
1573 "renesas,rcar-gen2-sata";
1574 reg = <0 0xee300000 0 0x200000>;
1575 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MOD 815>;
1577 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1578 resets = <&cpg 815>;
1579 status = "disabled";
1580 };
1581
1582 sata1: sata@ee500000 {
1583 compatible = "renesas,sata-r8a7790",
1584 "renesas,rcar-gen2-sata";
1585 reg = <0 0xee500000 0 0x200000>;
1586 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MOD 814>;
1588 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1589 resets = <&cpg 814>;
1590 status = "disabled";
1591 };
1592
1593 ether: ethernet@ee700000 {
1594 compatible = "renesas,ether-r8a7790",
1595 "renesas,rcar-gen2-ether";
1596 reg = <0 0xee700000 0 0x400>;
1597 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MOD 813>;
1599 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1600 resets = <&cpg 813>;
1601 phy-mode = "rmii";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 status = "disabled";
1605 };
1606
1607 gic: interrupt-controller@f1001000 {
1608 compatible = "arm,gic-400";
1609 #interrupt-cells = <3>;
1610 #address-cells = <0>;
1611 interrupt-controller;
1612 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1613 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1614 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1615 clocks = <&cpg CPG_MOD 408>;
1616 clock-names = "clk";
1617 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1618 resets = <&cpg 408>;
1619 };
1620
1621 pciec: pcie@fe000000 {
1622 compatible = "renesas,pcie-r8a7790",
1623 "renesas,pcie-rcar-gen2";
1624 reg = <0 0xfe000000 0 0x80000>;
1625 #address-cells = <3>;
1626 #size-cells = <2>;
1627 bus-range = <0x00 0xff>;
1628 device_type = "pci";
1629 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1630 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1631 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1632 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1633 /* Map all possible DDR as inbound ranges */
1634 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
1635 <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1636 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1639 #interrupt-cells = <1>;
1640 interrupt-map-mask = <0 0 0 0>;
1641 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1643 clock-names = "pcie", "pcie_bus";
1644 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1645 resets = <&cpg 319>;
1646 status = "disabled";
1647 };
1648
1649 vsp@fe920000 {
1650 compatible = "renesas,vsp1";
1651 reg = <0 0xfe920000 0 0x8000>;
1652 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1653 clocks = <&cpg CPG_MOD 130>;
1654 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1655 resets = <&cpg 130>;
1656 };
1657
1658 vsp@fe928000 {
1659 compatible = "renesas,vsp1";
1660 reg = <0 0xfe928000 0 0x8000>;
1661 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MOD 131>;
1663 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1664 resets = <&cpg 131>;
1665 };
1666
1667 vsp@fe930000 {
1668 compatible = "renesas,vsp1";
1669 reg = <0 0xfe930000 0 0x8000>;
1670 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1671 clocks = <&cpg CPG_MOD 128>;
1672 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1673 resets = <&cpg 128>;
1674 };
1675
1676 vsp@fe938000 {
1677 compatible = "renesas,vsp1";
1678 reg = <0 0xfe938000 0 0x8000>;
1679 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MOD 127>;
1681 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1682 resets = <&cpg 127>;
1683 };
1684
1685 fdp1@fe940000 {
1686 compatible = "renesas,fdp1";
1687 reg = <0 0xfe940000 0 0x2400>;
1688 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1689 clocks = <&cpg CPG_MOD 119>;
1690 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1691 resets = <&cpg 119>;
1692 };
1693
1694 fdp1@fe944000 {
1695 compatible = "renesas,fdp1";
1696 reg = <0 0xfe944000 0 0x2400>;
1697 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1698 clocks = <&cpg CPG_MOD 118>;
1699 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1700 resets = <&cpg 118>;
1701 };
1702
1703 fdp1@fe948000 {
1704 compatible = "renesas,fdp1";
1705 reg = <0 0xfe948000 0 0x2400>;
1706 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
1707 clocks = <&cpg CPG_MOD 117>;
1708 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1709 resets = <&cpg 117>;
1710 };
1711
1712 jpu: jpeg-codec@fe980000 {
1713 compatible = "renesas,jpu-r8a7790",
1714 "renesas,rcar-gen2-jpu";
1715 reg = <0 0xfe980000 0 0x10300>;
1716 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1717 clocks = <&cpg CPG_MOD 106>;
1718 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1719 resets = <&cpg 106>;
1720 };
1721
1722 du: display@feb00000 {
1723 compatible = "renesas,du-r8a7790";
1724 reg = <0 0xfeb00000 0 0x70000>;
1725 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1728 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
1729 <&cpg CPG_MOD 722>;
1730 clock-names = "du.0", "du.1", "du.2";
1731 resets = <&cpg 724>;
1732 reset-names = "du.0";
1733 status = "disabled";
1734
1735 ports {
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738
1739 port@0 {
1740 reg = <0>;
1741 du_out_rgb: endpoint {
1742 };
1743 };
1744 port@1 {
1745 reg = <1>;
1746 du_out_lvds0: endpoint {
1747 remote-endpoint = <&lvds0_in>;
1748 };
1749 };
1750 port@2 {
1751 reg = <2>;
1752 du_out_lvds1: endpoint {
1753 remote-endpoint = <&lvds1_in>;
1754 };
1755 };
1756 };
1757 };
1758
1759 lvds0: lvds@feb90000 {
1760 compatible = "renesas,r8a7790-lvds";
1761 reg = <0 0xfeb90000 0 0x1c>;
1762 clocks = <&cpg CPG_MOD 726>;
1763 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1764 resets = <&cpg 726>;
1765 status = "disabled";
1766
1767 ports {
1768 #address-cells = <1>;
1769 #size-cells = <0>;
1770
1771 port@0 {
1772 reg = <0>;
1773 lvds0_in: endpoint {
1774 remote-endpoint = <&du_out_lvds0>;
1775 };
1776 };
1777 port@1 {
1778 reg = <1>;
1779 lvds0_out: endpoint {
1780 };
1781 };
1782 };
1783 };
1784
1785 lvds1: lvds@feb94000 {
1786 compatible = "renesas,r8a7790-lvds";
1787 reg = <0 0xfeb94000 0 0x1c>;
1788 clocks = <&cpg CPG_MOD 725>;
1789 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1790 resets = <&cpg 725>;
1791 status = "disabled";
1792
1793 ports {
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796
1797 port@0 {
1798 reg = <0>;
1799 lvds1_in: endpoint {
1800 remote-endpoint = <&du_out_lvds1>;
1801 };
1802 };
1803 port@1 {
1804 reg = <1>;
1805 lvds1_out: endpoint {
1806 };
1807 };
1808 };
1809 };
1810
1811 prr: chipid@ff000044 {
1812 compatible = "renesas,prr";
1813 reg = <0 0xff000044 0 4>;
1814 };
1815
1816 cmt0: timer@ffca0000 {
1817 compatible = "renesas,r8a7790-cmt0",
1818 "renesas,rcar-gen2-cmt0";
1819 reg = <0 0xffca0000 0 0x1004>;
1820 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&cpg CPG_MOD 124>;
1823 clock-names = "fck";
1824 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1825 resets = <&cpg 124>;
1826
1827 status = "disabled";
1828 };
1829
1830 cmt1: timer@e6130000 {
1831 compatible = "renesas,r8a7790-cmt1",
1832 "renesas,rcar-gen2-cmt1";
1833 reg = <0 0xe6130000 0 0x1004>;
1834 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1842 clocks = <&cpg CPG_MOD 329>;
1843 clock-names = "fck";
1844 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1845 resets = <&cpg 329>;
1846
1847 status = "disabled";
1848 };
1849 };
1850
1851 thermal-zones {
1852 cpu_thermal: cpu-thermal {
1853 polling-delay-passive = <0>;
1854 polling-delay = <0>;
1855
1856 thermal-sensors = <&thermal>;
1857
1858 trips {
1859 cpu-crit {
1860 temperature = <95000>;
1861 hysteresis = <0>;
1862 type = "critical";
1863 };
1864 };
1865 cooling-maps {
1866 };
1867 };
1868 };
1869
1870 timer {
1871 compatible = "arm,armv7-timer";
1872 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1873 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1874 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1875 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1876 };
1877
1878 /* External USB clock - can be overridden by the board */
1879 usb_extal_clk: usb_extal {
1880 compatible = "fixed-clock";
1881 #clock-cells = <0>;
1882 clock-frequency = <48000000>;
1883 };
1884};
1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <dt-bindings/clock/r8a7790-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
32 spi0 = &qspi;
33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55 next-level-cache = <&L2_CA15>;
56
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
59 <1225000 1000000>,
60 <1050000 1000000>,
61 < 875000 1000000>,
62 < 700000 1000000>,
63 < 350000 1000000>;
64 };
65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <1>;
70 clock-frequency = <1300000000>;
71 next-level-cache = <&L2_CA15>;
72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <2>;
78 clock-frequency = <1300000000>;
79 next-level-cache = <&L2_CA15>;
80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <3>;
86 clock-frequency = <1300000000>;
87 next-level-cache = <&L2_CA15>;
88 };
89
90 cpu4: cpu@4 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <780000000>;
95 next-level-cache = <&L2_CA7>;
96 };
97
98 cpu5: cpu@5 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <780000000>;
103 next-level-cache = <&L2_CA7>;
104 };
105
106 cpu6: cpu@6 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <780000000>;
111 next-level-cache = <&L2_CA7>;
112 };
113
114 cpu7: cpu@7 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <780000000>;
119 next-level-cache = <&L2_CA7>;
120 };
121 };
122
123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
126 polling-delay = <0>;
127
128 thermal-sensors = <&thermal>;
129
130 trips {
131 cpu-crit {
132 temperature = <115000>;
133 hysteresis = <0>;
134 type = "critical";
135 };
136 };
137 cooling-maps {
138 };
139 };
140 };
141
142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
150 cache-unified;
151 cache-level = <2>;
152 };
153
154 gic: interrupt-controller@f1001000 {
155 compatible = "arm,gic-400";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
164 };
165
166 gpio0: gpio@e6050000 {
167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
168 reg = <0 0xe6050000 0 0x50>;
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
176 power-domains = <&cpg_clocks>;
177 };
178
179 gpio1: gpio@e6051000 {
180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
181 reg = <0 0xe6051000 0 0x50>;
182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 32 30>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
189 power-domains = <&cpg_clocks>;
190 };
191
192 gpio2: gpio@e6052000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6052000 0 0x50>;
195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 64 30>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
202 power-domains = <&cpg_clocks>;
203 };
204
205 gpio3: gpio@e6053000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6053000 0 0x50>;
208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
215 power-domains = <&cpg_clocks>;
216 };
217
218 gpio4: gpio@e6054000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6054000 0 0x50>;
221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
228 power-domains = <&cpg_clocks>;
229 };
230
231 gpio5: gpio@e6055000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6055000 0 0x50>;
234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
241 power-domains = <&cpg_clocks>;
242 };
243
244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
251 power-domains = <&cpg_clocks>;
252 #thermal-sensor-cells = <0>;
253 };
254
255 timer {
256 compatible = "arm,armv7-timer";
257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
261 };
262
263 cmt0: timer@ffca0000 {
264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
265 reg = <0 0xffca0000 0 0x1004>;
266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck";
270 power-domains = <&cpg_clocks>;
271
272 renesas,channels-mask = <0x60>;
273
274 status = "disabled";
275 };
276
277 cmt1: timer@e6130000 {
278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
279 reg = <0 0xe6130000 0 0x1004>;
280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck";
290 power-domains = <&cpg_clocks>;
291
292 renesas,channels-mask = <0xff>;
293
294 status = "disabled";
295 };
296
297 irqc0: interrupt-controller@e61c0000 {
298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 reg = <0 0xe61c0000 0 0x200>;
302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
307 power-domains = <&cpg_clocks>;
308 };
309
310 dmac0: dma-controller@e6700000 {
311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
312 reg = <0 0xe6700000 0 0x20000>;
313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck";
336 power-domains = <&cpg_clocks>;
337 #dma-cells = <1>;
338 dma-channels = <15>;
339 };
340
341 dmac1: dma-controller@e6720000 {
342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
343 reg = <0 0xe6720000 0 0x20000>;
344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck";
367 power-domains = <&cpg_clocks>;
368 #dma-cells = <1>;
369 dma-channels = <15>;
370 };
371
372 audma0: dma-controller@ec700000 {
373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
374 reg = <0 0xec700000 0 0x10000>;
375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
393 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck";
396 power-domains = <&cpg_clocks>;
397 #dma-cells = <1>;
398 dma-channels = <13>;
399 };
400
401 audma1: dma-controller@ec720000 {
402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
403 reg = <0 0xec720000 0 0x10000>;
404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
422 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck";
425 power-domains = <&cpg_clocks>;
426 #dma-cells = <1>;
427 dma-channels = <13>;
428 };
429
430 usb_dmac0: dma-controller@e65a0000 {
431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
432 reg = <0 0xe65a0000 0 0x100>;
433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
437 power-domains = <&cpg_clocks>;
438 #dma-cells = <1>;
439 dma-channels = <2>;
440 };
441
442 usb_dmac1: dma-controller@e65b0000 {
443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
444 reg = <0 0xe65b0000 0 0x100>;
445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
449 power-domains = <&cpg_clocks>;
450 #dma-cells = <1>;
451 dma-channels = <2>;
452 };
453
454 i2c0: i2c@e6508000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
461 power-domains = <&cpg_clocks>;
462 i2c-scl-internal-delay-ns = <110>;
463 status = "disabled";
464 };
465
466 i2c1: i2c@e6518000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
473 power-domains = <&cpg_clocks>;
474 i2c-scl-internal-delay-ns = <6>;
475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
485 power-domains = <&cpg_clocks>;
486 i2c-scl-internal-delay-ns = <6>;
487 status = "disabled";
488 };
489
490 i2c3: i2c@e6540000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
497 power-domains = <&cpg_clocks>;
498 i2c-scl-internal-delay-ns = <110>;
499 status = "disabled";
500 };
501
502 iic0: i2c@e6500000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>;
512 status = "disabled";
513 };
514
515 iic1: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
524 power-domains = <&cpg_clocks>;
525 status = "disabled";
526 };
527
528 iic2: i2c@e6520000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
537 power-domains = <&cpg_clocks>;
538 status = "disabled";
539 };
540
541 iic3: i2c@e60b0000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
550 power-domains = <&cpg_clocks>;
551 status = "disabled";
552 };
553
554 mmcif0: mmc@ee200000 {
555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
556 reg = <0 0xee200000 0 0x80>;
557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
561 power-domains = <&cpg_clocks>;
562 reg-io-width = <4>;
563 status = "disabled";
564 max-frequency = <97500000>;
565 };
566
567 mmcif1: mmc@ee220000 {
568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
569 reg = <0 0xee220000 0 0x80>;
570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>;
575 reg-io-width = <4>;
576 status = "disabled";
577 max-frequency = <97500000>;
578 };
579
580 pfc: pfc@e6060000 {
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
583 };
584
585 sdhi0: sd@ee100000 {
586 compatible = "renesas,sdhi-r8a7790";
587 reg = <0 0xee100000 0 0x328>;
588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>;
593 status = "disabled";
594 };
595
596 sdhi1: sd@ee120000 {
597 compatible = "renesas,sdhi-r8a7790";
598 reg = <0 0xee120000 0 0x328>;
599 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx";
603 power-domains = <&cpg_clocks>;
604 status = "disabled";
605 };
606
607 sdhi2: sd@ee140000 {
608 compatible = "renesas,sdhi-r8a7790";
609 reg = <0 0xee140000 0 0x100>;
610 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx";
614 power-domains = <&cpg_clocks>;
615 status = "disabled";
616 };
617
618 sdhi3: sd@ee160000 {
619 compatible = "renesas,sdhi-r8a7790";
620 reg = <0 0xee160000 0 0x100>;
621 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx";
625 power-domains = <&cpg_clocks>;
626 status = "disabled";
627 };
628
629 scifa0: serial@e6c40000 {
630 compatible = "renesas,scifa-r8a7790",
631 "renesas,rcar-gen2-scifa", "renesas,scifa";
632 reg = <0 0xe6c40000 0 64>;
633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
635 clock-names = "fck";
636 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
637 dma-names = "tx", "rx";
638 power-domains = <&cpg_clocks>;
639 status = "disabled";
640 };
641
642 scifa1: serial@e6c50000 {
643 compatible = "renesas,scifa-r8a7790",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
645 reg = <0 0xe6c50000 0 64>;
646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
648 clock-names = "fck";
649 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
652 status = "disabled";
653 };
654
655 scifa2: serial@e6c60000 {
656 compatible = "renesas,scifa-r8a7790",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
658 reg = <0 0xe6c60000 0 64>;
659 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
661 clock-names = "fck";
662 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
663 dma-names = "tx", "rx";
664 power-domains = <&cpg_clocks>;
665 status = "disabled";
666 };
667
668 scifb0: serial@e6c20000 {
669 compatible = "renesas,scifb-r8a7790",
670 "renesas,rcar-gen2-scifb", "renesas,scifb";
671 reg = <0 0xe6c20000 0 64>;
672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
674 clock-names = "fck";
675 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
676 dma-names = "tx", "rx";
677 power-domains = <&cpg_clocks>;
678 status = "disabled";
679 };
680
681 scifb1: serial@e6c30000 {
682 compatible = "renesas,scifb-r8a7790",
683 "renesas,rcar-gen2-scifb", "renesas,scifb";
684 reg = <0 0xe6c30000 0 64>;
685 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
687 clock-names = "fck";
688 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
689 dma-names = "tx", "rx";
690 power-domains = <&cpg_clocks>;
691 status = "disabled";
692 };
693
694 scifb2: serial@e6ce0000 {
695 compatible = "renesas,scifb-r8a7790",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
697 reg = <0 0xe6ce0000 0 64>;
698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
700 clock-names = "fck";
701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
702 dma-names = "tx", "rx";
703 power-domains = <&cpg_clocks>;
704 status = "disabled";
705 };
706
707 scif0: serial@e6e60000 {
708 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
709 "renesas,scif";
710 reg = <0 0xe6e60000 0 64>;
711 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
713 <&scif_clk>;
714 clock-names = "fck", "brg_int", "scif_clk";
715 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
716 dma-names = "tx", "rx";
717 power-domains = <&cpg_clocks>;
718 status = "disabled";
719 };
720
721 scif1: serial@e6e68000 {
722 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
723 "renesas,scif";
724 reg = <0 0xe6e68000 0 64>;
725 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
727 <&scif_clk>;
728 clock-names = "fck", "brg_int", "scif_clk";
729 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
730 dma-names = "tx", "rx";
731 power-domains = <&cpg_clocks>;
732 status = "disabled";
733 };
734
735 hscif0: serial@e62c0000 {
736 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif";
738 reg = <0 0xe62c0000 0 96>;
739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
744 dma-names = "tx", "rx";
745 power-domains = <&cpg_clocks>;
746 status = "disabled";
747 };
748
749 hscif1: serial@e62c8000 {
750 compatible = "renesas,hscif-r8a7790",
751 "renesas,rcar-gen2-hscif", "renesas,hscif";
752 reg = <0 0xe62c8000 0 96>;
753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
755 <&scif_clk>;
756 clock-names = "fck", "brg_int", "scif_clk";
757 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
758 dma-names = "tx", "rx";
759 power-domains = <&cpg_clocks>;
760 status = "disabled";
761 };
762
763 ether: ethernet@ee700000 {
764 compatible = "renesas,ether-r8a7790";
765 reg = <0 0xee700000 0 0x400>;
766 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
768 power-domains = <&cpg_clocks>;
769 phy-mode = "rmii";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 status = "disabled";
773 };
774
775 avb: ethernet@e6800000 {
776 compatible = "renesas,etheravb-r8a7790",
777 "renesas,etheravb-rcar-gen2";
778 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
779 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
781 power-domains = <&cpg_clocks>;
782 #address-cells = <1>;
783 #size-cells = <0>;
784 status = "disabled";
785 };
786
787 sata0: sata@ee300000 {
788 compatible = "renesas,sata-r8a7790";
789 reg = <0 0xee300000 0 0x2000>;
790 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
792 power-domains = <&cpg_clocks>;
793 status = "disabled";
794 };
795
796 sata1: sata@ee500000 {
797 compatible = "renesas,sata-r8a7790";
798 reg = <0 0xee500000 0 0x2000>;
799 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
801 power-domains = <&cpg_clocks>;
802 status = "disabled";
803 };
804
805 hsusb: usb@e6590000 {
806 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
807 reg = <0 0xe6590000 0 0x100>;
808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
810 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
811 <&usb_dmac1 0>, <&usb_dmac1 1>;
812 dma-names = "ch0", "ch1", "ch2", "ch3";
813 power-domains = <&cpg_clocks>;
814 renesas,buswait = <4>;
815 phys = <&usb0 1>;
816 phy-names = "usb";
817 status = "disabled";
818 };
819
820 usbphy: usb-phy@e6590100 {
821 compatible = "renesas,usb-phy-r8a7790";
822 reg = <0 0xe6590100 0 0x100>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
826 clock-names = "usbhs";
827 power-domains = <&cpg_clocks>;
828 status = "disabled";
829
830 usb0: usb-channel@0 {
831 reg = <0>;
832 #phy-cells = <1>;
833 };
834 usb2: usb-channel@2 {
835 reg = <2>;
836 #phy-cells = <1>;
837 };
838 };
839
840 vin0: video@e6ef0000 {
841 compatible = "renesas,vin-r8a7790";
842 reg = <0 0xe6ef0000 0 0x1000>;
843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
845 power-domains = <&cpg_clocks>;
846 status = "disabled";
847 };
848
849 vin1: video@e6ef1000 {
850 compatible = "renesas,vin-r8a7790";
851 reg = <0 0xe6ef1000 0 0x1000>;
852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
854 power-domains = <&cpg_clocks>;
855 status = "disabled";
856 };
857
858 vin2: video@e6ef2000 {
859 compatible = "renesas,vin-r8a7790";
860 reg = <0 0xe6ef2000 0 0x1000>;
861 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
863 power-domains = <&cpg_clocks>;
864 status = "disabled";
865 };
866
867 vin3: video@e6ef3000 {
868 compatible = "renesas,vin-r8a7790";
869 reg = <0 0xe6ef3000 0 0x1000>;
870 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
872 power-domains = <&cpg_clocks>;
873 status = "disabled";
874 };
875
876 vsp1@fe920000 {
877 compatible = "renesas,vsp1";
878 reg = <0 0xfe920000 0 0x8000>;
879 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
881 power-domains = <&cpg_clocks>;
882
883 renesas,has-sru;
884 renesas,#rpf = <5>;
885 renesas,#uds = <1>;
886 renesas,#wpf = <4>;
887 };
888
889 vsp1@fe928000 {
890 compatible = "renesas,vsp1";
891 reg = <0 0xfe928000 0 0x8000>;
892 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
894 power-domains = <&cpg_clocks>;
895
896 renesas,has-lut;
897 renesas,has-sru;
898 renesas,#rpf = <5>;
899 renesas,#uds = <3>;
900 renesas,#wpf = <4>;
901 };
902
903 vsp1@fe930000 {
904 compatible = "renesas,vsp1";
905 reg = <0 0xfe930000 0 0x8000>;
906 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
908 power-domains = <&cpg_clocks>;
909
910 renesas,has-lif;
911 renesas,has-lut;
912 renesas,#rpf = <4>;
913 renesas,#uds = <1>;
914 renesas,#wpf = <4>;
915 };
916
917 vsp1@fe938000 {
918 compatible = "renesas,vsp1";
919 reg = <0 0xfe938000 0 0x8000>;
920 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
922 power-domains = <&cpg_clocks>;
923
924 renesas,has-lif;
925 renesas,has-lut;
926 renesas,#rpf = <4>;
927 renesas,#uds = <1>;
928 renesas,#wpf = <4>;
929 };
930
931 du: display@feb00000 {
932 compatible = "renesas,du-r8a7790";
933 reg = <0 0xfeb00000 0 0x70000>,
934 <0 0xfeb90000 0 0x1c>,
935 <0 0xfeb94000 0 0x1c>;
936 reg-names = "du", "lvds.0", "lvds.1";
937 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
941 <&mstp7_clks R8A7790_CLK_DU1>,
942 <&mstp7_clks R8A7790_CLK_DU2>,
943 <&mstp7_clks R8A7790_CLK_LVDS0>,
944 <&mstp7_clks R8A7790_CLK_LVDS1>;
945 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
946 status = "disabled";
947
948 ports {
949 #address-cells = <1>;
950 #size-cells = <0>;
951
952 port@0 {
953 reg = <0>;
954 du_out_rgb: endpoint {
955 };
956 };
957 port@1 {
958 reg = <1>;
959 du_out_lvds0: endpoint {
960 };
961 };
962 port@2 {
963 reg = <2>;
964 du_out_lvds1: endpoint {
965 };
966 };
967 };
968 };
969
970 can0: can@e6e80000 {
971 compatible = "renesas,can-r8a7790";
972 reg = <0 0xe6e80000 0 0x1000>;
973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
975 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
976 clock-names = "clkp1", "clkp2", "can_clk";
977 power-domains = <&cpg_clocks>;
978 status = "disabled";
979 };
980
981 can1: can@e6e88000 {
982 compatible = "renesas,can-r8a7790";
983 reg = <0 0xe6e88000 0 0x1000>;
984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
986 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
987 clock-names = "clkp1", "clkp2", "can_clk";
988 power-domains = <&cpg_clocks>;
989 status = "disabled";
990 };
991
992 jpu: jpeg-codec@fe980000 {
993 compatible = "renesas,jpu-r8a7790";
994 reg = <0 0xfe980000 0 0x10300>;
995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
997 power-domains = <&cpg_clocks>;
998 };
999
1000 clocks {
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 ranges;
1004
1005 /* External root clock */
1006 extal_clk: extal_clk {
1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 /* This value must be overriden by the board. */
1010 clock-frequency = <0>;
1011 clock-output-names = "extal";
1012 };
1013
1014 /* External PCIe clock - can be overridden by the board */
1015 pcie_bus_clk: pcie_bus_clk {
1016 compatible = "fixed-clock";
1017 #clock-cells = <0>;
1018 clock-frequency = <100000000>;
1019 clock-output-names = "pcie_bus";
1020 status = "disabled";
1021 };
1022
1023 /*
1024 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1025 * default. Boards that provide audio clocks should override them.
1026 */
1027 audio_clk_a: audio_clk_a {
1028 compatible = "fixed-clock";
1029 #clock-cells = <0>;
1030 clock-frequency = <0>;
1031 clock-output-names = "audio_clk_a";
1032 };
1033 audio_clk_b: audio_clk_b {
1034 compatible = "fixed-clock";
1035 #clock-cells = <0>;
1036 clock-frequency = <0>;
1037 clock-output-names = "audio_clk_b";
1038 };
1039 audio_clk_c: audio_clk_c {
1040 compatible = "fixed-clock";
1041 #clock-cells = <0>;
1042 clock-frequency = <0>;
1043 clock-output-names = "audio_clk_c";
1044 };
1045
1046 /* External SCIF clock */
1047 scif_clk: scif {
1048 compatible = "fixed-clock";
1049 #clock-cells = <0>;
1050 /* This value must be overridden by the board. */
1051 clock-frequency = <0>;
1052 status = "disabled";
1053 };
1054
1055 /* External USB clock - can be overridden by the board */
1056 usb_extal_clk: usb_extal_clk {
1057 compatible = "fixed-clock";
1058 #clock-cells = <0>;
1059 clock-frequency = <48000000>;
1060 clock-output-names = "usb_extal";
1061 };
1062
1063 /* External CAN clock */
1064 can_clk: can_clk {
1065 compatible = "fixed-clock";
1066 #clock-cells = <0>;
1067 /* This value must be overridden by the board. */
1068 clock-frequency = <0>;
1069 clock-output-names = "can_clk";
1070 status = "disabled";
1071 };
1072
1073 /* Special CPG clocks */
1074 cpg_clocks: cpg_clocks@e6150000 {
1075 compatible = "renesas,r8a7790-cpg-clocks",
1076 "renesas,rcar-gen2-cpg-clocks";
1077 reg = <0 0xe6150000 0 0x1000>;
1078 clocks = <&extal_clk &usb_extal_clk>;
1079 #clock-cells = <1>;
1080 clock-output-names = "main", "pll0", "pll1", "pll3",
1081 "lb", "qspi", "sdh", "sd0", "sd1",
1082 "z", "rcan", "adsp";
1083 #power-domain-cells = <0>;
1084 };
1085
1086 /* Variable factor clocks */
1087 sd2_clk: sd2_clk@e6150078 {
1088 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1089 reg = <0 0xe6150078 0 4>;
1090 clocks = <&pll1_div2_clk>;
1091 #clock-cells = <0>;
1092 clock-output-names = "sd2";
1093 };
1094 sd3_clk: sd3_clk@e615026c {
1095 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1096 reg = <0 0xe615026c 0 4>;
1097 clocks = <&pll1_div2_clk>;
1098 #clock-cells = <0>;
1099 clock-output-names = "sd3";
1100 };
1101 mmc0_clk: mmc0_clk@e6150240 {
1102 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1103 reg = <0 0xe6150240 0 4>;
1104 clocks = <&pll1_div2_clk>;
1105 #clock-cells = <0>;
1106 clock-output-names = "mmc0";
1107 };
1108 mmc1_clk: mmc1_clk@e6150244 {
1109 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1110 reg = <0 0xe6150244 0 4>;
1111 clocks = <&pll1_div2_clk>;
1112 #clock-cells = <0>;
1113 clock-output-names = "mmc1";
1114 };
1115 ssp_clk: ssp_clk@e6150248 {
1116 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1117 reg = <0 0xe6150248 0 4>;
1118 clocks = <&pll1_div2_clk>;
1119 #clock-cells = <0>;
1120 clock-output-names = "ssp";
1121 };
1122 ssprs_clk: ssprs_clk@e615024c {
1123 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1124 reg = <0 0xe615024c 0 4>;
1125 clocks = <&pll1_div2_clk>;
1126 #clock-cells = <0>;
1127 clock-output-names = "ssprs";
1128 };
1129
1130 /* Fixed factor clocks */
1131 pll1_div2_clk: pll1_div2_clk {
1132 compatible = "fixed-factor-clock";
1133 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1134 #clock-cells = <0>;
1135 clock-div = <2>;
1136 clock-mult = <1>;
1137 clock-output-names = "pll1_div2";
1138 };
1139 z2_clk: z2_clk {
1140 compatible = "fixed-factor-clock";
1141 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1142 #clock-cells = <0>;
1143 clock-div = <2>;
1144 clock-mult = <1>;
1145 clock-output-names = "z2";
1146 };
1147 zg_clk: zg_clk {
1148 compatible = "fixed-factor-clock";
1149 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1150 #clock-cells = <0>;
1151 clock-div = <3>;
1152 clock-mult = <1>;
1153 clock-output-names = "zg";
1154 };
1155 zx_clk: zx_clk {
1156 compatible = "fixed-factor-clock";
1157 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1158 #clock-cells = <0>;
1159 clock-div = <3>;
1160 clock-mult = <1>;
1161 clock-output-names = "zx";
1162 };
1163 zs_clk: zs_clk {
1164 compatible = "fixed-factor-clock";
1165 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1166 #clock-cells = <0>;
1167 clock-div = <6>;
1168 clock-mult = <1>;
1169 clock-output-names = "zs";
1170 };
1171 hp_clk: hp_clk {
1172 compatible = "fixed-factor-clock";
1173 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1174 #clock-cells = <0>;
1175 clock-div = <12>;
1176 clock-mult = <1>;
1177 clock-output-names = "hp";
1178 };
1179 i_clk: i_clk {
1180 compatible = "fixed-factor-clock";
1181 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182 #clock-cells = <0>;
1183 clock-div = <2>;
1184 clock-mult = <1>;
1185 clock-output-names = "i";
1186 };
1187 b_clk: b_clk {
1188 compatible = "fixed-factor-clock";
1189 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1190 #clock-cells = <0>;
1191 clock-div = <12>;
1192 clock-mult = <1>;
1193 clock-output-names = "b";
1194 };
1195 p_clk: p_clk {
1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198 #clock-cells = <0>;
1199 clock-div = <24>;
1200 clock-mult = <1>;
1201 clock-output-names = "p";
1202 };
1203 cl_clk: cl_clk {
1204 compatible = "fixed-factor-clock";
1205 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1206 #clock-cells = <0>;
1207 clock-div = <48>;
1208 clock-mult = <1>;
1209 clock-output-names = "cl";
1210 };
1211 m2_clk: m2_clk {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1214 #clock-cells = <0>;
1215 clock-div = <8>;
1216 clock-mult = <1>;
1217 clock-output-names = "m2";
1218 };
1219 imp_clk: imp_clk {
1220 compatible = "fixed-factor-clock";
1221 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1222 #clock-cells = <0>;
1223 clock-div = <4>;
1224 clock-mult = <1>;
1225 clock-output-names = "imp";
1226 };
1227 rclk_clk: rclk_clk {
1228 compatible = "fixed-factor-clock";
1229 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1230 #clock-cells = <0>;
1231 clock-div = <(48 * 1024)>;
1232 clock-mult = <1>;
1233 clock-output-names = "rclk";
1234 };
1235 oscclk_clk: oscclk_clk {
1236 compatible = "fixed-factor-clock";
1237 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1238 #clock-cells = <0>;
1239 clock-div = <(12 * 1024)>;
1240 clock-mult = <1>;
1241 clock-output-names = "oscclk";
1242 };
1243 zb3_clk: zb3_clk {
1244 compatible = "fixed-factor-clock";
1245 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1246 #clock-cells = <0>;
1247 clock-div = <4>;
1248 clock-mult = <1>;
1249 clock-output-names = "zb3";
1250 };
1251 zb3d2_clk: zb3d2_clk {
1252 compatible = "fixed-factor-clock";
1253 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1254 #clock-cells = <0>;
1255 clock-div = <8>;
1256 clock-mult = <1>;
1257 clock-output-names = "zb3d2";
1258 };
1259 ddr_clk: ddr_clk {
1260 compatible = "fixed-factor-clock";
1261 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1262 #clock-cells = <0>;
1263 clock-div = <8>;
1264 clock-mult = <1>;
1265 clock-output-names = "ddr";
1266 };
1267 mp_clk: mp_clk {
1268 compatible = "fixed-factor-clock";
1269 clocks = <&pll1_div2_clk>;
1270 #clock-cells = <0>;
1271 clock-div = <15>;
1272 clock-mult = <1>;
1273 clock-output-names = "mp";
1274 };
1275 cp_clk: cp_clk {
1276 compatible = "fixed-factor-clock";
1277 clocks = <&extal_clk>;
1278 #clock-cells = <0>;
1279 clock-div = <2>;
1280 clock-mult = <1>;
1281 clock-output-names = "cp";
1282 };
1283
1284 /* Gate clocks */
1285 mstp0_clks: mstp0_clks@e6150130 {
1286 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1287 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1288 clocks = <&mp_clk>;
1289 #clock-cells = <1>;
1290 clock-indices = <R8A7790_CLK_MSIOF0>;
1291 clock-output-names = "msiof0";
1292 };
1293 mstp1_clks: mstp1_clks@e6150134 {
1294 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1295 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1296 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1297 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1298 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1299 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1300 #clock-cells = <1>;
1301 clock-indices = <
1302 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1303 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1304 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1305 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1306 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1307 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1308 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1309 >;
1310 clock-output-names =
1311 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1312 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1313 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1314 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1315 };
1316 mstp2_clks: mstp2_clks@e6150138 {
1317 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1318 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1319 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1320 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1321 <&zs_clk>;
1322 #clock-cells = <1>;
1323 clock-indices = <
1324 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1325 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1326 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1327 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1328 >;
1329 clock-output-names =
1330 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1331 "scifb1", "msiof1", "msiof3", "scifb2",
1332 "sys-dmac1", "sys-dmac0";
1333 };
1334 mstp3_clks: mstp3_clks@e615013c {
1335 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1336 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1337 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1338 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1339 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1340 <&hp_clk>, <&hp_clk>;
1341 #clock-cells = <1>;
1342 clock-indices = <
1343 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1344 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1345 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1346 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1347 >;
1348 clock-output-names =
1349 "iic2", "tpu0", "mmcif1", "sdhi3",
1350 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1351 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1352 "usbdmac0", "usbdmac1";
1353 };
1354 mstp4_clks: mstp4_clks@e6150140 {
1355 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1356 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1357 clocks = <&cp_clk>;
1358 #clock-cells = <1>;
1359 clock-indices = <R8A7790_CLK_IRQC>;
1360 clock-output-names = "irqc";
1361 };
1362 mstp5_clks: mstp5_clks@e6150144 {
1363 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1364 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1365 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1366 <&extal_clk>, <&p_clk>;
1367 #clock-cells = <1>;
1368 clock-indices = <
1369 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1370 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1371 R8A7790_CLK_PWM
1372 >;
1373 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1374 "thermal", "pwm";
1375 };
1376 mstp7_clks: mstp7_clks@e615014c {
1377 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1378 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1379 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1380 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1381 <&zx_clk>;
1382 #clock-cells = <1>;
1383 clock-indices = <
1384 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1385 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1386 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1387 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1388 >;
1389 clock-output-names =
1390 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1391 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1392 };
1393 mstp8_clks: mstp8_clks@e6150990 {
1394 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1395 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1396 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1397 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1398 <&zs_clk>;
1399 #clock-cells = <1>;
1400 clock-indices = <
1401 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1402 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1403 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1404 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1405 >;
1406 clock-output-names =
1407 "mlb", "vin3", "vin2", "vin1", "vin0",
1408 "etheravb", "ether", "sata1", "sata0";
1409 };
1410 mstp9_clks: mstp9_clks@e6150994 {
1411 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1412 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1413 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1414 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1415 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1416 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1417 #clock-cells = <1>;
1418 clock-indices = <
1419 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1420 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1421 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1422 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1423 >;
1424 clock-output-names =
1425 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1426 "rcan1", "rcan0", "qspi_mod", "iic3",
1427 "i2c3", "i2c2", "i2c1", "i2c0";
1428 };
1429 mstp10_clks: mstp10_clks@e6150998 {
1430 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1431 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1432 clocks = <&p_clk>,
1433 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1434 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1435 <&p_clk>,
1436 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1437 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1438 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1439 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1440 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1441 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1442 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1443
1444 #clock-cells = <1>;
1445 clock-indices = <
1446 R8A7790_CLK_SSI_ALL
1447 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1448 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1449 R8A7790_CLK_SCU_ALL
1450 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1451 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1452 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1453 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1454 >;
1455 clock-output-names =
1456 "ssi-all",
1457 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1458 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1459 "scu-all",
1460 "scu-dvc1", "scu-dvc0",
1461 "scu-ctu1-mix1", "scu-ctu0-mix0",
1462 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1463 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1464 };
1465 };
1466
1467 qspi: spi@e6b10000 {
1468 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1469 reg = <0 0xe6b10000 0 0x2c>;
1470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1472 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1473 dma-names = "tx", "rx";
1474 power-domains = <&cpg_clocks>;
1475 num-cs = <1>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 status = "disabled";
1479 };
1480
1481 msiof0: spi@e6e20000 {
1482 compatible = "renesas,msiof-r8a7790";
1483 reg = <0 0xe6e20000 0 0x0064>;
1484 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1486 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&cpg_clocks>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 status = "disabled";
1492 };
1493
1494 msiof1: spi@e6e10000 {
1495 compatible = "renesas,msiof-r8a7790";
1496 reg = <0 0xe6e10000 0 0x0064>;
1497 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1499 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1500 dma-names = "tx", "rx";
1501 power-domains = <&cpg_clocks>;
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504 status = "disabled";
1505 };
1506
1507 msiof2: spi@e6e00000 {
1508 compatible = "renesas,msiof-r8a7790";
1509 reg = <0 0xe6e00000 0 0x0064>;
1510 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1512 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1513 dma-names = "tx", "rx";
1514 power-domains = <&cpg_clocks>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 status = "disabled";
1518 };
1519
1520 msiof3: spi@e6c90000 {
1521 compatible = "renesas,msiof-r8a7790";
1522 reg = <0 0xe6c90000 0 0x0064>;
1523 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1525 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1526 dma-names = "tx", "rx";
1527 power-domains = <&cpg_clocks>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 xhci: usb@ee000000 {
1534 compatible = "renesas,xhci-r8a7790";
1535 reg = <0 0xee000000 0 0xc00>;
1536 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1538 power-domains = <&cpg_clocks>;
1539 phys = <&usb2 1>;
1540 phy-names = "usb";
1541 status = "disabled";
1542 };
1543
1544 pci0: pci@ee090000 {
1545 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1546 device_type = "pci";
1547 reg = <0 0xee090000 0 0xc00>,
1548 <0 0xee080000 0 0x1100>;
1549 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1551 power-domains = <&cpg_clocks>;
1552 status = "disabled";
1553
1554 bus-range = <0 0>;
1555 #address-cells = <3>;
1556 #size-cells = <2>;
1557 #interrupt-cells = <1>;
1558 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1559 interrupt-map-mask = <0xff00 0 0 0x7>;
1560 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1561 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1562 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1563
1564 usb@0,1 {
1565 reg = <0x800 0 0 0 0>;
1566 device_type = "pci";
1567 phys = <&usb0 0>;
1568 phy-names = "usb";
1569 };
1570
1571 usb@0,2 {
1572 reg = <0x1000 0 0 0 0>;
1573 device_type = "pci";
1574 phys = <&usb0 0>;
1575 phy-names = "usb";
1576 };
1577 };
1578
1579 pci1: pci@ee0b0000 {
1580 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1581 device_type = "pci";
1582 reg = <0 0xee0b0000 0 0xc00>,
1583 <0 0xee0a0000 0 0x1100>;
1584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1585 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1586 power-domains = <&cpg_clocks>;
1587 status = "disabled";
1588
1589 bus-range = <1 1>;
1590 #address-cells = <3>;
1591 #size-cells = <2>;
1592 #interrupt-cells = <1>;
1593 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1594 interrupt-map-mask = <0xff00 0 0 0x7>;
1595 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1596 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1597 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1598 };
1599
1600 pci2: pci@ee0d0000 {
1601 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1602 device_type = "pci";
1603 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1604 power-domains = <&cpg_clocks>;
1605 reg = <0 0xee0d0000 0 0xc00>,
1606 <0 0xee0c0000 0 0x1100>;
1607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1608 status = "disabled";
1609
1610 bus-range = <2 2>;
1611 #address-cells = <3>;
1612 #size-cells = <2>;
1613 #interrupt-cells = <1>;
1614 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1615 interrupt-map-mask = <0xff00 0 0 0x7>;
1616 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1617 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1618 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1619
1620 usb@0,1 {
1621 reg = <0x800 0 0 0 0>;
1622 device_type = "pci";
1623 phys = <&usb2 0>;
1624 phy-names = "usb";
1625 };
1626
1627 usb@0,2 {
1628 reg = <0x1000 0 0 0 0>;
1629 device_type = "pci";
1630 phys = <&usb2 0>;
1631 phy-names = "usb";
1632 };
1633 };
1634
1635 pciec: pcie@fe000000 {
1636 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1637 reg = <0 0xfe000000 0 0x80000>;
1638 #address-cells = <3>;
1639 #size-cells = <2>;
1640 bus-range = <0x00 0xff>;
1641 device_type = "pci";
1642 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1643 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1644 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1645 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1646 /* Map all possible DDR as inbound ranges */
1647 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1648 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1649 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1652 #interrupt-cells = <1>;
1653 interrupt-map-mask = <0 0 0 0>;
1654 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1656 clock-names = "pcie", "pcie_bus";
1657 power-domains = <&cpg_clocks>;
1658 status = "disabled";
1659 };
1660
1661 rcar_sound: sound@ec500000 {
1662 /*
1663 * #sound-dai-cells is required
1664 *
1665 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1666 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1667 */
1668 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1669 reg = <0 0xec500000 0 0x1000>, /* SCU */
1670 <0 0xec5a0000 0 0x100>, /* ADG */
1671 <0 0xec540000 0 0x1000>, /* SSIU */
1672 <0 0xec541000 0 0x280>, /* SSI */
1673 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1674 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1675
1676 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1677 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1678 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1679 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1680 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1681 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1682 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1683 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1684 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1685 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1686 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1687 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1688 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1689 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1690 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1691 clock-names = "ssi-all",
1692 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1693 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1694 "src.9", "src.8", "src.7", "src.6", "src.5",
1695 "src.4", "src.3", "src.2", "src.1", "src.0",
1696 "ctu.0", "ctu.1",
1697 "mix.0", "mix.1",
1698 "dvc.0", "dvc.1",
1699 "clk_a", "clk_b", "clk_c", "clk_i";
1700 power-domains = <&cpg_clocks>;
1701
1702 status = "disabled";
1703
1704 rcar_sound,dvc {
1705 dvc0: dvc@0 {
1706 dmas = <&audma0 0xbc>;
1707 dma-names = "tx";
1708 };
1709 dvc1: dvc@1 {
1710 dmas = <&audma0 0xbe>;
1711 dma-names = "tx";
1712 };
1713 };
1714
1715 rcar_sound,mix {
1716 mix0: mix@0 { };
1717 mix1: mix@1 { };
1718 };
1719
1720 rcar_sound,ctu {
1721 ctu00: ctu@0 { };
1722 ctu01: ctu@1 { };
1723 ctu02: ctu@2 { };
1724 ctu03: ctu@3 { };
1725 ctu10: ctu@4 { };
1726 ctu11: ctu@5 { };
1727 ctu12: ctu@6 { };
1728 ctu13: ctu@7 { };
1729 };
1730
1731 rcar_sound,src {
1732 src0: src@0 {
1733 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1735 dma-names = "rx", "tx";
1736 };
1737 src1: src@1 {
1738 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1740 dma-names = "rx", "tx";
1741 };
1742 src2: src@2 {
1743 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1744 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1745 dma-names = "rx", "tx";
1746 };
1747 src3: src@3 {
1748 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1749 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1750 dma-names = "rx", "tx";
1751 };
1752 src4: src@4 {
1753 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1754 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1755 dma-names = "rx", "tx";
1756 };
1757 src5: src@5 {
1758 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1760 dma-names = "rx", "tx";
1761 };
1762 src6: src@6 {
1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1765 dma-names = "rx", "tx";
1766 };
1767 src7: src@7 {
1768 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1769 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1770 dma-names = "rx", "tx";
1771 };
1772 src8: src@8 {
1773 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1774 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1775 dma-names = "rx", "tx";
1776 };
1777 src9: src@9 {
1778 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1779 dmas = <&audma0 0x97>, <&audma1 0xba>;
1780 dma-names = "rx", "tx";
1781 };
1782 };
1783
1784 rcar_sound,ssi {
1785 ssi0: ssi@0 {
1786 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1788 dma-names = "rx", "tx", "rxu", "txu";
1789 };
1790 ssi1: ssi@1 {
1791 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1793 dma-names = "rx", "tx", "rxu", "txu";
1794 };
1795 ssi2: ssi@2 {
1796 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1798 dma-names = "rx", "tx", "rxu", "txu";
1799 };
1800 ssi3: ssi@3 {
1801 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1803 dma-names = "rx", "tx", "rxu", "txu";
1804 };
1805 ssi4: ssi@4 {
1806 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1808 dma-names = "rx", "tx", "rxu", "txu";
1809 };
1810 ssi5: ssi@5 {
1811 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1813 dma-names = "rx", "tx", "rxu", "txu";
1814 };
1815 ssi6: ssi@6 {
1816 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1818 dma-names = "rx", "tx", "rxu", "txu";
1819 };
1820 ssi7: ssi@7 {
1821 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1823 dma-names = "rx", "tx", "rxu", "txu";
1824 };
1825 ssi8: ssi@8 {
1826 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1828 dma-names = "rx", "tx", "rxu", "txu";
1829 };
1830 ssi9: ssi@9 {
1831 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1832 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1833 dma-names = "rx", "tx", "rxu", "txu";
1834 };
1835 };
1836 };
1837
1838 ipmmu_sy0: mmu@e6280000 {
1839 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1840 reg = <0 0xe6280000 0 0x1000>;
1841 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1843 #iommu-cells = <1>;
1844 status = "disabled";
1845 };
1846
1847 ipmmu_sy1: mmu@e6290000 {
1848 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1849 reg = <0 0xe6290000 0 0x1000>;
1850 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1851 #iommu-cells = <1>;
1852 status = "disabled";
1853 };
1854
1855 ipmmu_ds: mmu@e6740000 {
1856 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1857 reg = <0 0xe6740000 0 0x1000>;
1858 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1860 #iommu-cells = <1>;
1861 status = "disabled";
1862 };
1863
1864 ipmmu_mp: mmu@ec680000 {
1865 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1866 reg = <0 0xec680000 0 0x1000>;
1867 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1868 #iommu-cells = <1>;
1869 status = "disabled";
1870 };
1871
1872 ipmmu_mx: mmu@fe951000 {
1873 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1874 reg = <0 0xfe951000 0 0x1000>;
1875 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1877 #iommu-cells = <1>;
1878 status = "disabled";
1879 };
1880
1881 ipmmu_rt: mmu@ffc80000 {
1882 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1883 reg = <0 0xffc80000 0 0x1000>;
1884 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1885 #iommu-cells = <1>;
1886 status = "disabled";
1887 };
1888};