1/*
 2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8/dts-v1/;
 9
10/include/ "skeleton.dtsi"
11
12/ {
13	compatible = "snps,nsim_hs";
14	interrupt-parent = <&core_intc>;
15
16	chosen {
17		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
18	};
19
20	aliases {
21		serial0 = &arcuart0;
22	};
23
24	fpga {
25		compatible = "simple-bus";
26		#address-cells = <1>;
27		#size-cells = <1>;
28
29		/* child and parent address space 1:1 mapped */
30		ranges;
31
32		core_intc: core-interrupt-controller {
33			compatible = "snps,archs-intc";
34			interrupt-controller;
35			#interrupt-cells = <1>;
36		};
37
38		idu_intc: idu-interrupt-controller {
39			compatible = "snps,archs-idu-intc";
40			interrupt-controller;
41			interrupt-parent = <&core_intc>;
42
43			/*
44			 * <hwirq  distribution>
45			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
46			 */
47			#interrupt-cells = <2>;
48
49			/*
50			 * upstream irqs to core intc - downstream these are
51			 * "COMMON" irq 0,1..
52			 */
53			interrupts = <24 25 26 27 28 29 30 31>;
54		};
55
56		arcuart0: serial@c0fc1000 {
57			compatible = "snps,arc-uart";
58			reg = <0xc0fc1000 0x100>;
59			interrupt-parent = <&idu_intc>;
60			interrupts = <0 0>;
61			clock-frequency = <80000000>;
62			current-speed = <115200>;
63			status = "okay";
64		};
65
66		arcpct0: pct {
67			compatible = "snps,archs-pct";
68			#interrupt-cells = <1>;
69			interrupts = <20>;
70		};
71	};
72};