1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 4 */
 5/dts-v1/;
 6
 7/include/ "skeleton_hs_idu.dtsi"
 8
 9/ {
10	model = "snps,nsim_hs-smp";
11	compatible = "snps,nsim_hs";
12	interrupt-parent = <&core_intc>;
13
14	chosen {
15		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
16	};
17
18	aliases {
19		serial0 = &arcuart0;
20	};
21
22	fpga {
23		compatible = "simple-bus";
24		#address-cells = <1>;
25		#size-cells = <1>;
26
27		/* child and parent address space 1:1 mapped */
28		ranges;
29
30		core_clk: core_clk {
31			#clock-cells = <0>;
32			compatible = "fixed-clock";
33			clock-frequency = <80000000>;
34		};
35
36		core_intc: core-interrupt-controller {
37			compatible = "snps,archs-intc";
38			interrupt-controller;
39			#interrupt-cells = <1>;
40		};
41
42		idu_intc: idu-interrupt-controller {
43			compatible = "snps,archs-idu-intc";
44			interrupt-controller;
45			interrupt-parent = <&core_intc>;
46			#interrupt-cells = <1>;
47		};
48
49		arcuart0: serial@c0fc1000 {
50			compatible = "snps,arc-uart";
51			reg = <0xc0fc1000 0x100>;
52			interrupt-parent = <&idu_intc>;
53			interrupts = <0>;
54			clock-frequency = <80000000>;
55			current-speed = <115200>;
56			status = "okay";
57		};
58
59		arcpct0: pct {
60			compatible = "snps,archs-pct";
61			#interrupt-cells = <1>;
62			interrupts = <20>;
63		};
64	};
65};