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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
120
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
122 limit >>= 3;
123
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
128 } else {
129 hs_ep->frame_overrun = false;
130 }
131}
132
133/**
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * by one.
136 * @hs_ep: The endpoint.
137 *
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
141 *
142 */
143static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144{
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
147
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
149 limit >>= 3;
150
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
153 else
154 hs_ep->target_frame = limit;
155}
156
157/**
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
161 */
162static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163{
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
165 u32 new_gsintmsk;
166
167 new_gsintmsk = gsintmsk | ints;
168
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
172 }
173}
174
175/**
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
179 */
180static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181{
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
183 u32 new_gsintmsk;
184
185 new_gsintmsk = gsintmsk & ~ints;
186
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
189}
190
191/**
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
197 *
198 * Set or clear the mask for an individual endpoint's interrupt
199 * request.
200 */
201static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
203 unsigned int en)
204{
205 unsigned long flags;
206 u32 bit = 1 << ep;
207 u32 daint;
208
209 if (!dir_in)
210 bit <<= 16;
211
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
214 if (en)
215 daint |= bit;
216 else
217 daint &= ~bit;
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
220}
221
222/**
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 *
225 * @hsotg: Programming view of the DWC_otg controller
226 */
227int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228{
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
232 else
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
235}
236
237/**
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
240 *
241 * @hsotg: Programming view of the DWC_otg controller
242 */
243int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
244{
245 int addr;
246 int tx_addr_max;
247 u32 np_tx_fifo_size;
248
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
251
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
254
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
257 return 0;
258
259 return tx_addr_max - addr;
260}
261
262/**
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 *
265 * @hsotg: Programming view of the DWC_otg controller
266 *
267 */
268static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
269{
270 u32 gintsts2;
271 u32 gintmsk2;
272
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
276
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
281 }
282}
283
284/**
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
286 * TX FIFOs
287 *
288 * @hsotg: Programming view of the DWC_otg controller
289 */
290int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
291{
292 int tx_fifo_count;
293 int tx_fifo_depth;
294
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
298
299 if (!tx_fifo_count)
300 return tx_fifo_depth;
301 else
302 return tx_fifo_depth / tx_fifo_count;
303}
304
305/**
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
308 */
309static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
310{
311 unsigned int ep;
312 unsigned int addr;
313 int timeout;
314
315 u32 val;
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
320 hsotg->fifo_map = 0;
321
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
327 GNPTXFSIZ);
328
329 /*
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
333 * known values.
334 */
335
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
338
339 /*
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
342 * given endpoint.
343 */
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
345 if (!txfsz[ep])
346 continue;
347 val = addr;
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
351 addr += txfsz[ep];
352
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
355 }
356
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
359 GDFIFOCFG);
360 /*
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
363 */
364
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
367
368 /* wait until the fifos are both flushed */
369 timeout = 100;
370 while (1) {
371 val = dwc2_readl(hsotg, GRSTCTL);
372
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
374 break;
375
376 if (--timeout == 0) {
377 dev_err(hsotg->dev,
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
379 __func__, val);
380 break;
381 }
382
383 udelay(1);
384 }
385
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
387}
388
389/**
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
393 *
394 * Allocate a new USB request structure appropriate for the specified endpoint
395 */
396static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
397 gfp_t flags)
398{
399 struct dwc2_hsotg_req *req;
400
401 req = kzalloc(sizeof(*req), flags);
402 if (!req)
403 return NULL;
404
405 INIT_LIST_HEAD(&req->queue);
406
407 return &req->req;
408}
409
410/**
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
413 *
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
416 */
417static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418{
419 return hs_ep->periodic;
420}
421
422/**
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
427 *
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
430 */
431static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
434{
435 struct usb_request *req = &hs_req->req;
436
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
438}
439
440/*
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
444 *
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
447 */
448static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449{
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
454 GFP_KERNEL);
455 if (!hsotg->setup_desc[0])
456 goto fail;
457
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
462 GFP_KERNEL);
463 if (!hsotg->setup_desc[1])
464 goto fail;
465
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
470 GFP_KERNEL);
471 if (!hsotg->ctrl_in_desc)
472 goto fail;
473
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
478 GFP_KERNEL);
479 if (!hsotg->ctrl_out_desc)
480 goto fail;
481
482 return 0;
483
484fail:
485 return -ENOMEM;
486}
487
488/**
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
493 *
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
497 * write the data.
498 *
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 *
502 * This routine is only needed for PIO
503 */
504static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
507{
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
512 void *data;
513 int can_write;
514 int pkt_round;
515 int max_transfer;
516
517 to_write -= (buf_pos - hs_ep->last_load);
518
519 /* if there's nothing to write, get out early */
520 if (to_write == 0)
521 return 0;
522
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
525 int size_left;
526 int size_done;
527
528 /*
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
531 */
532
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
534
535 /*
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
538 */
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
541 return -ENOSPC;
542 }
543
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 __func__, size_left,
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
550
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
555
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
559
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
562 return -ENOSPC;
563 }
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
567
568 can_write &= 0xffff;
569 can_write *= 4;
570 } else {
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 dev_dbg(hsotg->dev,
573 "%s: no queue slots available (0x%08x)\n",
574 __func__, gnptxsts);
575
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
577 return -ENOSPC;
578 }
579
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
582 }
583
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
588
589 /*
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
593 */
594 if (can_write > 512 && !periodic)
595 can_write = 512;
596
597 /*
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
600 * doing it.
601 */
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
604
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
609 GINTSTS_NPTXFEMP);
610 }
611
612 /* see if we can write data */
613
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
617
618 /*
619 * Round the write down to an
620 * exact number of packets.
621 *
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
624 */
625
626 if (pkt_round)
627 to_write -= pkt_round;
628
629 /*
630 * enable correct FIFO interrupt to alert us when there
631 * is more room left.
632 */
633
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
638 GINTSTS_NPTXFEMP);
639 }
640
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
643
644 if (to_write <= 0)
645 return -ENOSPC;
646
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
649
650 if (periodic)
651 hs_ep->fifo_load += to_write;
652
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
655
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657
658 return (to_write >= can_write) ? -ENOSPC : 0;
659}
660
661/**
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
664 *
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
667 */
668static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669{
670 int index = hs_ep->index;
671 unsigned int maxsize;
672 unsigned int maxpkt;
673
674 if (index != 0) {
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
677 } else {
678 maxsize = 64 + 64;
679 if (hs_ep->dir_in)
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
681 else
682 maxpkt = 2;
683 }
684
685 /* we made the constant loading easier above by using +1 */
686 maxpkt--;
687 maxsize--;
688
689 /*
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
692 */
693
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
696
697 return maxsize;
698}
699
700/**
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
703 *
704 * Return the current frame number
705 */
706static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
707{
708 u32 dsts;
709
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
713
714 return dsts;
715}
716
717/**
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
721 *
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
725 */
726static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727{
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
733
734 if (is_isoc)
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
738 else
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740
741 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (hs_ep->index)
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
745
746 return maxsize;
747}
748
749/*
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
753 *
754 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * characteristics.
756 * DMA descriptor transfer bytes limit depends on EP type:
757 * Control out - MPS,
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
763 *
764 * Selects corresponding mask for RX/TX bytes as well.
765 */
766static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767{
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
771 u32 desc_size = 0;
772
773 if (!hs_ep->index && !dir_in) {
774 desc_size = mps;
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
777 if (dir_in) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 } else {
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
783 }
784 } else {
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
787
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
790 }
791
792 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (hs_ep->index)
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 desc_size = mps;
796 *mask = DEV_DMA_NBYTES_MASK;
797 }
798
799 return desc_size;
800}
801
802static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
804 dma_addr_t dma_buff,
805 unsigned int len,
806 bool true_last)
807{
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
810 u32 maxsize = 0;
811 u32 offset = 0;
812 u32 mask = 0;
813 int i;
814
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
819 if (len == 0)
820 hs_ep->desc_count = 1;
821
822 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status = 0;
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
826
827 if (len > maxsize) {
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830
831 (*desc)->status |=
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
834
835 len -= maxsize;
836 offset += maxsize;
837 } else {
838 if (true_last)
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
840
841 if (dir_in)
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
844 DEV_DMA_SHORT : 0);
845
846 (*desc)->status |=
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
849 }
850
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
854 (*desc)++;
855 }
856}
857
858/*
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
864 *
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
867 */
868static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
869 dma_addr_t dma_buff,
870 unsigned int len)
871{
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
875 int i;
876 u8 desc_count = 0;
877
878 if (hs_ep->req)
879 ureq = &hs_ep->req->req;
880
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
885 return;
886 }
887
888 /* DMA sg buffer */
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 sg_is_last(sg));
893 desc_count += hs_ep->desc_count;
894 }
895
896 hs_ep->desc_count = desc_count;
897}
898
899/*
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
904 *
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
908 * status.
909 */
910static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
912{
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
915 u32 index;
916 u32 mask = 0;
917 u8 pid = 0;
918
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
920
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
923
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
928 return 1;
929 }
930
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
937
938 desc->status = 0;
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
944
945 if (hs_ep->dir_in) {
946 if (len)
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
948 else
949 pid = 1;
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
953 DEV_DMA_SHORT : 0) |
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
957 }
958
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961
962 /* Increment frame number by interval for IN */
963 if (hs_ep->dir_in)
964 dwc2_gadget_incr_frame_num(hs_ep);
965
966 /* Update index of last configured entry in the chain */
967 hs_ep->next_desc++;
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
970
971 return 0;
972}
973
974/*
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
977 *
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
980 */
981static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982{
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
986 int ret;
987 int i;
988 u32 dma_reg;
989 u32 depctl;
990 u32 ctrl;
991 struct dwc2_dma_desc *desc;
992
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
996 return;
997 }
998
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1002 desc->status = 0;
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1005 }
1006
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1010
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1014 }
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1017 if (ret)
1018 break;
1019 }
1020
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1031}
1032
1033static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1037 int result);
1038
1039/**
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1045 *
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1048 */
1049static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1052 bool continuing)
1053{
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1057 u32 epctrl_reg;
1058 u32 epsize_reg;
1059 u32 epsize;
1060 u32 ctrl;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1065
1066 if (index != 0) {
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1069 WARN_ON(1);
1070 return;
1071 } else if (hs_ep->req != hs_req && continuing) {
1072 dev_err(hsotg->dev,
1073 "%s: continue different req\n", __func__);
1074 WARN_ON(1);
1075 return;
1076 }
1077 }
1078
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1086
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1092 return;
1093 }
1094
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1098
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1101 else
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1106
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1109
1110 /* round down to multiple of packets */
1111 if (round)
1112 maxreq -= round;
1113
1114 length = maxreq;
1115 }
1116
1117 if (length)
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 else
1120 packets = 1; /* send one packet if length is zero. */
1121
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1125 else
1126 epsize = DXEPTSIZ_MC(1);
1127 else
1128 epsize = 0;
1129
1130 /*
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 */
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1139 }
1140
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1143
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1149
1150 if (using_desc_dma(hsotg)) {
1151 u32 offset = 0;
1152 u32 mps = hs_ep->ep.maxpacket;
1153
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1155 if (!dir_in) {
1156 if (!index)
1157 length = mps;
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1160 }
1161
1162 if (continuing)
1163 offset = ureq->actual;
1164
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1167 length);
1168
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 } else {
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1177
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 /*
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1182 */
1183
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1188 }
1189 }
1190
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1196 else
1197 ctrl |= DXEPCTL_SETEVENFR;
1198 }
1199 ctrl |= DXEPCTL_CNAK;
1200 } else {
1201 hs_req->req.frame_number = hs_ep->target_frame;
1202 hs_req->req.actual = 0;
1203 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1204 return;
1205 }
1206 }
1207
1208 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1209
1210 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1211
1212 /* For Setup request do not clear NAK */
1213 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1214 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1215
1216 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1217 dwc2_writel(hsotg, ctrl, epctrl_reg);
1218
1219 /*
1220 * set these, it seems that DMA support increments past the end
1221 * of the packet buffer so we need to calculate the length from
1222 * this information.
1223 */
1224 hs_ep->size_loaded = length;
1225 hs_ep->last_load = ureq->actual;
1226
1227 if (dir_in && !using_dma(hsotg)) {
1228 /* set these anyway, we may need them for non-periodic in */
1229 hs_ep->fifo_load = 0;
1230
1231 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1232 }
1233
1234 /*
1235 * Note, trying to clear the NAK here causes problems with transmit
1236 * on the S3C6400 ending up with the TXFIFO becoming full.
1237 */
1238
1239 /* check ep is enabled */
1240 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1241 dev_dbg(hsotg->dev,
1242 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1243 index, dwc2_readl(hsotg, epctrl_reg));
1244
1245 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1246 __func__, dwc2_readl(hsotg, epctrl_reg));
1247
1248 /* enable ep interrupts */
1249 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1250}
1251
1252/**
1253 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1254 * @hsotg: The device state.
1255 * @hs_ep: The endpoint the request is on.
1256 * @req: The request being processed.
1257 *
1258 * We've been asked to queue a request, so ensure that the memory buffer
1259 * is correctly setup for DMA. If we've been passed an extant DMA address
1260 * then ensure the buffer has been synced to memory. If our buffer has no
1261 * DMA memory, then we map the memory and mark our request to allow us to
1262 * cleanup on completion.
1263 */
1264static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1265 struct dwc2_hsotg_ep *hs_ep,
1266 struct usb_request *req)
1267{
1268 int ret;
1269
1270 hs_ep->map_dir = hs_ep->dir_in;
1271 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1272 if (ret)
1273 goto dma_error;
1274
1275 return 0;
1276
1277dma_error:
1278 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1279 __func__, req->buf, req->length);
1280
1281 return -EIO;
1282}
1283
1284static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1285 struct dwc2_hsotg_ep *hs_ep,
1286 struct dwc2_hsotg_req *hs_req)
1287{
1288 void *req_buf = hs_req->req.buf;
1289
1290 /* If dma is not being used or buffer is aligned */
1291 if (!using_dma(hsotg) || !((long)req_buf & 3))
1292 return 0;
1293
1294 WARN_ON(hs_req->saved_req_buf);
1295
1296 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1297 hs_ep->ep.name, req_buf, hs_req->req.length);
1298
1299 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1300 if (!hs_req->req.buf) {
1301 hs_req->req.buf = req_buf;
1302 dev_err(hsotg->dev,
1303 "%s: unable to allocate memory for bounce buffer\n",
1304 __func__);
1305 return -ENOMEM;
1306 }
1307
1308 /* Save actual buffer */
1309 hs_req->saved_req_buf = req_buf;
1310
1311 if (hs_ep->dir_in)
1312 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1313 return 0;
1314}
1315
1316static void
1317dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1318 struct dwc2_hsotg_ep *hs_ep,
1319 struct dwc2_hsotg_req *hs_req)
1320{
1321 /* If dma is not being used or buffer was aligned */
1322 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1323 return;
1324
1325 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1326 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1327
1328 /* Copy data from bounce buffer on successful out transfer */
1329 if (!hs_ep->dir_in && !hs_req->req.status)
1330 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1331 hs_req->req.actual);
1332
1333 /* Free bounce buffer */
1334 kfree(hs_req->req.buf);
1335
1336 hs_req->req.buf = hs_req->saved_req_buf;
1337 hs_req->saved_req_buf = NULL;
1338}
1339
1340/**
1341 * dwc2_gadget_target_frame_elapsed - Checks target frame
1342 * @hs_ep: The driver endpoint to check
1343 *
1344 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1345 * corresponding transfer.
1346 */
1347static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1348{
1349 struct dwc2_hsotg *hsotg = hs_ep->parent;
1350 u32 target_frame = hs_ep->target_frame;
1351 u32 current_frame = hsotg->frame_number;
1352 bool frame_overrun = hs_ep->frame_overrun;
1353 u16 limit = DSTS_SOFFN_LIMIT;
1354
1355 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1356 limit >>= 3;
1357
1358 if (!frame_overrun && current_frame >= target_frame)
1359 return true;
1360
1361 if (frame_overrun && current_frame >= target_frame &&
1362 ((current_frame - target_frame) < limit / 2))
1363 return true;
1364
1365 return false;
1366}
1367
1368/*
1369 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1370 * @hsotg: The driver state
1371 * @hs_ep: the ep descriptor chain is for
1372 *
1373 * Called to update EP0 structure's pointers depend on stage of
1374 * control transfer.
1375 */
1376static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1377 struct dwc2_hsotg_ep *hs_ep)
1378{
1379 switch (hsotg->ep0_state) {
1380 case DWC2_EP0_SETUP:
1381 case DWC2_EP0_STATUS_OUT:
1382 hs_ep->desc_list = hsotg->setup_desc[0];
1383 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1384 break;
1385 case DWC2_EP0_DATA_IN:
1386 case DWC2_EP0_STATUS_IN:
1387 hs_ep->desc_list = hsotg->ctrl_in_desc;
1388 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1389 break;
1390 case DWC2_EP0_DATA_OUT:
1391 hs_ep->desc_list = hsotg->ctrl_out_desc;
1392 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1393 break;
1394 default:
1395 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1396 hsotg->ep0_state);
1397 return -EINVAL;
1398 }
1399
1400 return 0;
1401}
1402
1403static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1404 gfp_t gfp_flags)
1405{
1406 struct dwc2_hsotg_req *hs_req = our_req(req);
1407 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1408 struct dwc2_hsotg *hs = hs_ep->parent;
1409 bool first;
1410 int ret;
1411 u32 maxsize = 0;
1412 u32 mask = 0;
1413
1414
1415 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1416 ep->name, req, req->length, req->buf, req->no_interrupt,
1417 req->zero, req->short_not_ok);
1418
1419 /* Prevent new request submission when controller is suspended */
1420 if (hs->lx_state != DWC2_L0) {
1421 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1422 __func__);
1423 return -EAGAIN;
1424 }
1425
1426 /* initialise status of the request */
1427 INIT_LIST_HEAD(&hs_req->queue);
1428 req->actual = 0;
1429 req->status = -EINPROGRESS;
1430
1431 /* Don't queue ISOC request if length greater than mps*mc */
1432 if (hs_ep->isochronous &&
1433 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1434 dev_err(hs->dev, "req length > maxpacket*mc\n");
1435 return -EINVAL;
1436 }
1437
1438 /* In DDMA mode for ISOC's don't queue request if length greater
1439 * than descriptor limits.
1440 */
1441 if (using_desc_dma(hs) && hs_ep->isochronous) {
1442 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1443 if (hs_ep->dir_in && req->length > maxsize) {
1444 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1445 req->length, maxsize);
1446 return -EINVAL;
1447 }
1448
1449 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1450 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1451 req->length, hs_ep->ep.maxpacket);
1452 return -EINVAL;
1453 }
1454 }
1455
1456 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1457 if (ret)
1458 return ret;
1459
1460 /* if we're using DMA, sync the buffers as necessary */
1461 if (using_dma(hs)) {
1462 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1463 if (ret)
1464 return ret;
1465 }
1466 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1467 if (using_desc_dma(hs) && !hs_ep->index) {
1468 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1469 if (ret)
1470 return ret;
1471 }
1472
1473 first = list_empty(&hs_ep->queue);
1474 list_add_tail(&hs_req->queue, &hs_ep->queue);
1475
1476 /*
1477 * Handle DDMA isochronous transfers separately - just add new entry
1478 * to the descriptor chain.
1479 * Transfer will be started once SW gets either one of NAK or
1480 * OutTknEpDis interrupts.
1481 */
1482 if (using_desc_dma(hs) && hs_ep->isochronous) {
1483 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1484 dma_addr_t dma_addr = hs_req->req.dma;
1485
1486 if (hs_req->req.num_sgs) {
1487 WARN_ON(hs_req->req.num_sgs > 1);
1488 dma_addr = sg_dma_address(hs_req->req.sg);
1489 }
1490 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1491 hs_req->req.length);
1492 }
1493 return 0;
1494 }
1495
1496 /* Change EP direction if status phase request is after data out */
1497 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1498 hs->ep0_state == DWC2_EP0_DATA_OUT)
1499 hs_ep->dir_in = 1;
1500
1501 if (first) {
1502 if (!hs_ep->isochronous) {
1503 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1504 return 0;
1505 }
1506
1507 /* Update current frame number value. */
1508 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1509 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1510 dwc2_gadget_incr_frame_num(hs_ep);
1511 /* Update current frame number value once more as it
1512 * changes here.
1513 */
1514 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1515 }
1516
1517 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1518 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1519 }
1520 return 0;
1521}
1522
1523static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1524 gfp_t gfp_flags)
1525{
1526 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1527 struct dwc2_hsotg *hs = hs_ep->parent;
1528 unsigned long flags;
1529 int ret;
1530
1531 spin_lock_irqsave(&hs->lock, flags);
1532 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1533 spin_unlock_irqrestore(&hs->lock, flags);
1534
1535 return ret;
1536}
1537
1538static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1539 struct usb_request *req)
1540{
1541 struct dwc2_hsotg_req *hs_req = our_req(req);
1542
1543 kfree(hs_req);
1544}
1545
1546/**
1547 * dwc2_hsotg_complete_oursetup - setup completion callback
1548 * @ep: The endpoint the request was on.
1549 * @req: The request completed.
1550 *
1551 * Called on completion of any requests the driver itself
1552 * submitted that need cleaning up.
1553 */
1554static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1555 struct usb_request *req)
1556{
1557 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1558 struct dwc2_hsotg *hsotg = hs_ep->parent;
1559
1560 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1561
1562 dwc2_hsotg_ep_free_request(ep, req);
1563}
1564
1565/**
1566 * ep_from_windex - convert control wIndex value to endpoint
1567 * @hsotg: The driver state.
1568 * @windex: The control request wIndex field (in host order).
1569 *
1570 * Convert the given wIndex into a pointer to an driver endpoint
1571 * structure, or return NULL if it is not a valid endpoint.
1572 */
1573static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1574 u32 windex)
1575{
1576 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1577 int idx = windex & 0x7F;
1578
1579 if (windex >= 0x100)
1580 return NULL;
1581
1582 if (idx > hsotg->num_of_eps)
1583 return NULL;
1584
1585 return index_to_ep(hsotg, idx, dir);
1586}
1587
1588/**
1589 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1590 * @hsotg: The driver state.
1591 * @testmode: requested usb test mode
1592 * Enable usb Test Mode requested by the Host.
1593 */
1594int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1595{
1596 int dctl = dwc2_readl(hsotg, DCTL);
1597
1598 dctl &= ~DCTL_TSTCTL_MASK;
1599 switch (testmode) {
1600 case USB_TEST_J:
1601 case USB_TEST_K:
1602 case USB_TEST_SE0_NAK:
1603 case USB_TEST_PACKET:
1604 case USB_TEST_FORCE_ENABLE:
1605 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1606 break;
1607 default:
1608 return -EINVAL;
1609 }
1610 dwc2_writel(hsotg, dctl, DCTL);
1611 return 0;
1612}
1613
1614/**
1615 * dwc2_hsotg_send_reply - send reply to control request
1616 * @hsotg: The device state
1617 * @ep: Endpoint 0
1618 * @buff: Buffer for request
1619 * @length: Length of reply.
1620 *
1621 * Create a request and queue it on the given endpoint. This is useful as
1622 * an internal method of sending replies to certain control requests, etc.
1623 */
1624static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1625 struct dwc2_hsotg_ep *ep,
1626 void *buff,
1627 int length)
1628{
1629 struct usb_request *req;
1630 int ret;
1631
1632 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1633
1634 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1635 hsotg->ep0_reply = req;
1636 if (!req) {
1637 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1638 return -ENOMEM;
1639 }
1640
1641 req->buf = hsotg->ep0_buff;
1642 req->length = length;
1643 /*
1644 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1645 * STATUS stage.
1646 */
1647 req->zero = 0;
1648 req->complete = dwc2_hsotg_complete_oursetup;
1649
1650 if (length)
1651 memcpy(req->buf, buff, length);
1652
1653 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1654 if (ret) {
1655 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1656 return ret;
1657 }
1658
1659 return 0;
1660}
1661
1662/**
1663 * dwc2_hsotg_process_req_status - process request GET_STATUS
1664 * @hsotg: The device state
1665 * @ctrl: USB control request
1666 */
1667static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1668 struct usb_ctrlrequest *ctrl)
1669{
1670 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1671 struct dwc2_hsotg_ep *ep;
1672 __le16 reply;
1673 u16 status;
1674 int ret;
1675
1676 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1677
1678 if (!ep0->dir_in) {
1679 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1680 return -EINVAL;
1681 }
1682
1683 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1684 case USB_RECIP_DEVICE:
1685 status = hsotg->gadget.is_selfpowered <<
1686 USB_DEVICE_SELF_POWERED;
1687 status |= hsotg->remote_wakeup_allowed <<
1688 USB_DEVICE_REMOTE_WAKEUP;
1689 reply = cpu_to_le16(status);
1690 break;
1691
1692 case USB_RECIP_INTERFACE:
1693 /* currently, the data result should be zero */
1694 reply = cpu_to_le16(0);
1695 break;
1696
1697 case USB_RECIP_ENDPOINT:
1698 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1699 if (!ep)
1700 return -ENOENT;
1701
1702 reply = cpu_to_le16(ep->halted ? 1 : 0);
1703 break;
1704
1705 default:
1706 return 0;
1707 }
1708
1709 if (le16_to_cpu(ctrl->wLength) != 2)
1710 return -EINVAL;
1711
1712 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1713 if (ret) {
1714 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1715 return ret;
1716 }
1717
1718 return 1;
1719}
1720
1721static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1722
1723/**
1724 * get_ep_head - return the first request on the endpoint
1725 * @hs_ep: The controller endpoint to get
1726 *
1727 * Get the first request on the endpoint.
1728 */
1729static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1730{
1731 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1732 queue);
1733}
1734
1735/**
1736 * dwc2_gadget_start_next_request - Starts next request from ep queue
1737 * @hs_ep: Endpoint structure
1738 *
1739 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1740 * in its handler. Hence we need to unmask it here to be able to do
1741 * resynchronization.
1742 */
1743static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1744{
1745 struct dwc2_hsotg *hsotg = hs_ep->parent;
1746 int dir_in = hs_ep->dir_in;
1747 struct dwc2_hsotg_req *hs_req;
1748
1749 if (!list_empty(&hs_ep->queue)) {
1750 hs_req = get_ep_head(hs_ep);
1751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1752 return;
1753 }
1754 if (!hs_ep->isochronous)
1755 return;
1756
1757 if (dir_in) {
1758 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1759 __func__);
1760 } else {
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1762 __func__);
1763 }
1764}
1765
1766/**
1767 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1768 * @hsotg: The device state
1769 * @ctrl: USB control request
1770 */
1771static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1772 struct usb_ctrlrequest *ctrl)
1773{
1774 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1775 struct dwc2_hsotg_req *hs_req;
1776 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1777 struct dwc2_hsotg_ep *ep;
1778 int ret;
1779 bool halted;
1780 u32 recip;
1781 u32 wValue;
1782 u32 wIndex;
1783
1784 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1785 __func__, set ? "SET" : "CLEAR");
1786
1787 wValue = le16_to_cpu(ctrl->wValue);
1788 wIndex = le16_to_cpu(ctrl->wIndex);
1789 recip = ctrl->bRequestType & USB_RECIP_MASK;
1790
1791 switch (recip) {
1792 case USB_RECIP_DEVICE:
1793 switch (wValue) {
1794 case USB_DEVICE_REMOTE_WAKEUP:
1795 if (set)
1796 hsotg->remote_wakeup_allowed = 1;
1797 else
1798 hsotg->remote_wakeup_allowed = 0;
1799 break;
1800
1801 case USB_DEVICE_TEST_MODE:
1802 if ((wIndex & 0xff) != 0)
1803 return -EINVAL;
1804 if (!set)
1805 return -EINVAL;
1806
1807 hsotg->test_mode = wIndex >> 8;
1808 break;
1809 default:
1810 return -ENOENT;
1811 }
1812
1813 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1814 if (ret) {
1815 dev_err(hsotg->dev,
1816 "%s: failed to send reply\n", __func__);
1817 return ret;
1818 }
1819 break;
1820
1821 case USB_RECIP_ENDPOINT:
1822 ep = ep_from_windex(hsotg, wIndex);
1823 if (!ep) {
1824 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1825 __func__, wIndex);
1826 return -ENOENT;
1827 }
1828
1829 switch (wValue) {
1830 case USB_ENDPOINT_HALT:
1831 halted = ep->halted;
1832
1833 if (!ep->wedged)
1834 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1835
1836 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1837 if (ret) {
1838 dev_err(hsotg->dev,
1839 "%s: failed to send reply\n", __func__);
1840 return ret;
1841 }
1842
1843 /*
1844 * we have to complete all requests for ep if it was
1845 * halted, and the halt was cleared by CLEAR_FEATURE
1846 */
1847
1848 if (!set && halted) {
1849 /*
1850 * If we have request in progress,
1851 * then complete it
1852 */
1853 if (ep->req) {
1854 hs_req = ep->req;
1855 ep->req = NULL;
1856 list_del_init(&hs_req->queue);
1857 if (hs_req->req.complete) {
1858 spin_unlock(&hsotg->lock);
1859 usb_gadget_giveback_request(
1860 &ep->ep, &hs_req->req);
1861 spin_lock(&hsotg->lock);
1862 }
1863 }
1864
1865 /* If we have pending request, then start it */
1866 if (!ep->req)
1867 dwc2_gadget_start_next_request(ep);
1868 }
1869
1870 break;
1871
1872 default:
1873 return -ENOENT;
1874 }
1875 break;
1876 default:
1877 return -ENOENT;
1878 }
1879 return 1;
1880}
1881
1882static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1883
1884/**
1885 * dwc2_hsotg_stall_ep0 - stall ep0
1886 * @hsotg: The device state
1887 *
1888 * Set stall for ep0 as response for setup request.
1889 */
1890static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1891{
1892 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1893 u32 reg;
1894 u32 ctrl;
1895
1896 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1897 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1898
1899 /*
1900 * DxEPCTL_Stall will be cleared by EP once it has
1901 * taken effect, so no need to clear later.
1902 */
1903
1904 ctrl = dwc2_readl(hsotg, reg);
1905 ctrl |= DXEPCTL_STALL;
1906 ctrl |= DXEPCTL_CNAK;
1907 dwc2_writel(hsotg, ctrl, reg);
1908
1909 dev_dbg(hsotg->dev,
1910 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1911 ctrl, reg, dwc2_readl(hsotg, reg));
1912
1913 /*
1914 * complete won't be called, so we enqueue
1915 * setup request here
1916 */
1917 dwc2_hsotg_enqueue_setup(hsotg);
1918}
1919
1920/**
1921 * dwc2_hsotg_process_control - process a control request
1922 * @hsotg: The device state
1923 * @ctrl: The control request received
1924 *
1925 * The controller has received the SETUP phase of a control request, and
1926 * needs to work out what to do next (and whether to pass it on to the
1927 * gadget driver).
1928 */
1929static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1930 struct usb_ctrlrequest *ctrl)
1931{
1932 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1933 int ret = 0;
1934 u32 dcfg;
1935
1936 dev_dbg(hsotg->dev,
1937 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1938 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1939 ctrl->wIndex, ctrl->wLength);
1940
1941 if (ctrl->wLength == 0) {
1942 ep0->dir_in = 1;
1943 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1944 } else if (ctrl->bRequestType & USB_DIR_IN) {
1945 ep0->dir_in = 1;
1946 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1947 } else {
1948 ep0->dir_in = 0;
1949 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1950 }
1951
1952 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1953 switch (ctrl->bRequest) {
1954 case USB_REQ_SET_ADDRESS:
1955 hsotg->connected = 1;
1956 dcfg = dwc2_readl(hsotg, DCFG);
1957 dcfg &= ~DCFG_DEVADDR_MASK;
1958 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1959 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1960 dwc2_writel(hsotg, dcfg, DCFG);
1961
1962 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1963
1964 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1965 return;
1966
1967 case USB_REQ_GET_STATUS:
1968 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1969 break;
1970
1971 case USB_REQ_CLEAR_FEATURE:
1972 case USB_REQ_SET_FEATURE:
1973 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1974 break;
1975 }
1976 }
1977
1978 /* as a fallback, try delivering it to the driver to deal with */
1979
1980 if (ret == 0 && hsotg->driver) {
1981 spin_unlock(&hsotg->lock);
1982 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1983 spin_lock(&hsotg->lock);
1984 if (ret < 0)
1985 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1986 }
1987
1988 hsotg->delayed_status = false;
1989 if (ret == USB_GADGET_DELAYED_STATUS)
1990 hsotg->delayed_status = true;
1991
1992 /*
1993 * the request is either unhandlable, or is not formatted correctly
1994 * so respond with a STALL for the status stage to indicate failure.
1995 */
1996
1997 if (ret < 0)
1998 dwc2_hsotg_stall_ep0(hsotg);
1999}
2000
2001/**
2002 * dwc2_hsotg_complete_setup - completion of a setup transfer
2003 * @ep: The endpoint the request was on.
2004 * @req: The request completed.
2005 *
2006 * Called on completion of any requests the driver itself submitted for
2007 * EP0 setup packets
2008 */
2009static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2010 struct usb_request *req)
2011{
2012 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2013 struct dwc2_hsotg *hsotg = hs_ep->parent;
2014
2015 if (req->status < 0) {
2016 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2017 return;
2018 }
2019
2020 spin_lock(&hsotg->lock);
2021 if (req->actual == 0)
2022 dwc2_hsotg_enqueue_setup(hsotg);
2023 else
2024 dwc2_hsotg_process_control(hsotg, req->buf);
2025 spin_unlock(&hsotg->lock);
2026}
2027
2028/**
2029 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2030 * @hsotg: The device state.
2031 *
2032 * Enqueue a request on EP0 if necessary to received any SETUP packets
2033 * received from the host.
2034 */
2035static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2036{
2037 struct usb_request *req = hsotg->ctrl_req;
2038 struct dwc2_hsotg_req *hs_req = our_req(req);
2039 int ret;
2040
2041 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2042
2043 req->zero = 0;
2044 req->length = 8;
2045 req->buf = hsotg->ctrl_buff;
2046 req->complete = dwc2_hsotg_complete_setup;
2047
2048 if (!list_empty(&hs_req->queue)) {
2049 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2050 return;
2051 }
2052
2053 hsotg->eps_out[0]->dir_in = 0;
2054 hsotg->eps_out[0]->send_zlp = 0;
2055 hsotg->ep0_state = DWC2_EP0_SETUP;
2056
2057 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2058 if (ret < 0) {
2059 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2060 /*
2061 * Don't think there's much we can do other than watch the
2062 * driver fail.
2063 */
2064 }
2065}
2066
2067static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2068 struct dwc2_hsotg_ep *hs_ep)
2069{
2070 u32 ctrl;
2071 u8 index = hs_ep->index;
2072 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2073 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2074
2075 if (hs_ep->dir_in)
2076 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2077 index);
2078 else
2079 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2080 index);
2081 if (using_desc_dma(hsotg)) {
2082 /* Not specific buffer needed for ep0 ZLP */
2083 dma_addr_t dma = hs_ep->desc_list_dma;
2084
2085 if (!index)
2086 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2087
2088 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2089 } else {
2090 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2091 DXEPTSIZ_XFERSIZE(0),
2092 epsiz_reg);
2093 }
2094
2095 ctrl = dwc2_readl(hsotg, epctl_reg);
2096 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2097 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2098 ctrl |= DXEPCTL_USBACTEP;
2099 dwc2_writel(hsotg, ctrl, epctl_reg);
2100}
2101
2102/**
2103 * dwc2_hsotg_complete_request - complete a request given to us
2104 * @hsotg: The device state.
2105 * @hs_ep: The endpoint the request was on.
2106 * @hs_req: The request to complete.
2107 * @result: The result code (0 => Ok, otherwise errno)
2108 *
2109 * The given request has finished, so call the necessary completion
2110 * if it has one and then look to see if we can start a new request
2111 * on the endpoint.
2112 *
2113 * Note, expects the ep to already be locked as appropriate.
2114 */
2115static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2116 struct dwc2_hsotg_ep *hs_ep,
2117 struct dwc2_hsotg_req *hs_req,
2118 int result)
2119{
2120 if (!hs_req) {
2121 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2122 return;
2123 }
2124
2125 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2126 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2127
2128 /*
2129 * only replace the status if we've not already set an error
2130 * from a previous transaction
2131 */
2132
2133 if (hs_req->req.status == -EINPROGRESS)
2134 hs_req->req.status = result;
2135
2136 if (using_dma(hsotg))
2137 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2138
2139 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2140
2141 hs_ep->req = NULL;
2142 list_del_init(&hs_req->queue);
2143
2144 /*
2145 * call the complete request with the locks off, just in case the
2146 * request tries to queue more work for this endpoint.
2147 */
2148
2149 if (hs_req->req.complete) {
2150 spin_unlock(&hsotg->lock);
2151 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2152 spin_lock(&hsotg->lock);
2153 }
2154
2155 /* In DDMA don't need to proceed to starting of next ISOC request */
2156 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2157 return;
2158
2159 /*
2160 * Look to see if there is anything else to do. Note, the completion
2161 * of the previous request may have caused a new request to be started
2162 * so be careful when doing this.
2163 */
2164
2165 if (!hs_ep->req && result >= 0)
2166 dwc2_gadget_start_next_request(hs_ep);
2167}
2168
2169/*
2170 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2171 * @hs_ep: The endpoint the request was on.
2172 *
2173 * Get first request from the ep queue, determine descriptor on which complete
2174 * happened. SW discovers which descriptor currently in use by HW, adjusts
2175 * dma_address and calculates index of completed descriptor based on the value
2176 * of DEPDMA register. Update actual length of request, giveback to gadget.
2177 */
2178static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2179{
2180 struct dwc2_hsotg *hsotg = hs_ep->parent;
2181 struct dwc2_hsotg_req *hs_req;
2182 struct usb_request *ureq;
2183 u32 desc_sts;
2184 u32 mask;
2185
2186 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2187
2188 /* Process only descriptors with buffer status set to DMA done */
2189 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2190 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2191
2192 hs_req = get_ep_head(hs_ep);
2193 if (!hs_req) {
2194 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2195 return;
2196 }
2197 ureq = &hs_req->req;
2198
2199 /* Check completion status */
2200 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2201 DEV_DMA_STS_SUCC) {
2202 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2203 DEV_DMA_ISOC_RX_NBYTES_MASK;
2204 ureq->actual = ureq->length - ((desc_sts & mask) >>
2205 DEV_DMA_ISOC_NBYTES_SHIFT);
2206
2207 /* Adjust actual len for ISOC Out if len is
2208 * not align of 4
2209 */
2210 if (!hs_ep->dir_in && ureq->length & 0x3)
2211 ureq->actual += 4 - (ureq->length & 0x3);
2212
2213 /* Set actual frame number for completed transfers */
2214 ureq->frame_number =
2215 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2216 DEV_DMA_ISOC_FRNUM_SHIFT;
2217 }
2218
2219 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2220
2221 hs_ep->compl_desc++;
2222 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2223 hs_ep->compl_desc = 0;
2224 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2225 }
2226}
2227
2228/*
2229 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2230 * @hs_ep: The isochronous endpoint.
2231 *
2232 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2233 * interrupt. Reset target frame and next_desc to allow to start
2234 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2235 * interrupt for OUT direction.
2236 */
2237static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2238{
2239 struct dwc2_hsotg *hsotg = hs_ep->parent;
2240
2241 if (!hs_ep->dir_in)
2242 dwc2_flush_rx_fifo(hsotg);
2243 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2244
2245 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2246 hs_ep->next_desc = 0;
2247 hs_ep->compl_desc = 0;
2248}
2249
2250/**
2251 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2252 * @hsotg: The device state.
2253 * @ep_idx: The endpoint index for the data
2254 * @size: The size of data in the fifo, in bytes
2255 *
2256 * The FIFO status shows there is data to read from the FIFO for a given
2257 * endpoint, so sort out whether we need to read the data into a request
2258 * that has been made for that endpoint.
2259 */
2260static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2261{
2262 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2263 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2264 int to_read;
2265 int max_req;
2266 int read_ptr;
2267
2268 if (!hs_req) {
2269 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2270 int ptr;
2271
2272 dev_dbg(hsotg->dev,
2273 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2274 __func__, size, ep_idx, epctl);
2275
2276 /* dump the data from the FIFO, we've nothing we can do */
2277 for (ptr = 0; ptr < size; ptr += 4)
2278 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2279
2280 return;
2281 }
2282
2283 to_read = size;
2284 read_ptr = hs_req->req.actual;
2285 max_req = hs_req->req.length - read_ptr;
2286
2287 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2288 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2289
2290 if (to_read > max_req) {
2291 /*
2292 * more data appeared than we where willing
2293 * to deal with in this request.
2294 */
2295
2296 /* currently we don't deal this */
2297 WARN_ON_ONCE(1);
2298 }
2299
2300 hs_ep->total_data += to_read;
2301 hs_req->req.actual += to_read;
2302 to_read = DIV_ROUND_UP(to_read, 4);
2303
2304 /*
2305 * note, we might over-write the buffer end by 3 bytes depending on
2306 * alignment of the data.
2307 */
2308 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2309 hs_req->req.buf + read_ptr, to_read);
2310}
2311
2312/**
2313 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2314 * @hsotg: The device instance
2315 * @dir_in: If IN zlp
2316 *
2317 * Generate a zero-length IN packet request for terminating a SETUP
2318 * transaction.
2319 *
2320 * Note, since we don't write any data to the TxFIFO, then it is
2321 * currently believed that we do not need to wait for any space in
2322 * the TxFIFO.
2323 */
2324static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2325{
2326 /* eps_out[0] is used in both directions */
2327 hsotg->eps_out[0]->dir_in = dir_in;
2328 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2329
2330 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2331}
2332
2333/*
2334 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2335 * @hs_ep - The endpoint on which transfer went
2336 *
2337 * Iterate over endpoints descriptor chain and get info on bytes remained
2338 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2339 */
2340static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2341{
2342 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2343 struct dwc2_hsotg *hsotg = hs_ep->parent;
2344 unsigned int bytes_rem = 0;
2345 unsigned int bytes_rem_correction = 0;
2346 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2347 int i;
2348 u32 status;
2349 u32 mps = hs_ep->ep.maxpacket;
2350 int dir_in = hs_ep->dir_in;
2351
2352 if (!desc)
2353 return -EINVAL;
2354
2355 /* Interrupt OUT EP with mps not multiple of 4 */
2356 if (hs_ep->index)
2357 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2358 bytes_rem_correction = 4 - (mps % 4);
2359
2360 for (i = 0; i < hs_ep->desc_count; ++i) {
2361 status = desc->status;
2362 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2363 bytes_rem -= bytes_rem_correction;
2364
2365 if (status & DEV_DMA_STS_MASK)
2366 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2367 i, status & DEV_DMA_STS_MASK);
2368
2369 if (status & DEV_DMA_L)
2370 break;
2371
2372 desc++;
2373 }
2374
2375 return bytes_rem;
2376}
2377
2378/**
2379 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2380 * @hsotg: The device instance
2381 * @epnum: The endpoint received from
2382 *
2383 * The RXFIFO has delivered an OutDone event, which means that the data
2384 * transfer for an OUT endpoint has been completed, either by a short
2385 * packet or by the finish of a transfer.
2386 */
2387static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2388{
2389 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2390 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2391 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2392 struct usb_request *req = &hs_req->req;
2393 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2394 int result = 0;
2395
2396 if (!hs_req) {
2397 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2398 return;
2399 }
2400
2401 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2402 dev_dbg(hsotg->dev, "zlp packet received\n");
2403 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2404 dwc2_hsotg_enqueue_setup(hsotg);
2405 return;
2406 }
2407
2408 if (using_desc_dma(hsotg))
2409 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2410
2411 if (using_dma(hsotg)) {
2412 unsigned int size_done;
2413
2414 /*
2415 * Calculate the size of the transfer by checking how much
2416 * is left in the endpoint size register and then working it
2417 * out from the amount we loaded for the transfer.
2418 *
2419 * We need to do this as DMA pointers are always 32bit aligned
2420 * so may overshoot/undershoot the transfer.
2421 */
2422
2423 size_done = hs_ep->size_loaded - size_left;
2424 size_done += hs_ep->last_load;
2425
2426 req->actual = size_done;
2427 }
2428
2429 /* if there is more request to do, schedule new transfer */
2430 if (req->actual < req->length && size_left == 0) {
2431 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2432 return;
2433 }
2434
2435 if (req->actual < req->length && req->short_not_ok) {
2436 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2437 __func__, req->actual, req->length);
2438
2439 /*
2440 * todo - what should we return here? there's no one else
2441 * even bothering to check the status.
2442 */
2443 }
2444
2445 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2446 if (!using_desc_dma(hsotg) && epnum == 0 &&
2447 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2448 /* Move to STATUS IN */
2449 if (!hsotg->delayed_status)
2450 dwc2_hsotg_ep0_zlp(hsotg, true);
2451 }
2452
2453 /* Set actual frame number for completed transfers */
2454 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2455 req->frame_number = hs_ep->target_frame;
2456 dwc2_gadget_incr_frame_num(hs_ep);
2457 }
2458
2459 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2460}
2461
2462/**
2463 * dwc2_hsotg_handle_rx - RX FIFO has data
2464 * @hsotg: The device instance
2465 *
2466 * The IRQ handler has detected that the RX FIFO has some data in it
2467 * that requires processing, so find out what is in there and do the
2468 * appropriate read.
2469 *
2470 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2471 * chunks, so if you have x packets received on an endpoint you'll get x
2472 * FIFO events delivered, each with a packet's worth of data in it.
2473 *
2474 * When using DMA, we should not be processing events from the RXFIFO
2475 * as the actual data should be sent to the memory directly and we turn
2476 * on the completion interrupts to get notifications of transfer completion.
2477 */
2478static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2479{
2480 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2481 u32 epnum, status, size;
2482
2483 WARN_ON(using_dma(hsotg));
2484
2485 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2486 status = grxstsr & GRXSTS_PKTSTS_MASK;
2487
2488 size = grxstsr & GRXSTS_BYTECNT_MASK;
2489 size >>= GRXSTS_BYTECNT_SHIFT;
2490
2491 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2492 __func__, grxstsr, size, epnum);
2493
2494 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2495 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2496 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2497 break;
2498
2499 case GRXSTS_PKTSTS_OUTDONE:
2500 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2501 dwc2_hsotg_read_frameno(hsotg));
2502
2503 if (!using_dma(hsotg))
2504 dwc2_hsotg_handle_outdone(hsotg, epnum);
2505 break;
2506
2507 case GRXSTS_PKTSTS_SETUPDONE:
2508 dev_dbg(hsotg->dev,
2509 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2510 dwc2_hsotg_read_frameno(hsotg),
2511 dwc2_readl(hsotg, DOEPCTL(0)));
2512 /*
2513 * Call dwc2_hsotg_handle_outdone here if it was not called from
2514 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2515 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2516 */
2517 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2518 dwc2_hsotg_handle_outdone(hsotg, epnum);
2519 break;
2520
2521 case GRXSTS_PKTSTS_OUTRX:
2522 dwc2_hsotg_rx_data(hsotg, epnum, size);
2523 break;
2524
2525 case GRXSTS_PKTSTS_SETUPRX:
2526 dev_dbg(hsotg->dev,
2527 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2528 dwc2_hsotg_read_frameno(hsotg),
2529 dwc2_readl(hsotg, DOEPCTL(0)));
2530
2531 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2532
2533 dwc2_hsotg_rx_data(hsotg, epnum, size);
2534 break;
2535
2536 default:
2537 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2538 __func__, grxstsr);
2539
2540 dwc2_hsotg_dump(hsotg);
2541 break;
2542 }
2543}
2544
2545/**
2546 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2547 * @mps: The maximum packet size in bytes.
2548 */
2549static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2550{
2551 switch (mps) {
2552 case 64:
2553 return D0EPCTL_MPS_64;
2554 case 32:
2555 return D0EPCTL_MPS_32;
2556 case 16:
2557 return D0EPCTL_MPS_16;
2558 case 8:
2559 return D0EPCTL_MPS_8;
2560 }
2561
2562 /* bad max packet size, warn and return invalid result */
2563 WARN_ON(1);
2564 return (u32)-1;
2565}
2566
2567/**
2568 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2569 * @hsotg: The driver state.
2570 * @ep: The index number of the endpoint
2571 * @mps: The maximum packet size in bytes
2572 * @mc: The multicount value
2573 * @dir_in: True if direction is in.
2574 *
2575 * Configure the maximum packet size for the given endpoint, updating
2576 * the hardware control registers to reflect this.
2577 */
2578static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2579 unsigned int ep, unsigned int mps,
2580 unsigned int mc, unsigned int dir_in)
2581{
2582 struct dwc2_hsotg_ep *hs_ep;
2583 u32 reg;
2584
2585 hs_ep = index_to_ep(hsotg, ep, dir_in);
2586 if (!hs_ep)
2587 return;
2588
2589 if (ep == 0) {
2590 u32 mps_bytes = mps;
2591
2592 /* EP0 is a special case */
2593 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2594 if (mps > 3)
2595 goto bad_mps;
2596 hs_ep->ep.maxpacket = mps_bytes;
2597 hs_ep->mc = 1;
2598 } else {
2599 if (mps > 1024)
2600 goto bad_mps;
2601 hs_ep->mc = mc;
2602 if (mc > 3)
2603 goto bad_mps;
2604 hs_ep->ep.maxpacket = mps;
2605 }
2606
2607 if (dir_in) {
2608 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2609 reg &= ~DXEPCTL_MPS_MASK;
2610 reg |= mps;
2611 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2612 } else {
2613 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2614 reg &= ~DXEPCTL_MPS_MASK;
2615 reg |= mps;
2616 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2617 }
2618
2619 return;
2620
2621bad_mps:
2622 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2623}
2624
2625/**
2626 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2627 * @hsotg: The driver state
2628 * @idx: The index for the endpoint (0..15)
2629 */
2630static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2631{
2632 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2633 GRSTCTL);
2634
2635 /* wait until the fifo is flushed */
2636 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2637 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2638 __func__);
2639}
2640
2641/**
2642 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2643 * @hsotg: The driver state
2644 * @hs_ep: The driver endpoint to check.
2645 *
2646 * Check to see if there is a request that has data to send, and if so
2647 * make an attempt to write data into the FIFO.
2648 */
2649static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2650 struct dwc2_hsotg_ep *hs_ep)
2651{
2652 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2653
2654 if (!hs_ep->dir_in || !hs_req) {
2655 /**
2656 * if request is not enqueued, we disable interrupts
2657 * for endpoints, excepting ep0
2658 */
2659 if (hs_ep->index != 0)
2660 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2661 hs_ep->dir_in, 0);
2662 return 0;
2663 }
2664
2665 if (hs_req->req.actual < hs_req->req.length) {
2666 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2667 hs_ep->index);
2668 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2669 }
2670
2671 return 0;
2672}
2673
2674/**
2675 * dwc2_hsotg_complete_in - complete IN transfer
2676 * @hsotg: The device state.
2677 * @hs_ep: The endpoint that has just completed.
2678 *
2679 * An IN transfer has been completed, update the transfer's state and then
2680 * call the relevant completion routines.
2681 */
2682static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2683 struct dwc2_hsotg_ep *hs_ep)
2684{
2685 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2686 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2687 int size_left, size_done;
2688
2689 if (!hs_req) {
2690 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2691 return;
2692 }
2693
2694 /* Finish ZLP handling for IN EP0 transactions */
2695 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2696 dev_dbg(hsotg->dev, "zlp packet sent\n");
2697
2698 /*
2699 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2700 * changed to IN. Change back to complete OUT transfer request
2701 */
2702 hs_ep->dir_in = 0;
2703
2704 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2705 if (hsotg->test_mode) {
2706 int ret;
2707
2708 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2709 if (ret < 0) {
2710 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2711 hsotg->test_mode);
2712 dwc2_hsotg_stall_ep0(hsotg);
2713 return;
2714 }
2715 }
2716 dwc2_hsotg_enqueue_setup(hsotg);
2717 return;
2718 }
2719
2720 /*
2721 * Calculate the size of the transfer by checking how much is left
2722 * in the endpoint size register and then working it out from
2723 * the amount we loaded for the transfer.
2724 *
2725 * We do this even for DMA, as the transfer may have incremented
2726 * past the end of the buffer (DMA transfers are always 32bit
2727 * aligned).
2728 */
2729 if (using_desc_dma(hsotg)) {
2730 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2731 if (size_left < 0)
2732 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2733 size_left);
2734 } else {
2735 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2736 }
2737
2738 size_done = hs_ep->size_loaded - size_left;
2739 size_done += hs_ep->last_load;
2740
2741 if (hs_req->req.actual != size_done)
2742 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2743 __func__, hs_req->req.actual, size_done);
2744
2745 hs_req->req.actual = size_done;
2746 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2747 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2748
2749 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2750 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2752 return;
2753 }
2754
2755 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2756 if (hs_ep->send_zlp) {
2757 hs_ep->send_zlp = 0;
2758 if (!using_desc_dma(hsotg)) {
2759 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2760 /* transfer will be completed on next complete interrupt */
2761 return;
2762 }
2763 }
2764
2765 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2766 /* Move to STATUS OUT */
2767 dwc2_hsotg_ep0_zlp(hsotg, false);
2768 return;
2769 }
2770
2771 /* Set actual frame number for completed transfers */
2772 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2773 hs_req->req.frame_number = hs_ep->target_frame;
2774 dwc2_gadget_incr_frame_num(hs_ep);
2775 }
2776
2777 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2778}
2779
2780/**
2781 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2782 * @hsotg: The device state.
2783 * @idx: Index of ep.
2784 * @dir_in: Endpoint direction 1-in 0-out.
2785 *
2786 * Reads for endpoint with given index and direction, by masking
2787 * epint_reg with coresponding mask.
2788 */
2789static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2790 unsigned int idx, int dir_in)
2791{
2792 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2793 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2794 u32 ints;
2795 u32 mask;
2796 u32 diepempmsk;
2797
2798 mask = dwc2_readl(hsotg, epmsk_reg);
2799 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2800 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2801 mask |= DXEPINT_SETUP_RCVD;
2802
2803 ints = dwc2_readl(hsotg, epint_reg);
2804 ints &= mask;
2805 return ints;
2806}
2807
2808/**
2809 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2810 * @hs_ep: The endpoint on which interrupt is asserted.
2811 *
2812 * This interrupt indicates that the endpoint has been disabled per the
2813 * application's request.
2814 *
2815 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2816 * in case of ISOC completes current request.
2817 *
2818 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2819 * request starts it.
2820 */
2821static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2822{
2823 struct dwc2_hsotg *hsotg = hs_ep->parent;
2824 struct dwc2_hsotg_req *hs_req;
2825 unsigned char idx = hs_ep->index;
2826 int dir_in = hs_ep->dir_in;
2827 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2828 int dctl = dwc2_readl(hsotg, DCTL);
2829
2830 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2831
2832 if (dir_in) {
2833 int epctl = dwc2_readl(hsotg, epctl_reg);
2834
2835 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2836
2837 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2838 int dctl = dwc2_readl(hsotg, DCTL);
2839
2840 dctl |= DCTL_CGNPINNAK;
2841 dwc2_writel(hsotg, dctl, DCTL);
2842 }
2843 } else {
2844
2845 if (dctl & DCTL_GOUTNAKSTS) {
2846 dctl |= DCTL_CGOUTNAK;
2847 dwc2_writel(hsotg, dctl, DCTL);
2848 }
2849 }
2850
2851 if (!hs_ep->isochronous)
2852 return;
2853
2854 if (list_empty(&hs_ep->queue)) {
2855 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2856 __func__, hs_ep);
2857 return;
2858 }
2859
2860 do {
2861 hs_req = get_ep_head(hs_ep);
2862 if (hs_req) {
2863 hs_req->req.frame_number = hs_ep->target_frame;
2864 hs_req->req.actual = 0;
2865 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2866 -ENODATA);
2867 }
2868 dwc2_gadget_incr_frame_num(hs_ep);
2869 /* Update current frame number value. */
2870 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2871 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2872}
2873
2874/**
2875 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2876 * @ep: The endpoint on which interrupt is asserted.
2877 *
2878 * This is starting point for ISOC-OUT transfer, synchronization done with
2879 * first out token received from host while corresponding EP is disabled.
2880 *
2881 * Device does not know initial frame in which out token will come. For this
2882 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2883 * getting this interrupt SW starts calculation for next transfer frame.
2884 */
2885static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2886{
2887 struct dwc2_hsotg *hsotg = ep->parent;
2888 struct dwc2_hsotg_req *hs_req;
2889 int dir_in = ep->dir_in;
2890
2891 if (dir_in || !ep->isochronous)
2892 return;
2893
2894 if (using_desc_dma(hsotg)) {
2895 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2896 /* Start first ISO Out */
2897 ep->target_frame = hsotg->frame_number;
2898 dwc2_gadget_start_isoc_ddma(ep);
2899 }
2900 return;
2901 }
2902
2903 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2904 u32 ctrl;
2905
2906 ep->target_frame = hsotg->frame_number;
2907 if (ep->interval > 1) {
2908 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2909 if (ep->target_frame & 0x1)
2910 ctrl |= DXEPCTL_SETODDFR;
2911 else
2912 ctrl |= DXEPCTL_SETEVENFR;
2913
2914 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2915 }
2916 }
2917
2918 while (dwc2_gadget_target_frame_elapsed(ep)) {
2919 hs_req = get_ep_head(ep);
2920 if (hs_req) {
2921 hs_req->req.frame_number = ep->target_frame;
2922 hs_req->req.actual = 0;
2923 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2924 }
2925
2926 dwc2_gadget_incr_frame_num(ep);
2927 /* Update current frame number value. */
2928 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2929 }
2930
2931 if (!ep->req)
2932 dwc2_gadget_start_next_request(ep);
2933
2934}
2935
2936static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2937 struct dwc2_hsotg_ep *hs_ep);
2938
2939/**
2940 * dwc2_gadget_handle_nak - handle NAK interrupt
2941 * @hs_ep: The endpoint on which interrupt is asserted.
2942 *
2943 * This is starting point for ISOC-IN transfer, synchronization done with
2944 * first IN token received from host while corresponding EP is disabled.
2945 *
2946 * Device does not know when first one token will arrive from host. On first
2947 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2948 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2949 * sent in response to that as there was no data in FIFO. SW is basing on this
2950 * interrupt to obtain frame in which token has come and then based on the
2951 * interval calculates next frame for transfer.
2952 */
2953static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2954{
2955 struct dwc2_hsotg *hsotg = hs_ep->parent;
2956 struct dwc2_hsotg_req *hs_req;
2957 int dir_in = hs_ep->dir_in;
2958 u32 ctrl;
2959
2960 if (!dir_in || !hs_ep->isochronous)
2961 return;
2962
2963 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2964
2965 if (using_desc_dma(hsotg)) {
2966 hs_ep->target_frame = hsotg->frame_number;
2967 dwc2_gadget_incr_frame_num(hs_ep);
2968
2969 /* In service interval mode target_frame must
2970 * be set to last (u)frame of the service interval.
2971 */
2972 if (hsotg->params.service_interval) {
2973 /* Set target_frame to the first (u)frame of
2974 * the service interval
2975 */
2976 hs_ep->target_frame &= ~hs_ep->interval + 1;
2977
2978 /* Set target_frame to the last (u)frame of
2979 * the service interval
2980 */
2981 dwc2_gadget_incr_frame_num(hs_ep);
2982 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2983 }
2984
2985 dwc2_gadget_start_isoc_ddma(hs_ep);
2986 return;
2987 }
2988
2989 hs_ep->target_frame = hsotg->frame_number;
2990 if (hs_ep->interval > 1) {
2991 u32 ctrl = dwc2_readl(hsotg,
2992 DIEPCTL(hs_ep->index));
2993 if (hs_ep->target_frame & 0x1)
2994 ctrl |= DXEPCTL_SETODDFR;
2995 else
2996 ctrl |= DXEPCTL_SETEVENFR;
2997
2998 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2999 }
3000 }
3001
3002 if (using_desc_dma(hsotg))
3003 return;
3004
3005 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3006 if (ctrl & DXEPCTL_EPENA)
3007 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3008 else
3009 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3010
3011 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3012 hs_req = get_ep_head(hs_ep);
3013 if (hs_req) {
3014 hs_req->req.frame_number = hs_ep->target_frame;
3015 hs_req->req.actual = 0;
3016 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3017 }
3018
3019 dwc2_gadget_incr_frame_num(hs_ep);
3020 /* Update current frame number value. */
3021 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3022 }
3023
3024 if (!hs_ep->req)
3025 dwc2_gadget_start_next_request(hs_ep);
3026}
3027
3028/**
3029 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3030 * @hsotg: The driver state
3031 * @idx: The index for the endpoint (0..15)
3032 * @dir_in: Set if this is an IN endpoint
3033 *
3034 * Process and clear any interrupt pending for an individual endpoint
3035 */
3036static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3037 int dir_in)
3038{
3039 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3040 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3041 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3042 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3043 u32 ints;
3044
3045 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3046
3047 /* Clear endpoint interrupts */
3048 dwc2_writel(hsotg, ints, epint_reg);
3049
3050 if (!hs_ep) {
3051 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3052 __func__, idx, dir_in ? "in" : "out");
3053 return;
3054 }
3055
3056 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3057 __func__, idx, dir_in ? "in" : "out", ints);
3058
3059 /* Don't process XferCompl interrupt if it is a setup packet */
3060 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3061 ints &= ~DXEPINT_XFERCOMPL;
3062
3063 /*
3064 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3065 * stage and xfercomplete was generated without SETUP phase done
3066 * interrupt. SW should parse received setup packet only after host's
3067 * exit from setup phase of control transfer.
3068 */
3069 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3070 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3071 ints &= ~DXEPINT_XFERCOMPL;
3072
3073 if (ints & DXEPINT_XFERCOMPL) {
3074 dev_dbg(hsotg->dev,
3075 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3076 __func__, dwc2_readl(hsotg, epctl_reg),
3077 dwc2_readl(hsotg, epsiz_reg));
3078
3079 /* In DDMA handle isochronous requests separately */
3080 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3081 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3082 } else if (dir_in) {
3083 /*
3084 * We get OutDone from the FIFO, so we only
3085 * need to look at completing IN requests here
3086 * if operating slave mode
3087 */
3088 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3089 dwc2_hsotg_complete_in(hsotg, hs_ep);
3090
3091 if (idx == 0 && !hs_ep->req)
3092 dwc2_hsotg_enqueue_setup(hsotg);
3093 } else if (using_dma(hsotg)) {
3094 /*
3095 * We're using DMA, we need to fire an OutDone here
3096 * as we ignore the RXFIFO.
3097 */
3098 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3099 dwc2_hsotg_handle_outdone(hsotg, idx);
3100 }
3101 }
3102
3103 if (ints & DXEPINT_EPDISBLD)
3104 dwc2_gadget_handle_ep_disabled(hs_ep);
3105
3106 if (ints & DXEPINT_OUTTKNEPDIS)
3107 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3108
3109 if (ints & DXEPINT_NAKINTRPT)
3110 dwc2_gadget_handle_nak(hs_ep);
3111
3112 if (ints & DXEPINT_AHBERR)
3113 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3114
3115 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3116 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3117
3118 if (using_dma(hsotg) && idx == 0) {
3119 /*
3120 * this is the notification we've received a
3121 * setup packet. In non-DMA mode we'd get this
3122 * from the RXFIFO, instead we need to process
3123 * the setup here.
3124 */
3125
3126 if (dir_in)
3127 WARN_ON_ONCE(1);
3128 else
3129 dwc2_hsotg_handle_outdone(hsotg, 0);
3130 }
3131 }
3132
3133 if (ints & DXEPINT_STSPHSERCVD) {
3134 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3135
3136 /* Safety check EP0 state when STSPHSERCVD asserted */
3137 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3138 /* Move to STATUS IN for DDMA */
3139 if (using_desc_dma(hsotg)) {
3140 if (!hsotg->delayed_status)
3141 dwc2_hsotg_ep0_zlp(hsotg, true);
3142 else
3143 /* In case of 3 stage Control Write with delayed
3144 * status, when Status IN transfer started
3145 * before STSPHSERCVD asserted, NAKSTS bit not
3146 * cleared by CNAK in dwc2_hsotg_start_req()
3147 * function. Clear now NAKSTS to allow complete
3148 * transfer.
3149 */
3150 dwc2_set_bit(hsotg, DIEPCTL(0),
3151 DXEPCTL_CNAK);
3152 }
3153 }
3154
3155 }
3156
3157 if (ints & DXEPINT_BACK2BACKSETUP)
3158 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3159
3160 if (ints & DXEPINT_BNAINTR) {
3161 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3162 if (hs_ep->isochronous)
3163 dwc2_gadget_handle_isoc_bna(hs_ep);
3164 }
3165
3166 if (dir_in && !hs_ep->isochronous) {
3167 /* not sure if this is important, but we'll clear it anyway */
3168 if (ints & DXEPINT_INTKNTXFEMP) {
3169 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3170 __func__, idx);
3171 }
3172
3173 /* this probably means something bad is happening */
3174 if (ints & DXEPINT_INTKNEPMIS) {
3175 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3176 __func__, idx);
3177 }
3178
3179 /* FIFO has space or is empty (see GAHBCFG) */
3180 if (hsotg->dedicated_fifos &&
3181 ints & DXEPINT_TXFEMP) {
3182 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3183 __func__, idx);
3184 if (!using_dma(hsotg))
3185 dwc2_hsotg_trytx(hsotg, hs_ep);
3186 }
3187 }
3188}
3189
3190/**
3191 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3192 * @hsotg: The device state.
3193 *
3194 * Handle updating the device settings after the enumeration phase has
3195 * been completed.
3196 */
3197static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3198{
3199 u32 dsts = dwc2_readl(hsotg, DSTS);
3200 int ep0_mps = 0, ep_mps = 8;
3201
3202 /*
3203 * This should signal the finish of the enumeration phase
3204 * of the USB handshaking, so we should now know what rate
3205 * we connected at.
3206 */
3207
3208 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3209
3210 /*
3211 * note, since we're limited by the size of transfer on EP0, and
3212 * it seems IN transfers must be a even number of packets we do
3213 * not advertise a 64byte MPS on EP0.
3214 */
3215
3216 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3217 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3218 case DSTS_ENUMSPD_FS:
3219 case DSTS_ENUMSPD_FS48:
3220 hsotg->gadget.speed = USB_SPEED_FULL;
3221 ep0_mps = EP0_MPS_LIMIT;
3222 ep_mps = 1023;
3223 break;
3224
3225 case DSTS_ENUMSPD_HS:
3226 hsotg->gadget.speed = USB_SPEED_HIGH;
3227 ep0_mps = EP0_MPS_LIMIT;
3228 ep_mps = 1024;
3229 break;
3230
3231 case DSTS_ENUMSPD_LS:
3232 hsotg->gadget.speed = USB_SPEED_LOW;
3233 ep0_mps = 8;
3234 ep_mps = 8;
3235 /*
3236 * note, we don't actually support LS in this driver at the
3237 * moment, and the documentation seems to imply that it isn't
3238 * supported by the PHYs on some of the devices.
3239 */
3240 break;
3241 }
3242 dev_info(hsotg->dev, "new device is %s\n",
3243 usb_speed_string(hsotg->gadget.speed));
3244
3245 /*
3246 * we should now know the maximum packet size for an
3247 * endpoint, so set the endpoints to a default value.
3248 */
3249
3250 if (ep0_mps) {
3251 int i;
3252 /* Initialize ep0 for both in and out directions */
3253 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3254 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3255 for (i = 1; i < hsotg->num_of_eps; i++) {
3256 if (hsotg->eps_in[i])
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3258 0, 1);
3259 if (hsotg->eps_out[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3261 0, 0);
3262 }
3263 }
3264
3265 /* ensure after enumeration our EP0 is active */
3266
3267 dwc2_hsotg_enqueue_setup(hsotg);
3268
3269 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3270 dwc2_readl(hsotg, DIEPCTL0),
3271 dwc2_readl(hsotg, DOEPCTL0));
3272}
3273
3274/**
3275 * kill_all_requests - remove all requests from the endpoint's queue
3276 * @hsotg: The device state.
3277 * @ep: The endpoint the requests may be on.
3278 * @result: The result code to use.
3279 *
3280 * Go through the requests on the given endpoint and mark them
3281 * completed with the given result code.
3282 */
3283static void kill_all_requests(struct dwc2_hsotg *hsotg,
3284 struct dwc2_hsotg_ep *ep,
3285 int result)
3286{
3287 unsigned int size;
3288
3289 ep->req = NULL;
3290
3291 while (!list_empty(&ep->queue)) {
3292 struct dwc2_hsotg_req *req = get_ep_head(ep);
3293
3294 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3295 }
3296
3297 if (!hsotg->dedicated_fifos)
3298 return;
3299 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3300 if (size < ep->fifo_size)
3301 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3302}
3303
3304/**
3305 * dwc2_hsotg_disconnect - disconnect service
3306 * @hsotg: The device state.
3307 *
3308 * The device has been disconnected. Remove all current
3309 * transactions and signal the gadget driver that this
3310 * has happened.
3311 */
3312void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3313{
3314 unsigned int ep;
3315
3316 if (!hsotg->connected)
3317 return;
3318
3319 hsotg->connected = 0;
3320 hsotg->test_mode = 0;
3321
3322 /* all endpoints should be shutdown */
3323 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3324 if (hsotg->eps_in[ep])
3325 kill_all_requests(hsotg, hsotg->eps_in[ep],
3326 -ESHUTDOWN);
3327 if (hsotg->eps_out[ep])
3328 kill_all_requests(hsotg, hsotg->eps_out[ep],
3329 -ESHUTDOWN);
3330 }
3331
3332 call_gadget(hsotg, disconnect);
3333 hsotg->lx_state = DWC2_L3;
3334
3335 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3336}
3337
3338/**
3339 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3340 * @hsotg: The device state:
3341 * @periodic: True if this is a periodic FIFO interrupt
3342 */
3343static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3344{
3345 struct dwc2_hsotg_ep *ep;
3346 int epno, ret;
3347
3348 /* look through for any more data to transmit */
3349 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3350 ep = index_to_ep(hsotg, epno, 1);
3351
3352 if (!ep)
3353 continue;
3354
3355 if (!ep->dir_in)
3356 continue;
3357
3358 if ((periodic && !ep->periodic) ||
3359 (!periodic && ep->periodic))
3360 continue;
3361
3362 ret = dwc2_hsotg_trytx(hsotg, ep);
3363 if (ret < 0)
3364 break;
3365 }
3366}
3367
3368/* IRQ flags which will trigger a retry around the IRQ loop */
3369#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3370 GINTSTS_PTXFEMP | \
3371 GINTSTS_RXFLVL)
3372
3373static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3374/**
3375 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3376 * @hsotg: The device state
3377 * @is_usb_reset: Usb resetting flag
3378 *
3379 * Issue a soft reset to the core, and await the core finishing it.
3380 */
3381void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3382 bool is_usb_reset)
3383{
3384 u32 intmsk;
3385 u32 val;
3386 u32 usbcfg;
3387 u32 dcfg = 0;
3388 int ep;
3389
3390 /* Kill any ep0 requests as controller will be reinitialized */
3391 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3392
3393 if (!is_usb_reset) {
3394 if (dwc2_core_reset(hsotg, true))
3395 return;
3396 } else {
3397 /* all endpoints should be shutdown */
3398 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3399 if (hsotg->eps_in[ep])
3400 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3401 if (hsotg->eps_out[ep])
3402 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3403 }
3404 }
3405
3406 /*
3407 * we must now enable ep0 ready for host detection and then
3408 * set configuration.
3409 */
3410
3411 /* keep other bits untouched (so e.g. forced modes are not lost) */
3412 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3413 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3414 usbcfg |= GUSBCFG_TOUTCAL(7);
3415
3416 /* remove the HNP/SRP and set the PHY */
3417 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3418 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3419
3420 dwc2_phy_init(hsotg, true);
3421
3422 dwc2_hsotg_init_fifo(hsotg);
3423
3424 if (!is_usb_reset)
3425 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3426
3427 dcfg |= DCFG_EPMISCNT(1);
3428
3429 switch (hsotg->params.speed) {
3430 case DWC2_SPEED_PARAM_LOW:
3431 dcfg |= DCFG_DEVSPD_LS;
3432 break;
3433 case DWC2_SPEED_PARAM_FULL:
3434 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3435 dcfg |= DCFG_DEVSPD_FS48;
3436 else
3437 dcfg |= DCFG_DEVSPD_FS;
3438 break;
3439 default:
3440 dcfg |= DCFG_DEVSPD_HS;
3441 }
3442
3443 if (hsotg->params.ipg_isoc_en)
3444 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3445
3446 dwc2_writel(hsotg, dcfg, DCFG);
3447
3448 /* Clear any pending OTG interrupts */
3449 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3450
3451 /* Clear any pending interrupts */
3452 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3453 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3454 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3455 GINTSTS_USBRST | GINTSTS_RESETDET |
3456 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3457 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3458 GINTSTS_LPMTRANRCVD;
3459
3460 if (!using_desc_dma(hsotg))
3461 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3462
3463 if (!hsotg->params.external_id_pin_ctl)
3464 intmsk |= GINTSTS_CONIDSTSCHNG;
3465
3466 dwc2_writel(hsotg, intmsk, GINTMSK);
3467
3468 if (using_dma(hsotg)) {
3469 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3470 hsotg->params.ahbcfg,
3471 GAHBCFG);
3472
3473 /* Set DDMA mode support in the core if needed */
3474 if (using_desc_dma(hsotg))
3475 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3476
3477 } else {
3478 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3479 (GAHBCFG_NP_TXF_EMP_LVL |
3480 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3481 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3482 }
3483
3484 /*
3485 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3486 * when we have no data to transfer. Otherwise we get being flooded by
3487 * interrupts.
3488 */
3489
3490 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3491 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3492 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3493 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3494 DIEPMSK);
3495
3496 /*
3497 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3498 * DMA mode we may need this and StsPhseRcvd.
3499 */
3500 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3501 DOEPMSK_STSPHSERCVDMSK) : 0) |
3502 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3503 DOEPMSK_SETUPMSK,
3504 DOEPMSK);
3505
3506 /* Enable BNA interrupt for DDMA */
3507 if (using_desc_dma(hsotg)) {
3508 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3509 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3510 }
3511
3512 /* Enable Service Interval mode if supported */
3513 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3514 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3515
3516 dwc2_writel(hsotg, 0, DAINTMSK);
3517
3518 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3519 dwc2_readl(hsotg, DIEPCTL0),
3520 dwc2_readl(hsotg, DOEPCTL0));
3521
3522 /* enable in and out endpoint interrupts */
3523 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3524
3525 /*
3526 * Enable the RXFIFO when in slave mode, as this is how we collect
3527 * the data. In DMA mode, we get events from the FIFO but also
3528 * things we cannot process, so do not use it.
3529 */
3530 if (!using_dma(hsotg))
3531 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3532
3533 /* Enable interrupts for EP0 in and out */
3534 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3535 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3536
3537 if (!is_usb_reset) {
3538 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3539 udelay(10); /* see openiboot */
3540 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3541 }
3542
3543 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3544
3545 /*
3546 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3547 * writing to the EPCTL register..
3548 */
3549
3550 /* set to read 1 8byte packet */
3551 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3552 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3553
3554 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3555 DXEPCTL_CNAK | DXEPCTL_EPENA |
3556 DXEPCTL_USBACTEP,
3557 DOEPCTL0);
3558
3559 /* enable, but don't activate EP0in */
3560 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3561 DXEPCTL_USBACTEP, DIEPCTL0);
3562
3563 /* clear global NAKs */
3564 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3565 if (!is_usb_reset)
3566 val |= DCTL_SFTDISCON;
3567 dwc2_set_bit(hsotg, DCTL, val);
3568
3569 /* configure the core to support LPM */
3570 dwc2_gadget_init_lpm(hsotg);
3571
3572 /* program GREFCLK register if needed */
3573 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3574 dwc2_gadget_program_ref_clk(hsotg);
3575
3576 /* must be at-least 3ms to allow bus to see disconnect */
3577 mdelay(3);
3578
3579 hsotg->lx_state = DWC2_L0;
3580
3581 dwc2_hsotg_enqueue_setup(hsotg);
3582
3583 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3584 dwc2_readl(hsotg, DIEPCTL0),
3585 dwc2_readl(hsotg, DOEPCTL0));
3586}
3587
3588void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3589{
3590 /* set the soft-disconnect bit */
3591 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3592}
3593
3594void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3595{
3596 /* remove the soft-disconnect and let's go */
3597 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3598 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3599}
3600
3601/**
3602 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3603 * @hsotg: The device state:
3604 *
3605 * This interrupt indicates one of the following conditions occurred while
3606 * transmitting an ISOC transaction.
3607 * - Corrupted IN Token for ISOC EP.
3608 * - Packet not complete in FIFO.
3609 *
3610 * The following actions will be taken:
3611 * - Determine the EP
3612 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3613 */
3614static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3615{
3616 struct dwc2_hsotg_ep *hs_ep;
3617 u32 epctrl;
3618 u32 daintmsk;
3619 u32 idx;
3620
3621 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3622
3623 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3624
3625 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3626 hs_ep = hsotg->eps_in[idx];
3627 /* Proceed only unmasked ISOC EPs */
3628 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3629 continue;
3630
3631 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3632 if ((epctrl & DXEPCTL_EPENA) &&
3633 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3634 epctrl |= DXEPCTL_SNAK;
3635 epctrl |= DXEPCTL_EPDIS;
3636 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3637 }
3638 }
3639
3640 /* Clear interrupt */
3641 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3642}
3643
3644/**
3645 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3646 * @hsotg: The device state:
3647 *
3648 * This interrupt indicates one of the following conditions occurred while
3649 * transmitting an ISOC transaction.
3650 * - Corrupted OUT Token for ISOC EP.
3651 * - Packet not complete in FIFO.
3652 *
3653 * The following actions will be taken:
3654 * - Determine the EP
3655 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3656 */
3657static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3658{
3659 u32 gintsts;
3660 u32 gintmsk;
3661 u32 daintmsk;
3662 u32 epctrl;
3663 struct dwc2_hsotg_ep *hs_ep;
3664 int idx;
3665
3666 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3667
3668 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3669 daintmsk >>= DAINT_OUTEP_SHIFT;
3670
3671 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3672 hs_ep = hsotg->eps_out[idx];
3673 /* Proceed only unmasked ISOC EPs */
3674 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3675 continue;
3676
3677 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3678 if ((epctrl & DXEPCTL_EPENA) &&
3679 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3680 /* Unmask GOUTNAKEFF interrupt */
3681 gintmsk = dwc2_readl(hsotg, GINTMSK);
3682 gintmsk |= GINTSTS_GOUTNAKEFF;
3683 dwc2_writel(hsotg, gintmsk, GINTMSK);
3684
3685 gintsts = dwc2_readl(hsotg, GINTSTS);
3686 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3687 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3688 break;
3689 }
3690 }
3691 }
3692
3693 /* Clear interrupt */
3694 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3695}
3696
3697/**
3698 * dwc2_hsotg_irq - handle device interrupt
3699 * @irq: The IRQ number triggered
3700 * @pw: The pw value when registered the handler.
3701 */
3702static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3703{
3704 struct dwc2_hsotg *hsotg = pw;
3705 int retry_count = 8;
3706 u32 gintsts;
3707 u32 gintmsk;
3708
3709 if (!dwc2_is_device_mode(hsotg))
3710 return IRQ_NONE;
3711
3712 spin_lock(&hsotg->lock);
3713irq_retry:
3714 gintsts = dwc2_readl(hsotg, GINTSTS);
3715 gintmsk = dwc2_readl(hsotg, GINTMSK);
3716
3717 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3718 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3719
3720 gintsts &= gintmsk;
3721
3722 if (gintsts & GINTSTS_RESETDET) {
3723 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3724
3725 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3726
3727 /* This event must be used only if controller is suspended */
3728 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3729 dwc2_exit_partial_power_down(hsotg, 0, true);
3730
3731 hsotg->lx_state = DWC2_L0;
3732 }
3733
3734 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3735 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3736 u32 connected = hsotg->connected;
3737
3738 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3739 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3740 dwc2_readl(hsotg, GNPTXSTS));
3741
3742 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3743
3744 /* Report disconnection if it is not already done. */
3745 dwc2_hsotg_disconnect(hsotg);
3746
3747 /* Reset device address to zero */
3748 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3749
3750 if (usb_status & GOTGCTL_BSESVLD && connected)
3751 dwc2_hsotg_core_init_disconnected(hsotg, true);
3752 }
3753
3754 if (gintsts & GINTSTS_ENUMDONE) {
3755 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3756
3757 dwc2_hsotg_irq_enumdone(hsotg);
3758 }
3759
3760 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3761 u32 daint = dwc2_readl(hsotg, DAINT);
3762 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3763 u32 daint_out, daint_in;
3764 int ep;
3765
3766 daint &= daintmsk;
3767 daint_out = daint >> DAINT_OUTEP_SHIFT;
3768 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3769
3770 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3771
3772 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3773 ep++, daint_out >>= 1) {
3774 if (daint_out & 1)
3775 dwc2_hsotg_epint(hsotg, ep, 0);
3776 }
3777
3778 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3779 ep++, daint_in >>= 1) {
3780 if (daint_in & 1)
3781 dwc2_hsotg_epint(hsotg, ep, 1);
3782 }
3783 }
3784
3785 /* check both FIFOs */
3786
3787 if (gintsts & GINTSTS_NPTXFEMP) {
3788 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3789
3790 /*
3791 * Disable the interrupt to stop it happening again
3792 * unless one of these endpoint routines decides that
3793 * it needs re-enabling
3794 */
3795
3796 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3797 dwc2_hsotg_irq_fifoempty(hsotg, false);
3798 }
3799
3800 if (gintsts & GINTSTS_PTXFEMP) {
3801 dev_dbg(hsotg->dev, "PTxFEmp\n");
3802
3803 /* See note in GINTSTS_NPTxFEmp */
3804
3805 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3806 dwc2_hsotg_irq_fifoempty(hsotg, true);
3807 }
3808
3809 if (gintsts & GINTSTS_RXFLVL) {
3810 /*
3811 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3812 * we need to retry dwc2_hsotg_handle_rx if this is still
3813 * set.
3814 */
3815
3816 dwc2_hsotg_handle_rx(hsotg);
3817 }
3818
3819 if (gintsts & GINTSTS_ERLYSUSP) {
3820 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3821 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3822 }
3823
3824 /*
3825 * these next two seem to crop-up occasionally causing the core
3826 * to shutdown the USB transfer, so try clearing them and logging
3827 * the occurrence.
3828 */
3829
3830 if (gintsts & GINTSTS_GOUTNAKEFF) {
3831 u8 idx;
3832 u32 epctrl;
3833 u32 gintmsk;
3834 u32 daintmsk;
3835 struct dwc2_hsotg_ep *hs_ep;
3836
3837 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3838 daintmsk >>= DAINT_OUTEP_SHIFT;
3839 /* Mask this interrupt */
3840 gintmsk = dwc2_readl(hsotg, GINTMSK);
3841 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3842 dwc2_writel(hsotg, gintmsk, GINTMSK);
3843
3844 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3845 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3846 hs_ep = hsotg->eps_out[idx];
3847 /* Proceed only unmasked ISOC EPs */
3848 if (BIT(idx) & ~daintmsk)
3849 continue;
3850
3851 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3852
3853 //ISOC Ep's only
3854 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3855 epctrl |= DXEPCTL_SNAK;
3856 epctrl |= DXEPCTL_EPDIS;
3857 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3858 continue;
3859 }
3860
3861 //Non-ISOC EP's
3862 if (hs_ep->halted) {
3863 if (!(epctrl & DXEPCTL_EPENA))
3864 epctrl |= DXEPCTL_EPENA;
3865 epctrl |= DXEPCTL_EPDIS;
3866 epctrl |= DXEPCTL_STALL;
3867 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3868 }
3869 }
3870
3871 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3872 }
3873
3874 if (gintsts & GINTSTS_GINNAKEFF) {
3875 dev_info(hsotg->dev, "GINNakEff triggered\n");
3876
3877 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3878
3879 dwc2_hsotg_dump(hsotg);
3880 }
3881
3882 if (gintsts & GINTSTS_INCOMPL_SOIN)
3883 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3884
3885 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3886 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3887
3888 /*
3889 * if we've had fifo events, we should try and go around the
3890 * loop again to see if there's any point in returning yet.
3891 */
3892
3893 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3894 goto irq_retry;
3895
3896 /* Check WKUP_ALERT interrupt*/
3897 if (hsotg->params.service_interval)
3898 dwc2_gadget_wkup_alert_handler(hsotg);
3899
3900 spin_unlock(&hsotg->lock);
3901
3902 return IRQ_HANDLED;
3903}
3904
3905static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3906 struct dwc2_hsotg_ep *hs_ep)
3907{
3908 u32 epctrl_reg;
3909 u32 epint_reg;
3910
3911 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3912 DOEPCTL(hs_ep->index);
3913 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3914 DOEPINT(hs_ep->index);
3915
3916 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3917 hs_ep->name);
3918
3919 if (hs_ep->dir_in) {
3920 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3921 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3922 /* Wait for Nak effect */
3923 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3924 DXEPINT_INEPNAKEFF, 100))
3925 dev_warn(hsotg->dev,
3926 "%s: timeout DIEPINT.NAKEFF\n",
3927 __func__);
3928 } else {
3929 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3930 /* Wait for Nak effect */
3931 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3932 GINTSTS_GINNAKEFF, 100))
3933 dev_warn(hsotg->dev,
3934 "%s: timeout GINTSTS.GINNAKEFF\n",
3935 __func__);
3936 }
3937 } else {
3938 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3939 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3940
3941 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3942 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3943
3944 if (!using_dma(hsotg)) {
3945 /* Wait for GINTSTS_RXFLVL interrupt */
3946 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3947 GINTSTS_RXFLVL, 100)) {
3948 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3949 __func__);
3950 } else {
3951 /*
3952 * Pop GLOBAL OUT NAK status packet from RxFIFO
3953 * to assert GOUTNAKEFF interrupt
3954 */
3955 dwc2_readl(hsotg, GRXSTSP);
3956 }
3957 }
3958
3959 /* Wait for global nak to take effect */
3960 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3961 GINTSTS_GOUTNAKEFF, 100))
3962 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3963 __func__);
3964 }
3965
3966 /* Disable ep */
3967 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3968
3969 /* Wait for ep to be disabled */
3970 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3971 dev_warn(hsotg->dev,
3972 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3973
3974 /* Clear EPDISBLD interrupt */
3975 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3976
3977 if (hs_ep->dir_in) {
3978 unsigned short fifo_index;
3979
3980 if (hsotg->dedicated_fifos || hs_ep->periodic)
3981 fifo_index = hs_ep->fifo_index;
3982 else
3983 fifo_index = 0;
3984
3985 /* Flush TX FIFO */
3986 dwc2_flush_tx_fifo(hsotg, fifo_index);
3987
3988 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3989 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3990 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3991
3992 } else {
3993 /* Remove global NAKs */
3994 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3995 }
3996}
3997
3998/**
3999 * dwc2_hsotg_ep_enable - enable the given endpoint
4000 * @ep: The USB endpint to configure
4001 * @desc: The USB endpoint descriptor to configure with.
4002 *
4003 * This is called from the USB gadget code's usb_ep_enable().
4004 */
4005static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4006 const struct usb_endpoint_descriptor *desc)
4007{
4008 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4009 struct dwc2_hsotg *hsotg = hs_ep->parent;
4010 unsigned long flags;
4011 unsigned int index = hs_ep->index;
4012 u32 epctrl_reg;
4013 u32 epctrl;
4014 u32 mps;
4015 u32 mc;
4016 u32 mask;
4017 unsigned int dir_in;
4018 unsigned int i, val, size;
4019 int ret = 0;
4020 unsigned char ep_type;
4021 int desc_num;
4022
4023 dev_dbg(hsotg->dev,
4024 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4025 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4026 desc->wMaxPacketSize, desc->bInterval);
4027
4028 /* not to be called for EP0 */
4029 if (index == 0) {
4030 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4031 return -EINVAL;
4032 }
4033
4034 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4035 if (dir_in != hs_ep->dir_in) {
4036 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4037 return -EINVAL;
4038 }
4039
4040 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4041 mps = usb_endpoint_maxp(desc);
4042 mc = usb_endpoint_maxp_mult(desc);
4043
4044 /* ISOC IN in DDMA supported bInterval up to 10 */
4045 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4046 dir_in && desc->bInterval > 10) {
4047 dev_err(hsotg->dev,
4048 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4049 return -EINVAL;
4050 }
4051
4052 /* High bandwidth ISOC OUT in DDMA not supported */
4053 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4054 !dir_in && mc > 1) {
4055 dev_err(hsotg->dev,
4056 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4057 return -EINVAL;
4058 }
4059
4060 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4061
4062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4063 epctrl = dwc2_readl(hsotg, epctrl_reg);
4064
4065 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4066 __func__, epctrl, epctrl_reg);
4067
4068 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4069 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4070 else
4071 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4072
4073 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4074 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4075 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4076 desc_num * sizeof(struct dwc2_dma_desc),
4077 &hs_ep->desc_list_dma, GFP_ATOMIC);
4078 if (!hs_ep->desc_list) {
4079 ret = -ENOMEM;
4080 goto error2;
4081 }
4082 }
4083
4084 spin_lock_irqsave(&hsotg->lock, flags);
4085
4086 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4087 epctrl |= DXEPCTL_MPS(mps);
4088
4089 /*
4090 * mark the endpoint as active, otherwise the core may ignore
4091 * transactions entirely for this endpoint
4092 */
4093 epctrl |= DXEPCTL_USBACTEP;
4094
4095 /* update the endpoint state */
4096 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4097
4098 /* default, set to non-periodic */
4099 hs_ep->isochronous = 0;
4100 hs_ep->periodic = 0;
4101 hs_ep->halted = 0;
4102 hs_ep->wedged = 0;
4103 hs_ep->interval = desc->bInterval;
4104
4105 switch (ep_type) {
4106 case USB_ENDPOINT_XFER_ISOC:
4107 epctrl |= DXEPCTL_EPTYPE_ISO;
4108 epctrl |= DXEPCTL_SETEVENFR;
4109 hs_ep->isochronous = 1;
4110 hs_ep->interval = 1 << (desc->bInterval - 1);
4111 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4112 hs_ep->next_desc = 0;
4113 hs_ep->compl_desc = 0;
4114 if (dir_in) {
4115 hs_ep->periodic = 1;
4116 mask = dwc2_readl(hsotg, DIEPMSK);
4117 mask |= DIEPMSK_NAKMSK;
4118 dwc2_writel(hsotg, mask, DIEPMSK);
4119 } else {
4120 epctrl |= DXEPCTL_SNAK;
4121 mask = dwc2_readl(hsotg, DOEPMSK);
4122 mask |= DOEPMSK_OUTTKNEPDISMSK;
4123 dwc2_writel(hsotg, mask, DOEPMSK);
4124 }
4125 break;
4126
4127 case USB_ENDPOINT_XFER_BULK:
4128 epctrl |= DXEPCTL_EPTYPE_BULK;
4129 break;
4130
4131 case USB_ENDPOINT_XFER_INT:
4132 if (dir_in)
4133 hs_ep->periodic = 1;
4134
4135 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4136 hs_ep->interval = 1 << (desc->bInterval - 1);
4137
4138 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4139 break;
4140
4141 case USB_ENDPOINT_XFER_CONTROL:
4142 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4143 break;
4144 }
4145
4146 /*
4147 * if the hardware has dedicated fifos, we must give each IN EP
4148 * a unique tx-fifo even if it is non-periodic.
4149 */
4150 if (dir_in && hsotg->dedicated_fifos) {
4151 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4152 u32 fifo_index = 0;
4153 u32 fifo_size = UINT_MAX;
4154
4155 size = hs_ep->ep.maxpacket * hs_ep->mc;
4156 for (i = 1; i <= fifo_count; ++i) {
4157 if (hsotg->fifo_map & (1 << i))
4158 continue;
4159 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4160 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4161 if (val < size)
4162 continue;
4163 /* Search for smallest acceptable fifo */
4164 if (val < fifo_size) {
4165 fifo_size = val;
4166 fifo_index = i;
4167 }
4168 }
4169 if (!fifo_index) {
4170 dev_err(hsotg->dev,
4171 "%s: No suitable fifo found\n", __func__);
4172 ret = -ENOMEM;
4173 goto error1;
4174 }
4175 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4176 hsotg->fifo_map |= 1 << fifo_index;
4177 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4178 hs_ep->fifo_index = fifo_index;
4179 hs_ep->fifo_size = fifo_size;
4180 }
4181
4182 /* for non control endpoints, set PID to D0 */
4183 if (index && !hs_ep->isochronous)
4184 epctrl |= DXEPCTL_SETD0PID;
4185
4186 /* WA for Full speed ISOC IN in DDMA mode.
4187 * By Clear NAK status of EP, core will send ZLP
4188 * to IN token and assert NAK interrupt relying
4189 * on TxFIFO status only
4190 */
4191
4192 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4193 hs_ep->isochronous && dir_in) {
4194 /* The WA applies only to core versions from 2.72a
4195 * to 4.00a (including both). Also for FS_IOT_1.00a
4196 * and HS_IOT_1.00a.
4197 */
4198 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4199
4200 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4201 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4202 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4203 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4204 epctrl |= DXEPCTL_CNAK;
4205 }
4206
4207 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4208 __func__, epctrl);
4209
4210 dwc2_writel(hsotg, epctrl, epctrl_reg);
4211 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4212 __func__, dwc2_readl(hsotg, epctrl_reg));
4213
4214 /* enable the endpoint interrupt */
4215 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4216
4217error1:
4218 spin_unlock_irqrestore(&hsotg->lock, flags);
4219
4220error2:
4221 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4222 dmam_free_coherent(hsotg->dev, desc_num *
4223 sizeof(struct dwc2_dma_desc),
4224 hs_ep->desc_list, hs_ep->desc_list_dma);
4225 hs_ep->desc_list = NULL;
4226 }
4227
4228 return ret;
4229}
4230
4231/**
4232 * dwc2_hsotg_ep_disable - disable given endpoint
4233 * @ep: The endpoint to disable.
4234 */
4235static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4236{
4237 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4238 struct dwc2_hsotg *hsotg = hs_ep->parent;
4239 int dir_in = hs_ep->dir_in;
4240 int index = hs_ep->index;
4241 u32 epctrl_reg;
4242 u32 ctrl;
4243
4244 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4245
4246 if (ep == &hsotg->eps_out[0]->ep) {
4247 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4248 return -EINVAL;
4249 }
4250
4251 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4252 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4253 return -EINVAL;
4254 }
4255
4256 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4257
4258 ctrl = dwc2_readl(hsotg, epctrl_reg);
4259
4260 if (ctrl & DXEPCTL_EPENA)
4261 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4262
4263 ctrl &= ~DXEPCTL_EPENA;
4264 ctrl &= ~DXEPCTL_USBACTEP;
4265 ctrl |= DXEPCTL_SNAK;
4266
4267 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4268 dwc2_writel(hsotg, ctrl, epctrl_reg);
4269
4270 /* disable endpoint interrupts */
4271 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4272
4273 /* terminate all requests with shutdown */
4274 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4275
4276 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4277 hs_ep->fifo_index = 0;
4278 hs_ep->fifo_size = 0;
4279
4280 return 0;
4281}
4282
4283static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4284{
4285 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4286 struct dwc2_hsotg *hsotg = hs_ep->parent;
4287 unsigned long flags;
4288 int ret;
4289
4290 spin_lock_irqsave(&hsotg->lock, flags);
4291 ret = dwc2_hsotg_ep_disable(ep);
4292 spin_unlock_irqrestore(&hsotg->lock, flags);
4293 return ret;
4294}
4295
4296/**
4297 * on_list - check request is on the given endpoint
4298 * @ep: The endpoint to check.
4299 * @test: The request to test if it is on the endpoint.
4300 */
4301static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4302{
4303 struct dwc2_hsotg_req *req, *treq;
4304
4305 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4306 if (req == test)
4307 return true;
4308 }
4309
4310 return false;
4311}
4312
4313/**
4314 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4315 * @ep: The endpoint to dequeue.
4316 * @req: The request to be removed from a queue.
4317 */
4318static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4319{
4320 struct dwc2_hsotg_req *hs_req = our_req(req);
4321 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4322 struct dwc2_hsotg *hs = hs_ep->parent;
4323 unsigned long flags;
4324
4325 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4326
4327 spin_lock_irqsave(&hs->lock, flags);
4328
4329 if (!on_list(hs_ep, hs_req)) {
4330 spin_unlock_irqrestore(&hs->lock, flags);
4331 return -EINVAL;
4332 }
4333
4334 /* Dequeue already started request */
4335 if (req == &hs_ep->req->req)
4336 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4337
4338 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4339 spin_unlock_irqrestore(&hs->lock, flags);
4340
4341 return 0;
4342}
4343
4344/**
4345 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4346 * @ep: The endpoint to be wedged.
4347 *
4348 */
4349static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4350{
4351 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4352 struct dwc2_hsotg *hs = hs_ep->parent;
4353
4354 unsigned long flags;
4355 int ret;
4356
4357 spin_lock_irqsave(&hs->lock, flags);
4358 hs_ep->wedged = 1;
4359 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4360 spin_unlock_irqrestore(&hs->lock, flags);
4361
4362 return ret;
4363}
4364
4365/**
4366 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4367 * @ep: The endpoint to set halt.
4368 * @value: Set or unset the halt.
4369 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4370 * the endpoint is busy processing requests.
4371 *
4372 * We need to stall the endpoint immediately if request comes from set_feature
4373 * protocol command handler.
4374 */
4375static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4376{
4377 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4378 struct dwc2_hsotg *hs = hs_ep->parent;
4379 int index = hs_ep->index;
4380 u32 epreg;
4381 u32 epctl;
4382 u32 xfertype;
4383
4384 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4385
4386 if (index == 0) {
4387 if (value)
4388 dwc2_hsotg_stall_ep0(hs);
4389 else
4390 dev_warn(hs->dev,
4391 "%s: can't clear halt on ep0\n", __func__);
4392 return 0;
4393 }
4394
4395 if (hs_ep->isochronous) {
4396 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4397 return -EINVAL;
4398 }
4399
4400 if (!now && value && !list_empty(&hs_ep->queue)) {
4401 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4402 ep->name);
4403 return -EAGAIN;
4404 }
4405
4406 if (hs_ep->dir_in) {
4407 epreg = DIEPCTL(index);
4408 epctl = dwc2_readl(hs, epreg);
4409
4410 if (value) {
4411 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4412 if (epctl & DXEPCTL_EPENA)
4413 epctl |= DXEPCTL_EPDIS;
4414 } else {
4415 epctl &= ~DXEPCTL_STALL;
4416 hs_ep->wedged = 0;
4417 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4418 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4419 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4420 epctl |= DXEPCTL_SETD0PID;
4421 }
4422 dwc2_writel(hs, epctl, epreg);
4423 } else {
4424 epreg = DOEPCTL(index);
4425 epctl = dwc2_readl(hs, epreg);
4426
4427 if (value) {
4428 /* Unmask GOUTNAKEFF interrupt */
4429 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4430
4431 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4432 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4433 // STALL bit will be set in GOUTNAKEFF interrupt handler
4434 } else {
4435 epctl &= ~DXEPCTL_STALL;
4436 hs_ep->wedged = 0;
4437 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4438 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4439 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4440 epctl |= DXEPCTL_SETD0PID;
4441 dwc2_writel(hs, epctl, epreg);
4442 }
4443 }
4444
4445 hs_ep->halted = value;
4446 return 0;
4447}
4448
4449/**
4450 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4451 * @ep: The endpoint to set halt.
4452 * @value: Set or unset the halt.
4453 */
4454static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4455{
4456 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4457 struct dwc2_hsotg *hs = hs_ep->parent;
4458 unsigned long flags;
4459 int ret;
4460
4461 spin_lock_irqsave(&hs->lock, flags);
4462 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4463 spin_unlock_irqrestore(&hs->lock, flags);
4464
4465 return ret;
4466}
4467
4468static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4469 .enable = dwc2_hsotg_ep_enable,
4470 .disable = dwc2_hsotg_ep_disable_lock,
4471 .alloc_request = dwc2_hsotg_ep_alloc_request,
4472 .free_request = dwc2_hsotg_ep_free_request,
4473 .queue = dwc2_hsotg_ep_queue_lock,
4474 .dequeue = dwc2_hsotg_ep_dequeue,
4475 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4476 .set_wedge = dwc2_gadget_ep_set_wedge,
4477 /* note, don't believe we have any call for the fifo routines */
4478};
4479
4480/**
4481 * dwc2_hsotg_init - initialize the usb core
4482 * @hsotg: The driver state
4483 */
4484static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4485{
4486 /* unmask subset of endpoint interrupts */
4487
4488 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4489 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4490 DIEPMSK);
4491
4492 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4493 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4494 DOEPMSK);
4495
4496 dwc2_writel(hsotg, 0, DAINTMSK);
4497
4498 /* Be in disconnected state until gadget is registered */
4499 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4500
4501 /* setup fifos */
4502
4503 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4504 dwc2_readl(hsotg, GRXFSIZ),
4505 dwc2_readl(hsotg, GNPTXFSIZ));
4506
4507 dwc2_hsotg_init_fifo(hsotg);
4508
4509 if (using_dma(hsotg))
4510 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4511}
4512
4513/**
4514 * dwc2_hsotg_udc_start - prepare the udc for work
4515 * @gadget: The usb gadget state
4516 * @driver: The usb gadget driver
4517 *
4518 * Perform initialization to prepare udc device and driver
4519 * to work.
4520 */
4521static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4522 struct usb_gadget_driver *driver)
4523{
4524 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4525 unsigned long flags;
4526 int ret;
4527
4528 if (!hsotg) {
4529 pr_err("%s: called with no device\n", __func__);
4530 return -ENODEV;
4531 }
4532
4533 if (!driver) {
4534 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4535 return -EINVAL;
4536 }
4537
4538 if (driver->max_speed < USB_SPEED_FULL)
4539 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4540
4541 if (!driver->setup) {
4542 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4543 return -EINVAL;
4544 }
4545
4546 WARN_ON(hsotg->driver);
4547
4548 hsotg->driver = driver;
4549 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4550 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4551
4552 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL ||
4553 (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg))) {
4554 ret = dwc2_lowlevel_hw_enable(hsotg);
4555 if (ret)
4556 goto err;
4557 }
4558
4559 if (!IS_ERR_OR_NULL(hsotg->uphy))
4560 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4561
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 if (dwc2_hw_is_device(hsotg)) {
4564 dwc2_hsotg_init(hsotg);
4565 dwc2_hsotg_core_init_disconnected(hsotg, false);
4566 }
4567
4568 hsotg->enabled = 0;
4569 spin_unlock_irqrestore(&hsotg->lock, flags);
4570
4571 gadget->sg_supported = using_desc_dma(hsotg);
4572 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4573
4574 return 0;
4575
4576err:
4577 hsotg->driver = NULL;
4578 return ret;
4579}
4580
4581/**
4582 * dwc2_hsotg_udc_stop - stop the udc
4583 * @gadget: The usb gadget state
4584 *
4585 * Stop udc hw block and stay tunned for future transmissions
4586 */
4587static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4588{
4589 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4590 unsigned long flags;
4591 int ep;
4592
4593 if (!hsotg)
4594 return -ENODEV;
4595
4596 /* all endpoints should be shutdown */
4597 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4598 if (hsotg->eps_in[ep])
4599 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4600 if (hsotg->eps_out[ep])
4601 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4602 }
4603
4604 spin_lock_irqsave(&hsotg->lock, flags);
4605
4606 hsotg->driver = NULL;
4607 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4608 hsotg->enabled = 0;
4609
4610 spin_unlock_irqrestore(&hsotg->lock, flags);
4611
4612 if (!IS_ERR_OR_NULL(hsotg->uphy))
4613 otg_set_peripheral(hsotg->uphy->otg, NULL);
4614
4615 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL ||
4616 (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)))
4617 dwc2_lowlevel_hw_disable(hsotg);
4618
4619 return 0;
4620}
4621
4622/**
4623 * dwc2_hsotg_gadget_getframe - read the frame number
4624 * @gadget: The usb gadget state
4625 *
4626 * Read the {micro} frame number
4627 */
4628static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4629{
4630 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4631}
4632
4633/**
4634 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4635 * @gadget: The usb gadget state
4636 * @is_selfpowered: Whether the device is self-powered
4637 *
4638 * Set if the device is self or bus powered.
4639 */
4640static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4641 int is_selfpowered)
4642{
4643 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4644 unsigned long flags;
4645
4646 spin_lock_irqsave(&hsotg->lock, flags);
4647 gadget->is_selfpowered = !!is_selfpowered;
4648 spin_unlock_irqrestore(&hsotg->lock, flags);
4649
4650 return 0;
4651}
4652
4653/**
4654 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4655 * @gadget: The usb gadget state
4656 * @is_on: Current state of the USB PHY
4657 *
4658 * Connect/Disconnect the USB PHY pullup
4659 */
4660static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4661{
4662 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4663 unsigned long flags;
4664
4665 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4666 hsotg->op_state);
4667
4668 /* Don't modify pullup state while in host mode */
4669 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4670 hsotg->enabled = is_on;
4671 return 0;
4672 }
4673
4674 spin_lock_irqsave(&hsotg->lock, flags);
4675 if (is_on) {
4676 hsotg->enabled = 1;
4677 dwc2_hsotg_core_init_disconnected(hsotg, false);
4678 /* Enable ACG feature in device mode,if supported */
4679 dwc2_enable_acg(hsotg);
4680 dwc2_hsotg_core_connect(hsotg);
4681 } else {
4682 dwc2_hsotg_core_disconnect(hsotg);
4683 dwc2_hsotg_disconnect(hsotg);
4684 hsotg->enabled = 0;
4685 }
4686
4687 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4688 spin_unlock_irqrestore(&hsotg->lock, flags);
4689
4690 return 0;
4691}
4692
4693static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4694{
4695 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4696 unsigned long flags;
4697
4698 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4699 spin_lock_irqsave(&hsotg->lock, flags);
4700
4701 /*
4702 * If controller is in partial power down state, it must exit from
4703 * that state before being initialized / de-initialized
4704 */
4705 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4706 /*
4707 * No need to check the return value as
4708 * registers are not being restored.
4709 */
4710 dwc2_exit_partial_power_down(hsotg, 0, false);
4711
4712 if (is_active) {
4713 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4714
4715 dwc2_hsotg_core_init_disconnected(hsotg, false);
4716 if (hsotg->enabled) {
4717 /* Enable ACG feature in device mode,if supported */
4718 dwc2_enable_acg(hsotg);
4719 dwc2_hsotg_core_connect(hsotg);
4720 }
4721 } else {
4722 dwc2_hsotg_core_disconnect(hsotg);
4723 dwc2_hsotg_disconnect(hsotg);
4724 }
4725
4726 spin_unlock_irqrestore(&hsotg->lock, flags);
4727 return 0;
4728}
4729
4730/**
4731 * dwc2_hsotg_vbus_draw - report bMaxPower field
4732 * @gadget: The usb gadget state
4733 * @mA: Amount of current
4734 *
4735 * Report how much power the device may consume to the phy.
4736 */
4737static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4738{
4739 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4740
4741 if (IS_ERR_OR_NULL(hsotg->uphy))
4742 return -ENOTSUPP;
4743 return usb_phy_set_power(hsotg->uphy, mA);
4744}
4745
4746static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4747{
4748 struct dwc2_hsotg *hsotg = to_hsotg(g);
4749 unsigned long flags;
4750
4751 spin_lock_irqsave(&hsotg->lock, flags);
4752 switch (speed) {
4753 case USB_SPEED_HIGH:
4754 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4755 break;
4756 case USB_SPEED_FULL:
4757 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4758 break;
4759 case USB_SPEED_LOW:
4760 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4761 break;
4762 default:
4763 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4764 }
4765 spin_unlock_irqrestore(&hsotg->lock, flags);
4766}
4767
4768static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4769 .get_frame = dwc2_hsotg_gadget_getframe,
4770 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4771 .udc_start = dwc2_hsotg_udc_start,
4772 .udc_stop = dwc2_hsotg_udc_stop,
4773 .pullup = dwc2_hsotg_pullup,
4774 .udc_set_speed = dwc2_gadget_set_speed,
4775 .vbus_session = dwc2_hsotg_vbus_session,
4776 .vbus_draw = dwc2_hsotg_vbus_draw,
4777};
4778
4779/**
4780 * dwc2_hsotg_initep - initialise a single endpoint
4781 * @hsotg: The device state.
4782 * @hs_ep: The endpoint to be initialised.
4783 * @epnum: The endpoint number
4784 * @dir_in: True if direction is in.
4785 *
4786 * Initialise the given endpoint (as part of the probe and device state
4787 * creation) to give to the gadget driver. Setup the endpoint name, any
4788 * direction information and other state that may be required.
4789 */
4790static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4791 struct dwc2_hsotg_ep *hs_ep,
4792 int epnum,
4793 bool dir_in)
4794{
4795 char *dir;
4796
4797 if (epnum == 0)
4798 dir = "";
4799 else if (dir_in)
4800 dir = "in";
4801 else
4802 dir = "out";
4803
4804 hs_ep->dir_in = dir_in;
4805 hs_ep->index = epnum;
4806
4807 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4808
4809 INIT_LIST_HEAD(&hs_ep->queue);
4810 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4811
4812 /* add to the list of endpoints known by the gadget driver */
4813 if (epnum)
4814 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4815
4816 hs_ep->parent = hsotg;
4817 hs_ep->ep.name = hs_ep->name;
4818
4819 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4820 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4821 else
4822 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4823 epnum ? 1024 : EP0_MPS_LIMIT);
4824 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4825
4826 if (epnum == 0) {
4827 hs_ep->ep.caps.type_control = true;
4828 } else {
4829 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4830 hs_ep->ep.caps.type_iso = true;
4831 hs_ep->ep.caps.type_bulk = true;
4832 }
4833 hs_ep->ep.caps.type_int = true;
4834 }
4835
4836 if (dir_in)
4837 hs_ep->ep.caps.dir_in = true;
4838 else
4839 hs_ep->ep.caps.dir_out = true;
4840
4841 /*
4842 * if we're using dma, we need to set the next-endpoint pointer
4843 * to be something valid.
4844 */
4845
4846 if (using_dma(hsotg)) {
4847 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4848
4849 if (dir_in)
4850 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4851 else
4852 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4853 }
4854}
4855
4856/**
4857 * dwc2_hsotg_hw_cfg - read HW configuration registers
4858 * @hsotg: Programming view of the DWC_otg controller
4859 *
4860 * Read the USB core HW configuration registers
4861 */
4862static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4863{
4864 u32 cfg;
4865 u32 ep_type;
4866 u32 i;
4867
4868 /* check hardware configuration */
4869
4870 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4871
4872 /* Add ep0 */
4873 hsotg->num_of_eps++;
4874
4875 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4876 sizeof(struct dwc2_hsotg_ep),
4877 GFP_KERNEL);
4878 if (!hsotg->eps_in[0])
4879 return -ENOMEM;
4880 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4881 hsotg->eps_out[0] = hsotg->eps_in[0];
4882
4883 cfg = hsotg->hw_params.dev_ep_dirs;
4884 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4885 ep_type = cfg & 3;
4886 /* Direction in or both */
4887 if (!(ep_type & 2)) {
4888 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4889 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4890 if (!hsotg->eps_in[i])
4891 return -ENOMEM;
4892 }
4893 /* Direction out or both */
4894 if (!(ep_type & 1)) {
4895 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4896 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4897 if (!hsotg->eps_out[i])
4898 return -ENOMEM;
4899 }
4900 }
4901
4902 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4903 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4904
4905 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4906 hsotg->num_of_eps,
4907 hsotg->dedicated_fifos ? "dedicated" : "shared",
4908 hsotg->fifo_mem);
4909 return 0;
4910}
4911
4912/**
4913 * dwc2_hsotg_dump - dump state of the udc
4914 * @hsotg: Programming view of the DWC_otg controller
4915 *
4916 */
4917static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4918{
4919#ifdef DEBUG
4920 struct device *dev = hsotg->dev;
4921 u32 val;
4922 int idx;
4923
4924 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4925 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4926 dwc2_readl(hsotg, DIEPMSK));
4927
4928 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4929 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4930
4931 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4932 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4933
4934 /* show periodic fifo settings */
4935
4936 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4937 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4938 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4939 val >> FIFOSIZE_DEPTH_SHIFT,
4940 val & FIFOSIZE_STARTADDR_MASK);
4941 }
4942
4943 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4944 dev_info(dev,
4945 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4946 dwc2_readl(hsotg, DIEPCTL(idx)),
4947 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4948 dwc2_readl(hsotg, DIEPDMA(idx)));
4949
4950 val = dwc2_readl(hsotg, DOEPCTL(idx));
4951 dev_info(dev,
4952 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4953 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4954 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4955 dwc2_readl(hsotg, DOEPDMA(idx)));
4956 }
4957
4958 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4959 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4960#endif
4961}
4962
4963/**
4964 * dwc2_gadget_init - init function for gadget
4965 * @hsotg: Programming view of the DWC_otg controller
4966 *
4967 */
4968int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4969{
4970 struct device *dev = hsotg->dev;
4971 int epnum;
4972 int ret;
4973
4974 /* Dump fifo information */
4975 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4976 hsotg->params.g_np_tx_fifo_size);
4977 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4978
4979 switch (hsotg->params.speed) {
4980 case DWC2_SPEED_PARAM_LOW:
4981 hsotg->gadget.max_speed = USB_SPEED_LOW;
4982 break;
4983 case DWC2_SPEED_PARAM_FULL:
4984 hsotg->gadget.max_speed = USB_SPEED_FULL;
4985 break;
4986 default:
4987 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4988 break;
4989 }
4990
4991 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4992 hsotg->gadget.name = dev_name(dev);
4993 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
4994 hsotg->remote_wakeup_allowed = 0;
4995
4996 if (hsotg->params.lpm)
4997 hsotg->gadget.lpm_capable = true;
4998
4999 if (hsotg->dr_mode == USB_DR_MODE_OTG)
5000 hsotg->gadget.is_otg = 1;
5001 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5002 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5003
5004 ret = dwc2_hsotg_hw_cfg(hsotg);
5005 if (ret) {
5006 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5007 return ret;
5008 }
5009
5010 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5011 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5012 if (!hsotg->ctrl_buff)
5013 return -ENOMEM;
5014
5015 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5016 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5017 if (!hsotg->ep0_buff)
5018 return -ENOMEM;
5019
5020 if (using_desc_dma(hsotg)) {
5021 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5022 if (ret < 0)
5023 return ret;
5024 }
5025
5026 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5027 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5028 if (ret < 0) {
5029 dev_err(dev, "cannot claim IRQ for gadget\n");
5030 return ret;
5031 }
5032
5033 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5034
5035 if (hsotg->num_of_eps == 0) {
5036 dev_err(dev, "wrong number of EPs (zero)\n");
5037 return -EINVAL;
5038 }
5039
5040 /* setup endpoint information */
5041
5042 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5043 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5044
5045 /* allocate EP0 request */
5046
5047 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5048 GFP_KERNEL);
5049 if (!hsotg->ctrl_req) {
5050 dev_err(dev, "failed to allocate ctrl req\n");
5051 return -ENOMEM;
5052 }
5053
5054 /* initialise the endpoints now the core has been initialised */
5055 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5056 if (hsotg->eps_in[epnum])
5057 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5058 epnum, 1);
5059 if (hsotg->eps_out[epnum])
5060 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5061 epnum, 0);
5062 }
5063
5064 dwc2_hsotg_dump(hsotg);
5065
5066 return 0;
5067}
5068
5069/**
5070 * dwc2_hsotg_remove - remove function for hsotg driver
5071 * @hsotg: Programming view of the DWC_otg controller
5072 *
5073 */
5074int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5075{
5076 usb_del_gadget_udc(&hsotg->gadget);
5077 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5078
5079 return 0;
5080}
5081
5082int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5083{
5084 unsigned long flags;
5085
5086 if (hsotg->lx_state != DWC2_L0)
5087 return 0;
5088
5089 if (hsotg->driver) {
5090 int ep;
5091
5092 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5093 hsotg->driver->driver.name);
5094
5095 spin_lock_irqsave(&hsotg->lock, flags);
5096 if (hsotg->enabled)
5097 dwc2_hsotg_core_disconnect(hsotg);
5098 dwc2_hsotg_disconnect(hsotg);
5099 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5100 spin_unlock_irqrestore(&hsotg->lock, flags);
5101
5102 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5103 if (hsotg->eps_in[ep])
5104 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5105 if (hsotg->eps_out[ep])
5106 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5107 }
5108 }
5109
5110 return 0;
5111}
5112
5113int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5114{
5115 unsigned long flags;
5116
5117 if (hsotg->lx_state == DWC2_L2)
5118 return 0;
5119
5120 if (hsotg->driver) {
5121 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5122 hsotg->driver->driver.name);
5123
5124 spin_lock_irqsave(&hsotg->lock, flags);
5125 dwc2_hsotg_core_init_disconnected(hsotg, false);
5126 if (hsotg->enabled) {
5127 /* Enable ACG feature in device mode,if supported */
5128 dwc2_enable_acg(hsotg);
5129 dwc2_hsotg_core_connect(hsotg);
5130 }
5131 spin_unlock_irqrestore(&hsotg->lock, flags);
5132 }
5133
5134 return 0;
5135}
5136
5137/**
5138 * dwc2_backup_device_registers() - Backup controller device registers.
5139 * When suspending usb bus, registers needs to be backuped
5140 * if controller power is disabled once suspended.
5141 *
5142 * @hsotg: Programming view of the DWC_otg controller
5143 */
5144int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5145{
5146 struct dwc2_dregs_backup *dr;
5147 int i;
5148
5149 dev_dbg(hsotg->dev, "%s\n", __func__);
5150
5151 /* Backup dev regs */
5152 dr = &hsotg->dr_backup;
5153
5154 dr->dcfg = dwc2_readl(hsotg, DCFG);
5155 dr->dctl = dwc2_readl(hsotg, DCTL);
5156 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5157 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5158 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5159
5160 for (i = 0; i < hsotg->num_of_eps; i++) {
5161 /* Backup IN EPs */
5162 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5163
5164 /* Ensure DATA PID is correctly configured */
5165 if (dr->diepctl[i] & DXEPCTL_DPID)
5166 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5167 else
5168 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5169
5170 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5171 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5172
5173 /* Backup OUT EPs */
5174 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5175
5176 /* Ensure DATA PID is correctly configured */
5177 if (dr->doepctl[i] & DXEPCTL_DPID)
5178 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5179 else
5180 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5181
5182 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5183 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5184 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5185 }
5186 dr->valid = true;
5187 return 0;
5188}
5189
5190/**
5191 * dwc2_restore_device_registers() - Restore controller device registers.
5192 * When resuming usb bus, device registers needs to be restored
5193 * if controller power were disabled.
5194 *
5195 * @hsotg: Programming view of the DWC_otg controller
5196 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5197 *
5198 * Return: 0 if successful, negative error code otherwise
5199 */
5200int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5201{
5202 struct dwc2_dregs_backup *dr;
5203 int i;
5204
5205 dev_dbg(hsotg->dev, "%s\n", __func__);
5206
5207 /* Restore dev regs */
5208 dr = &hsotg->dr_backup;
5209 if (!dr->valid) {
5210 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5211 __func__);
5212 return -EINVAL;
5213 }
5214 dr->valid = false;
5215
5216 if (!remote_wakeup)
5217 dwc2_writel(hsotg, dr->dctl, DCTL);
5218
5219 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5220 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5221 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5222
5223 for (i = 0; i < hsotg->num_of_eps; i++) {
5224 /* Restore IN EPs */
5225 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5226 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5227 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5228 /** WA for enabled EPx's IN in DDMA mode. On entering to
5229 * hibernation wrong value read and saved from DIEPDMAx,
5230 * as result BNA interrupt asserted on hibernation exit
5231 * by restoring from saved area.
5232 */
5233 if (using_desc_dma(hsotg) &&
5234 (dr->diepctl[i] & DXEPCTL_EPENA))
5235 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5236 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5237 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5238 /* Restore OUT EPs */
5239 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5240 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5241 * hibernation wrong value read and saved from DOEPDMAx,
5242 * as result BNA interrupt asserted on hibernation exit
5243 * by restoring from saved area.
5244 */
5245 if (using_desc_dma(hsotg) &&
5246 (dr->doepctl[i] & DXEPCTL_EPENA))
5247 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5248 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5249 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5250 }
5251
5252 return 0;
5253}
5254
5255/**
5256 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5257 *
5258 * @hsotg: Programming view of DWC_otg controller
5259 *
5260 */
5261void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5262{
5263 u32 val;
5264
5265 if (!hsotg->params.lpm)
5266 return;
5267
5268 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5269 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5270 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5271 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5272 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5273 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5274 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5275 dwc2_writel(hsotg, val, GLPMCFG);
5276 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5277
5278 /* Unmask WKUP_ALERT Interrupt */
5279 if (hsotg->params.service_interval)
5280 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5281}
5282
5283/**
5284 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5285 *
5286 * @hsotg: Programming view of DWC_otg controller
5287 *
5288 */
5289void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5290{
5291 u32 val = 0;
5292
5293 val |= GREFCLK_REF_CLK_MODE;
5294 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5295 val |= hsotg->params.sof_cnt_wkup_alert <<
5296 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5297
5298 dwc2_writel(hsotg, val, GREFCLK);
5299 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5300}
5301
5302/**
5303 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5304 *
5305 * @hsotg: Programming view of the DWC_otg controller
5306 *
5307 * Return non-zero if failed to enter to hibernation.
5308 */
5309int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5310{
5311 u32 gpwrdn;
5312 int ret = 0;
5313
5314 /* Change to L2(suspend) state */
5315 hsotg->lx_state = DWC2_L2;
5316 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5317 ret = dwc2_backup_global_registers(hsotg);
5318 if (ret) {
5319 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5320 __func__);
5321 return ret;
5322 }
5323 ret = dwc2_backup_device_registers(hsotg);
5324 if (ret) {
5325 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5326 __func__);
5327 return ret;
5328 }
5329
5330 gpwrdn = GPWRDN_PWRDNRSTN;
5331 gpwrdn |= GPWRDN_PMUACTV;
5332 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5333 udelay(10);
5334
5335 /* Set flag to indicate that we are in hibernation */
5336 hsotg->hibernated = 1;
5337
5338 /* Enable interrupts from wake up logic */
5339 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5340 gpwrdn |= GPWRDN_PMUINTSEL;
5341 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5342 udelay(10);
5343
5344 /* Unmask device mode interrupts in GPWRDN */
5345 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5346 gpwrdn |= GPWRDN_RST_DET_MSK;
5347 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5348 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5349 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5350 udelay(10);
5351
5352 /* Enable Power Down Clamp */
5353 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5354 gpwrdn |= GPWRDN_PWRDNCLMP;
5355 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5356 udelay(10);
5357
5358 /* Switch off VDD */
5359 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5360 gpwrdn |= GPWRDN_PWRDNSWTCH;
5361 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5362 udelay(10);
5363
5364 /* Save gpwrdn register for further usage if stschng interrupt */
5365 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5366 dev_dbg(hsotg->dev, "Hibernation completed\n");
5367
5368 return ret;
5369}
5370
5371/**
5372 * dwc2_gadget_exit_hibernation()
5373 * This function is for exiting from Device mode hibernation by host initiated
5374 * resume/reset and device initiated remote-wakeup.
5375 *
5376 * @hsotg: Programming view of the DWC_otg controller
5377 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5378 * @reset: indicates whether resume is initiated by Reset.
5379 *
5380 * Return non-zero if failed to exit from hibernation.
5381 */
5382int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5383 int rem_wakeup, int reset)
5384{
5385 u32 pcgcctl;
5386 u32 gpwrdn;
5387 u32 dctl;
5388 int ret = 0;
5389 struct dwc2_gregs_backup *gr;
5390 struct dwc2_dregs_backup *dr;
5391
5392 gr = &hsotg->gr_backup;
5393 dr = &hsotg->dr_backup;
5394
5395 if (!hsotg->hibernated) {
5396 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5397 return 1;
5398 }
5399 dev_dbg(hsotg->dev,
5400 "%s: called with rem_wakeup = %d reset = %d\n",
5401 __func__, rem_wakeup, reset);
5402
5403 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5404
5405 if (!reset) {
5406 /* Clear all pending interupts */
5407 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5408 }
5409
5410 /* De-assert Restore */
5411 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5412 gpwrdn &= ~GPWRDN_RESTORE;
5413 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5414 udelay(10);
5415
5416 if (!rem_wakeup) {
5417 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5418 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5419 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5420 }
5421
5422 /* Restore GUSBCFG, DCFG and DCTL */
5423 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5424 dwc2_writel(hsotg, dr->dcfg, DCFG);
5425 dwc2_writel(hsotg, dr->dctl, DCTL);
5426
5427 /* On USB Reset, reset device address to zero */
5428 if (reset)
5429 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5430
5431 /* De-assert Wakeup Logic */
5432 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5433 gpwrdn &= ~GPWRDN_PMUACTV;
5434 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5435
5436 if (rem_wakeup) {
5437 udelay(10);
5438 /* Start Remote Wakeup Signaling */
5439 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5440 } else {
5441 udelay(50);
5442 /* Set Device programming done bit */
5443 dctl = dwc2_readl(hsotg, DCTL);
5444 dctl |= DCTL_PWRONPRGDONE;
5445 dwc2_writel(hsotg, dctl, DCTL);
5446 }
5447 /* Wait for interrupts which must be cleared */
5448 mdelay(2);
5449 /* Clear all pending interupts */
5450 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5451
5452 /* Restore global registers */
5453 ret = dwc2_restore_global_registers(hsotg);
5454 if (ret) {
5455 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5456 __func__);
5457 return ret;
5458 }
5459
5460 /* Restore device registers */
5461 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5462 if (ret) {
5463 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5464 __func__);
5465 return ret;
5466 }
5467
5468 if (rem_wakeup) {
5469 mdelay(10);
5470 dctl = dwc2_readl(hsotg, DCTL);
5471 dctl &= ~DCTL_RMTWKUPSIG;
5472 dwc2_writel(hsotg, dctl, DCTL);
5473 }
5474
5475 hsotg->hibernated = 0;
5476 hsotg->lx_state = DWC2_L0;
5477 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5478
5479 return ret;
5480}
5481
5482/**
5483 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5484 * power down.
5485 *
5486 * @hsotg: Programming view of the DWC_otg controller
5487 *
5488 * Return: non-zero if failed to enter device partial power down.
5489 *
5490 * This function is for entering device mode partial power down.
5491 */
5492int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5493{
5494 u32 pcgcctl;
5495 int ret = 0;
5496
5497 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5498
5499 /* Backup all registers */
5500 ret = dwc2_backup_global_registers(hsotg);
5501 if (ret) {
5502 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5503 __func__);
5504 return ret;
5505 }
5506
5507 ret = dwc2_backup_device_registers(hsotg);
5508 if (ret) {
5509 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5510 __func__);
5511 return ret;
5512 }
5513
5514 /*
5515 * Clear any pending interrupts since dwc2 will not be able to
5516 * clear them after entering partial_power_down.
5517 */
5518 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5519
5520 /* Put the controller in low power state */
5521 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5522
5523 pcgcctl |= PCGCTL_PWRCLMP;
5524 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5525 udelay(5);
5526
5527 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5528 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5529 udelay(5);
5530
5531 pcgcctl |= PCGCTL_STOPPCLK;
5532 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5533
5534 /* Set in_ppd flag to 1 as here core enters suspend. */
5535 hsotg->in_ppd = 1;
5536 hsotg->lx_state = DWC2_L2;
5537
5538 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5539
5540 return ret;
5541}
5542
5543/*
5544 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5545 * power down.
5546 *
5547 * @hsotg: Programming view of the DWC_otg controller
5548 * @restore: indicates whether need to restore the registers or not.
5549 *
5550 * Return: non-zero if failed to exit device partial power down.
5551 *
5552 * This function is for exiting from device mode partial power down.
5553 */
5554int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5555 bool restore)
5556{
5557 u32 pcgcctl;
5558 u32 dctl;
5559 struct dwc2_dregs_backup *dr;
5560 int ret = 0;
5561
5562 dr = &hsotg->dr_backup;
5563
5564 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5565
5566 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5567 pcgcctl &= ~PCGCTL_STOPPCLK;
5568 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5569
5570 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5571 pcgcctl &= ~PCGCTL_PWRCLMP;
5572 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5573
5574 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5575 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5576 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577
5578 udelay(100);
5579 if (restore) {
5580 ret = dwc2_restore_global_registers(hsotg);
5581 if (ret) {
5582 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5583 __func__);
5584 return ret;
5585 }
5586 /* Restore DCFG */
5587 dwc2_writel(hsotg, dr->dcfg, DCFG);
5588
5589 ret = dwc2_restore_device_registers(hsotg, 0);
5590 if (ret) {
5591 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5592 __func__);
5593 return ret;
5594 }
5595 }
5596
5597 /* Set the Power-On Programming done bit */
5598 dctl = dwc2_readl(hsotg, DCTL);
5599 dctl |= DCTL_PWRONPRGDONE;
5600 dwc2_writel(hsotg, dctl, DCTL);
5601
5602 /* Set in_ppd flag to 0 as here core exits from suspend. */
5603 hsotg->in_ppd = 0;
5604 hsotg->lx_state = DWC2_L0;
5605
5606 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5607 return ret;
5608}
5609
5610/**
5611 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5612 *
5613 * @hsotg: Programming view of the DWC_otg controller
5614 *
5615 * Return: non-zero if failed to enter device partial power down.
5616 *
5617 * This function is for entering device mode clock gating.
5618 */
5619void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5620{
5621 u32 pcgctl;
5622
5623 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5624
5625 /* Set the Phy Clock bit as suspend is received. */
5626 pcgctl = dwc2_readl(hsotg, PCGCTL);
5627 pcgctl |= PCGCTL_STOPPCLK;
5628 dwc2_writel(hsotg, pcgctl, PCGCTL);
5629 udelay(5);
5630
5631 /* Set the Gate hclk as suspend is received. */
5632 pcgctl = dwc2_readl(hsotg, PCGCTL);
5633 pcgctl |= PCGCTL_GATEHCLK;
5634 dwc2_writel(hsotg, pcgctl, PCGCTL);
5635 udelay(5);
5636
5637 hsotg->lx_state = DWC2_L2;
5638 hsotg->bus_suspended = true;
5639}
5640
5641/*
5642 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5643 *
5644 * @hsotg: Programming view of the DWC_otg controller
5645 * @rem_wakeup: indicates whether remote wake up is enabled.
5646 *
5647 * This function is for exiting from device mode clock gating.
5648 */
5649void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5650{
5651 u32 pcgctl;
5652 u32 dctl;
5653
5654 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5655
5656 /* Clear the Gate hclk. */
5657 pcgctl = dwc2_readl(hsotg, PCGCTL);
5658 pcgctl &= ~PCGCTL_GATEHCLK;
5659 dwc2_writel(hsotg, pcgctl, PCGCTL);
5660 udelay(5);
5661
5662 /* Phy Clock bit. */
5663 pcgctl = dwc2_readl(hsotg, PCGCTL);
5664 pcgctl &= ~PCGCTL_STOPPCLK;
5665 dwc2_writel(hsotg, pcgctl, PCGCTL);
5666 udelay(5);
5667
5668 if (rem_wakeup) {
5669 /* Set Remote Wakeup Signaling */
5670 dctl = dwc2_readl(hsotg, DCTL);
5671 dctl |= DCTL_RMTWKUPSIG;
5672 dwc2_writel(hsotg, dctl, DCTL);
5673 }
5674
5675 /* Change to L0 state */
5676 call_gadget(hsotg, resume);
5677 hsotg->lx_state = DWC2_L0;
5678 hsotg->bus_suspended = false;
5679}
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30
31#include "core.h"
32#include "hw.h"
33
34/* conversion functions */
35static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
36{
37 return container_of(req, struct dwc2_hsotg_req, req);
38}
39
40static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
41{
42 return container_of(ep, struct dwc2_hsotg_ep, ep);
43}
44
45static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
46{
47 return container_of(gadget, struct dwc2_hsotg, gadget);
48}
49
50static inline void dwc2_set_bit(void __iomem *ptr, u32 val)
51{
52 dwc2_writel(dwc2_readl(ptr) | val, ptr);
53}
54
55static inline void dwc2_clear_bit(void __iomem *ptr, u32 val)
56{
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
58}
59
60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
61 u32 ep_index, u32 dir_in)
62{
63 if (dir_in)
64 return hsotg->eps_in[ep_index];
65 else
66 return hsotg->eps_out[ep_index];
67}
68
69/* forward declaration of functions */
70static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
71
72/**
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
75 *
76 * Return true if we're using DMA.
77 *
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
82 * not 32bit aligned.
83 *
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
88 *
89 * g_using_dma is set depending on dts flag.
90 */
91static inline bool using_dma(struct dwc2_hsotg *hsotg)
92{
93 return hsotg->params.g_dma;
94}
95
96/*
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
99 *
100 * Return true if we're using descriptor DMA.
101 */
102static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
103{
104 return hsotg->params.g_dma_desc;
105}
106
107/**
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
110 * @increment: The value to increment by
111 *
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 */
115static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116{
117 hs_ep->target_frame += hs_ep->interval;
118 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
119 hs_ep->frame_overrun = true;
120 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 } else {
122 hs_ep->frame_overrun = false;
123 }
124}
125
126/**
127 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
128 * @hsotg: The device state
129 * @ints: A bitmask of the interrupts to enable
130 */
131static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
132{
133 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
134 u32 new_gsintmsk;
135
136 new_gsintmsk = gsintmsk | ints;
137
138 if (new_gsintmsk != gsintmsk) {
139 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
140 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
141 }
142}
143
144/**
145 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
146 * @hsotg: The device state
147 * @ints: A bitmask of the interrupts to enable
148 */
149static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
150{
151 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
152 u32 new_gsintmsk;
153
154 new_gsintmsk = gsintmsk & ~ints;
155
156 if (new_gsintmsk != gsintmsk)
157 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
158}
159
160/**
161 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
162 * @hsotg: The device state
163 * @ep: The endpoint index
164 * @dir_in: True if direction is in.
165 * @en: The enable value, true to enable
166 *
167 * Set or clear the mask for an individual endpoint's interrupt
168 * request.
169 */
170static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
171 unsigned int ep, unsigned int dir_in,
172 unsigned int en)
173{
174 unsigned long flags;
175 u32 bit = 1 << ep;
176 u32 daint;
177
178 if (!dir_in)
179 bit <<= 16;
180
181 local_irq_save(flags);
182 daint = dwc2_readl(hsotg->regs + DAINTMSK);
183 if (en)
184 daint |= bit;
185 else
186 daint &= ~bit;
187 dwc2_writel(daint, hsotg->regs + DAINTMSK);
188 local_irq_restore(flags);
189}
190
191/**
192 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
193 */
194int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
195{
196 if (hsotg->hw_params.en_multiple_tx_fifo)
197 /* In dedicated FIFO mode we need count of IN EPs */
198 return hsotg->hw_params.num_dev_in_eps;
199 else
200 /* In shared FIFO mode we need count of Periodic IN EPs */
201 return hsotg->hw_params.num_dev_perio_in_ep;
202}
203
204/**
205 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
206 * device mode TX FIFOs
207 */
208int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
209{
210 int addr;
211 int tx_addr_max;
212 u32 np_tx_fifo_size;
213
214 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
215 hsotg->params.g_np_tx_fifo_size);
216
217 /* Get Endpoint Info Control block size in DWORDs. */
218 tx_addr_max = hsotg->hw_params.total_fifo_size;
219
220 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
221 if (tx_addr_max <= addr)
222 return 0;
223
224 return tx_addr_max - addr;
225}
226
227/**
228 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
229 * TX FIFOs
230 */
231int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
232{
233 int tx_fifo_count;
234 int tx_fifo_depth;
235
236 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
237
238 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
239
240 if (!tx_fifo_count)
241 return tx_fifo_depth;
242 else
243 return tx_fifo_depth / tx_fifo_count;
244}
245
246/**
247 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
248 * @hsotg: The device instance.
249 */
250static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
251{
252 unsigned int ep;
253 unsigned int addr;
254 int timeout;
255
256 u32 val;
257 u32 *txfsz = hsotg->params.g_tx_fifo_size;
258
259 /* Reset fifo map if not correctly cleared during previous session */
260 WARN_ON(hsotg->fifo_map);
261 hsotg->fifo_map = 0;
262
263 /* set RX/NPTX FIFO sizes */
264 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
265 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
266 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
267 hsotg->regs + GNPTXFSIZ);
268
269 /*
270 * arange all the rest of the TX FIFOs, as some versions of this
271 * block have overlapping default addresses. This also ensures
272 * that if the settings have been changed, then they are set to
273 * known values.
274 */
275
276 /* start at the end of the GNPTXFSIZ, rounded up */
277 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
278
279 /*
280 * Configure fifos sizes from provided configuration and assign
281 * them to endpoints dynamically according to maxpacket size value of
282 * given endpoint.
283 */
284 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
285 if (!txfsz[ep])
286 continue;
287 val = addr;
288 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
289 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
290 "insufficient fifo memory");
291 addr += txfsz[ep];
292
293 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
294 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
295 }
296
297 dwc2_writel(hsotg->hw_params.total_fifo_size |
298 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
299 hsotg->regs + GDFIFOCFG);
300 /*
301 * according to p428 of the design guide, we need to ensure that
302 * all fifos are flushed before continuing
303 */
304
305 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
306 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
307
308 /* wait until the fifos are both flushed */
309 timeout = 100;
310 while (1) {
311 val = dwc2_readl(hsotg->regs + GRSTCTL);
312
313 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
314 break;
315
316 if (--timeout == 0) {
317 dev_err(hsotg->dev,
318 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
319 __func__, val);
320 break;
321 }
322
323 udelay(1);
324 }
325
326 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
327}
328
329/**
330 * @ep: USB endpoint to allocate request for.
331 * @flags: Allocation flags
332 *
333 * Allocate a new USB request structure appropriate for the specified endpoint
334 */
335static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
336 gfp_t flags)
337{
338 struct dwc2_hsotg_req *req;
339
340 req = kzalloc(sizeof(*req), flags);
341 if (!req)
342 return NULL;
343
344 INIT_LIST_HEAD(&req->queue);
345
346 return &req->req;
347}
348
349/**
350 * is_ep_periodic - return true if the endpoint is in periodic mode.
351 * @hs_ep: The endpoint to query.
352 *
353 * Returns true if the endpoint is in periodic mode, meaning it is being
354 * used for an Interrupt or ISO transfer.
355 */
356static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
357{
358 return hs_ep->periodic;
359}
360
361/**
362 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
363 * @hsotg: The device state.
364 * @hs_ep: The endpoint for the request
365 * @hs_req: The request being processed.
366 *
367 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
368 * of a request to ensure the buffer is ready for access by the caller.
369 */
370static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
371 struct dwc2_hsotg_ep *hs_ep,
372 struct dwc2_hsotg_req *hs_req)
373{
374 struct usb_request *req = &hs_req->req;
375
376 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
377}
378
379/*
380 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
381 * for Control endpoint
382 * @hsotg: The device state.
383 *
384 * This function will allocate 4 descriptor chains for EP 0: 2 for
385 * Setup stage, per one for IN and OUT data/status transactions.
386 */
387static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
388{
389 hsotg->setup_desc[0] =
390 dmam_alloc_coherent(hsotg->dev,
391 sizeof(struct dwc2_dma_desc),
392 &hsotg->setup_desc_dma[0],
393 GFP_KERNEL);
394 if (!hsotg->setup_desc[0])
395 goto fail;
396
397 hsotg->setup_desc[1] =
398 dmam_alloc_coherent(hsotg->dev,
399 sizeof(struct dwc2_dma_desc),
400 &hsotg->setup_desc_dma[1],
401 GFP_KERNEL);
402 if (!hsotg->setup_desc[1])
403 goto fail;
404
405 hsotg->ctrl_in_desc =
406 dmam_alloc_coherent(hsotg->dev,
407 sizeof(struct dwc2_dma_desc),
408 &hsotg->ctrl_in_desc_dma,
409 GFP_KERNEL);
410 if (!hsotg->ctrl_in_desc)
411 goto fail;
412
413 hsotg->ctrl_out_desc =
414 dmam_alloc_coherent(hsotg->dev,
415 sizeof(struct dwc2_dma_desc),
416 &hsotg->ctrl_out_desc_dma,
417 GFP_KERNEL);
418 if (!hsotg->ctrl_out_desc)
419 goto fail;
420
421 return 0;
422
423fail:
424 return -ENOMEM;
425}
426
427/**
428 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
429 * @hsotg: The controller state.
430 * @hs_ep: The endpoint we're going to write for.
431 * @hs_req: The request to write data for.
432 *
433 * This is called when the TxFIFO has some space in it to hold a new
434 * transmission and we have something to give it. The actual setup of
435 * the data size is done elsewhere, so all we have to do is to actually
436 * write the data.
437 *
438 * The return value is zero if there is more space (or nothing was done)
439 * otherwise -ENOSPC is returned if the FIFO space was used up.
440 *
441 * This routine is only needed for PIO
442 */
443static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
444 struct dwc2_hsotg_ep *hs_ep,
445 struct dwc2_hsotg_req *hs_req)
446{
447 bool periodic = is_ep_periodic(hs_ep);
448 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
449 int buf_pos = hs_req->req.actual;
450 int to_write = hs_ep->size_loaded;
451 void *data;
452 int can_write;
453 int pkt_round;
454 int max_transfer;
455
456 to_write -= (buf_pos - hs_ep->last_load);
457
458 /* if there's nothing to write, get out early */
459 if (to_write == 0)
460 return 0;
461
462 if (periodic && !hsotg->dedicated_fifos) {
463 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
464 int size_left;
465 int size_done;
466
467 /*
468 * work out how much data was loaded so we can calculate
469 * how much data is left in the fifo.
470 */
471
472 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
473
474 /*
475 * if shared fifo, we cannot write anything until the
476 * previous data has been completely sent.
477 */
478 if (hs_ep->fifo_load != 0) {
479 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
480 return -ENOSPC;
481 }
482
483 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
484 __func__, size_left,
485 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
486
487 /* how much of the data has moved */
488 size_done = hs_ep->size_loaded - size_left;
489
490 /* how much data is left in the fifo */
491 can_write = hs_ep->fifo_load - size_done;
492 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
493 __func__, can_write);
494
495 can_write = hs_ep->fifo_size - can_write;
496 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
497 __func__, can_write);
498
499 if (can_write <= 0) {
500 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
501 return -ENOSPC;
502 }
503 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
504 can_write = dwc2_readl(hsotg->regs +
505 DTXFSTS(hs_ep->fifo_index));
506
507 can_write &= 0xffff;
508 can_write *= 4;
509 } else {
510 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
511 dev_dbg(hsotg->dev,
512 "%s: no queue slots available (0x%08x)\n",
513 __func__, gnptxsts);
514
515 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
516 return -ENOSPC;
517 }
518
519 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
520 can_write *= 4; /* fifo size is in 32bit quantities. */
521 }
522
523 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
524
525 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
526 __func__, gnptxsts, can_write, to_write, max_transfer);
527
528 /*
529 * limit to 512 bytes of data, it seems at least on the non-periodic
530 * FIFO, requests of >512 cause the endpoint to get stuck with a
531 * fragment of the end of the transfer in it.
532 */
533 if (can_write > 512 && !periodic)
534 can_write = 512;
535
536 /*
537 * limit the write to one max-packet size worth of data, but allow
538 * the transfer to return that it did not run out of fifo space
539 * doing it.
540 */
541 if (to_write > max_transfer) {
542 to_write = max_transfer;
543
544 /* it's needed only when we do not use dedicated fifos */
545 if (!hsotg->dedicated_fifos)
546 dwc2_hsotg_en_gsint(hsotg,
547 periodic ? GINTSTS_PTXFEMP :
548 GINTSTS_NPTXFEMP);
549 }
550
551 /* see if we can write data */
552
553 if (to_write > can_write) {
554 to_write = can_write;
555 pkt_round = to_write % max_transfer;
556
557 /*
558 * Round the write down to an
559 * exact number of packets.
560 *
561 * Note, we do not currently check to see if we can ever
562 * write a full packet or not to the FIFO.
563 */
564
565 if (pkt_round)
566 to_write -= pkt_round;
567
568 /*
569 * enable correct FIFO interrupt to alert us when there
570 * is more room left.
571 */
572
573 /* it's needed only when we do not use dedicated fifos */
574 if (!hsotg->dedicated_fifos)
575 dwc2_hsotg_en_gsint(hsotg,
576 periodic ? GINTSTS_PTXFEMP :
577 GINTSTS_NPTXFEMP);
578 }
579
580 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
581 to_write, hs_req->req.length, can_write, buf_pos);
582
583 if (to_write <= 0)
584 return -ENOSPC;
585
586 hs_req->req.actual = buf_pos + to_write;
587 hs_ep->total_data += to_write;
588
589 if (periodic)
590 hs_ep->fifo_load += to_write;
591
592 to_write = DIV_ROUND_UP(to_write, 4);
593 data = hs_req->req.buf + buf_pos;
594
595 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
596
597 return (to_write >= can_write) ? -ENOSPC : 0;
598}
599
600/**
601 * get_ep_limit - get the maximum data legnth for this endpoint
602 * @hs_ep: The endpoint
603 *
604 * Return the maximum data that can be queued in one go on a given endpoint
605 * so that transfers that are too long can be split.
606 */
607static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
608{
609 int index = hs_ep->index;
610 unsigned int maxsize;
611 unsigned int maxpkt;
612
613 if (index != 0) {
614 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
615 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
616 } else {
617 maxsize = 64 + 64;
618 if (hs_ep->dir_in)
619 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
620 else
621 maxpkt = 2;
622 }
623
624 /* we made the constant loading easier above by using +1 */
625 maxpkt--;
626 maxsize--;
627
628 /*
629 * constrain by packet count if maxpkts*pktsize is greater
630 * than the length register size.
631 */
632
633 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
634 maxsize = maxpkt * hs_ep->ep.maxpacket;
635
636 return maxsize;
637}
638
639/**
640 * dwc2_hsotg_read_frameno - read current frame number
641 * @hsotg: The device instance
642 *
643 * Return the current frame number
644 */
645static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
646{
647 u32 dsts;
648
649 dsts = dwc2_readl(hsotg->regs + DSTS);
650 dsts &= DSTS_SOFFN_MASK;
651 dsts >>= DSTS_SOFFN_SHIFT;
652
653 return dsts;
654}
655
656/**
657 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
658 * DMA descriptor chain prepared for specific endpoint
659 * @hs_ep: The endpoint
660 *
661 * Return the maximum data that can be queued in one go on a given endpoint
662 * depending on its descriptor chain capacity so that transfers that
663 * are too long can be split.
664 */
665static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
666{
667 int is_isoc = hs_ep->isochronous;
668 unsigned int maxsize;
669
670 if (is_isoc)
671 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
672 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
673 else
674 maxsize = DEV_DMA_NBYTES_LIMIT;
675
676 /* Above size of one descriptor was chosen, multiple it */
677 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
678
679 return maxsize;
680}
681
682/*
683 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
684 * @hs_ep: The endpoint
685 * @mask: RX/TX bytes mask to be defined
686 *
687 * Returns maximum data payload for one descriptor after analyzing endpoint
688 * characteristics.
689 * DMA descriptor transfer bytes limit depends on EP type:
690 * Control out - MPS,
691 * Isochronous - descriptor rx/tx bytes bitfield limit,
692 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
693 * have concatenations from various descriptors within one packet.
694 *
695 * Selects corresponding mask for RX/TX bytes as well.
696 */
697static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
698{
699 u32 mps = hs_ep->ep.maxpacket;
700 int dir_in = hs_ep->dir_in;
701 u32 desc_size = 0;
702
703 if (!hs_ep->index && !dir_in) {
704 desc_size = mps;
705 *mask = DEV_DMA_NBYTES_MASK;
706 } else if (hs_ep->isochronous) {
707 if (dir_in) {
708 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
709 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
710 } else {
711 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
712 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
713 }
714 } else {
715 desc_size = DEV_DMA_NBYTES_LIMIT;
716 *mask = DEV_DMA_NBYTES_MASK;
717
718 /* Round down desc_size to be mps multiple */
719 desc_size -= desc_size % mps;
720 }
721
722 return desc_size;
723}
724
725/*
726 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
727 * @hs_ep: The endpoint
728 * @dma_buff: DMA address to use
729 * @len: Length of the transfer
730 *
731 * This function will iterate over descriptor chain and fill its entries
732 * with corresponding information based on transfer data.
733 */
734static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
735 dma_addr_t dma_buff,
736 unsigned int len)
737{
738 struct dwc2_hsotg *hsotg = hs_ep->parent;
739 int dir_in = hs_ep->dir_in;
740 struct dwc2_dma_desc *desc = hs_ep->desc_list;
741 u32 mps = hs_ep->ep.maxpacket;
742 u32 maxsize = 0;
743 u32 offset = 0;
744 u32 mask = 0;
745 int i;
746
747 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
748
749 hs_ep->desc_count = (len / maxsize) +
750 ((len % maxsize) ? 1 : 0);
751 if (len == 0)
752 hs_ep->desc_count = 1;
753
754 for (i = 0; i < hs_ep->desc_count; ++i) {
755 desc->status = 0;
756 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
757 << DEV_DMA_BUFF_STS_SHIFT);
758
759 if (len > maxsize) {
760 if (!hs_ep->index && !dir_in)
761 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
762
763 desc->status |= (maxsize <<
764 DEV_DMA_NBYTES_SHIFT & mask);
765 desc->buf = dma_buff + offset;
766
767 len -= maxsize;
768 offset += maxsize;
769 } else {
770 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
771
772 if (dir_in)
773 desc->status |= (len % mps) ? DEV_DMA_SHORT :
774 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
775 if (len > maxsize)
776 dev_err(hsotg->dev, "wrong len %d\n", len);
777
778 desc->status |=
779 len << DEV_DMA_NBYTES_SHIFT & mask;
780 desc->buf = dma_buff + offset;
781 }
782
783 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
784 desc->status |= (DEV_DMA_BUFF_STS_HREADY
785 << DEV_DMA_BUFF_STS_SHIFT);
786 desc++;
787 }
788}
789
790/*
791 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
792 * @hs_ep: The isochronous endpoint.
793 * @dma_buff: usb requests dma buffer.
794 * @len: usb request transfer length.
795 *
796 * Finds out index of first free entry either in the bottom or up half of
797 * descriptor chain depend on which is under SW control and not processed
798 * by HW. Then fills that descriptor with the data of the arrived usb request,
799 * frame info, sets Last and IOC bits increments next_desc. If filled
800 * descriptor is not the first one, removes L bit from the previous descriptor
801 * status.
802 */
803static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
804 dma_addr_t dma_buff, unsigned int len)
805{
806 struct dwc2_dma_desc *desc;
807 struct dwc2_hsotg *hsotg = hs_ep->parent;
808 u32 index;
809 u32 maxsize = 0;
810 u32 mask = 0;
811
812 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
813 if (len > maxsize) {
814 dev_err(hsotg->dev, "wrong len %d\n", len);
815 return -EINVAL;
816 }
817
818 /*
819 * If SW has already filled half of chain, then return and wait for
820 * the other chain to be processed by HW.
821 */
822 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
823 return -EBUSY;
824
825 /* Increment frame number by interval for IN */
826 if (hs_ep->dir_in)
827 dwc2_gadget_incr_frame_num(hs_ep);
828
829 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
830 hs_ep->next_desc;
831
832 /* Sanity check of calculated index */
833 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
834 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
835 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
836 return -EINVAL;
837 }
838
839 desc = &hs_ep->desc_list[index];
840
841 /* Clear L bit of previous desc if more than one entries in the chain */
842 if (hs_ep->next_desc)
843 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
844
845 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
846 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
847
848 desc->status = 0;
849 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
850
851 desc->buf = dma_buff;
852 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
853 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
854
855 if (hs_ep->dir_in) {
856 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
857 DEV_DMA_ISOC_PID_MASK) |
858 ((len % hs_ep->ep.maxpacket) ?
859 DEV_DMA_SHORT : 0) |
860 ((hs_ep->target_frame <<
861 DEV_DMA_ISOC_FRNUM_SHIFT) &
862 DEV_DMA_ISOC_FRNUM_MASK);
863 }
864
865 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
866 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
867
868 /* Update index of last configured entry in the chain */
869 hs_ep->next_desc++;
870
871 return 0;
872}
873
874/*
875 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
876 * @hs_ep: The isochronous endpoint.
877 *
878 * Prepare first descriptor chain for isochronous endpoints. Afterwards
879 * write DMA address to HW and enable the endpoint.
880 *
881 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
882 * to prepare second descriptor chain while first one is being processed by HW.
883 */
884static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
885{
886 struct dwc2_hsotg *hsotg = hs_ep->parent;
887 struct dwc2_hsotg_req *hs_req, *treq;
888 int index = hs_ep->index;
889 int ret;
890 u32 dma_reg;
891 u32 depctl;
892 u32 ctrl;
893
894 if (list_empty(&hs_ep->queue)) {
895 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
896 return;
897 }
898
899 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
900 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
901 hs_req->req.length);
902 if (ret) {
903 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
904 break;
905 }
906 }
907
908 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
909 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
910
911 /* write descriptor chain address to control register */
912 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
913
914 ctrl = dwc2_readl(hsotg->regs + depctl);
915 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
916 dwc2_writel(ctrl, hsotg->regs + depctl);
917
918 /* Switch ISOC descriptor chain number being processed by SW*/
919 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
920 hs_ep->next_desc = 0;
921}
922
923/**
924 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
925 * @hsotg: The controller state.
926 * @hs_ep: The endpoint to process a request for
927 * @hs_req: The request to start.
928 * @continuing: True if we are doing more for the current request.
929 *
930 * Start the given request running by setting the endpoint registers
931 * appropriately, and writing any data to the FIFOs.
932 */
933static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
934 struct dwc2_hsotg_ep *hs_ep,
935 struct dwc2_hsotg_req *hs_req,
936 bool continuing)
937{
938 struct usb_request *ureq = &hs_req->req;
939 int index = hs_ep->index;
940 int dir_in = hs_ep->dir_in;
941 u32 epctrl_reg;
942 u32 epsize_reg;
943 u32 epsize;
944 u32 ctrl;
945 unsigned int length;
946 unsigned int packets;
947 unsigned int maxreq;
948 unsigned int dma_reg;
949
950 if (index != 0) {
951 if (hs_ep->req && !continuing) {
952 dev_err(hsotg->dev, "%s: active request\n", __func__);
953 WARN_ON(1);
954 return;
955 } else if (hs_ep->req != hs_req && continuing) {
956 dev_err(hsotg->dev,
957 "%s: continue different req\n", __func__);
958 WARN_ON(1);
959 return;
960 }
961 }
962
963 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
964 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
965 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
966
967 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
968 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
969 hs_ep->dir_in ? "in" : "out");
970
971 /* If endpoint is stalled, we will restart request later */
972 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
973
974 if (index && ctrl & DXEPCTL_STALL) {
975 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
976 return;
977 }
978
979 length = ureq->length - ureq->actual;
980 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
981 ureq->length, ureq->actual);
982
983 if (!using_desc_dma(hsotg))
984 maxreq = get_ep_limit(hs_ep);
985 else
986 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
987
988 if (length > maxreq) {
989 int round = maxreq % hs_ep->ep.maxpacket;
990
991 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
992 __func__, length, maxreq, round);
993
994 /* round down to multiple of packets */
995 if (round)
996 maxreq -= round;
997
998 length = maxreq;
999 }
1000
1001 if (length)
1002 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1003 else
1004 packets = 1; /* send one packet if length is zero. */
1005
1006 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1007 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1008 return;
1009 }
1010
1011 if (dir_in && index != 0)
1012 if (hs_ep->isochronous)
1013 epsize = DXEPTSIZ_MC(packets);
1014 else
1015 epsize = DXEPTSIZ_MC(1);
1016 else
1017 epsize = 0;
1018
1019 /*
1020 * zero length packet should be programmed on its own and should not
1021 * be counted in DIEPTSIZ.PktCnt with other packets.
1022 */
1023 if (dir_in && ureq->zero && !continuing) {
1024 /* Test if zlp is actually required. */
1025 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1026 !(ureq->length % hs_ep->ep.maxpacket))
1027 hs_ep->send_zlp = 1;
1028 }
1029
1030 epsize |= DXEPTSIZ_PKTCNT(packets);
1031 epsize |= DXEPTSIZ_XFERSIZE(length);
1032
1033 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1034 __func__, packets, length, ureq->length, epsize, epsize_reg);
1035
1036 /* store the request as the current one we're doing */
1037 hs_ep->req = hs_req;
1038
1039 if (using_desc_dma(hsotg)) {
1040 u32 offset = 0;
1041 u32 mps = hs_ep->ep.maxpacket;
1042
1043 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1044 if (!dir_in) {
1045 if (!index)
1046 length = mps;
1047 else if (length % mps)
1048 length += (mps - (length % mps));
1049 }
1050
1051 /*
1052 * If more data to send, adjust DMA for EP0 out data stage.
1053 * ureq->dma stays unchanged, hence increment it by already
1054 * passed passed data count before starting new transaction.
1055 */
1056 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1057 continuing)
1058 offset = ureq->actual;
1059
1060 /* Fill DDMA chain entries */
1061 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1062 length);
1063
1064 /* write descriptor chain address to control register */
1065 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1066
1067 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1068 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1069 } else {
1070 /* write size / packets */
1071 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1072
1073 if (using_dma(hsotg) && !continuing && (length != 0)) {
1074 /*
1075 * write DMA address to control register, buffer
1076 * already synced by dwc2_hsotg_ep_queue().
1077 */
1078
1079 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1080
1081 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1082 __func__, &ureq->dma, dma_reg);
1083 }
1084 }
1085
1086 if (hs_ep->isochronous && hs_ep->interval == 1) {
1087 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1088 dwc2_gadget_incr_frame_num(hs_ep);
1089
1090 if (hs_ep->target_frame & 0x1)
1091 ctrl |= DXEPCTL_SETODDFR;
1092 else
1093 ctrl |= DXEPCTL_SETEVENFR;
1094 }
1095
1096 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1097
1098 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1099
1100 /* For Setup request do not clear NAK */
1101 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1102 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1103
1104 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1105 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1106
1107 /*
1108 * set these, it seems that DMA support increments past the end
1109 * of the packet buffer so we need to calculate the length from
1110 * this information.
1111 */
1112 hs_ep->size_loaded = length;
1113 hs_ep->last_load = ureq->actual;
1114
1115 if (dir_in && !using_dma(hsotg)) {
1116 /* set these anyway, we may need them for non-periodic in */
1117 hs_ep->fifo_load = 0;
1118
1119 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1120 }
1121
1122 /*
1123 * Note, trying to clear the NAK here causes problems with transmit
1124 * on the S3C6400 ending up with the TXFIFO becoming full.
1125 */
1126
1127 /* check ep is enabled */
1128 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1129 dev_dbg(hsotg->dev,
1130 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1131 index, dwc2_readl(hsotg->regs + epctrl_reg));
1132
1133 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1134 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1135
1136 /* enable ep interrupts */
1137 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1138}
1139
1140/**
1141 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1142 * @hsotg: The device state.
1143 * @hs_ep: The endpoint the request is on.
1144 * @req: The request being processed.
1145 *
1146 * We've been asked to queue a request, so ensure that the memory buffer
1147 * is correctly setup for DMA. If we've been passed an extant DMA address
1148 * then ensure the buffer has been synced to memory. If our buffer has no
1149 * DMA memory, then we map the memory and mark our request to allow us to
1150 * cleanup on completion.
1151 */
1152static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1153 struct dwc2_hsotg_ep *hs_ep,
1154 struct usb_request *req)
1155{
1156 int ret;
1157
1158 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1159 if (ret)
1160 goto dma_error;
1161
1162 return 0;
1163
1164dma_error:
1165 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1166 __func__, req->buf, req->length);
1167
1168 return -EIO;
1169}
1170
1171static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1172 struct dwc2_hsotg_ep *hs_ep,
1173 struct dwc2_hsotg_req *hs_req)
1174{
1175 void *req_buf = hs_req->req.buf;
1176
1177 /* If dma is not being used or buffer is aligned */
1178 if (!using_dma(hsotg) || !((long)req_buf & 3))
1179 return 0;
1180
1181 WARN_ON(hs_req->saved_req_buf);
1182
1183 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1184 hs_ep->ep.name, req_buf, hs_req->req.length);
1185
1186 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1187 if (!hs_req->req.buf) {
1188 hs_req->req.buf = req_buf;
1189 dev_err(hsotg->dev,
1190 "%s: unable to allocate memory for bounce buffer\n",
1191 __func__);
1192 return -ENOMEM;
1193 }
1194
1195 /* Save actual buffer */
1196 hs_req->saved_req_buf = req_buf;
1197
1198 if (hs_ep->dir_in)
1199 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1200 return 0;
1201}
1202
1203static void
1204dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1205 struct dwc2_hsotg_ep *hs_ep,
1206 struct dwc2_hsotg_req *hs_req)
1207{
1208 /* If dma is not being used or buffer was aligned */
1209 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1210 return;
1211
1212 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1213 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1214
1215 /* Copy data from bounce buffer on successful out transfer */
1216 if (!hs_ep->dir_in && !hs_req->req.status)
1217 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1218 hs_req->req.actual);
1219
1220 /* Free bounce buffer */
1221 kfree(hs_req->req.buf);
1222
1223 hs_req->req.buf = hs_req->saved_req_buf;
1224 hs_req->saved_req_buf = NULL;
1225}
1226
1227/**
1228 * dwc2_gadget_target_frame_elapsed - Checks target frame
1229 * @hs_ep: The driver endpoint to check
1230 *
1231 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1232 * corresponding transfer.
1233 */
1234static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1235{
1236 struct dwc2_hsotg *hsotg = hs_ep->parent;
1237 u32 target_frame = hs_ep->target_frame;
1238 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1239 bool frame_overrun = hs_ep->frame_overrun;
1240
1241 if (!frame_overrun && current_frame >= target_frame)
1242 return true;
1243
1244 if (frame_overrun && current_frame >= target_frame &&
1245 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1246 return true;
1247
1248 return false;
1249}
1250
1251/*
1252 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1253 * @hsotg: The driver state
1254 * @hs_ep: the ep descriptor chain is for
1255 *
1256 * Called to update EP0 structure's pointers depend on stage of
1257 * control transfer.
1258 */
1259static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1260 struct dwc2_hsotg_ep *hs_ep)
1261{
1262 switch (hsotg->ep0_state) {
1263 case DWC2_EP0_SETUP:
1264 case DWC2_EP0_STATUS_OUT:
1265 hs_ep->desc_list = hsotg->setup_desc[0];
1266 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1267 break;
1268 case DWC2_EP0_DATA_IN:
1269 case DWC2_EP0_STATUS_IN:
1270 hs_ep->desc_list = hsotg->ctrl_in_desc;
1271 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1272 break;
1273 case DWC2_EP0_DATA_OUT:
1274 hs_ep->desc_list = hsotg->ctrl_out_desc;
1275 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1276 break;
1277 default:
1278 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1279 hsotg->ep0_state);
1280 return -EINVAL;
1281 }
1282
1283 return 0;
1284}
1285
1286static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1287 gfp_t gfp_flags)
1288{
1289 struct dwc2_hsotg_req *hs_req = our_req(req);
1290 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1291 struct dwc2_hsotg *hs = hs_ep->parent;
1292 bool first;
1293 int ret;
1294
1295 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1296 ep->name, req, req->length, req->buf, req->no_interrupt,
1297 req->zero, req->short_not_ok);
1298
1299 /* Prevent new request submission when controller is suspended */
1300 if (hs->lx_state != DWC2_L0) {
1301 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1302 __func__);
1303 return -EAGAIN;
1304 }
1305
1306 /* initialise status of the request */
1307 INIT_LIST_HEAD(&hs_req->queue);
1308 req->actual = 0;
1309 req->status = -EINPROGRESS;
1310
1311 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1312 if (ret)
1313 return ret;
1314
1315 /* if we're using DMA, sync the buffers as necessary */
1316 if (using_dma(hs)) {
1317 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1318 if (ret)
1319 return ret;
1320 }
1321 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1322 if (using_desc_dma(hs) && !hs_ep->index) {
1323 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1324 if (ret)
1325 return ret;
1326 }
1327
1328 first = list_empty(&hs_ep->queue);
1329 list_add_tail(&hs_req->queue, &hs_ep->queue);
1330
1331 /*
1332 * Handle DDMA isochronous transfers separately - just add new entry
1333 * to the half of descriptor chain that is not processed by HW.
1334 * Transfer will be started once SW gets either one of NAK or
1335 * OutTknEpDis interrupts.
1336 */
1337 if (using_desc_dma(hs) && hs_ep->isochronous &&
1338 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1339 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1340 hs_req->req.length);
1341 if (ret)
1342 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1343
1344 return 0;
1345 }
1346
1347 if (first) {
1348 if (!hs_ep->isochronous) {
1349 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1350 return 0;
1351 }
1352
1353 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1354 dwc2_gadget_incr_frame_num(hs_ep);
1355
1356 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1357 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1358 }
1359 return 0;
1360}
1361
1362static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1363 gfp_t gfp_flags)
1364{
1365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1366 struct dwc2_hsotg *hs = hs_ep->parent;
1367 unsigned long flags = 0;
1368 int ret = 0;
1369
1370 spin_lock_irqsave(&hs->lock, flags);
1371 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1372 spin_unlock_irqrestore(&hs->lock, flags);
1373
1374 return ret;
1375}
1376
1377static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1378 struct usb_request *req)
1379{
1380 struct dwc2_hsotg_req *hs_req = our_req(req);
1381
1382 kfree(hs_req);
1383}
1384
1385/**
1386 * dwc2_hsotg_complete_oursetup - setup completion callback
1387 * @ep: The endpoint the request was on.
1388 * @req: The request completed.
1389 *
1390 * Called on completion of any requests the driver itself
1391 * submitted that need cleaning up.
1392 */
1393static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1394 struct usb_request *req)
1395{
1396 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1397 struct dwc2_hsotg *hsotg = hs_ep->parent;
1398
1399 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1400
1401 dwc2_hsotg_ep_free_request(ep, req);
1402}
1403
1404/**
1405 * ep_from_windex - convert control wIndex value to endpoint
1406 * @hsotg: The driver state.
1407 * @windex: The control request wIndex field (in host order).
1408 *
1409 * Convert the given wIndex into a pointer to an driver endpoint
1410 * structure, or return NULL if it is not a valid endpoint.
1411 */
1412static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1413 u32 windex)
1414{
1415 struct dwc2_hsotg_ep *ep;
1416 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1417 int idx = windex & 0x7F;
1418
1419 if (windex >= 0x100)
1420 return NULL;
1421
1422 if (idx > hsotg->num_of_eps)
1423 return NULL;
1424
1425 ep = index_to_ep(hsotg, idx, dir);
1426
1427 if (idx && ep->dir_in != dir)
1428 return NULL;
1429
1430 return ep;
1431}
1432
1433/**
1434 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1435 * @hsotg: The driver state.
1436 * @testmode: requested usb test mode
1437 * Enable usb Test Mode requested by the Host.
1438 */
1439int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1440{
1441 int dctl = dwc2_readl(hsotg->regs + DCTL);
1442
1443 dctl &= ~DCTL_TSTCTL_MASK;
1444 switch (testmode) {
1445 case TEST_J:
1446 case TEST_K:
1447 case TEST_SE0_NAK:
1448 case TEST_PACKET:
1449 case TEST_FORCE_EN:
1450 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1451 break;
1452 default:
1453 return -EINVAL;
1454 }
1455 dwc2_writel(dctl, hsotg->regs + DCTL);
1456 return 0;
1457}
1458
1459/**
1460 * dwc2_hsotg_send_reply - send reply to control request
1461 * @hsotg: The device state
1462 * @ep: Endpoint 0
1463 * @buff: Buffer for request
1464 * @length: Length of reply.
1465 *
1466 * Create a request and queue it on the given endpoint. This is useful as
1467 * an internal method of sending replies to certain control requests, etc.
1468 */
1469static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1470 struct dwc2_hsotg_ep *ep,
1471 void *buff,
1472 int length)
1473{
1474 struct usb_request *req;
1475 int ret;
1476
1477 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1478
1479 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1480 hsotg->ep0_reply = req;
1481 if (!req) {
1482 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1483 return -ENOMEM;
1484 }
1485
1486 req->buf = hsotg->ep0_buff;
1487 req->length = length;
1488 /*
1489 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1490 * STATUS stage.
1491 */
1492 req->zero = 0;
1493 req->complete = dwc2_hsotg_complete_oursetup;
1494
1495 if (length)
1496 memcpy(req->buf, buff, length);
1497
1498 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1499 if (ret) {
1500 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1501 return ret;
1502 }
1503
1504 return 0;
1505}
1506
1507/**
1508 * dwc2_hsotg_process_req_status - process request GET_STATUS
1509 * @hsotg: The device state
1510 * @ctrl: USB control request
1511 */
1512static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1513 struct usb_ctrlrequest *ctrl)
1514{
1515 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1516 struct dwc2_hsotg_ep *ep;
1517 __le16 reply;
1518 int ret;
1519
1520 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1521
1522 if (!ep0->dir_in) {
1523 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1524 return -EINVAL;
1525 }
1526
1527 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1528 case USB_RECIP_DEVICE:
1529 /*
1530 * bit 0 => self powered
1531 * bit 1 => remote wakeup
1532 */
1533 reply = cpu_to_le16(0);
1534 break;
1535
1536 case USB_RECIP_INTERFACE:
1537 /* currently, the data result should be zero */
1538 reply = cpu_to_le16(0);
1539 break;
1540
1541 case USB_RECIP_ENDPOINT:
1542 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1543 if (!ep)
1544 return -ENOENT;
1545
1546 reply = cpu_to_le16(ep->halted ? 1 : 0);
1547 break;
1548
1549 default:
1550 return 0;
1551 }
1552
1553 if (le16_to_cpu(ctrl->wLength) != 2)
1554 return -EINVAL;
1555
1556 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1557 if (ret) {
1558 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1559 return ret;
1560 }
1561
1562 return 1;
1563}
1564
1565static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1566
1567/**
1568 * get_ep_head - return the first request on the endpoint
1569 * @hs_ep: The controller endpoint to get
1570 *
1571 * Get the first request on the endpoint.
1572 */
1573static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1574{
1575 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1576 queue);
1577}
1578
1579/**
1580 * dwc2_gadget_start_next_request - Starts next request from ep queue
1581 * @hs_ep: Endpoint structure
1582 *
1583 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1584 * in its handler. Hence we need to unmask it here to be able to do
1585 * resynchronization.
1586 */
1587static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1588{
1589 u32 mask;
1590 struct dwc2_hsotg *hsotg = hs_ep->parent;
1591 int dir_in = hs_ep->dir_in;
1592 struct dwc2_hsotg_req *hs_req;
1593 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1594
1595 if (!list_empty(&hs_ep->queue)) {
1596 hs_req = get_ep_head(hs_ep);
1597 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1598 return;
1599 }
1600 if (!hs_ep->isochronous)
1601 return;
1602
1603 if (dir_in) {
1604 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1605 __func__);
1606 } else {
1607 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1608 __func__);
1609 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1610 mask |= DOEPMSK_OUTTKNEPDISMSK;
1611 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1612 }
1613}
1614
1615/**
1616 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1617 * @hsotg: The device state
1618 * @ctrl: USB control request
1619 */
1620static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1621 struct usb_ctrlrequest *ctrl)
1622{
1623 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1624 struct dwc2_hsotg_req *hs_req;
1625 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1626 struct dwc2_hsotg_ep *ep;
1627 int ret;
1628 bool halted;
1629 u32 recip;
1630 u32 wValue;
1631 u32 wIndex;
1632
1633 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1634 __func__, set ? "SET" : "CLEAR");
1635
1636 wValue = le16_to_cpu(ctrl->wValue);
1637 wIndex = le16_to_cpu(ctrl->wIndex);
1638 recip = ctrl->bRequestType & USB_RECIP_MASK;
1639
1640 switch (recip) {
1641 case USB_RECIP_DEVICE:
1642 switch (wValue) {
1643 case USB_DEVICE_REMOTE_WAKEUP:
1644 hsotg->remote_wakeup_allowed = 1;
1645 break;
1646
1647 case USB_DEVICE_TEST_MODE:
1648 if ((wIndex & 0xff) != 0)
1649 return -EINVAL;
1650 if (!set)
1651 return -EINVAL;
1652
1653 hsotg->test_mode = wIndex >> 8;
1654 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1655 if (ret) {
1656 dev_err(hsotg->dev,
1657 "%s: failed to send reply\n", __func__);
1658 return ret;
1659 }
1660 break;
1661 default:
1662 return -ENOENT;
1663 }
1664 break;
1665
1666 case USB_RECIP_ENDPOINT:
1667 ep = ep_from_windex(hsotg, wIndex);
1668 if (!ep) {
1669 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1670 __func__, wIndex);
1671 return -ENOENT;
1672 }
1673
1674 switch (wValue) {
1675 case USB_ENDPOINT_HALT:
1676 halted = ep->halted;
1677
1678 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1679
1680 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1681 if (ret) {
1682 dev_err(hsotg->dev,
1683 "%s: failed to send reply\n", __func__);
1684 return ret;
1685 }
1686
1687 /*
1688 * we have to complete all requests for ep if it was
1689 * halted, and the halt was cleared by CLEAR_FEATURE
1690 */
1691
1692 if (!set && halted) {
1693 /*
1694 * If we have request in progress,
1695 * then complete it
1696 */
1697 if (ep->req) {
1698 hs_req = ep->req;
1699 ep->req = NULL;
1700 list_del_init(&hs_req->queue);
1701 if (hs_req->req.complete) {
1702 spin_unlock(&hsotg->lock);
1703 usb_gadget_giveback_request(
1704 &ep->ep, &hs_req->req);
1705 spin_lock(&hsotg->lock);
1706 }
1707 }
1708
1709 /* If we have pending request, then start it */
1710 if (!ep->req)
1711 dwc2_gadget_start_next_request(ep);
1712 }
1713
1714 break;
1715
1716 default:
1717 return -ENOENT;
1718 }
1719 break;
1720 default:
1721 return -ENOENT;
1722 }
1723 return 1;
1724}
1725
1726static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1727
1728/**
1729 * dwc2_hsotg_stall_ep0 - stall ep0
1730 * @hsotg: The device state
1731 *
1732 * Set stall for ep0 as response for setup request.
1733 */
1734static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1735{
1736 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1737 u32 reg;
1738 u32 ctrl;
1739
1740 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1741 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1742
1743 /*
1744 * DxEPCTL_Stall will be cleared by EP once it has
1745 * taken effect, so no need to clear later.
1746 */
1747
1748 ctrl = dwc2_readl(hsotg->regs + reg);
1749 ctrl |= DXEPCTL_STALL;
1750 ctrl |= DXEPCTL_CNAK;
1751 dwc2_writel(ctrl, hsotg->regs + reg);
1752
1753 dev_dbg(hsotg->dev,
1754 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1755 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1756
1757 /*
1758 * complete won't be called, so we enqueue
1759 * setup request here
1760 */
1761 dwc2_hsotg_enqueue_setup(hsotg);
1762}
1763
1764/**
1765 * dwc2_hsotg_process_control - process a control request
1766 * @hsotg: The device state
1767 * @ctrl: The control request received
1768 *
1769 * The controller has received the SETUP phase of a control request, and
1770 * needs to work out what to do next (and whether to pass it on to the
1771 * gadget driver).
1772 */
1773static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1774 struct usb_ctrlrequest *ctrl)
1775{
1776 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1777 int ret = 0;
1778 u32 dcfg;
1779
1780 dev_dbg(hsotg->dev,
1781 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1782 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1783 ctrl->wIndex, ctrl->wLength);
1784
1785 if (ctrl->wLength == 0) {
1786 ep0->dir_in = 1;
1787 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1788 } else if (ctrl->bRequestType & USB_DIR_IN) {
1789 ep0->dir_in = 1;
1790 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1791 } else {
1792 ep0->dir_in = 0;
1793 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1794 }
1795
1796 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1797 switch (ctrl->bRequest) {
1798 case USB_REQ_SET_ADDRESS:
1799 hsotg->connected = 1;
1800 dcfg = dwc2_readl(hsotg->regs + DCFG);
1801 dcfg &= ~DCFG_DEVADDR_MASK;
1802 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1803 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1804 dwc2_writel(dcfg, hsotg->regs + DCFG);
1805
1806 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1807
1808 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1809 return;
1810
1811 case USB_REQ_GET_STATUS:
1812 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1813 break;
1814
1815 case USB_REQ_CLEAR_FEATURE:
1816 case USB_REQ_SET_FEATURE:
1817 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1818 break;
1819 }
1820 }
1821
1822 /* as a fallback, try delivering it to the driver to deal with */
1823
1824 if (ret == 0 && hsotg->driver) {
1825 spin_unlock(&hsotg->lock);
1826 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1827 spin_lock(&hsotg->lock);
1828 if (ret < 0)
1829 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1830 }
1831
1832 /*
1833 * the request is either unhandlable, or is not formatted correctly
1834 * so respond with a STALL for the status stage to indicate failure.
1835 */
1836
1837 if (ret < 0)
1838 dwc2_hsotg_stall_ep0(hsotg);
1839}
1840
1841/**
1842 * dwc2_hsotg_complete_setup - completion of a setup transfer
1843 * @ep: The endpoint the request was on.
1844 * @req: The request completed.
1845 *
1846 * Called on completion of any requests the driver itself submitted for
1847 * EP0 setup packets
1848 */
1849static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1850 struct usb_request *req)
1851{
1852 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1853 struct dwc2_hsotg *hsotg = hs_ep->parent;
1854
1855 if (req->status < 0) {
1856 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1857 return;
1858 }
1859
1860 spin_lock(&hsotg->lock);
1861 if (req->actual == 0)
1862 dwc2_hsotg_enqueue_setup(hsotg);
1863 else
1864 dwc2_hsotg_process_control(hsotg, req->buf);
1865 spin_unlock(&hsotg->lock);
1866}
1867
1868/**
1869 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1870 * @hsotg: The device state.
1871 *
1872 * Enqueue a request on EP0 if necessary to received any SETUP packets
1873 * received from the host.
1874 */
1875static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1876{
1877 struct usb_request *req = hsotg->ctrl_req;
1878 struct dwc2_hsotg_req *hs_req = our_req(req);
1879 int ret;
1880
1881 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1882
1883 req->zero = 0;
1884 req->length = 8;
1885 req->buf = hsotg->ctrl_buff;
1886 req->complete = dwc2_hsotg_complete_setup;
1887
1888 if (!list_empty(&hs_req->queue)) {
1889 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1890 return;
1891 }
1892
1893 hsotg->eps_out[0]->dir_in = 0;
1894 hsotg->eps_out[0]->send_zlp = 0;
1895 hsotg->ep0_state = DWC2_EP0_SETUP;
1896
1897 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1898 if (ret < 0) {
1899 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1900 /*
1901 * Don't think there's much we can do other than watch the
1902 * driver fail.
1903 */
1904 }
1905}
1906
1907static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1908 struct dwc2_hsotg_ep *hs_ep)
1909{
1910 u32 ctrl;
1911 u8 index = hs_ep->index;
1912 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1913 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1914
1915 if (hs_ep->dir_in)
1916 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1917 index);
1918 else
1919 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1920 index);
1921 if (using_desc_dma(hsotg)) {
1922 /* Not specific buffer needed for ep0 ZLP */
1923 dma_addr_t dma = hs_ep->desc_list_dma;
1924
1925 if (!index)
1926 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1927
1928 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1929 } else {
1930 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1931 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1932 epsiz_reg);
1933 }
1934
1935 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1936 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1937 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1938 ctrl |= DXEPCTL_USBACTEP;
1939 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1940}
1941
1942/**
1943 * dwc2_hsotg_complete_request - complete a request given to us
1944 * @hsotg: The device state.
1945 * @hs_ep: The endpoint the request was on.
1946 * @hs_req: The request to complete.
1947 * @result: The result code (0 => Ok, otherwise errno)
1948 *
1949 * The given request has finished, so call the necessary completion
1950 * if it has one and then look to see if we can start a new request
1951 * on the endpoint.
1952 *
1953 * Note, expects the ep to already be locked as appropriate.
1954 */
1955static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1956 struct dwc2_hsotg_ep *hs_ep,
1957 struct dwc2_hsotg_req *hs_req,
1958 int result)
1959{
1960 if (!hs_req) {
1961 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1962 return;
1963 }
1964
1965 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1966 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1967
1968 /*
1969 * only replace the status if we've not already set an error
1970 * from a previous transaction
1971 */
1972
1973 if (hs_req->req.status == -EINPROGRESS)
1974 hs_req->req.status = result;
1975
1976 if (using_dma(hsotg))
1977 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1978
1979 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1980
1981 hs_ep->req = NULL;
1982 list_del_init(&hs_req->queue);
1983
1984 /*
1985 * call the complete request with the locks off, just in case the
1986 * request tries to queue more work for this endpoint.
1987 */
1988
1989 if (hs_req->req.complete) {
1990 spin_unlock(&hsotg->lock);
1991 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1992 spin_lock(&hsotg->lock);
1993 }
1994
1995 /* In DDMA don't need to proceed to starting of next ISOC request */
1996 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1997 return;
1998
1999 /*
2000 * Look to see if there is anything else to do. Note, the completion
2001 * of the previous request may have caused a new request to be started
2002 * so be careful when doing this.
2003 */
2004
2005 if (!hs_ep->req && result >= 0)
2006 dwc2_gadget_start_next_request(hs_ep);
2007}
2008
2009/*
2010 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2011 * @hs_ep: The endpoint the request was on.
2012 *
2013 * Get first request from the ep queue, determine descriptor on which complete
2014 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2015 * chain is currently in use by HW, adjusts dma_address and calculates index
2016 * of completed descriptor based on the value of DEPDMA register. Update actual
2017 * length of request, giveback to gadget.
2018 */
2019static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2020{
2021 struct dwc2_hsotg *hsotg = hs_ep->parent;
2022 struct dwc2_hsotg_req *hs_req;
2023 struct usb_request *ureq;
2024 int index;
2025 dma_addr_t dma_addr;
2026 u32 dma_reg;
2027 u32 depdma;
2028 u32 desc_sts;
2029 u32 mask;
2030
2031 hs_req = get_ep_head(hs_ep);
2032 if (!hs_req) {
2033 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2034 return;
2035 }
2036 ureq = &hs_req->req;
2037
2038 dma_addr = hs_ep->desc_list_dma;
2039
2040 /*
2041 * If lower half of descriptor chain is currently use by SW,
2042 * that means higher half is being processed by HW, so shift
2043 * DMA address to higher half of descriptor chain.
2044 */
2045 if (!hs_ep->isoc_chain_num)
2046 dma_addr += sizeof(struct dwc2_dma_desc) *
2047 (MAX_DMA_DESC_NUM_GENERIC / 2);
2048
2049 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
2050 depdma = dwc2_readl(hsotg->regs + dma_reg);
2051
2052 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
2053 desc_sts = hs_ep->desc_list[index].status;
2054
2055 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2056 DEV_DMA_ISOC_RX_NBYTES_MASK;
2057 ureq->actual = ureq->length -
2058 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2059
2060 /* Adjust actual length for ISOC Out if length is not align of 4 */
2061 if (!hs_ep->dir_in && ureq->length & 0x3)
2062 ureq->actual += 4 - (ureq->length & 0x3);
2063
2064 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2065}
2066
2067/*
2068 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2069 * @hs_ep: The isochronous endpoint to be re-enabled.
2070 *
2071 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2072 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2073 * was under SW control till HW was busy and restart the endpoint if needed.
2074 */
2075static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2076{
2077 struct dwc2_hsotg *hsotg = hs_ep->parent;
2078 u32 depctl;
2079 u32 dma_reg;
2080 u32 ctrl;
2081 u32 dma_addr = hs_ep->desc_list_dma;
2082 unsigned char index = hs_ep->index;
2083
2084 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2085 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2086
2087 ctrl = dwc2_readl(hsotg->regs + depctl);
2088
2089 /*
2090 * EP was disabled if HW has processed last descriptor or BNA was set.
2091 * So restart ep if SW has prepared new descriptor chain in ep_queue
2092 * routine while HW was busy.
2093 */
2094 if (!(ctrl & DXEPCTL_EPENA)) {
2095 if (!hs_ep->next_desc) {
2096 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2097 __func__);
2098 return;
2099 }
2100
2101 dma_addr += sizeof(struct dwc2_dma_desc) *
2102 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2103 hs_ep->isoc_chain_num;
2104 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2105
2106 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2107 dwc2_writel(ctrl, hsotg->regs + depctl);
2108
2109 /* Switch ISOC descriptor chain number being processed by SW*/
2110 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2111 hs_ep->next_desc = 0;
2112
2113 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2114 __func__);
2115 }
2116}
2117
2118/**
2119 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2120 * @hsotg: The device state.
2121 * @ep_idx: The endpoint index for the data
2122 * @size: The size of data in the fifo, in bytes
2123 *
2124 * The FIFO status shows there is data to read from the FIFO for a given
2125 * endpoint, so sort out whether we need to read the data into a request
2126 * that has been made for that endpoint.
2127 */
2128static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2129{
2130 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2131 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2132 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2133 int to_read;
2134 int max_req;
2135 int read_ptr;
2136
2137 if (!hs_req) {
2138 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2139 int ptr;
2140
2141 dev_dbg(hsotg->dev,
2142 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2143 __func__, size, ep_idx, epctl);
2144
2145 /* dump the data from the FIFO, we've nothing we can do */
2146 for (ptr = 0; ptr < size; ptr += 4)
2147 (void)dwc2_readl(fifo);
2148
2149 return;
2150 }
2151
2152 to_read = size;
2153 read_ptr = hs_req->req.actual;
2154 max_req = hs_req->req.length - read_ptr;
2155
2156 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2157 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2158
2159 if (to_read > max_req) {
2160 /*
2161 * more data appeared than we where willing
2162 * to deal with in this request.
2163 */
2164
2165 /* currently we don't deal this */
2166 WARN_ON_ONCE(1);
2167 }
2168
2169 hs_ep->total_data += to_read;
2170 hs_req->req.actual += to_read;
2171 to_read = DIV_ROUND_UP(to_read, 4);
2172
2173 /*
2174 * note, we might over-write the buffer end by 3 bytes depending on
2175 * alignment of the data.
2176 */
2177 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2178}
2179
2180/**
2181 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2182 * @hsotg: The device instance
2183 * @dir_in: If IN zlp
2184 *
2185 * Generate a zero-length IN packet request for terminating a SETUP
2186 * transaction.
2187 *
2188 * Note, since we don't write any data to the TxFIFO, then it is
2189 * currently believed that we do not need to wait for any space in
2190 * the TxFIFO.
2191 */
2192static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2193{
2194 /* eps_out[0] is used in both directions */
2195 hsotg->eps_out[0]->dir_in = dir_in;
2196 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2197
2198 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2199}
2200
2201static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2202 u32 epctl_reg)
2203{
2204 u32 ctrl;
2205
2206 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2207 if (ctrl & DXEPCTL_EOFRNUM)
2208 ctrl |= DXEPCTL_SETEVENFR;
2209 else
2210 ctrl |= DXEPCTL_SETODDFR;
2211 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2212}
2213
2214/*
2215 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2216 * @hs_ep - The endpoint on which transfer went
2217 *
2218 * Iterate over endpoints descriptor chain and get info on bytes remained
2219 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2220 */
2221static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2222{
2223 struct dwc2_hsotg *hsotg = hs_ep->parent;
2224 unsigned int bytes_rem = 0;
2225 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2226 int i;
2227 u32 status;
2228
2229 if (!desc)
2230 return -EINVAL;
2231
2232 for (i = 0; i < hs_ep->desc_count; ++i) {
2233 status = desc->status;
2234 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2235
2236 if (status & DEV_DMA_STS_MASK)
2237 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2238 i, status & DEV_DMA_STS_MASK);
2239 }
2240
2241 return bytes_rem;
2242}
2243
2244/**
2245 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2246 * @hsotg: The device instance
2247 * @epnum: The endpoint received from
2248 *
2249 * The RXFIFO has delivered an OutDone event, which means that the data
2250 * transfer for an OUT endpoint has been completed, either by a short
2251 * packet or by the finish of a transfer.
2252 */
2253static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2254{
2255 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2256 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2257 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2258 struct usb_request *req = &hs_req->req;
2259 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2260 int result = 0;
2261
2262 if (!hs_req) {
2263 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2264 return;
2265 }
2266
2267 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2268 dev_dbg(hsotg->dev, "zlp packet received\n");
2269 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2270 dwc2_hsotg_enqueue_setup(hsotg);
2271 return;
2272 }
2273
2274 if (using_desc_dma(hsotg))
2275 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2276
2277 if (using_dma(hsotg)) {
2278 unsigned int size_done;
2279
2280 /*
2281 * Calculate the size of the transfer by checking how much
2282 * is left in the endpoint size register and then working it
2283 * out from the amount we loaded for the transfer.
2284 *
2285 * We need to do this as DMA pointers are always 32bit aligned
2286 * so may overshoot/undershoot the transfer.
2287 */
2288
2289 size_done = hs_ep->size_loaded - size_left;
2290 size_done += hs_ep->last_load;
2291
2292 req->actual = size_done;
2293 }
2294
2295 /* if there is more request to do, schedule new transfer */
2296 if (req->actual < req->length && size_left == 0) {
2297 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2298 return;
2299 }
2300
2301 if (req->actual < req->length && req->short_not_ok) {
2302 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2303 __func__, req->actual, req->length);
2304
2305 /*
2306 * todo - what should we return here? there's no one else
2307 * even bothering to check the status.
2308 */
2309 }
2310
2311 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2312 if (!using_desc_dma(hsotg) && epnum == 0 &&
2313 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2314 /* Move to STATUS IN */
2315 dwc2_hsotg_ep0_zlp(hsotg, true);
2316 return;
2317 }
2318
2319 /*
2320 * Slave mode OUT transfers do not go through XferComplete so
2321 * adjust the ISOC parity here.
2322 */
2323 if (!using_dma(hsotg)) {
2324 if (hs_ep->isochronous && hs_ep->interval == 1)
2325 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2326 else if (hs_ep->isochronous && hs_ep->interval > 1)
2327 dwc2_gadget_incr_frame_num(hs_ep);
2328 }
2329
2330 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2331}
2332
2333/**
2334 * dwc2_hsotg_handle_rx - RX FIFO has data
2335 * @hsotg: The device instance
2336 *
2337 * The IRQ handler has detected that the RX FIFO has some data in it
2338 * that requires processing, so find out what is in there and do the
2339 * appropriate read.
2340 *
2341 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2342 * chunks, so if you have x packets received on an endpoint you'll get x
2343 * FIFO events delivered, each with a packet's worth of data in it.
2344 *
2345 * When using DMA, we should not be processing events from the RXFIFO
2346 * as the actual data should be sent to the memory directly and we turn
2347 * on the completion interrupts to get notifications of transfer completion.
2348 */
2349static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2350{
2351 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2352 u32 epnum, status, size;
2353
2354 WARN_ON(using_dma(hsotg));
2355
2356 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2357 status = grxstsr & GRXSTS_PKTSTS_MASK;
2358
2359 size = grxstsr & GRXSTS_BYTECNT_MASK;
2360 size >>= GRXSTS_BYTECNT_SHIFT;
2361
2362 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2363 __func__, grxstsr, size, epnum);
2364
2365 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2366 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2367 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2368 break;
2369
2370 case GRXSTS_PKTSTS_OUTDONE:
2371 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2372 dwc2_hsotg_read_frameno(hsotg));
2373
2374 if (!using_dma(hsotg))
2375 dwc2_hsotg_handle_outdone(hsotg, epnum);
2376 break;
2377
2378 case GRXSTS_PKTSTS_SETUPDONE:
2379 dev_dbg(hsotg->dev,
2380 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2381 dwc2_hsotg_read_frameno(hsotg),
2382 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2383 /*
2384 * Call dwc2_hsotg_handle_outdone here if it was not called from
2385 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2386 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2387 */
2388 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2389 dwc2_hsotg_handle_outdone(hsotg, epnum);
2390 break;
2391
2392 case GRXSTS_PKTSTS_OUTRX:
2393 dwc2_hsotg_rx_data(hsotg, epnum, size);
2394 break;
2395
2396 case GRXSTS_PKTSTS_SETUPRX:
2397 dev_dbg(hsotg->dev,
2398 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2399 dwc2_hsotg_read_frameno(hsotg),
2400 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2401
2402 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2403
2404 dwc2_hsotg_rx_data(hsotg, epnum, size);
2405 break;
2406
2407 default:
2408 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2409 __func__, grxstsr);
2410
2411 dwc2_hsotg_dump(hsotg);
2412 break;
2413 }
2414}
2415
2416/**
2417 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2418 * @mps: The maximum packet size in bytes.
2419 */
2420static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2421{
2422 switch (mps) {
2423 case 64:
2424 return D0EPCTL_MPS_64;
2425 case 32:
2426 return D0EPCTL_MPS_32;
2427 case 16:
2428 return D0EPCTL_MPS_16;
2429 case 8:
2430 return D0EPCTL_MPS_8;
2431 }
2432
2433 /* bad max packet size, warn and return invalid result */
2434 WARN_ON(1);
2435 return (u32)-1;
2436}
2437
2438/**
2439 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2440 * @hsotg: The driver state.
2441 * @ep: The index number of the endpoint
2442 * @mps: The maximum packet size in bytes
2443 * @mc: The multicount value
2444 *
2445 * Configure the maximum packet size for the given endpoint, updating
2446 * the hardware control registers to reflect this.
2447 */
2448static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2449 unsigned int ep, unsigned int mps,
2450 unsigned int mc, unsigned int dir_in)
2451{
2452 struct dwc2_hsotg_ep *hs_ep;
2453 void __iomem *regs = hsotg->regs;
2454 u32 reg;
2455
2456 hs_ep = index_to_ep(hsotg, ep, dir_in);
2457 if (!hs_ep)
2458 return;
2459
2460 if (ep == 0) {
2461 u32 mps_bytes = mps;
2462
2463 /* EP0 is a special case */
2464 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2465 if (mps > 3)
2466 goto bad_mps;
2467 hs_ep->ep.maxpacket = mps_bytes;
2468 hs_ep->mc = 1;
2469 } else {
2470 if (mps > 1024)
2471 goto bad_mps;
2472 hs_ep->mc = mc;
2473 if (mc > 3)
2474 goto bad_mps;
2475 hs_ep->ep.maxpacket = mps;
2476 }
2477
2478 if (dir_in) {
2479 reg = dwc2_readl(regs + DIEPCTL(ep));
2480 reg &= ~DXEPCTL_MPS_MASK;
2481 reg |= mps;
2482 dwc2_writel(reg, regs + DIEPCTL(ep));
2483 } else {
2484 reg = dwc2_readl(regs + DOEPCTL(ep));
2485 reg &= ~DXEPCTL_MPS_MASK;
2486 reg |= mps;
2487 dwc2_writel(reg, regs + DOEPCTL(ep));
2488 }
2489
2490 return;
2491
2492bad_mps:
2493 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2494}
2495
2496/**
2497 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2498 * @hsotg: The driver state
2499 * @idx: The index for the endpoint (0..15)
2500 */
2501static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2502{
2503 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2504 hsotg->regs + GRSTCTL);
2505
2506 /* wait until the fifo is flushed */
2507 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2508 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2509 __func__);
2510}
2511
2512/**
2513 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2514 * @hsotg: The driver state
2515 * @hs_ep: The driver endpoint to check.
2516 *
2517 * Check to see if there is a request that has data to send, and if so
2518 * make an attempt to write data into the FIFO.
2519 */
2520static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2521 struct dwc2_hsotg_ep *hs_ep)
2522{
2523 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2524
2525 if (!hs_ep->dir_in || !hs_req) {
2526 /**
2527 * if request is not enqueued, we disable interrupts
2528 * for endpoints, excepting ep0
2529 */
2530 if (hs_ep->index != 0)
2531 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2532 hs_ep->dir_in, 0);
2533 return 0;
2534 }
2535
2536 if (hs_req->req.actual < hs_req->req.length) {
2537 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2538 hs_ep->index);
2539 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2540 }
2541
2542 return 0;
2543}
2544
2545/**
2546 * dwc2_hsotg_complete_in - complete IN transfer
2547 * @hsotg: The device state.
2548 * @hs_ep: The endpoint that has just completed.
2549 *
2550 * An IN transfer has been completed, update the transfer's state and then
2551 * call the relevant completion routines.
2552 */
2553static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2554 struct dwc2_hsotg_ep *hs_ep)
2555{
2556 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2557 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2558 int size_left, size_done;
2559
2560 if (!hs_req) {
2561 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2562 return;
2563 }
2564
2565 /* Finish ZLP handling for IN EP0 transactions */
2566 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2567 dev_dbg(hsotg->dev, "zlp packet sent\n");
2568
2569 /*
2570 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2571 * changed to IN. Change back to complete OUT transfer request
2572 */
2573 hs_ep->dir_in = 0;
2574
2575 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2576 if (hsotg->test_mode) {
2577 int ret;
2578
2579 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2580 if (ret < 0) {
2581 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2582 hsotg->test_mode);
2583 dwc2_hsotg_stall_ep0(hsotg);
2584 return;
2585 }
2586 }
2587 dwc2_hsotg_enqueue_setup(hsotg);
2588 return;
2589 }
2590
2591 /*
2592 * Calculate the size of the transfer by checking how much is left
2593 * in the endpoint size register and then working it out from
2594 * the amount we loaded for the transfer.
2595 *
2596 * We do this even for DMA, as the transfer may have incremented
2597 * past the end of the buffer (DMA transfers are always 32bit
2598 * aligned).
2599 */
2600 if (using_desc_dma(hsotg)) {
2601 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2602 if (size_left < 0)
2603 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2604 size_left);
2605 } else {
2606 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2607 }
2608
2609 size_done = hs_ep->size_loaded - size_left;
2610 size_done += hs_ep->last_load;
2611
2612 if (hs_req->req.actual != size_done)
2613 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2614 __func__, hs_req->req.actual, size_done);
2615
2616 hs_req->req.actual = size_done;
2617 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2618 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2619
2620 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2621 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2622 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2623 return;
2624 }
2625
2626 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2627 if (hs_ep->send_zlp) {
2628 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2629 hs_ep->send_zlp = 0;
2630 /* transfer will be completed on next complete interrupt */
2631 return;
2632 }
2633
2634 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2635 /* Move to STATUS OUT */
2636 dwc2_hsotg_ep0_zlp(hsotg, false);
2637 return;
2638 }
2639
2640 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2641}
2642
2643/**
2644 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2645 * @hsotg: The device state.
2646 * @idx: Index of ep.
2647 * @dir_in: Endpoint direction 1-in 0-out.
2648 *
2649 * Reads for endpoint with given index and direction, by masking
2650 * epint_reg with coresponding mask.
2651 */
2652static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2653 unsigned int idx, int dir_in)
2654{
2655 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2656 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2657 u32 ints;
2658 u32 mask;
2659 u32 diepempmsk;
2660
2661 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2662 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2663 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2664 mask |= DXEPINT_SETUP_RCVD;
2665
2666 ints = dwc2_readl(hsotg->regs + epint_reg);
2667 ints &= mask;
2668 return ints;
2669}
2670
2671/**
2672 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2673 * @hs_ep: The endpoint on which interrupt is asserted.
2674 *
2675 * This interrupt indicates that the endpoint has been disabled per the
2676 * application's request.
2677 *
2678 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2679 * in case of ISOC completes current request.
2680 *
2681 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2682 * request starts it.
2683 */
2684static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2685{
2686 struct dwc2_hsotg *hsotg = hs_ep->parent;
2687 struct dwc2_hsotg_req *hs_req;
2688 unsigned char idx = hs_ep->index;
2689 int dir_in = hs_ep->dir_in;
2690 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2691 int dctl = dwc2_readl(hsotg->regs + DCTL);
2692
2693 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2694
2695 if (dir_in) {
2696 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2697
2698 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2699
2700 if (hs_ep->isochronous) {
2701 dwc2_hsotg_complete_in(hsotg, hs_ep);
2702 return;
2703 }
2704
2705 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2706 int dctl = dwc2_readl(hsotg->regs + DCTL);
2707
2708 dctl |= DCTL_CGNPINNAK;
2709 dwc2_writel(dctl, hsotg->regs + DCTL);
2710 }
2711 return;
2712 }
2713
2714 if (dctl & DCTL_GOUTNAKSTS) {
2715 dctl |= DCTL_CGOUTNAK;
2716 dwc2_writel(dctl, hsotg->regs + DCTL);
2717 }
2718
2719 if (!hs_ep->isochronous)
2720 return;
2721
2722 if (list_empty(&hs_ep->queue)) {
2723 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2724 __func__, hs_ep);
2725 return;
2726 }
2727
2728 do {
2729 hs_req = get_ep_head(hs_ep);
2730 if (hs_req)
2731 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2732 -ENODATA);
2733 dwc2_gadget_incr_frame_num(hs_ep);
2734 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2735
2736 dwc2_gadget_start_next_request(hs_ep);
2737}
2738
2739/**
2740 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2741 * @hs_ep: The endpoint on which interrupt is asserted.
2742 *
2743 * This is starting point for ISOC-OUT transfer, synchronization done with
2744 * first out token received from host while corresponding EP is disabled.
2745 *
2746 * Device does not know initial frame in which out token will come. For this
2747 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2748 * getting this interrupt SW starts calculation for next transfer frame.
2749 */
2750static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2751{
2752 struct dwc2_hsotg *hsotg = ep->parent;
2753 int dir_in = ep->dir_in;
2754 u32 doepmsk;
2755 u32 tmp;
2756
2757 if (dir_in || !ep->isochronous)
2758 return;
2759
2760 /*
2761 * Store frame in which irq was asserted here, as
2762 * it can change while completing request below.
2763 */
2764 tmp = dwc2_hsotg_read_frameno(hsotg);
2765
2766 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2767
2768 if (using_desc_dma(hsotg)) {
2769 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2770 /* Start first ISO Out */
2771 ep->target_frame = tmp;
2772 dwc2_gadget_start_isoc_ddma(ep);
2773 }
2774 return;
2775 }
2776
2777 if (ep->interval > 1 &&
2778 ep->target_frame == TARGET_FRAME_INITIAL) {
2779 u32 dsts;
2780 u32 ctrl;
2781
2782 dsts = dwc2_readl(hsotg->regs + DSTS);
2783 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2784 dwc2_gadget_incr_frame_num(ep);
2785
2786 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2787 if (ep->target_frame & 0x1)
2788 ctrl |= DXEPCTL_SETODDFR;
2789 else
2790 ctrl |= DXEPCTL_SETEVENFR;
2791
2792 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2793 }
2794
2795 dwc2_gadget_start_next_request(ep);
2796 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2797 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2798 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2799}
2800
2801/**
2802 * dwc2_gadget_handle_nak - handle NAK interrupt
2803 * @hs_ep: The endpoint on which interrupt is asserted.
2804 *
2805 * This is starting point for ISOC-IN transfer, synchronization done with
2806 * first IN token received from host while corresponding EP is disabled.
2807 *
2808 * Device does not know when first one token will arrive from host. On first
2809 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2810 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2811 * sent in response to that as there was no data in FIFO. SW is basing on this
2812 * interrupt to obtain frame in which token has come and then based on the
2813 * interval calculates next frame for transfer.
2814 */
2815static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2816{
2817 struct dwc2_hsotg *hsotg = hs_ep->parent;
2818 int dir_in = hs_ep->dir_in;
2819
2820 if (!dir_in || !hs_ep->isochronous)
2821 return;
2822
2823 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2824 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2825
2826 if (using_desc_dma(hsotg)) {
2827 dwc2_gadget_start_isoc_ddma(hs_ep);
2828 return;
2829 }
2830
2831 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs +
2833 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR;
2836 else
2837 ctrl |= DXEPCTL_SETEVENFR;
2838
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2840 }
2841
2842 dwc2_hsotg_complete_request(hsotg, hs_ep,
2843 get_ep_head(hs_ep), 0);
2844 }
2845
2846 dwc2_gadget_incr_frame_num(hs_ep);
2847}
2848
2849/**
2850 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2851 * @hsotg: The driver state
2852 * @idx: The index for the endpoint (0..15)
2853 * @dir_in: Set if this is an IN endpoint
2854 *
2855 * Process and clear any interrupt pending for an individual endpoint
2856 */
2857static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2858 int dir_in)
2859{
2860 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2861 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2862 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2863 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2864 u32 ints;
2865 u32 ctrl;
2866
2867 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2868 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2869
2870 /* Clear endpoint interrupts */
2871 dwc2_writel(ints, hsotg->regs + epint_reg);
2872
2873 if (!hs_ep) {
2874 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2875 __func__, idx, dir_in ? "in" : "out");
2876 return;
2877 }
2878
2879 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2880 __func__, idx, dir_in ? "in" : "out", ints);
2881
2882 /* Don't process XferCompl interrupt if it is a setup packet */
2883 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2884 ints &= ~DXEPINT_XFERCOMPL;
2885
2886 /*
2887 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2888 * stage and xfercomplete was generated without SETUP phase done
2889 * interrupt. SW should parse received setup packet only after host's
2890 * exit from setup phase of control transfer.
2891 */
2892 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2893 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2894 ints &= ~DXEPINT_XFERCOMPL;
2895
2896 if (ints & DXEPINT_XFERCOMPL) {
2897 dev_dbg(hsotg->dev,
2898 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2899 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2900 dwc2_readl(hsotg->regs + epsiz_reg));
2901
2902 /* In DDMA handle isochronous requests separately */
2903 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2904 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2905 /* Try to start next isoc request */
2906 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2907 } else if (dir_in) {
2908 /*
2909 * We get OutDone from the FIFO, so we only
2910 * need to look at completing IN requests here
2911 * if operating slave mode
2912 */
2913 if (hs_ep->isochronous && hs_ep->interval > 1)
2914 dwc2_gadget_incr_frame_num(hs_ep);
2915
2916 dwc2_hsotg_complete_in(hsotg, hs_ep);
2917 if (ints & DXEPINT_NAKINTRPT)
2918 ints &= ~DXEPINT_NAKINTRPT;
2919
2920 if (idx == 0 && !hs_ep->req)
2921 dwc2_hsotg_enqueue_setup(hsotg);
2922 } else if (using_dma(hsotg)) {
2923 /*
2924 * We're using DMA, we need to fire an OutDone here
2925 * as we ignore the RXFIFO.
2926 */
2927 if (hs_ep->isochronous && hs_ep->interval > 1)
2928 dwc2_gadget_incr_frame_num(hs_ep);
2929
2930 dwc2_hsotg_handle_outdone(hsotg, idx);
2931 }
2932 }
2933
2934 if (ints & DXEPINT_EPDISBLD)
2935 dwc2_gadget_handle_ep_disabled(hs_ep);
2936
2937 if (ints & DXEPINT_OUTTKNEPDIS)
2938 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2939
2940 if (ints & DXEPINT_NAKINTRPT)
2941 dwc2_gadget_handle_nak(hs_ep);
2942
2943 if (ints & DXEPINT_AHBERR)
2944 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2945
2946 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2947 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2948
2949 if (using_dma(hsotg) && idx == 0) {
2950 /*
2951 * this is the notification we've received a
2952 * setup packet. In non-DMA mode we'd get this
2953 * from the RXFIFO, instead we need to process
2954 * the setup here.
2955 */
2956
2957 if (dir_in)
2958 WARN_ON_ONCE(1);
2959 else
2960 dwc2_hsotg_handle_outdone(hsotg, 0);
2961 }
2962 }
2963
2964 if (ints & DXEPINT_STSPHSERCVD) {
2965 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2966
2967 /* Safety check EP0 state when STSPHSERCVD asserted */
2968 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2969 /* Move to STATUS IN for DDMA */
2970 if (using_desc_dma(hsotg))
2971 dwc2_hsotg_ep0_zlp(hsotg, true);
2972 }
2973
2974 }
2975
2976 if (ints & DXEPINT_BACK2BACKSETUP)
2977 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2978
2979 if (ints & DXEPINT_BNAINTR) {
2980 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2981
2982 /*
2983 * Try to start next isoc request, if any.
2984 * Sometimes the endpoint remains enabled after BNA interrupt
2985 * assertion, which is not expected, hence we can enter here
2986 * couple of times.
2987 */
2988 if (hs_ep->isochronous)
2989 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2990 }
2991
2992 if (dir_in && !hs_ep->isochronous) {
2993 /* not sure if this is important, but we'll clear it anyway */
2994 if (ints & DXEPINT_INTKNTXFEMP) {
2995 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2996 __func__, idx);
2997 }
2998
2999 /* this probably means something bad is happening */
3000 if (ints & DXEPINT_INTKNEPMIS) {
3001 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3002 __func__, idx);
3003 }
3004
3005 /* FIFO has space or is empty (see GAHBCFG) */
3006 if (hsotg->dedicated_fifos &&
3007 ints & DXEPINT_TXFEMP) {
3008 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3009 __func__, idx);
3010 if (!using_dma(hsotg))
3011 dwc2_hsotg_trytx(hsotg, hs_ep);
3012 }
3013 }
3014}
3015
3016/**
3017 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3018 * @hsotg: The device state.
3019 *
3020 * Handle updating the device settings after the enumeration phase has
3021 * been completed.
3022 */
3023static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3024{
3025 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
3026 int ep0_mps = 0, ep_mps = 8;
3027
3028 /*
3029 * This should signal the finish of the enumeration phase
3030 * of the USB handshaking, so we should now know what rate
3031 * we connected at.
3032 */
3033
3034 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3035
3036 /*
3037 * note, since we're limited by the size of transfer on EP0, and
3038 * it seems IN transfers must be a even number of packets we do
3039 * not advertise a 64byte MPS on EP0.
3040 */
3041
3042 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3043 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3044 case DSTS_ENUMSPD_FS:
3045 case DSTS_ENUMSPD_FS48:
3046 hsotg->gadget.speed = USB_SPEED_FULL;
3047 ep0_mps = EP0_MPS_LIMIT;
3048 ep_mps = 1023;
3049 break;
3050
3051 case DSTS_ENUMSPD_HS:
3052 hsotg->gadget.speed = USB_SPEED_HIGH;
3053 ep0_mps = EP0_MPS_LIMIT;
3054 ep_mps = 1024;
3055 break;
3056
3057 case DSTS_ENUMSPD_LS:
3058 hsotg->gadget.speed = USB_SPEED_LOW;
3059 ep0_mps = 8;
3060 ep_mps = 8;
3061 /*
3062 * note, we don't actually support LS in this driver at the
3063 * moment, and the documentation seems to imply that it isn't
3064 * supported by the PHYs on some of the devices.
3065 */
3066 break;
3067 }
3068 dev_info(hsotg->dev, "new device is %s\n",
3069 usb_speed_string(hsotg->gadget.speed));
3070
3071 /*
3072 * we should now know the maximum packet size for an
3073 * endpoint, so set the endpoints to a default value.
3074 */
3075
3076 if (ep0_mps) {
3077 int i;
3078 /* Initialize ep0 for both in and out directions */
3079 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3080 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3081 for (i = 1; i < hsotg->num_of_eps; i++) {
3082 if (hsotg->eps_in[i])
3083 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3084 0, 1);
3085 if (hsotg->eps_out[i])
3086 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3087 0, 0);
3088 }
3089 }
3090
3091 /* ensure after enumeration our EP0 is active */
3092
3093 dwc2_hsotg_enqueue_setup(hsotg);
3094
3095 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3096 dwc2_readl(hsotg->regs + DIEPCTL0),
3097 dwc2_readl(hsotg->regs + DOEPCTL0));
3098}
3099
3100/**
3101 * kill_all_requests - remove all requests from the endpoint's queue
3102 * @hsotg: The device state.
3103 * @ep: The endpoint the requests may be on.
3104 * @result: The result code to use.
3105 *
3106 * Go through the requests on the given endpoint and mark them
3107 * completed with the given result code.
3108 */
3109static void kill_all_requests(struct dwc2_hsotg *hsotg,
3110 struct dwc2_hsotg_ep *ep,
3111 int result)
3112{
3113 struct dwc2_hsotg_req *req, *treq;
3114 unsigned int size;
3115
3116 ep->req = NULL;
3117
3118 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3119 dwc2_hsotg_complete_request(hsotg, ep, req,
3120 result);
3121
3122 if (!hsotg->dedicated_fifos)
3123 return;
3124 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3125 if (size < ep->fifo_size)
3126 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3127}
3128
3129/**
3130 * dwc2_hsotg_disconnect - disconnect service
3131 * @hsotg: The device state.
3132 *
3133 * The device has been disconnected. Remove all current
3134 * transactions and signal the gadget driver that this
3135 * has happened.
3136 */
3137void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3138{
3139 unsigned int ep;
3140
3141 if (!hsotg->connected)
3142 return;
3143
3144 hsotg->connected = 0;
3145 hsotg->test_mode = 0;
3146
3147 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3148 if (hsotg->eps_in[ep])
3149 kill_all_requests(hsotg, hsotg->eps_in[ep],
3150 -ESHUTDOWN);
3151 if (hsotg->eps_out[ep])
3152 kill_all_requests(hsotg, hsotg->eps_out[ep],
3153 -ESHUTDOWN);
3154 }
3155
3156 call_gadget(hsotg, disconnect);
3157 hsotg->lx_state = DWC2_L3;
3158
3159 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3160}
3161
3162/**
3163 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3164 * @hsotg: The device state:
3165 * @periodic: True if this is a periodic FIFO interrupt
3166 */
3167static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3168{
3169 struct dwc2_hsotg_ep *ep;
3170 int epno, ret;
3171
3172 /* look through for any more data to transmit */
3173 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3174 ep = index_to_ep(hsotg, epno, 1);
3175
3176 if (!ep)
3177 continue;
3178
3179 if (!ep->dir_in)
3180 continue;
3181
3182 if ((periodic && !ep->periodic) ||
3183 (!periodic && ep->periodic))
3184 continue;
3185
3186 ret = dwc2_hsotg_trytx(hsotg, ep);
3187 if (ret < 0)
3188 break;
3189 }
3190}
3191
3192/* IRQ flags which will trigger a retry around the IRQ loop */
3193#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3194 GINTSTS_PTXFEMP | \
3195 GINTSTS_RXFLVL)
3196
3197/**
3198 * dwc2_hsotg_core_init - issue softreset to the core
3199 * @hsotg: The device state
3200 *
3201 * Issue a soft reset to the core, and await the core finishing it.
3202 */
3203void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3204 bool is_usb_reset)
3205{
3206 u32 intmsk;
3207 u32 val;
3208 u32 usbcfg;
3209 u32 dcfg = 0;
3210
3211 /* Kill any ep0 requests as controller will be reinitialized */
3212 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3213
3214 if (!is_usb_reset)
3215 if (dwc2_core_reset(hsotg, true))
3216 return;
3217
3218 /*
3219 * we must now enable ep0 ready for host detection and then
3220 * set configuration.
3221 */
3222
3223 /* keep other bits untouched (so e.g. forced modes are not lost) */
3224 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3225 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3226 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3227
3228 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3229 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3230 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3231 /* FS/LS Dedicated Transceiver Interface */
3232 usbcfg |= GUSBCFG_PHYSEL;
3233 } else {
3234 /* set the PLL on, remove the HNP/SRP and set the PHY */
3235 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3236 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3237 (val << GUSBCFG_USBTRDTIM_SHIFT);
3238 }
3239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3240
3241 dwc2_hsotg_init_fifo(hsotg);
3242
3243 if (!is_usb_reset)
3244 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3245
3246 dcfg |= DCFG_EPMISCNT(1);
3247
3248 switch (hsotg->params.speed) {
3249 case DWC2_SPEED_PARAM_LOW:
3250 dcfg |= DCFG_DEVSPD_LS;
3251 break;
3252 case DWC2_SPEED_PARAM_FULL:
3253 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3254 dcfg |= DCFG_DEVSPD_FS48;
3255 else
3256 dcfg |= DCFG_DEVSPD_FS;
3257 break;
3258 default:
3259 dcfg |= DCFG_DEVSPD_HS;
3260 }
3261
3262 dwc2_writel(dcfg, hsotg->regs + DCFG);
3263
3264 /* Clear any pending OTG interrupts */
3265 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3266
3267 /* Clear any pending interrupts */
3268 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3269 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3270 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3271 GINTSTS_USBRST | GINTSTS_RESETDET |
3272 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3273 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3274 GINTSTS_LPMTRANRCVD;
3275
3276 if (!using_desc_dma(hsotg))
3277 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3278
3279 if (!hsotg->params.external_id_pin_ctl)
3280 intmsk |= GINTSTS_CONIDSTSCHNG;
3281
3282 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3283
3284 if (using_dma(hsotg)) {
3285 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3286 hsotg->params.ahbcfg,
3287 hsotg->regs + GAHBCFG);
3288
3289 /* Set DDMA mode support in the core if needed */
3290 if (using_desc_dma(hsotg))
3291 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3292
3293 } else {
3294 dwc2_writel(((hsotg->dedicated_fifos) ?
3295 (GAHBCFG_NP_TXF_EMP_LVL |
3296 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3297 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3298 }
3299
3300 /*
3301 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3302 * when we have no data to transfer. Otherwise we get being flooded by
3303 * interrupts.
3304 */
3305
3306 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3307 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3308 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3309 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3310 hsotg->regs + DIEPMSK);
3311
3312 /*
3313 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3314 * DMA mode we may need this and StsPhseRcvd.
3315 */
3316 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3317 DOEPMSK_STSPHSERCVDMSK) : 0) |
3318 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3319 DOEPMSK_SETUPMSK,
3320 hsotg->regs + DOEPMSK);
3321
3322 /* Enable BNA interrupt for DDMA */
3323 if (using_desc_dma(hsotg))
3324 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3325
3326 dwc2_writel(0, hsotg->regs + DAINTMSK);
3327
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg->regs + DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0));
3331
3332 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3334
3335 /*
3336 * Enable the RXFIFO when in slave mode, as this is how we collect
3337 * the data. In DMA mode, we get events from the FIFO but also
3338 * things we cannot process, so do not use it.
3339 */
3340 if (!using_dma(hsotg))
3341 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3342
3343 /* Enable interrupts for EP0 in and out */
3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3346
3347 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3351 }
3352
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3354
3355 /*
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3357 * writing to the EPCTL register..
3358 */
3359
3360 /* set to read 1 8byte packet */
3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3363
3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3366 DXEPCTL_USBACTEP,
3367 hsotg->regs + DOEPCTL0);
3368
3369 /* enable, but don't activate EP0in */
3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3372
3373 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3375 if (!is_usb_reset)
3376 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg->regs + DCTL, val);
3378
3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg);
3381
3382 /* must be at-least 3ms to allow bus to see disconnect */
3383 mdelay(3);
3384
3385 hsotg->lx_state = DWC2_L0;
3386
3387 dwc2_hsotg_enqueue_setup(hsotg);
3388
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0));
3392}
3393
3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3395{
3396 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3398}
3399
3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3401{
3402 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3404}
3405
3406/**
3407 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3408 * @hsotg: The device state:
3409 *
3410 * This interrupt indicates one of the following conditions occurred while
3411 * transmitting an ISOC transaction.
3412 * - Corrupted IN Token for ISOC EP.
3413 * - Packet not complete in FIFO.
3414 *
3415 * The following actions will be taken:
3416 * - Determine the EP
3417 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3418 */
3419static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3420{
3421 struct dwc2_hsotg_ep *hs_ep;
3422 u32 epctrl;
3423 u32 daintmsk;
3424 u32 idx;
3425
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3427
3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3429
3430 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx];
3432 /* Proceed only unmasked ISOC EPs */
3433 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3434 continue;
3435
3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3442 }
3443 }
3444
3445 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3447}
3448
3449/**
3450 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3451 * @hsotg: The device state:
3452 *
3453 * This interrupt indicates one of the following conditions occurred while
3454 * transmitting an ISOC transaction.
3455 * - Corrupted OUT Token for ISOC EP.
3456 * - Packet not complete in FIFO.
3457 *
3458 * The following actions will be taken:
3459 * - Determine the EP
3460 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3461 */
3462static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3463{
3464 u32 gintsts;
3465 u32 gintmsk;
3466 u32 daintmsk;
3467 u32 epctrl;
3468 struct dwc2_hsotg_ep *hs_ep;
3469 int idx;
3470
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3472
3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3475
3476 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3477 hs_ep = hsotg->eps_out[idx];
3478 /* Proceed only unmasked ISOC EPs */
3479 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3480 continue;
3481
3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3489
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3493 break;
3494 }
3495 }
3496 }
3497
3498 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3500}
3501
3502/**
3503 * dwc2_hsotg_irq - handle device interrupt
3504 * @irq: The IRQ number triggered
3505 * @pw: The pw value when registered the handler.
3506 */
3507static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3508{
3509 struct dwc2_hsotg *hsotg = pw;
3510 int retry_count = 8;
3511 u32 gintsts;
3512 u32 gintmsk;
3513
3514 if (!dwc2_is_device_mode(hsotg))
3515 return IRQ_NONE;
3516
3517 spin_lock(&hsotg->lock);
3518irq_retry:
3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3521
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3524
3525 gintsts &= gintmsk;
3526
3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3529
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3531
3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) {
3534 dwc2_exit_partial_power_down(hsotg, true);
3535 hsotg->lx_state = DWC2_L0;
3536 }
3537 }
3538
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3541 u32 connected = hsotg->connected;
3542
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS));
3546
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3548
3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg);
3551
3552 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
3554
3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3557 }
3558
3559 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3561
3562 dwc2_hsotg_irq_enumdone(hsotg);
3563 }
3564
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3568 u32 daint_out, daint_in;
3569 int ep;
3570
3571 daint &= daintmsk;
3572 daint_out = daint >> DAINT_OUTEP_SHIFT;
3573 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3574
3575 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3576
3577 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3578 ep++, daint_out >>= 1) {
3579 if (daint_out & 1)
3580 dwc2_hsotg_epint(hsotg, ep, 0);
3581 }
3582
3583 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3584 ep++, daint_in >>= 1) {
3585 if (daint_in & 1)
3586 dwc2_hsotg_epint(hsotg, ep, 1);
3587 }
3588 }
3589
3590 /* check both FIFOs */
3591
3592 if (gintsts & GINTSTS_NPTXFEMP) {
3593 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3594
3595 /*
3596 * Disable the interrupt to stop it happening again
3597 * unless one of these endpoint routines decides that
3598 * it needs re-enabling
3599 */
3600
3601 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3602 dwc2_hsotg_irq_fifoempty(hsotg, false);
3603 }
3604
3605 if (gintsts & GINTSTS_PTXFEMP) {
3606 dev_dbg(hsotg->dev, "PTxFEmp\n");
3607
3608 /* See note in GINTSTS_NPTxFEmp */
3609
3610 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3611 dwc2_hsotg_irq_fifoempty(hsotg, true);
3612 }
3613
3614 if (gintsts & GINTSTS_RXFLVL) {
3615 /*
3616 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3617 * we need to retry dwc2_hsotg_handle_rx if this is still
3618 * set.
3619 */
3620
3621 dwc2_hsotg_handle_rx(hsotg);
3622 }
3623
3624 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3627 }
3628
3629 /*
3630 * these next two seem to crop-up occasionally causing the core
3631 * to shutdown the USB transfer, so try clearing them and logging
3632 * the occurrence.
3633 */
3634
3635 if (gintsts & GINTSTS_GOUTNAKEFF) {
3636 u8 idx;
3637 u32 epctrl;
3638 u32 gintmsk;
3639 u32 daintmsk;
3640 struct dwc2_hsotg_ep *hs_ep;
3641
3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3648
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3651 hs_ep = hsotg->eps_out[idx];
3652 /* Proceed only unmasked ISOC EPs */
3653 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3654 continue;
3655
3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3657
3658 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3662 }
3663 }
3664
3665 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3666 }
3667
3668 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3670
3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3672
3673 dwc2_hsotg_dump(hsotg);
3674 }
3675
3676 if (gintsts & GINTSTS_INCOMPL_SOIN)
3677 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3678
3679 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3680 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3681
3682 /*
3683 * if we've had fifo events, we should try and go around the
3684 * loop again to see if there's any point in returning yet.
3685 */
3686
3687 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3688 goto irq_retry;
3689
3690 spin_unlock(&hsotg->lock);
3691
3692 return IRQ_HANDLED;
3693}
3694
3695static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3696 struct dwc2_hsotg_ep *hs_ep)
3697{
3698 u32 epctrl_reg;
3699 u32 epint_reg;
3700
3701 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3702 DOEPCTL(hs_ep->index);
3703 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3704 DOEPINT(hs_ep->index);
3705
3706 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3707 hs_ep->name);
3708
3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout DIEPINT.NAKEFF\n",
3717 __func__);
3718 } else {
3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100))
3723 dev_warn(hsotg->dev,
3724 "%s: timeout GINTSTS.GINNAKEFF\n",
3725 __func__);
3726 }
3727 } else {
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3730
3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3733 GINTSTS_GOUTNAKEFF, 100))
3734 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3735 __func__);
3736 }
3737
3738 /* Disable ep */
3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3740
3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3743 dev_warn(hsotg->dev,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3745
3746 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3748
3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index;
3751
3752 if (hsotg->dedicated_fifos || hs_ep->periodic)
3753 fifo_index = hs_ep->fifo_index;
3754 else
3755 fifo_index = 0;
3756
3757 /* Flush TX FIFO */
3758 dwc2_flush_tx_fifo(hsotg, fifo_index);
3759
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3763
3764 } else {
3765 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3767 }
3768}
3769
3770/**
3771 * dwc2_hsotg_ep_enable - enable the given endpoint
3772 * @ep: The USB endpint to configure
3773 * @desc: The USB endpoint descriptor to configure with.
3774 *
3775 * This is called from the USB gadget code's usb_ep_enable().
3776 */
3777static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3778 const struct usb_endpoint_descriptor *desc)
3779{
3780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3781 struct dwc2_hsotg *hsotg = hs_ep->parent;
3782 unsigned long flags;
3783 unsigned int index = hs_ep->index;
3784 u32 epctrl_reg;
3785 u32 epctrl;
3786 u32 mps;
3787 u32 mc;
3788 u32 mask;
3789 unsigned int dir_in;
3790 unsigned int i, val, size;
3791 int ret = 0;
3792
3793 dev_dbg(hsotg->dev,
3794 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3795 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3796 desc->wMaxPacketSize, desc->bInterval);
3797
3798 /* not to be called for EP0 */
3799 if (index == 0) {
3800 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3801 return -EINVAL;
3802 }
3803
3804 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3805 if (dir_in != hs_ep->dir_in) {
3806 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3807 return -EINVAL;
3808 }
3809
3810 mps = usb_endpoint_maxp(desc);
3811 mc = usb_endpoint_maxp_mult(desc);
3812
3813 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3814
3815 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3816 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3817
3818 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3819 __func__, epctrl, epctrl_reg);
3820
3821 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3822 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3823 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3824 MAX_DMA_DESC_NUM_GENERIC *
3825 sizeof(struct dwc2_dma_desc),
3826 &hs_ep->desc_list_dma, GFP_ATOMIC);
3827 if (!hs_ep->desc_list) {
3828 ret = -ENOMEM;
3829 goto error2;
3830 }
3831 }
3832
3833 spin_lock_irqsave(&hsotg->lock, flags);
3834
3835 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3836 epctrl |= DXEPCTL_MPS(mps);
3837
3838 /*
3839 * mark the endpoint as active, otherwise the core may ignore
3840 * transactions entirely for this endpoint
3841 */
3842 epctrl |= DXEPCTL_USBACTEP;
3843
3844 /* update the endpoint state */
3845 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3846
3847 /* default, set to non-periodic */
3848 hs_ep->isochronous = 0;
3849 hs_ep->periodic = 0;
3850 hs_ep->halted = 0;
3851 hs_ep->interval = desc->bInterval;
3852
3853 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3854 case USB_ENDPOINT_XFER_ISOC:
3855 epctrl |= DXEPCTL_EPTYPE_ISO;
3856 epctrl |= DXEPCTL_SETEVENFR;
3857 hs_ep->isochronous = 1;
3858 hs_ep->interval = 1 << (desc->bInterval - 1);
3859 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3860 hs_ep->isoc_chain_num = 0;
3861 hs_ep->next_desc = 0;
3862 if (dir_in) {
3863 hs_ep->periodic = 1;
3864 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3865 mask |= DIEPMSK_NAKMSK;
3866 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3867 } else {
3868 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3869 mask |= DOEPMSK_OUTTKNEPDISMSK;
3870 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3871 }
3872 break;
3873
3874 case USB_ENDPOINT_XFER_BULK:
3875 epctrl |= DXEPCTL_EPTYPE_BULK;
3876 break;
3877
3878 case USB_ENDPOINT_XFER_INT:
3879 if (dir_in)
3880 hs_ep->periodic = 1;
3881
3882 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3883 hs_ep->interval = 1 << (desc->bInterval - 1);
3884
3885 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3886 break;
3887
3888 case USB_ENDPOINT_XFER_CONTROL:
3889 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3890 break;
3891 }
3892
3893 /*
3894 * if the hardware has dedicated fifos, we must give each IN EP
3895 * a unique tx-fifo even if it is non-periodic.
3896 */
3897 if (dir_in && hsotg->dedicated_fifos) {
3898 u32 fifo_index = 0;
3899 u32 fifo_size = UINT_MAX;
3900
3901 size = hs_ep->ep.maxpacket * hs_ep->mc;
3902 for (i = 1; i < hsotg->num_of_eps; ++i) {
3903 if (hsotg->fifo_map & (1 << i))
3904 continue;
3905 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3906 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3907 if (val < size)
3908 continue;
3909 /* Search for smallest acceptable fifo */
3910 if (val < fifo_size) {
3911 fifo_size = val;
3912 fifo_index = i;
3913 }
3914 }
3915 if (!fifo_index) {
3916 dev_err(hsotg->dev,
3917 "%s: No suitable fifo found\n", __func__);
3918 ret = -ENOMEM;
3919 goto error1;
3920 }
3921 hsotg->fifo_map |= 1 << fifo_index;
3922 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3923 hs_ep->fifo_index = fifo_index;
3924 hs_ep->fifo_size = fifo_size;
3925 }
3926
3927 /* for non control endpoints, set PID to D0 */
3928 if (index && !hs_ep->isochronous)
3929 epctrl |= DXEPCTL_SETD0PID;
3930
3931 /* WA for Full speed ISOC IN in DDMA mode.
3932 * By Clear NAK status of EP, core will send ZLP
3933 * to IN token and assert NAK interrupt relying
3934 * on TxFIFO status only
3935 */
3936
3937 if (hsotg->gadget.speed == USB_SPEED_FULL &&
3938 hs_ep->isochronous && dir_in) {
3939 /* The WA applies only to core versions from 2.72a
3940 * to 4.00a (including both). Also for FS_IOT_1.00a
3941 * and HS_IOT_1.00a.
3942 */
3943 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
3944
3945 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3946 gsnpsid <= DWC2_CORE_REV_4_00a) ||
3947 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
3948 gsnpsid == DWC2_HS_IOT_REV_1_00a)
3949 epctrl |= DXEPCTL_CNAK;
3950 }
3951
3952 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3953 __func__, epctrl);
3954
3955 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3956 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3957 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3958
3959 /* enable the endpoint interrupt */
3960 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3961
3962error1:
3963 spin_unlock_irqrestore(&hsotg->lock, flags);
3964
3965error2:
3966 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3967 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3968 sizeof(struct dwc2_dma_desc),
3969 hs_ep->desc_list, hs_ep->desc_list_dma);
3970 hs_ep->desc_list = NULL;
3971 }
3972
3973 return ret;
3974}
3975
3976/**
3977 * dwc2_hsotg_ep_disable - disable given endpoint
3978 * @ep: The endpoint to disable.
3979 */
3980static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3981{
3982 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3983 struct dwc2_hsotg *hsotg = hs_ep->parent;
3984 int dir_in = hs_ep->dir_in;
3985 int index = hs_ep->index;
3986 unsigned long flags;
3987 u32 epctrl_reg;
3988 u32 ctrl;
3989
3990 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3991
3992 if (ep == &hsotg->eps_out[0]->ep) {
3993 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3994 return -EINVAL;
3995 }
3996
3997 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3998 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
3999 return -EINVAL;
4000 }
4001
4002 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4003
4004 spin_lock_irqsave(&hsotg->lock, flags);
4005
4006 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
4007
4008 if (ctrl & DXEPCTL_EPENA)
4009 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4010
4011 ctrl &= ~DXEPCTL_EPENA;
4012 ctrl &= ~DXEPCTL_USBACTEP;
4013 ctrl |= DXEPCTL_SNAK;
4014
4015 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4016 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
4017
4018 /* disable endpoint interrupts */
4019 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4020
4021 /* terminate all requests with shutdown */
4022 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4023
4024 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4025 hs_ep->fifo_index = 0;
4026 hs_ep->fifo_size = 0;
4027
4028 spin_unlock_irqrestore(&hsotg->lock, flags);
4029 return 0;
4030}
4031
4032/**
4033 * on_list - check request is on the given endpoint
4034 * @ep: The endpoint to check.
4035 * @test: The request to test if it is on the endpoint.
4036 */
4037static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4038{
4039 struct dwc2_hsotg_req *req, *treq;
4040
4041 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4042 if (req == test)
4043 return true;
4044 }
4045
4046 return false;
4047}
4048
4049/**
4050 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4051 * @ep: The endpoint to dequeue.
4052 * @req: The request to be removed from a queue.
4053 */
4054static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4055{
4056 struct dwc2_hsotg_req *hs_req = our_req(req);
4057 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4058 struct dwc2_hsotg *hs = hs_ep->parent;
4059 unsigned long flags;
4060
4061 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4062
4063 spin_lock_irqsave(&hs->lock, flags);
4064
4065 if (!on_list(hs_ep, hs_req)) {
4066 spin_unlock_irqrestore(&hs->lock, flags);
4067 return -EINVAL;
4068 }
4069
4070 /* Dequeue already started request */
4071 if (req == &hs_ep->req->req)
4072 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4073
4074 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4075 spin_unlock_irqrestore(&hs->lock, flags);
4076
4077 return 0;
4078}
4079
4080/**
4081 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4082 * @ep: The endpoint to set halt.
4083 * @value: Set or unset the halt.
4084 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4085 * the endpoint is busy processing requests.
4086 *
4087 * We need to stall the endpoint immediately if request comes from set_feature
4088 * protocol command handler.
4089 */
4090static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4091{
4092 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4093 struct dwc2_hsotg *hs = hs_ep->parent;
4094 int index = hs_ep->index;
4095 u32 epreg;
4096 u32 epctl;
4097 u32 xfertype;
4098
4099 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4100
4101 if (index == 0) {
4102 if (value)
4103 dwc2_hsotg_stall_ep0(hs);
4104 else
4105 dev_warn(hs->dev,
4106 "%s: can't clear halt on ep0\n", __func__);
4107 return 0;
4108 }
4109
4110 if (hs_ep->isochronous) {
4111 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4112 return -EINVAL;
4113 }
4114
4115 if (!now && value && !list_empty(&hs_ep->queue)) {
4116 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4117 ep->name);
4118 return -EAGAIN;
4119 }
4120
4121 if (hs_ep->dir_in) {
4122 epreg = DIEPCTL(index);
4123 epctl = dwc2_readl(hs->regs + epreg);
4124
4125 if (value) {
4126 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4127 if (epctl & DXEPCTL_EPENA)
4128 epctl |= DXEPCTL_EPDIS;
4129 } else {
4130 epctl &= ~DXEPCTL_STALL;
4131 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4132 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4133 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4134 epctl |= DXEPCTL_SETD0PID;
4135 }
4136 dwc2_writel(epctl, hs->regs + epreg);
4137 } else {
4138 epreg = DOEPCTL(index);
4139 epctl = dwc2_readl(hs->regs + epreg);
4140
4141 if (value) {
4142 epctl |= DXEPCTL_STALL;
4143 } else {
4144 epctl &= ~DXEPCTL_STALL;
4145 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4146 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4147 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4148 epctl |= DXEPCTL_SETD0PID;
4149 }
4150 dwc2_writel(epctl, hs->regs + epreg);
4151 }
4152
4153 hs_ep->halted = value;
4154
4155 return 0;
4156}
4157
4158/**
4159 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4160 * @ep: The endpoint to set halt.
4161 * @value: Set or unset the halt.
4162 */
4163static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4164{
4165 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4166 struct dwc2_hsotg *hs = hs_ep->parent;
4167 unsigned long flags = 0;
4168 int ret = 0;
4169
4170 spin_lock_irqsave(&hs->lock, flags);
4171 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4172 spin_unlock_irqrestore(&hs->lock, flags);
4173
4174 return ret;
4175}
4176
4177static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4178 .enable = dwc2_hsotg_ep_enable,
4179 .disable = dwc2_hsotg_ep_disable,
4180 .alloc_request = dwc2_hsotg_ep_alloc_request,
4181 .free_request = dwc2_hsotg_ep_free_request,
4182 .queue = dwc2_hsotg_ep_queue_lock,
4183 .dequeue = dwc2_hsotg_ep_dequeue,
4184 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4185 /* note, don't believe we have any call for the fifo routines */
4186};
4187
4188/**
4189 * dwc2_hsotg_init - initialize the usb core
4190 * @hsotg: The driver state
4191 */
4192static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4193{
4194 u32 trdtim;
4195 u32 usbcfg;
4196 /* unmask subset of endpoint interrupts */
4197
4198 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4199 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4200 hsotg->regs + DIEPMSK);
4201
4202 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4203 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4204 hsotg->regs + DOEPMSK);
4205
4206 dwc2_writel(0, hsotg->regs + DAINTMSK);
4207
4208 /* Be in disconnected state until gadget is registered */
4209 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
4210
4211 /* setup fifos */
4212
4213 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4214 dwc2_readl(hsotg->regs + GRXFSIZ),
4215 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4216
4217 dwc2_hsotg_init_fifo(hsotg);
4218
4219 /* keep other bits untouched (so e.g. forced modes are not lost) */
4220 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4221 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4222 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4223
4224 /* set the PLL on, remove the HNP/SRP and set the PHY */
4225 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4226 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4227 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4228 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4229
4230 if (using_dma(hsotg))
4231 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4232}
4233
4234/**
4235 * dwc2_hsotg_udc_start - prepare the udc for work
4236 * @gadget: The usb gadget state
4237 * @driver: The usb gadget driver
4238 *
4239 * Perform initialization to prepare udc device and driver
4240 * to work.
4241 */
4242static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4243 struct usb_gadget_driver *driver)
4244{
4245 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4246 unsigned long flags;
4247 int ret;
4248
4249 if (!hsotg) {
4250 pr_err("%s: called with no device\n", __func__);
4251 return -ENODEV;
4252 }
4253
4254 if (!driver) {
4255 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4256 return -EINVAL;
4257 }
4258
4259 if (driver->max_speed < USB_SPEED_FULL)
4260 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4261
4262 if (!driver->setup) {
4263 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4264 return -EINVAL;
4265 }
4266
4267 WARN_ON(hsotg->driver);
4268
4269 driver->driver.bus = NULL;
4270 hsotg->driver = driver;
4271 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4272 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4273
4274 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4275 ret = dwc2_lowlevel_hw_enable(hsotg);
4276 if (ret)
4277 goto err;
4278 }
4279
4280 if (!IS_ERR_OR_NULL(hsotg->uphy))
4281 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4282
4283 spin_lock_irqsave(&hsotg->lock, flags);
4284 if (dwc2_hw_is_device(hsotg)) {
4285 dwc2_hsotg_init(hsotg);
4286 dwc2_hsotg_core_init_disconnected(hsotg, false);
4287 }
4288
4289 hsotg->enabled = 0;
4290 spin_unlock_irqrestore(&hsotg->lock, flags);
4291
4292 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4293
4294 return 0;
4295
4296err:
4297 hsotg->driver = NULL;
4298 return ret;
4299}
4300
4301/**
4302 * dwc2_hsotg_udc_stop - stop the udc
4303 * @gadget: The usb gadget state
4304 * @driver: The usb gadget driver
4305 *
4306 * Stop udc hw block and stay tunned for future transmissions
4307 */
4308static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4309{
4310 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4311 unsigned long flags = 0;
4312 int ep;
4313
4314 if (!hsotg)
4315 return -ENODEV;
4316
4317 /* all endpoints should be shutdown */
4318 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4319 if (hsotg->eps_in[ep])
4320 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4321 if (hsotg->eps_out[ep])
4322 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4323 }
4324
4325 spin_lock_irqsave(&hsotg->lock, flags);
4326
4327 hsotg->driver = NULL;
4328 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4329 hsotg->enabled = 0;
4330
4331 spin_unlock_irqrestore(&hsotg->lock, flags);
4332
4333 if (!IS_ERR_OR_NULL(hsotg->uphy))
4334 otg_set_peripheral(hsotg->uphy->otg, NULL);
4335
4336 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4337 dwc2_lowlevel_hw_disable(hsotg);
4338
4339 return 0;
4340}
4341
4342/**
4343 * dwc2_hsotg_gadget_getframe - read the frame number
4344 * @gadget: The usb gadget state
4345 *
4346 * Read the {micro} frame number
4347 */
4348static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4349{
4350 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4351}
4352
4353/**
4354 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4355 * @gadget: The usb gadget state
4356 * @is_on: Current state of the USB PHY
4357 *
4358 * Connect/Disconnect the USB PHY pullup
4359 */
4360static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4361{
4362 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4363 unsigned long flags = 0;
4364
4365 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4366 hsotg->op_state);
4367
4368 /* Don't modify pullup state while in host mode */
4369 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4370 hsotg->enabled = is_on;
4371 return 0;
4372 }
4373
4374 spin_lock_irqsave(&hsotg->lock, flags);
4375 if (is_on) {
4376 hsotg->enabled = 1;
4377 dwc2_hsotg_core_init_disconnected(hsotg, false);
4378 /* Enable ACG feature in device mode,if supported */
4379 dwc2_enable_acg(hsotg);
4380 dwc2_hsotg_core_connect(hsotg);
4381 } else {
4382 dwc2_hsotg_core_disconnect(hsotg);
4383 dwc2_hsotg_disconnect(hsotg);
4384 hsotg->enabled = 0;
4385 }
4386
4387 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4388 spin_unlock_irqrestore(&hsotg->lock, flags);
4389
4390 return 0;
4391}
4392
4393static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4394{
4395 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4396 unsigned long flags;
4397
4398 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4399 spin_lock_irqsave(&hsotg->lock, flags);
4400
4401 /*
4402 * If controller is hibernated, it must exit from power_down
4403 * before being initialized / de-initialized
4404 */
4405 if (hsotg->lx_state == DWC2_L2)
4406 dwc2_exit_partial_power_down(hsotg, false);
4407
4408 if (is_active) {
4409 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4410
4411 dwc2_hsotg_core_init_disconnected(hsotg, false);
4412 if (hsotg->enabled) {
4413 /* Enable ACG feature in device mode,if supported */
4414 dwc2_enable_acg(hsotg);
4415 dwc2_hsotg_core_connect(hsotg);
4416 }
4417 } else {
4418 dwc2_hsotg_core_disconnect(hsotg);
4419 dwc2_hsotg_disconnect(hsotg);
4420 }
4421
4422 spin_unlock_irqrestore(&hsotg->lock, flags);
4423 return 0;
4424}
4425
4426/**
4427 * dwc2_hsotg_vbus_draw - report bMaxPower field
4428 * @gadget: The usb gadget state
4429 * @mA: Amount of current
4430 *
4431 * Report how much power the device may consume to the phy.
4432 */
4433static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4434{
4435 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4436
4437 if (IS_ERR_OR_NULL(hsotg->uphy))
4438 return -ENOTSUPP;
4439 return usb_phy_set_power(hsotg->uphy, mA);
4440}
4441
4442static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4443 .get_frame = dwc2_hsotg_gadget_getframe,
4444 .udc_start = dwc2_hsotg_udc_start,
4445 .udc_stop = dwc2_hsotg_udc_stop,
4446 .pullup = dwc2_hsotg_pullup,
4447 .vbus_session = dwc2_hsotg_vbus_session,
4448 .vbus_draw = dwc2_hsotg_vbus_draw,
4449};
4450
4451/**
4452 * dwc2_hsotg_initep - initialise a single endpoint
4453 * @hsotg: The device state.
4454 * @hs_ep: The endpoint to be initialised.
4455 * @epnum: The endpoint number
4456 *
4457 * Initialise the given endpoint (as part of the probe and device state
4458 * creation) to give to the gadget driver. Setup the endpoint name, any
4459 * direction information and other state that may be required.
4460 */
4461static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4462 struct dwc2_hsotg_ep *hs_ep,
4463 int epnum,
4464 bool dir_in)
4465{
4466 char *dir;
4467
4468 if (epnum == 0)
4469 dir = "";
4470 else if (dir_in)
4471 dir = "in";
4472 else
4473 dir = "out";
4474
4475 hs_ep->dir_in = dir_in;
4476 hs_ep->index = epnum;
4477
4478 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4479
4480 INIT_LIST_HEAD(&hs_ep->queue);
4481 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4482
4483 /* add to the list of endpoints known by the gadget driver */
4484 if (epnum)
4485 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4486
4487 hs_ep->parent = hsotg;
4488 hs_ep->ep.name = hs_ep->name;
4489
4490 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4491 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4492 else
4493 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4494 epnum ? 1024 : EP0_MPS_LIMIT);
4495 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4496
4497 if (epnum == 0) {
4498 hs_ep->ep.caps.type_control = true;
4499 } else {
4500 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4501 hs_ep->ep.caps.type_iso = true;
4502 hs_ep->ep.caps.type_bulk = true;
4503 }
4504 hs_ep->ep.caps.type_int = true;
4505 }
4506
4507 if (dir_in)
4508 hs_ep->ep.caps.dir_in = true;
4509 else
4510 hs_ep->ep.caps.dir_out = true;
4511
4512 /*
4513 * if we're using dma, we need to set the next-endpoint pointer
4514 * to be something valid.
4515 */
4516
4517 if (using_dma(hsotg)) {
4518 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4519
4520 if (dir_in)
4521 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4522 else
4523 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4524 }
4525}
4526
4527/**
4528 * dwc2_hsotg_hw_cfg - read HW configuration registers
4529 * @param: The device state
4530 *
4531 * Read the USB core HW configuration registers
4532 */
4533static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4534{
4535 u32 cfg;
4536 u32 ep_type;
4537 u32 i;
4538
4539 /* check hardware configuration */
4540
4541 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4542
4543 /* Add ep0 */
4544 hsotg->num_of_eps++;
4545
4546 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4547 sizeof(struct dwc2_hsotg_ep),
4548 GFP_KERNEL);
4549 if (!hsotg->eps_in[0])
4550 return -ENOMEM;
4551 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4552 hsotg->eps_out[0] = hsotg->eps_in[0];
4553
4554 cfg = hsotg->hw_params.dev_ep_dirs;
4555 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4556 ep_type = cfg & 3;
4557 /* Direction in or both */
4558 if (!(ep_type & 2)) {
4559 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4560 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4561 if (!hsotg->eps_in[i])
4562 return -ENOMEM;
4563 }
4564 /* Direction out or both */
4565 if (!(ep_type & 1)) {
4566 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4567 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4568 if (!hsotg->eps_out[i])
4569 return -ENOMEM;
4570 }
4571 }
4572
4573 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4574 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4575
4576 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4577 hsotg->num_of_eps,
4578 hsotg->dedicated_fifos ? "dedicated" : "shared",
4579 hsotg->fifo_mem);
4580 return 0;
4581}
4582
4583/**
4584 * dwc2_hsotg_dump - dump state of the udc
4585 * @param: The device state
4586 */
4587static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4588{
4589#ifdef DEBUG
4590 struct device *dev = hsotg->dev;
4591 void __iomem *regs = hsotg->regs;
4592 u32 val;
4593 int idx;
4594
4595 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4596 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4597 dwc2_readl(regs + DIEPMSK));
4598
4599 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4600 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4601
4602 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4603 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4604
4605 /* show periodic fifo settings */
4606
4607 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4608 val = dwc2_readl(regs + DPTXFSIZN(idx));
4609 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4610 val >> FIFOSIZE_DEPTH_SHIFT,
4611 val & FIFOSIZE_STARTADDR_MASK);
4612 }
4613
4614 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4615 dev_info(dev,
4616 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4617 dwc2_readl(regs + DIEPCTL(idx)),
4618 dwc2_readl(regs + DIEPTSIZ(idx)),
4619 dwc2_readl(regs + DIEPDMA(idx)));
4620
4621 val = dwc2_readl(regs + DOEPCTL(idx));
4622 dev_info(dev,
4623 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4624 idx, dwc2_readl(regs + DOEPCTL(idx)),
4625 dwc2_readl(regs + DOEPTSIZ(idx)),
4626 dwc2_readl(regs + DOEPDMA(idx)));
4627 }
4628
4629 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4630 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4631#endif
4632}
4633
4634/**
4635 * dwc2_gadget_init - init function for gadget
4636 * @dwc2: The data structure for the DWC2 driver.
4637 */
4638int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4639{
4640 struct device *dev = hsotg->dev;
4641 int epnum;
4642 int ret;
4643
4644 /* Dump fifo information */
4645 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4646 hsotg->params.g_np_tx_fifo_size);
4647 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4648
4649 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4650 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4651 hsotg->gadget.name = dev_name(dev);
4652 hsotg->remote_wakeup_allowed = 0;
4653
4654 if (hsotg->params.lpm)
4655 hsotg->gadget.lpm_capable = true;
4656
4657 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4658 hsotg->gadget.is_otg = 1;
4659 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4660 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4661
4662 ret = dwc2_hsotg_hw_cfg(hsotg);
4663 if (ret) {
4664 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4665 return ret;
4666 }
4667
4668 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4669 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4670 if (!hsotg->ctrl_buff)
4671 return -ENOMEM;
4672
4673 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4674 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4675 if (!hsotg->ep0_buff)
4676 return -ENOMEM;
4677
4678 if (using_desc_dma(hsotg)) {
4679 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4680 if (ret < 0)
4681 return ret;
4682 }
4683
4684 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4685 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4686 if (ret < 0) {
4687 dev_err(dev, "cannot claim IRQ for gadget\n");
4688 return ret;
4689 }
4690
4691 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4692
4693 if (hsotg->num_of_eps == 0) {
4694 dev_err(dev, "wrong number of EPs (zero)\n");
4695 return -EINVAL;
4696 }
4697
4698 /* setup endpoint information */
4699
4700 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4701 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4702
4703 /* allocate EP0 request */
4704
4705 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4706 GFP_KERNEL);
4707 if (!hsotg->ctrl_req) {
4708 dev_err(dev, "failed to allocate ctrl req\n");
4709 return -ENOMEM;
4710 }
4711
4712 /* initialise the endpoints now the core has been initialised */
4713 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4714 if (hsotg->eps_in[epnum])
4715 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4716 epnum, 1);
4717 if (hsotg->eps_out[epnum])
4718 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4719 epnum, 0);
4720 }
4721
4722 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4723 if (ret)
4724 return ret;
4725
4726 dwc2_hsotg_dump(hsotg);
4727
4728 return 0;
4729}
4730
4731/**
4732 * dwc2_hsotg_remove - remove function for hsotg driver
4733 * @pdev: The platform information for the driver
4734 */
4735int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4736{
4737 usb_del_gadget_udc(&hsotg->gadget);
4738
4739 return 0;
4740}
4741
4742int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4743{
4744 unsigned long flags;
4745
4746 if (hsotg->lx_state != DWC2_L0)
4747 return 0;
4748
4749 if (hsotg->driver) {
4750 int ep;
4751
4752 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4753 hsotg->driver->driver.name);
4754
4755 spin_lock_irqsave(&hsotg->lock, flags);
4756 if (hsotg->enabled)
4757 dwc2_hsotg_core_disconnect(hsotg);
4758 dwc2_hsotg_disconnect(hsotg);
4759 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4760 spin_unlock_irqrestore(&hsotg->lock, flags);
4761
4762 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4763 if (hsotg->eps_in[ep])
4764 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4765 if (hsotg->eps_out[ep])
4766 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4767 }
4768 }
4769
4770 return 0;
4771}
4772
4773int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4774{
4775 unsigned long flags;
4776
4777 if (hsotg->lx_state == DWC2_L2)
4778 return 0;
4779
4780 if (hsotg->driver) {
4781 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4782 hsotg->driver->driver.name);
4783
4784 spin_lock_irqsave(&hsotg->lock, flags);
4785 dwc2_hsotg_core_init_disconnected(hsotg, false);
4786 if (hsotg->enabled) {
4787 /* Enable ACG feature in device mode,if supported */
4788 dwc2_enable_acg(hsotg);
4789 dwc2_hsotg_core_connect(hsotg);
4790 }
4791 spin_unlock_irqrestore(&hsotg->lock, flags);
4792 }
4793
4794 return 0;
4795}
4796
4797/**
4798 * dwc2_backup_device_registers() - Backup controller device registers.
4799 * When suspending usb bus, registers needs to be backuped
4800 * if controller power is disabled once suspended.
4801 *
4802 * @hsotg: Programming view of the DWC_otg controller
4803 */
4804int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4805{
4806 struct dwc2_dregs_backup *dr;
4807 int i;
4808
4809 dev_dbg(hsotg->dev, "%s\n", __func__);
4810
4811 /* Backup dev regs */
4812 dr = &hsotg->dr_backup;
4813
4814 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4815 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4816 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4817 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4818 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4819
4820 for (i = 0; i < hsotg->num_of_eps; i++) {
4821 /* Backup IN EPs */
4822 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4823
4824 /* Ensure DATA PID is correctly configured */
4825 if (dr->diepctl[i] & DXEPCTL_DPID)
4826 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4827 else
4828 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4829
4830 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4831 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4832
4833 /* Backup OUT EPs */
4834 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4835
4836 /* Ensure DATA PID is correctly configured */
4837 if (dr->doepctl[i] & DXEPCTL_DPID)
4838 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4839 else
4840 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4841
4842 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4843 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4844 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
4845 }
4846 dr->valid = true;
4847 return 0;
4848}
4849
4850/**
4851 * dwc2_restore_device_registers() - Restore controller device registers.
4852 * When resuming usb bus, device registers needs to be restored
4853 * if controller power were disabled.
4854 *
4855 * @hsotg: Programming view of the DWC_otg controller
4856 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
4857 *
4858 * Return: 0 if successful, negative error code otherwise
4859 */
4860int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4861{
4862 struct dwc2_dregs_backup *dr;
4863 int i;
4864
4865 dev_dbg(hsotg->dev, "%s\n", __func__);
4866
4867 /* Restore dev regs */
4868 dr = &hsotg->dr_backup;
4869 if (!dr->valid) {
4870 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4871 __func__);
4872 return -EINVAL;
4873 }
4874 dr->valid = false;
4875
4876 if (!remote_wakeup)
4877 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4878
4879 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4880 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4881 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4882
4883 for (i = 0; i < hsotg->num_of_eps; i++) {
4884 /* Restore IN EPs */
4885 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4886 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4887 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4888 /** WA for enabled EPx's IN in DDMA mode. On entering to
4889 * hibernation wrong value read and saved from DIEPDMAx,
4890 * as result BNA interrupt asserted on hibernation exit
4891 * by restoring from saved area.
4892 */
4893 if (hsotg->params.g_dma_desc &&
4894 (dr->diepctl[i] & DXEPCTL_EPENA))
4895 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4896 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
4897 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4898 /* Restore OUT EPs */
4899 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4900 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4901 * hibernation wrong value read and saved from DOEPDMAx,
4902 * as result BNA interrupt asserted on hibernation exit
4903 * by restoring from saved area.
4904 */
4905 if (hsotg->params.g_dma_desc &&
4906 (dr->doepctl[i] & DXEPCTL_EPENA))
4907 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4908 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4909 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4910 }
4911
4912 return 0;
4913}
4914
4915/**
4916 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
4917 *
4918 * @hsotg: Programming view of DWC_otg controller
4919 *
4920 */
4921void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4922{
4923 u32 val;
4924
4925 if (!hsotg->params.lpm)
4926 return;
4927
4928 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
4929 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
4930 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4931 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4932 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4933 dwc2_writel(val, hsotg->regs + GLPMCFG);
4934 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs
4935 + GLPMCFG));
4936}
4937
4938/**
4939 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
4940 *
4941 * @hsotg: Programming view of the DWC_otg controller
4942 *
4943 * Return non-zero if failed to enter to hibernation.
4944 */
4945int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4946{
4947 u32 gpwrdn;
4948 int ret = 0;
4949
4950 /* Change to L2(suspend) state */
4951 hsotg->lx_state = DWC2_L2;
4952 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
4953 ret = dwc2_backup_global_registers(hsotg);
4954 if (ret) {
4955 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
4956 __func__);
4957 return ret;
4958 }
4959 ret = dwc2_backup_device_registers(hsotg);
4960 if (ret) {
4961 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
4962 __func__);
4963 return ret;
4964 }
4965
4966 gpwrdn = GPWRDN_PWRDNRSTN;
4967 gpwrdn |= GPWRDN_PMUACTV;
4968 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4969 udelay(10);
4970
4971 /* Set flag to indicate that we are in hibernation */
4972 hsotg->hibernated = 1;
4973
4974 /* Enable interrupts from wake up logic */
4975 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4976 gpwrdn |= GPWRDN_PMUINTSEL;
4977 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4978 udelay(10);
4979
4980 /* Unmask device mode interrupts in GPWRDN */
4981 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4982 gpwrdn |= GPWRDN_RST_DET_MSK;
4983 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
4984 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
4985 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4986 udelay(10);
4987
4988 /* Enable Power Down Clamp */
4989 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4990 gpwrdn |= GPWRDN_PWRDNCLMP;
4991 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4992 udelay(10);
4993
4994 /* Switch off VDD */
4995 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4996 gpwrdn |= GPWRDN_PWRDNSWTCH;
4997 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4998 udelay(10);
4999
5000 /* Save gpwrdn register for further usage if stschng interrupt */
5001 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5002 dev_dbg(hsotg->dev, "Hibernation completed\n");
5003
5004 return ret;
5005}
5006
5007/**
5008 * dwc2_gadget_exit_hibernation()
5009 * This function is for exiting from Device mode hibernation by host initiated
5010 * resume/reset and device initiated remote-wakeup.
5011 *
5012 * @hsotg: Programming view of the DWC_otg controller
5013 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5014 * @param reset: indicates whether resume is initiated by Reset.
5015 *
5016 * Return non-zero if failed to exit from hibernation.
5017 */
5018int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5019 int rem_wakeup, int reset)
5020{
5021 u32 pcgcctl;
5022 u32 gpwrdn;
5023 u32 dctl;
5024 int ret = 0;
5025 struct dwc2_gregs_backup *gr;
5026 struct dwc2_dregs_backup *dr;
5027
5028 gr = &hsotg->gr_backup;
5029 dr = &hsotg->dr_backup;
5030
5031 if (!hsotg->hibernated) {
5032 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5033 return 1;
5034 }
5035 dev_dbg(hsotg->dev,
5036 "%s: called with rem_wakeup = %d reset = %d\n",
5037 __func__, rem_wakeup, reset);
5038
5039 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5040
5041 if (!reset) {
5042 /* Clear all pending interupts */
5043 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5044 }
5045
5046 /* De-assert Restore */
5047 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5048 gpwrdn &= ~GPWRDN_RESTORE;
5049 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5050 udelay(10);
5051
5052 if (!rem_wakeup) {
5053 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5054 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5055 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5056 }
5057
5058 /* Restore GUSBCFG, DCFG and DCTL */
5059 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5060 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
5061 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
5062
5063 /* De-assert Wakeup Logic */
5064 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5065 gpwrdn &= ~GPWRDN_PMUACTV;
5066 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5067
5068 if (rem_wakeup) {
5069 udelay(10);
5070 /* Start Remote Wakeup Signaling */
5071 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL);
5072 } else {
5073 udelay(50);
5074 /* Set Device programming done bit */
5075 dctl = dwc2_readl(hsotg->regs + DCTL);
5076 dctl |= DCTL_PWRONPRGDONE;
5077 dwc2_writel(dctl, hsotg->regs + DCTL);
5078 }
5079 /* Wait for interrupts which must be cleared */
5080 mdelay(2);
5081 /* Clear all pending interupts */
5082 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5083
5084 /* Restore global registers */
5085 ret = dwc2_restore_global_registers(hsotg);
5086 if (ret) {
5087 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5088 __func__);
5089 return ret;
5090 }
5091
5092 /* Restore device registers */
5093 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5094 if (ret) {
5095 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5096 __func__);
5097 return ret;
5098 }
5099
5100 if (rem_wakeup) {
5101 mdelay(10);
5102 dctl = dwc2_readl(hsotg->regs + DCTL);
5103 dctl &= ~DCTL_RMTWKUPSIG;
5104 dwc2_writel(dctl, hsotg->regs + DCTL);
5105 }
5106
5107 hsotg->hibernated = 0;
5108 hsotg->lx_state = DWC2_L0;
5109 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5110
5111 return ret;
5112}