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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
120
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
122 limit >>= 3;
123
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
128 } else {
129 hs_ep->frame_overrun = false;
130 }
131}
132
133/**
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * by one.
136 * @hs_ep: The endpoint.
137 *
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
141 *
142 */
143static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144{
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
147
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
149 limit >>= 3;
150
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
153 else
154 hs_ep->target_frame = limit;
155}
156
157/**
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
161 */
162static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163{
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
165 u32 new_gsintmsk;
166
167 new_gsintmsk = gsintmsk | ints;
168
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
172 }
173}
174
175/**
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
179 */
180static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181{
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
183 u32 new_gsintmsk;
184
185 new_gsintmsk = gsintmsk & ~ints;
186
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
189}
190
191/**
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
197 *
198 * Set or clear the mask for an individual endpoint's interrupt
199 * request.
200 */
201static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
203 unsigned int en)
204{
205 unsigned long flags;
206 u32 bit = 1 << ep;
207 u32 daint;
208
209 if (!dir_in)
210 bit <<= 16;
211
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
214 if (en)
215 daint |= bit;
216 else
217 daint &= ~bit;
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
220}
221
222/**
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 *
225 * @hsotg: Programming view of the DWC_otg controller
226 */
227int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228{
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
232 else
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
235}
236
237/**
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
240 *
241 * @hsotg: Programming view of the DWC_otg controller
242 */
243int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
244{
245 int addr;
246 int tx_addr_max;
247 u32 np_tx_fifo_size;
248
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
251
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
254
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
257 return 0;
258
259 return tx_addr_max - addr;
260}
261
262/**
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 *
265 * @hsotg: Programming view of the DWC_otg controller
266 *
267 */
268static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
269{
270 u32 gintsts2;
271 u32 gintmsk2;
272
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
276
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
281 }
282}
283
284/**
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
286 * TX FIFOs
287 *
288 * @hsotg: Programming view of the DWC_otg controller
289 */
290int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
291{
292 int tx_fifo_count;
293 int tx_fifo_depth;
294
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
298
299 if (!tx_fifo_count)
300 return tx_fifo_depth;
301 else
302 return tx_fifo_depth / tx_fifo_count;
303}
304
305/**
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
308 */
309static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
310{
311 unsigned int ep;
312 unsigned int addr;
313 int timeout;
314
315 u32 val;
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
320 hsotg->fifo_map = 0;
321
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
327 GNPTXFSIZ);
328
329 /*
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
333 * known values.
334 */
335
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
338
339 /*
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
342 * given endpoint.
343 */
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
345 if (!txfsz[ep])
346 continue;
347 val = addr;
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
351 addr += txfsz[ep];
352
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
355 }
356
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
359 GDFIFOCFG);
360 /*
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
363 */
364
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
367
368 /* wait until the fifos are both flushed */
369 timeout = 100;
370 while (1) {
371 val = dwc2_readl(hsotg, GRSTCTL);
372
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
374 break;
375
376 if (--timeout == 0) {
377 dev_err(hsotg->dev,
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
379 __func__, val);
380 break;
381 }
382
383 udelay(1);
384 }
385
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
387}
388
389/**
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
393 *
394 * Allocate a new USB request structure appropriate for the specified endpoint
395 */
396static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
397 gfp_t flags)
398{
399 struct dwc2_hsotg_req *req;
400
401 req = kzalloc(sizeof(*req), flags);
402 if (!req)
403 return NULL;
404
405 INIT_LIST_HEAD(&req->queue);
406
407 return &req->req;
408}
409
410/**
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
413 *
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
416 */
417static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418{
419 return hs_ep->periodic;
420}
421
422/**
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
427 *
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
430 */
431static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
434{
435 struct usb_request *req = &hs_req->req;
436
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
438}
439
440/*
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
444 *
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
447 */
448static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449{
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
454 GFP_KERNEL);
455 if (!hsotg->setup_desc[0])
456 goto fail;
457
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
462 GFP_KERNEL);
463 if (!hsotg->setup_desc[1])
464 goto fail;
465
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
470 GFP_KERNEL);
471 if (!hsotg->ctrl_in_desc)
472 goto fail;
473
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
478 GFP_KERNEL);
479 if (!hsotg->ctrl_out_desc)
480 goto fail;
481
482 return 0;
483
484fail:
485 return -ENOMEM;
486}
487
488/**
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
493 *
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
497 * write the data.
498 *
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 *
502 * This routine is only needed for PIO
503 */
504static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
507{
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
512 void *data;
513 int can_write;
514 int pkt_round;
515 int max_transfer;
516
517 to_write -= (buf_pos - hs_ep->last_load);
518
519 /* if there's nothing to write, get out early */
520 if (to_write == 0)
521 return 0;
522
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
525 int size_left;
526 int size_done;
527
528 /*
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
531 */
532
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
534
535 /*
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
538 */
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
541 return -ENOSPC;
542 }
543
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 __func__, size_left,
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
550
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
555
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
559
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
562 return -ENOSPC;
563 }
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
567
568 can_write &= 0xffff;
569 can_write *= 4;
570 } else {
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 dev_dbg(hsotg->dev,
573 "%s: no queue slots available (0x%08x)\n",
574 __func__, gnptxsts);
575
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
577 return -ENOSPC;
578 }
579
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
582 }
583
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
588
589 /*
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
593 */
594 if (can_write > 512 && !periodic)
595 can_write = 512;
596
597 /*
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
600 * doing it.
601 */
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
604
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
609 GINTSTS_NPTXFEMP);
610 }
611
612 /* see if we can write data */
613
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
617
618 /*
619 * Round the write down to an
620 * exact number of packets.
621 *
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
624 */
625
626 if (pkt_round)
627 to_write -= pkt_round;
628
629 /*
630 * enable correct FIFO interrupt to alert us when there
631 * is more room left.
632 */
633
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
638 GINTSTS_NPTXFEMP);
639 }
640
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
643
644 if (to_write <= 0)
645 return -ENOSPC;
646
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
649
650 if (periodic)
651 hs_ep->fifo_load += to_write;
652
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
655
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657
658 return (to_write >= can_write) ? -ENOSPC : 0;
659}
660
661/**
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
664 *
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
667 */
668static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669{
670 int index = hs_ep->index;
671 unsigned int maxsize;
672 unsigned int maxpkt;
673
674 if (index != 0) {
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
677 } else {
678 maxsize = 64 + 64;
679 if (hs_ep->dir_in)
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
681 else
682 maxpkt = 2;
683 }
684
685 /* we made the constant loading easier above by using +1 */
686 maxpkt--;
687 maxsize--;
688
689 /*
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
692 */
693
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
696
697 return maxsize;
698}
699
700/**
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
703 *
704 * Return the current frame number
705 */
706static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
707{
708 u32 dsts;
709
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
713
714 return dsts;
715}
716
717/**
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
721 *
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
725 */
726static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727{
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
733
734 if (is_isoc)
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
738 else
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740
741 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (hs_ep->index)
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
745
746 return maxsize;
747}
748
749/*
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
753 *
754 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * characteristics.
756 * DMA descriptor transfer bytes limit depends on EP type:
757 * Control out - MPS,
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
763 *
764 * Selects corresponding mask for RX/TX bytes as well.
765 */
766static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767{
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
771 u32 desc_size = 0;
772
773 if (!hs_ep->index && !dir_in) {
774 desc_size = mps;
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
777 if (dir_in) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 } else {
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
783 }
784 } else {
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
787
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
790 }
791
792 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (hs_ep->index)
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 desc_size = mps;
796 *mask = DEV_DMA_NBYTES_MASK;
797 }
798
799 return desc_size;
800}
801
802static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
804 dma_addr_t dma_buff,
805 unsigned int len,
806 bool true_last)
807{
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
810 u32 maxsize = 0;
811 u32 offset = 0;
812 u32 mask = 0;
813 int i;
814
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
819 if (len == 0)
820 hs_ep->desc_count = 1;
821
822 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status = 0;
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
826
827 if (len > maxsize) {
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830
831 (*desc)->status |=
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
834
835 len -= maxsize;
836 offset += maxsize;
837 } else {
838 if (true_last)
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
840
841 if (dir_in)
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
844 DEV_DMA_SHORT : 0);
845
846 (*desc)->status |=
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
849 }
850
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
854 (*desc)++;
855 }
856}
857
858/*
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
864 *
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
867 */
868static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
869 dma_addr_t dma_buff,
870 unsigned int len)
871{
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
875 int i;
876 u8 desc_count = 0;
877
878 if (hs_ep->req)
879 ureq = &hs_ep->req->req;
880
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
885 return;
886 }
887
888 /* DMA sg buffer */
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 sg_is_last(sg));
893 desc_count += hs_ep->desc_count;
894 }
895
896 hs_ep->desc_count = desc_count;
897}
898
899/*
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
904 *
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
908 * status.
909 */
910static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
912{
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
915 u32 index;
916 u32 mask = 0;
917 u8 pid = 0;
918
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
920
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
923
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
928 return 1;
929 }
930
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
937
938 desc->status = 0;
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
944
945 if (hs_ep->dir_in) {
946 if (len)
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
948 else
949 pid = 1;
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
953 DEV_DMA_SHORT : 0) |
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
957 }
958
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961
962 /* Increment frame number by interval for IN */
963 if (hs_ep->dir_in)
964 dwc2_gadget_incr_frame_num(hs_ep);
965
966 /* Update index of last configured entry in the chain */
967 hs_ep->next_desc++;
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
970
971 return 0;
972}
973
974/*
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
977 *
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
980 */
981static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982{
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
986 int ret;
987 int i;
988 u32 dma_reg;
989 u32 depctl;
990 u32 ctrl;
991 struct dwc2_dma_desc *desc;
992
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
996 return;
997 }
998
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1002 desc->status = 0;
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1005 }
1006
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1010
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1014 }
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1017 if (ret)
1018 break;
1019 }
1020
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1031}
1032
1033static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1037 int result);
1038
1039/**
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1045 *
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1048 */
1049static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1052 bool continuing)
1053{
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1057 u32 epctrl_reg;
1058 u32 epsize_reg;
1059 u32 epsize;
1060 u32 ctrl;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1065
1066 if (index != 0) {
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1069 WARN_ON(1);
1070 return;
1071 } else if (hs_ep->req != hs_req && continuing) {
1072 dev_err(hsotg->dev,
1073 "%s: continue different req\n", __func__);
1074 WARN_ON(1);
1075 return;
1076 }
1077 }
1078
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1086
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1092 return;
1093 }
1094
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1098
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1101 else
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1106
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1109
1110 /* round down to multiple of packets */
1111 if (round)
1112 maxreq -= round;
1113
1114 length = maxreq;
1115 }
1116
1117 if (length)
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 else
1120 packets = 1; /* send one packet if length is zero. */
1121
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1125 else
1126 epsize = DXEPTSIZ_MC(1);
1127 else
1128 epsize = 0;
1129
1130 /*
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 */
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1139 }
1140
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1143
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1149
1150 if (using_desc_dma(hsotg)) {
1151 u32 offset = 0;
1152 u32 mps = hs_ep->ep.maxpacket;
1153
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1155 if (!dir_in) {
1156 if (!index)
1157 length = mps;
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1160 }
1161
1162 if (continuing)
1163 offset = ureq->actual;
1164
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1167 length);
1168
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 } else {
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1177
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 /*
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1182 */
1183
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1188 }
1189 }
1190
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1196 else
1197 ctrl |= DXEPCTL_SETEVENFR;
1198 }
1199 ctrl |= DXEPCTL_CNAK;
1200 } else {
1201 hs_req->req.frame_number = hs_ep->target_frame;
1202 hs_req->req.actual = 0;
1203 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1204 return;
1205 }
1206 }
1207
1208 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1209
1210 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1211
1212 /* For Setup request do not clear NAK */
1213 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1214 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1215
1216 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1217 dwc2_writel(hsotg, ctrl, epctrl_reg);
1218
1219 /*
1220 * set these, it seems that DMA support increments past the end
1221 * of the packet buffer so we need to calculate the length from
1222 * this information.
1223 */
1224 hs_ep->size_loaded = length;
1225 hs_ep->last_load = ureq->actual;
1226
1227 if (dir_in && !using_dma(hsotg)) {
1228 /* set these anyway, we may need them for non-periodic in */
1229 hs_ep->fifo_load = 0;
1230
1231 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1232 }
1233
1234 /*
1235 * Note, trying to clear the NAK here causes problems with transmit
1236 * on the S3C6400 ending up with the TXFIFO becoming full.
1237 */
1238
1239 /* check ep is enabled */
1240 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1241 dev_dbg(hsotg->dev,
1242 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1243 index, dwc2_readl(hsotg, epctrl_reg));
1244
1245 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1246 __func__, dwc2_readl(hsotg, epctrl_reg));
1247
1248 /* enable ep interrupts */
1249 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1250}
1251
1252/**
1253 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1254 * @hsotg: The device state.
1255 * @hs_ep: The endpoint the request is on.
1256 * @req: The request being processed.
1257 *
1258 * We've been asked to queue a request, so ensure that the memory buffer
1259 * is correctly setup for DMA. If we've been passed an extant DMA address
1260 * then ensure the buffer has been synced to memory. If our buffer has no
1261 * DMA memory, then we map the memory and mark our request to allow us to
1262 * cleanup on completion.
1263 */
1264static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1265 struct dwc2_hsotg_ep *hs_ep,
1266 struct usb_request *req)
1267{
1268 int ret;
1269
1270 hs_ep->map_dir = hs_ep->dir_in;
1271 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1272 if (ret)
1273 goto dma_error;
1274
1275 return 0;
1276
1277dma_error:
1278 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1279 __func__, req->buf, req->length);
1280
1281 return -EIO;
1282}
1283
1284static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1285 struct dwc2_hsotg_ep *hs_ep,
1286 struct dwc2_hsotg_req *hs_req)
1287{
1288 void *req_buf = hs_req->req.buf;
1289
1290 /* If dma is not being used or buffer is aligned */
1291 if (!using_dma(hsotg) || !((long)req_buf & 3))
1292 return 0;
1293
1294 WARN_ON(hs_req->saved_req_buf);
1295
1296 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1297 hs_ep->ep.name, req_buf, hs_req->req.length);
1298
1299 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1300 if (!hs_req->req.buf) {
1301 hs_req->req.buf = req_buf;
1302 dev_err(hsotg->dev,
1303 "%s: unable to allocate memory for bounce buffer\n",
1304 __func__);
1305 return -ENOMEM;
1306 }
1307
1308 /* Save actual buffer */
1309 hs_req->saved_req_buf = req_buf;
1310
1311 if (hs_ep->dir_in)
1312 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1313 return 0;
1314}
1315
1316static void
1317dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1318 struct dwc2_hsotg_ep *hs_ep,
1319 struct dwc2_hsotg_req *hs_req)
1320{
1321 /* If dma is not being used or buffer was aligned */
1322 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1323 return;
1324
1325 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1326 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1327
1328 /* Copy data from bounce buffer on successful out transfer */
1329 if (!hs_ep->dir_in && !hs_req->req.status)
1330 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1331 hs_req->req.actual);
1332
1333 /* Free bounce buffer */
1334 kfree(hs_req->req.buf);
1335
1336 hs_req->req.buf = hs_req->saved_req_buf;
1337 hs_req->saved_req_buf = NULL;
1338}
1339
1340/**
1341 * dwc2_gadget_target_frame_elapsed - Checks target frame
1342 * @hs_ep: The driver endpoint to check
1343 *
1344 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1345 * corresponding transfer.
1346 */
1347static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1348{
1349 struct dwc2_hsotg *hsotg = hs_ep->parent;
1350 u32 target_frame = hs_ep->target_frame;
1351 u32 current_frame = hsotg->frame_number;
1352 bool frame_overrun = hs_ep->frame_overrun;
1353 u16 limit = DSTS_SOFFN_LIMIT;
1354
1355 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1356 limit >>= 3;
1357
1358 if (!frame_overrun && current_frame >= target_frame)
1359 return true;
1360
1361 if (frame_overrun && current_frame >= target_frame &&
1362 ((current_frame - target_frame) < limit / 2))
1363 return true;
1364
1365 return false;
1366}
1367
1368/*
1369 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1370 * @hsotg: The driver state
1371 * @hs_ep: the ep descriptor chain is for
1372 *
1373 * Called to update EP0 structure's pointers depend on stage of
1374 * control transfer.
1375 */
1376static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1377 struct dwc2_hsotg_ep *hs_ep)
1378{
1379 switch (hsotg->ep0_state) {
1380 case DWC2_EP0_SETUP:
1381 case DWC2_EP0_STATUS_OUT:
1382 hs_ep->desc_list = hsotg->setup_desc[0];
1383 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1384 break;
1385 case DWC2_EP0_DATA_IN:
1386 case DWC2_EP0_STATUS_IN:
1387 hs_ep->desc_list = hsotg->ctrl_in_desc;
1388 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1389 break;
1390 case DWC2_EP0_DATA_OUT:
1391 hs_ep->desc_list = hsotg->ctrl_out_desc;
1392 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1393 break;
1394 default:
1395 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1396 hsotg->ep0_state);
1397 return -EINVAL;
1398 }
1399
1400 return 0;
1401}
1402
1403static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1404 gfp_t gfp_flags)
1405{
1406 struct dwc2_hsotg_req *hs_req = our_req(req);
1407 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1408 struct dwc2_hsotg *hs = hs_ep->parent;
1409 bool first;
1410 int ret;
1411 u32 maxsize = 0;
1412 u32 mask = 0;
1413
1414
1415 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1416 ep->name, req, req->length, req->buf, req->no_interrupt,
1417 req->zero, req->short_not_ok);
1418
1419 /* Prevent new request submission when controller is suspended */
1420 if (hs->lx_state != DWC2_L0) {
1421 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1422 __func__);
1423 return -EAGAIN;
1424 }
1425
1426 /* initialise status of the request */
1427 INIT_LIST_HEAD(&hs_req->queue);
1428 req->actual = 0;
1429 req->status = -EINPROGRESS;
1430
1431 /* Don't queue ISOC request if length greater than mps*mc */
1432 if (hs_ep->isochronous &&
1433 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1434 dev_err(hs->dev, "req length > maxpacket*mc\n");
1435 return -EINVAL;
1436 }
1437
1438 /* In DDMA mode for ISOC's don't queue request if length greater
1439 * than descriptor limits.
1440 */
1441 if (using_desc_dma(hs) && hs_ep->isochronous) {
1442 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1443 if (hs_ep->dir_in && req->length > maxsize) {
1444 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1445 req->length, maxsize);
1446 return -EINVAL;
1447 }
1448
1449 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1450 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1451 req->length, hs_ep->ep.maxpacket);
1452 return -EINVAL;
1453 }
1454 }
1455
1456 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1457 if (ret)
1458 return ret;
1459
1460 /* if we're using DMA, sync the buffers as necessary */
1461 if (using_dma(hs)) {
1462 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1463 if (ret)
1464 return ret;
1465 }
1466 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1467 if (using_desc_dma(hs) && !hs_ep->index) {
1468 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1469 if (ret)
1470 return ret;
1471 }
1472
1473 first = list_empty(&hs_ep->queue);
1474 list_add_tail(&hs_req->queue, &hs_ep->queue);
1475
1476 /*
1477 * Handle DDMA isochronous transfers separately - just add new entry
1478 * to the descriptor chain.
1479 * Transfer will be started once SW gets either one of NAK or
1480 * OutTknEpDis interrupts.
1481 */
1482 if (using_desc_dma(hs) && hs_ep->isochronous) {
1483 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1484 dma_addr_t dma_addr = hs_req->req.dma;
1485
1486 if (hs_req->req.num_sgs) {
1487 WARN_ON(hs_req->req.num_sgs > 1);
1488 dma_addr = sg_dma_address(hs_req->req.sg);
1489 }
1490 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1491 hs_req->req.length);
1492 }
1493 return 0;
1494 }
1495
1496 /* Change EP direction if status phase request is after data out */
1497 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1498 hs->ep0_state == DWC2_EP0_DATA_OUT)
1499 hs_ep->dir_in = 1;
1500
1501 if (first) {
1502 if (!hs_ep->isochronous) {
1503 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1504 return 0;
1505 }
1506
1507 /* Update current frame number value. */
1508 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1509 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1510 dwc2_gadget_incr_frame_num(hs_ep);
1511 /* Update current frame number value once more as it
1512 * changes here.
1513 */
1514 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1515 }
1516
1517 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1518 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1519 }
1520 return 0;
1521}
1522
1523static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1524 gfp_t gfp_flags)
1525{
1526 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1527 struct dwc2_hsotg *hs = hs_ep->parent;
1528 unsigned long flags;
1529 int ret;
1530
1531 spin_lock_irqsave(&hs->lock, flags);
1532 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1533 spin_unlock_irqrestore(&hs->lock, flags);
1534
1535 return ret;
1536}
1537
1538static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1539 struct usb_request *req)
1540{
1541 struct dwc2_hsotg_req *hs_req = our_req(req);
1542
1543 kfree(hs_req);
1544}
1545
1546/**
1547 * dwc2_hsotg_complete_oursetup - setup completion callback
1548 * @ep: The endpoint the request was on.
1549 * @req: The request completed.
1550 *
1551 * Called on completion of any requests the driver itself
1552 * submitted that need cleaning up.
1553 */
1554static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1555 struct usb_request *req)
1556{
1557 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1558 struct dwc2_hsotg *hsotg = hs_ep->parent;
1559
1560 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1561
1562 dwc2_hsotg_ep_free_request(ep, req);
1563}
1564
1565/**
1566 * ep_from_windex - convert control wIndex value to endpoint
1567 * @hsotg: The driver state.
1568 * @windex: The control request wIndex field (in host order).
1569 *
1570 * Convert the given wIndex into a pointer to an driver endpoint
1571 * structure, or return NULL if it is not a valid endpoint.
1572 */
1573static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1574 u32 windex)
1575{
1576 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1577 int idx = windex & 0x7F;
1578
1579 if (windex >= 0x100)
1580 return NULL;
1581
1582 if (idx > hsotg->num_of_eps)
1583 return NULL;
1584
1585 return index_to_ep(hsotg, idx, dir);
1586}
1587
1588/**
1589 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1590 * @hsotg: The driver state.
1591 * @testmode: requested usb test mode
1592 * Enable usb Test Mode requested by the Host.
1593 */
1594int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1595{
1596 int dctl = dwc2_readl(hsotg, DCTL);
1597
1598 dctl &= ~DCTL_TSTCTL_MASK;
1599 switch (testmode) {
1600 case USB_TEST_J:
1601 case USB_TEST_K:
1602 case USB_TEST_SE0_NAK:
1603 case USB_TEST_PACKET:
1604 case USB_TEST_FORCE_ENABLE:
1605 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1606 break;
1607 default:
1608 return -EINVAL;
1609 }
1610 dwc2_writel(hsotg, dctl, DCTL);
1611 return 0;
1612}
1613
1614/**
1615 * dwc2_hsotg_send_reply - send reply to control request
1616 * @hsotg: The device state
1617 * @ep: Endpoint 0
1618 * @buff: Buffer for request
1619 * @length: Length of reply.
1620 *
1621 * Create a request and queue it on the given endpoint. This is useful as
1622 * an internal method of sending replies to certain control requests, etc.
1623 */
1624static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1625 struct dwc2_hsotg_ep *ep,
1626 void *buff,
1627 int length)
1628{
1629 struct usb_request *req;
1630 int ret;
1631
1632 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1633
1634 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1635 hsotg->ep0_reply = req;
1636 if (!req) {
1637 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1638 return -ENOMEM;
1639 }
1640
1641 req->buf = hsotg->ep0_buff;
1642 req->length = length;
1643 /*
1644 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1645 * STATUS stage.
1646 */
1647 req->zero = 0;
1648 req->complete = dwc2_hsotg_complete_oursetup;
1649
1650 if (length)
1651 memcpy(req->buf, buff, length);
1652
1653 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1654 if (ret) {
1655 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1656 return ret;
1657 }
1658
1659 return 0;
1660}
1661
1662/**
1663 * dwc2_hsotg_process_req_status - process request GET_STATUS
1664 * @hsotg: The device state
1665 * @ctrl: USB control request
1666 */
1667static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1668 struct usb_ctrlrequest *ctrl)
1669{
1670 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1671 struct dwc2_hsotg_ep *ep;
1672 __le16 reply;
1673 u16 status;
1674 int ret;
1675
1676 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1677
1678 if (!ep0->dir_in) {
1679 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1680 return -EINVAL;
1681 }
1682
1683 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1684 case USB_RECIP_DEVICE:
1685 status = hsotg->gadget.is_selfpowered <<
1686 USB_DEVICE_SELF_POWERED;
1687 status |= hsotg->remote_wakeup_allowed <<
1688 USB_DEVICE_REMOTE_WAKEUP;
1689 reply = cpu_to_le16(status);
1690 break;
1691
1692 case USB_RECIP_INTERFACE:
1693 /* currently, the data result should be zero */
1694 reply = cpu_to_le16(0);
1695 break;
1696
1697 case USB_RECIP_ENDPOINT:
1698 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1699 if (!ep)
1700 return -ENOENT;
1701
1702 reply = cpu_to_le16(ep->halted ? 1 : 0);
1703 break;
1704
1705 default:
1706 return 0;
1707 }
1708
1709 if (le16_to_cpu(ctrl->wLength) != 2)
1710 return -EINVAL;
1711
1712 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1713 if (ret) {
1714 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1715 return ret;
1716 }
1717
1718 return 1;
1719}
1720
1721static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1722
1723/**
1724 * get_ep_head - return the first request on the endpoint
1725 * @hs_ep: The controller endpoint to get
1726 *
1727 * Get the first request on the endpoint.
1728 */
1729static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1730{
1731 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1732 queue);
1733}
1734
1735/**
1736 * dwc2_gadget_start_next_request - Starts next request from ep queue
1737 * @hs_ep: Endpoint structure
1738 *
1739 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1740 * in its handler. Hence we need to unmask it here to be able to do
1741 * resynchronization.
1742 */
1743static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1744{
1745 struct dwc2_hsotg *hsotg = hs_ep->parent;
1746 int dir_in = hs_ep->dir_in;
1747 struct dwc2_hsotg_req *hs_req;
1748
1749 if (!list_empty(&hs_ep->queue)) {
1750 hs_req = get_ep_head(hs_ep);
1751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1752 return;
1753 }
1754 if (!hs_ep->isochronous)
1755 return;
1756
1757 if (dir_in) {
1758 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1759 __func__);
1760 } else {
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1762 __func__);
1763 }
1764}
1765
1766/**
1767 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1768 * @hsotg: The device state
1769 * @ctrl: USB control request
1770 */
1771static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1772 struct usb_ctrlrequest *ctrl)
1773{
1774 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1775 struct dwc2_hsotg_req *hs_req;
1776 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1777 struct dwc2_hsotg_ep *ep;
1778 int ret;
1779 bool halted;
1780 u32 recip;
1781 u32 wValue;
1782 u32 wIndex;
1783
1784 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1785 __func__, set ? "SET" : "CLEAR");
1786
1787 wValue = le16_to_cpu(ctrl->wValue);
1788 wIndex = le16_to_cpu(ctrl->wIndex);
1789 recip = ctrl->bRequestType & USB_RECIP_MASK;
1790
1791 switch (recip) {
1792 case USB_RECIP_DEVICE:
1793 switch (wValue) {
1794 case USB_DEVICE_REMOTE_WAKEUP:
1795 if (set)
1796 hsotg->remote_wakeup_allowed = 1;
1797 else
1798 hsotg->remote_wakeup_allowed = 0;
1799 break;
1800
1801 case USB_DEVICE_TEST_MODE:
1802 if ((wIndex & 0xff) != 0)
1803 return -EINVAL;
1804 if (!set)
1805 return -EINVAL;
1806
1807 hsotg->test_mode = wIndex >> 8;
1808 break;
1809 default:
1810 return -ENOENT;
1811 }
1812
1813 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1814 if (ret) {
1815 dev_err(hsotg->dev,
1816 "%s: failed to send reply\n", __func__);
1817 return ret;
1818 }
1819 break;
1820
1821 case USB_RECIP_ENDPOINT:
1822 ep = ep_from_windex(hsotg, wIndex);
1823 if (!ep) {
1824 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1825 __func__, wIndex);
1826 return -ENOENT;
1827 }
1828
1829 switch (wValue) {
1830 case USB_ENDPOINT_HALT:
1831 halted = ep->halted;
1832
1833 if (!ep->wedged)
1834 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1835
1836 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1837 if (ret) {
1838 dev_err(hsotg->dev,
1839 "%s: failed to send reply\n", __func__);
1840 return ret;
1841 }
1842
1843 /*
1844 * we have to complete all requests for ep if it was
1845 * halted, and the halt was cleared by CLEAR_FEATURE
1846 */
1847
1848 if (!set && halted) {
1849 /*
1850 * If we have request in progress,
1851 * then complete it
1852 */
1853 if (ep->req) {
1854 hs_req = ep->req;
1855 ep->req = NULL;
1856 list_del_init(&hs_req->queue);
1857 if (hs_req->req.complete) {
1858 spin_unlock(&hsotg->lock);
1859 usb_gadget_giveback_request(
1860 &ep->ep, &hs_req->req);
1861 spin_lock(&hsotg->lock);
1862 }
1863 }
1864
1865 /* If we have pending request, then start it */
1866 if (!ep->req)
1867 dwc2_gadget_start_next_request(ep);
1868 }
1869
1870 break;
1871
1872 default:
1873 return -ENOENT;
1874 }
1875 break;
1876 default:
1877 return -ENOENT;
1878 }
1879 return 1;
1880}
1881
1882static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1883
1884/**
1885 * dwc2_hsotg_stall_ep0 - stall ep0
1886 * @hsotg: The device state
1887 *
1888 * Set stall for ep0 as response for setup request.
1889 */
1890static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1891{
1892 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1893 u32 reg;
1894 u32 ctrl;
1895
1896 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1897 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1898
1899 /*
1900 * DxEPCTL_Stall will be cleared by EP once it has
1901 * taken effect, so no need to clear later.
1902 */
1903
1904 ctrl = dwc2_readl(hsotg, reg);
1905 ctrl |= DXEPCTL_STALL;
1906 ctrl |= DXEPCTL_CNAK;
1907 dwc2_writel(hsotg, ctrl, reg);
1908
1909 dev_dbg(hsotg->dev,
1910 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1911 ctrl, reg, dwc2_readl(hsotg, reg));
1912
1913 /*
1914 * complete won't be called, so we enqueue
1915 * setup request here
1916 */
1917 dwc2_hsotg_enqueue_setup(hsotg);
1918}
1919
1920/**
1921 * dwc2_hsotg_process_control - process a control request
1922 * @hsotg: The device state
1923 * @ctrl: The control request received
1924 *
1925 * The controller has received the SETUP phase of a control request, and
1926 * needs to work out what to do next (and whether to pass it on to the
1927 * gadget driver).
1928 */
1929static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1930 struct usb_ctrlrequest *ctrl)
1931{
1932 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1933 int ret = 0;
1934 u32 dcfg;
1935
1936 dev_dbg(hsotg->dev,
1937 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1938 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1939 ctrl->wIndex, ctrl->wLength);
1940
1941 if (ctrl->wLength == 0) {
1942 ep0->dir_in = 1;
1943 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1944 } else if (ctrl->bRequestType & USB_DIR_IN) {
1945 ep0->dir_in = 1;
1946 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1947 } else {
1948 ep0->dir_in = 0;
1949 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1950 }
1951
1952 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1953 switch (ctrl->bRequest) {
1954 case USB_REQ_SET_ADDRESS:
1955 hsotg->connected = 1;
1956 dcfg = dwc2_readl(hsotg, DCFG);
1957 dcfg &= ~DCFG_DEVADDR_MASK;
1958 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1959 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1960 dwc2_writel(hsotg, dcfg, DCFG);
1961
1962 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1963
1964 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1965 return;
1966
1967 case USB_REQ_GET_STATUS:
1968 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1969 break;
1970
1971 case USB_REQ_CLEAR_FEATURE:
1972 case USB_REQ_SET_FEATURE:
1973 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1974 break;
1975 }
1976 }
1977
1978 /* as a fallback, try delivering it to the driver to deal with */
1979
1980 if (ret == 0 && hsotg->driver) {
1981 spin_unlock(&hsotg->lock);
1982 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1983 spin_lock(&hsotg->lock);
1984 if (ret < 0)
1985 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1986 }
1987
1988 hsotg->delayed_status = false;
1989 if (ret == USB_GADGET_DELAYED_STATUS)
1990 hsotg->delayed_status = true;
1991
1992 /*
1993 * the request is either unhandlable, or is not formatted correctly
1994 * so respond with a STALL for the status stage to indicate failure.
1995 */
1996
1997 if (ret < 0)
1998 dwc2_hsotg_stall_ep0(hsotg);
1999}
2000
2001/**
2002 * dwc2_hsotg_complete_setup - completion of a setup transfer
2003 * @ep: The endpoint the request was on.
2004 * @req: The request completed.
2005 *
2006 * Called on completion of any requests the driver itself submitted for
2007 * EP0 setup packets
2008 */
2009static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2010 struct usb_request *req)
2011{
2012 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2013 struct dwc2_hsotg *hsotg = hs_ep->parent;
2014
2015 if (req->status < 0) {
2016 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2017 return;
2018 }
2019
2020 spin_lock(&hsotg->lock);
2021 if (req->actual == 0)
2022 dwc2_hsotg_enqueue_setup(hsotg);
2023 else
2024 dwc2_hsotg_process_control(hsotg, req->buf);
2025 spin_unlock(&hsotg->lock);
2026}
2027
2028/**
2029 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2030 * @hsotg: The device state.
2031 *
2032 * Enqueue a request on EP0 if necessary to received any SETUP packets
2033 * received from the host.
2034 */
2035static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2036{
2037 struct usb_request *req = hsotg->ctrl_req;
2038 struct dwc2_hsotg_req *hs_req = our_req(req);
2039 int ret;
2040
2041 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2042
2043 req->zero = 0;
2044 req->length = 8;
2045 req->buf = hsotg->ctrl_buff;
2046 req->complete = dwc2_hsotg_complete_setup;
2047
2048 if (!list_empty(&hs_req->queue)) {
2049 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2050 return;
2051 }
2052
2053 hsotg->eps_out[0]->dir_in = 0;
2054 hsotg->eps_out[0]->send_zlp = 0;
2055 hsotg->ep0_state = DWC2_EP0_SETUP;
2056
2057 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2058 if (ret < 0) {
2059 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2060 /*
2061 * Don't think there's much we can do other than watch the
2062 * driver fail.
2063 */
2064 }
2065}
2066
2067static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2068 struct dwc2_hsotg_ep *hs_ep)
2069{
2070 u32 ctrl;
2071 u8 index = hs_ep->index;
2072 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2073 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2074
2075 if (hs_ep->dir_in)
2076 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2077 index);
2078 else
2079 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2080 index);
2081 if (using_desc_dma(hsotg)) {
2082 /* Not specific buffer needed for ep0 ZLP */
2083 dma_addr_t dma = hs_ep->desc_list_dma;
2084
2085 if (!index)
2086 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2087
2088 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2089 } else {
2090 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2091 DXEPTSIZ_XFERSIZE(0),
2092 epsiz_reg);
2093 }
2094
2095 ctrl = dwc2_readl(hsotg, epctl_reg);
2096 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2097 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2098 ctrl |= DXEPCTL_USBACTEP;
2099 dwc2_writel(hsotg, ctrl, epctl_reg);
2100}
2101
2102/**
2103 * dwc2_hsotg_complete_request - complete a request given to us
2104 * @hsotg: The device state.
2105 * @hs_ep: The endpoint the request was on.
2106 * @hs_req: The request to complete.
2107 * @result: The result code (0 => Ok, otherwise errno)
2108 *
2109 * The given request has finished, so call the necessary completion
2110 * if it has one and then look to see if we can start a new request
2111 * on the endpoint.
2112 *
2113 * Note, expects the ep to already be locked as appropriate.
2114 */
2115static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2116 struct dwc2_hsotg_ep *hs_ep,
2117 struct dwc2_hsotg_req *hs_req,
2118 int result)
2119{
2120 if (!hs_req) {
2121 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2122 return;
2123 }
2124
2125 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2126 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2127
2128 /*
2129 * only replace the status if we've not already set an error
2130 * from a previous transaction
2131 */
2132
2133 if (hs_req->req.status == -EINPROGRESS)
2134 hs_req->req.status = result;
2135
2136 if (using_dma(hsotg))
2137 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2138
2139 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2140
2141 hs_ep->req = NULL;
2142 list_del_init(&hs_req->queue);
2143
2144 /*
2145 * call the complete request with the locks off, just in case the
2146 * request tries to queue more work for this endpoint.
2147 */
2148
2149 if (hs_req->req.complete) {
2150 spin_unlock(&hsotg->lock);
2151 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2152 spin_lock(&hsotg->lock);
2153 }
2154
2155 /* In DDMA don't need to proceed to starting of next ISOC request */
2156 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2157 return;
2158
2159 /*
2160 * Look to see if there is anything else to do. Note, the completion
2161 * of the previous request may have caused a new request to be started
2162 * so be careful when doing this.
2163 */
2164
2165 if (!hs_ep->req && result >= 0)
2166 dwc2_gadget_start_next_request(hs_ep);
2167}
2168
2169/*
2170 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2171 * @hs_ep: The endpoint the request was on.
2172 *
2173 * Get first request from the ep queue, determine descriptor on which complete
2174 * happened. SW discovers which descriptor currently in use by HW, adjusts
2175 * dma_address and calculates index of completed descriptor based on the value
2176 * of DEPDMA register. Update actual length of request, giveback to gadget.
2177 */
2178static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2179{
2180 struct dwc2_hsotg *hsotg = hs_ep->parent;
2181 struct dwc2_hsotg_req *hs_req;
2182 struct usb_request *ureq;
2183 u32 desc_sts;
2184 u32 mask;
2185
2186 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2187
2188 /* Process only descriptors with buffer status set to DMA done */
2189 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2190 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2191
2192 hs_req = get_ep_head(hs_ep);
2193 if (!hs_req) {
2194 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2195 return;
2196 }
2197 ureq = &hs_req->req;
2198
2199 /* Check completion status */
2200 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2201 DEV_DMA_STS_SUCC) {
2202 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2203 DEV_DMA_ISOC_RX_NBYTES_MASK;
2204 ureq->actual = ureq->length - ((desc_sts & mask) >>
2205 DEV_DMA_ISOC_NBYTES_SHIFT);
2206
2207 /* Adjust actual len for ISOC Out if len is
2208 * not align of 4
2209 */
2210 if (!hs_ep->dir_in && ureq->length & 0x3)
2211 ureq->actual += 4 - (ureq->length & 0x3);
2212
2213 /* Set actual frame number for completed transfers */
2214 ureq->frame_number =
2215 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2216 DEV_DMA_ISOC_FRNUM_SHIFT;
2217 }
2218
2219 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2220
2221 hs_ep->compl_desc++;
2222 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2223 hs_ep->compl_desc = 0;
2224 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2225 }
2226}
2227
2228/*
2229 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2230 * @hs_ep: The isochronous endpoint.
2231 *
2232 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2233 * interrupt. Reset target frame and next_desc to allow to start
2234 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2235 * interrupt for OUT direction.
2236 */
2237static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2238{
2239 struct dwc2_hsotg *hsotg = hs_ep->parent;
2240
2241 if (!hs_ep->dir_in)
2242 dwc2_flush_rx_fifo(hsotg);
2243 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2244
2245 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2246 hs_ep->next_desc = 0;
2247 hs_ep->compl_desc = 0;
2248}
2249
2250/**
2251 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2252 * @hsotg: The device state.
2253 * @ep_idx: The endpoint index for the data
2254 * @size: The size of data in the fifo, in bytes
2255 *
2256 * The FIFO status shows there is data to read from the FIFO for a given
2257 * endpoint, so sort out whether we need to read the data into a request
2258 * that has been made for that endpoint.
2259 */
2260static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2261{
2262 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2263 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2264 int to_read;
2265 int max_req;
2266 int read_ptr;
2267
2268 if (!hs_req) {
2269 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2270 int ptr;
2271
2272 dev_dbg(hsotg->dev,
2273 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2274 __func__, size, ep_idx, epctl);
2275
2276 /* dump the data from the FIFO, we've nothing we can do */
2277 for (ptr = 0; ptr < size; ptr += 4)
2278 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2279
2280 return;
2281 }
2282
2283 to_read = size;
2284 read_ptr = hs_req->req.actual;
2285 max_req = hs_req->req.length - read_ptr;
2286
2287 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2288 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2289
2290 if (to_read > max_req) {
2291 /*
2292 * more data appeared than we where willing
2293 * to deal with in this request.
2294 */
2295
2296 /* currently we don't deal this */
2297 WARN_ON_ONCE(1);
2298 }
2299
2300 hs_ep->total_data += to_read;
2301 hs_req->req.actual += to_read;
2302 to_read = DIV_ROUND_UP(to_read, 4);
2303
2304 /*
2305 * note, we might over-write the buffer end by 3 bytes depending on
2306 * alignment of the data.
2307 */
2308 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2309 hs_req->req.buf + read_ptr, to_read);
2310}
2311
2312/**
2313 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2314 * @hsotg: The device instance
2315 * @dir_in: If IN zlp
2316 *
2317 * Generate a zero-length IN packet request for terminating a SETUP
2318 * transaction.
2319 *
2320 * Note, since we don't write any data to the TxFIFO, then it is
2321 * currently believed that we do not need to wait for any space in
2322 * the TxFIFO.
2323 */
2324static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2325{
2326 /* eps_out[0] is used in both directions */
2327 hsotg->eps_out[0]->dir_in = dir_in;
2328 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2329
2330 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2331}
2332
2333/*
2334 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2335 * @hs_ep - The endpoint on which transfer went
2336 *
2337 * Iterate over endpoints descriptor chain and get info on bytes remained
2338 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2339 */
2340static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2341{
2342 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2343 struct dwc2_hsotg *hsotg = hs_ep->parent;
2344 unsigned int bytes_rem = 0;
2345 unsigned int bytes_rem_correction = 0;
2346 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2347 int i;
2348 u32 status;
2349 u32 mps = hs_ep->ep.maxpacket;
2350 int dir_in = hs_ep->dir_in;
2351
2352 if (!desc)
2353 return -EINVAL;
2354
2355 /* Interrupt OUT EP with mps not multiple of 4 */
2356 if (hs_ep->index)
2357 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2358 bytes_rem_correction = 4 - (mps % 4);
2359
2360 for (i = 0; i < hs_ep->desc_count; ++i) {
2361 status = desc->status;
2362 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2363 bytes_rem -= bytes_rem_correction;
2364
2365 if (status & DEV_DMA_STS_MASK)
2366 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2367 i, status & DEV_DMA_STS_MASK);
2368
2369 if (status & DEV_DMA_L)
2370 break;
2371
2372 desc++;
2373 }
2374
2375 return bytes_rem;
2376}
2377
2378/**
2379 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2380 * @hsotg: The device instance
2381 * @epnum: The endpoint received from
2382 *
2383 * The RXFIFO has delivered an OutDone event, which means that the data
2384 * transfer for an OUT endpoint has been completed, either by a short
2385 * packet or by the finish of a transfer.
2386 */
2387static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2388{
2389 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2390 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2391 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2392 struct usb_request *req = &hs_req->req;
2393 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2394 int result = 0;
2395
2396 if (!hs_req) {
2397 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2398 return;
2399 }
2400
2401 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2402 dev_dbg(hsotg->dev, "zlp packet received\n");
2403 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2404 dwc2_hsotg_enqueue_setup(hsotg);
2405 return;
2406 }
2407
2408 if (using_desc_dma(hsotg))
2409 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2410
2411 if (using_dma(hsotg)) {
2412 unsigned int size_done;
2413
2414 /*
2415 * Calculate the size of the transfer by checking how much
2416 * is left in the endpoint size register and then working it
2417 * out from the amount we loaded for the transfer.
2418 *
2419 * We need to do this as DMA pointers are always 32bit aligned
2420 * so may overshoot/undershoot the transfer.
2421 */
2422
2423 size_done = hs_ep->size_loaded - size_left;
2424 size_done += hs_ep->last_load;
2425
2426 req->actual = size_done;
2427 }
2428
2429 /* if there is more request to do, schedule new transfer */
2430 if (req->actual < req->length && size_left == 0) {
2431 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2432 return;
2433 }
2434
2435 if (req->actual < req->length && req->short_not_ok) {
2436 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2437 __func__, req->actual, req->length);
2438
2439 /*
2440 * todo - what should we return here? there's no one else
2441 * even bothering to check the status.
2442 */
2443 }
2444
2445 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2446 if (!using_desc_dma(hsotg) && epnum == 0 &&
2447 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2448 /* Move to STATUS IN */
2449 if (!hsotg->delayed_status)
2450 dwc2_hsotg_ep0_zlp(hsotg, true);
2451 }
2452
2453 /* Set actual frame number for completed transfers */
2454 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2455 req->frame_number = hs_ep->target_frame;
2456 dwc2_gadget_incr_frame_num(hs_ep);
2457 }
2458
2459 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2460}
2461
2462/**
2463 * dwc2_hsotg_handle_rx - RX FIFO has data
2464 * @hsotg: The device instance
2465 *
2466 * The IRQ handler has detected that the RX FIFO has some data in it
2467 * that requires processing, so find out what is in there and do the
2468 * appropriate read.
2469 *
2470 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2471 * chunks, so if you have x packets received on an endpoint you'll get x
2472 * FIFO events delivered, each with a packet's worth of data in it.
2473 *
2474 * When using DMA, we should not be processing events from the RXFIFO
2475 * as the actual data should be sent to the memory directly and we turn
2476 * on the completion interrupts to get notifications of transfer completion.
2477 */
2478static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2479{
2480 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2481 u32 epnum, status, size;
2482
2483 WARN_ON(using_dma(hsotg));
2484
2485 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2486 status = grxstsr & GRXSTS_PKTSTS_MASK;
2487
2488 size = grxstsr & GRXSTS_BYTECNT_MASK;
2489 size >>= GRXSTS_BYTECNT_SHIFT;
2490
2491 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2492 __func__, grxstsr, size, epnum);
2493
2494 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2495 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2496 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2497 break;
2498
2499 case GRXSTS_PKTSTS_OUTDONE:
2500 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2501 dwc2_hsotg_read_frameno(hsotg));
2502
2503 if (!using_dma(hsotg))
2504 dwc2_hsotg_handle_outdone(hsotg, epnum);
2505 break;
2506
2507 case GRXSTS_PKTSTS_SETUPDONE:
2508 dev_dbg(hsotg->dev,
2509 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2510 dwc2_hsotg_read_frameno(hsotg),
2511 dwc2_readl(hsotg, DOEPCTL(0)));
2512 /*
2513 * Call dwc2_hsotg_handle_outdone here if it was not called from
2514 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2515 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2516 */
2517 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2518 dwc2_hsotg_handle_outdone(hsotg, epnum);
2519 break;
2520
2521 case GRXSTS_PKTSTS_OUTRX:
2522 dwc2_hsotg_rx_data(hsotg, epnum, size);
2523 break;
2524
2525 case GRXSTS_PKTSTS_SETUPRX:
2526 dev_dbg(hsotg->dev,
2527 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2528 dwc2_hsotg_read_frameno(hsotg),
2529 dwc2_readl(hsotg, DOEPCTL(0)));
2530
2531 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2532
2533 dwc2_hsotg_rx_data(hsotg, epnum, size);
2534 break;
2535
2536 default:
2537 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2538 __func__, grxstsr);
2539
2540 dwc2_hsotg_dump(hsotg);
2541 break;
2542 }
2543}
2544
2545/**
2546 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2547 * @mps: The maximum packet size in bytes.
2548 */
2549static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2550{
2551 switch (mps) {
2552 case 64:
2553 return D0EPCTL_MPS_64;
2554 case 32:
2555 return D0EPCTL_MPS_32;
2556 case 16:
2557 return D0EPCTL_MPS_16;
2558 case 8:
2559 return D0EPCTL_MPS_8;
2560 }
2561
2562 /* bad max packet size, warn and return invalid result */
2563 WARN_ON(1);
2564 return (u32)-1;
2565}
2566
2567/**
2568 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2569 * @hsotg: The driver state.
2570 * @ep: The index number of the endpoint
2571 * @mps: The maximum packet size in bytes
2572 * @mc: The multicount value
2573 * @dir_in: True if direction is in.
2574 *
2575 * Configure the maximum packet size for the given endpoint, updating
2576 * the hardware control registers to reflect this.
2577 */
2578static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2579 unsigned int ep, unsigned int mps,
2580 unsigned int mc, unsigned int dir_in)
2581{
2582 struct dwc2_hsotg_ep *hs_ep;
2583 u32 reg;
2584
2585 hs_ep = index_to_ep(hsotg, ep, dir_in);
2586 if (!hs_ep)
2587 return;
2588
2589 if (ep == 0) {
2590 u32 mps_bytes = mps;
2591
2592 /* EP0 is a special case */
2593 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2594 if (mps > 3)
2595 goto bad_mps;
2596 hs_ep->ep.maxpacket = mps_bytes;
2597 hs_ep->mc = 1;
2598 } else {
2599 if (mps > 1024)
2600 goto bad_mps;
2601 hs_ep->mc = mc;
2602 if (mc > 3)
2603 goto bad_mps;
2604 hs_ep->ep.maxpacket = mps;
2605 }
2606
2607 if (dir_in) {
2608 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2609 reg &= ~DXEPCTL_MPS_MASK;
2610 reg |= mps;
2611 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2612 } else {
2613 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2614 reg &= ~DXEPCTL_MPS_MASK;
2615 reg |= mps;
2616 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2617 }
2618
2619 return;
2620
2621bad_mps:
2622 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2623}
2624
2625/**
2626 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2627 * @hsotg: The driver state
2628 * @idx: The index for the endpoint (0..15)
2629 */
2630static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2631{
2632 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2633 GRSTCTL);
2634
2635 /* wait until the fifo is flushed */
2636 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2637 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2638 __func__);
2639}
2640
2641/**
2642 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2643 * @hsotg: The driver state
2644 * @hs_ep: The driver endpoint to check.
2645 *
2646 * Check to see if there is a request that has data to send, and if so
2647 * make an attempt to write data into the FIFO.
2648 */
2649static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2650 struct dwc2_hsotg_ep *hs_ep)
2651{
2652 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2653
2654 if (!hs_ep->dir_in || !hs_req) {
2655 /**
2656 * if request is not enqueued, we disable interrupts
2657 * for endpoints, excepting ep0
2658 */
2659 if (hs_ep->index != 0)
2660 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2661 hs_ep->dir_in, 0);
2662 return 0;
2663 }
2664
2665 if (hs_req->req.actual < hs_req->req.length) {
2666 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2667 hs_ep->index);
2668 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2669 }
2670
2671 return 0;
2672}
2673
2674/**
2675 * dwc2_hsotg_complete_in - complete IN transfer
2676 * @hsotg: The device state.
2677 * @hs_ep: The endpoint that has just completed.
2678 *
2679 * An IN transfer has been completed, update the transfer's state and then
2680 * call the relevant completion routines.
2681 */
2682static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2683 struct dwc2_hsotg_ep *hs_ep)
2684{
2685 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2686 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2687 int size_left, size_done;
2688
2689 if (!hs_req) {
2690 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2691 return;
2692 }
2693
2694 /* Finish ZLP handling for IN EP0 transactions */
2695 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2696 dev_dbg(hsotg->dev, "zlp packet sent\n");
2697
2698 /*
2699 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2700 * changed to IN. Change back to complete OUT transfer request
2701 */
2702 hs_ep->dir_in = 0;
2703
2704 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2705 if (hsotg->test_mode) {
2706 int ret;
2707
2708 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2709 if (ret < 0) {
2710 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2711 hsotg->test_mode);
2712 dwc2_hsotg_stall_ep0(hsotg);
2713 return;
2714 }
2715 }
2716 dwc2_hsotg_enqueue_setup(hsotg);
2717 return;
2718 }
2719
2720 /*
2721 * Calculate the size of the transfer by checking how much is left
2722 * in the endpoint size register and then working it out from
2723 * the amount we loaded for the transfer.
2724 *
2725 * We do this even for DMA, as the transfer may have incremented
2726 * past the end of the buffer (DMA transfers are always 32bit
2727 * aligned).
2728 */
2729 if (using_desc_dma(hsotg)) {
2730 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2731 if (size_left < 0)
2732 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2733 size_left);
2734 } else {
2735 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2736 }
2737
2738 size_done = hs_ep->size_loaded - size_left;
2739 size_done += hs_ep->last_load;
2740
2741 if (hs_req->req.actual != size_done)
2742 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2743 __func__, hs_req->req.actual, size_done);
2744
2745 hs_req->req.actual = size_done;
2746 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2747 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2748
2749 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2750 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2752 return;
2753 }
2754
2755 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2756 if (hs_ep->send_zlp) {
2757 hs_ep->send_zlp = 0;
2758 if (!using_desc_dma(hsotg)) {
2759 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2760 /* transfer will be completed on next complete interrupt */
2761 return;
2762 }
2763 }
2764
2765 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2766 /* Move to STATUS OUT */
2767 dwc2_hsotg_ep0_zlp(hsotg, false);
2768 return;
2769 }
2770
2771 /* Set actual frame number for completed transfers */
2772 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2773 hs_req->req.frame_number = hs_ep->target_frame;
2774 dwc2_gadget_incr_frame_num(hs_ep);
2775 }
2776
2777 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2778}
2779
2780/**
2781 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2782 * @hsotg: The device state.
2783 * @idx: Index of ep.
2784 * @dir_in: Endpoint direction 1-in 0-out.
2785 *
2786 * Reads for endpoint with given index and direction, by masking
2787 * epint_reg with coresponding mask.
2788 */
2789static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2790 unsigned int idx, int dir_in)
2791{
2792 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2793 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2794 u32 ints;
2795 u32 mask;
2796 u32 diepempmsk;
2797
2798 mask = dwc2_readl(hsotg, epmsk_reg);
2799 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2800 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2801 mask |= DXEPINT_SETUP_RCVD;
2802
2803 ints = dwc2_readl(hsotg, epint_reg);
2804 ints &= mask;
2805 return ints;
2806}
2807
2808/**
2809 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2810 * @hs_ep: The endpoint on which interrupt is asserted.
2811 *
2812 * This interrupt indicates that the endpoint has been disabled per the
2813 * application's request.
2814 *
2815 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2816 * in case of ISOC completes current request.
2817 *
2818 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2819 * request starts it.
2820 */
2821static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2822{
2823 struct dwc2_hsotg *hsotg = hs_ep->parent;
2824 struct dwc2_hsotg_req *hs_req;
2825 unsigned char idx = hs_ep->index;
2826 int dir_in = hs_ep->dir_in;
2827 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2828 int dctl = dwc2_readl(hsotg, DCTL);
2829
2830 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2831
2832 if (dir_in) {
2833 int epctl = dwc2_readl(hsotg, epctl_reg);
2834
2835 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2836
2837 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2838 int dctl = dwc2_readl(hsotg, DCTL);
2839
2840 dctl |= DCTL_CGNPINNAK;
2841 dwc2_writel(hsotg, dctl, DCTL);
2842 }
2843 } else {
2844
2845 if (dctl & DCTL_GOUTNAKSTS) {
2846 dctl |= DCTL_CGOUTNAK;
2847 dwc2_writel(hsotg, dctl, DCTL);
2848 }
2849 }
2850
2851 if (!hs_ep->isochronous)
2852 return;
2853
2854 if (list_empty(&hs_ep->queue)) {
2855 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2856 __func__, hs_ep);
2857 return;
2858 }
2859
2860 do {
2861 hs_req = get_ep_head(hs_ep);
2862 if (hs_req) {
2863 hs_req->req.frame_number = hs_ep->target_frame;
2864 hs_req->req.actual = 0;
2865 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2866 -ENODATA);
2867 }
2868 dwc2_gadget_incr_frame_num(hs_ep);
2869 /* Update current frame number value. */
2870 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2871 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2872}
2873
2874/**
2875 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2876 * @ep: The endpoint on which interrupt is asserted.
2877 *
2878 * This is starting point for ISOC-OUT transfer, synchronization done with
2879 * first out token received from host while corresponding EP is disabled.
2880 *
2881 * Device does not know initial frame in which out token will come. For this
2882 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2883 * getting this interrupt SW starts calculation for next transfer frame.
2884 */
2885static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2886{
2887 struct dwc2_hsotg *hsotg = ep->parent;
2888 struct dwc2_hsotg_req *hs_req;
2889 int dir_in = ep->dir_in;
2890
2891 if (dir_in || !ep->isochronous)
2892 return;
2893
2894 if (using_desc_dma(hsotg)) {
2895 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2896 /* Start first ISO Out */
2897 ep->target_frame = hsotg->frame_number;
2898 dwc2_gadget_start_isoc_ddma(ep);
2899 }
2900 return;
2901 }
2902
2903 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2904 u32 ctrl;
2905
2906 ep->target_frame = hsotg->frame_number;
2907 if (ep->interval > 1) {
2908 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2909 if (ep->target_frame & 0x1)
2910 ctrl |= DXEPCTL_SETODDFR;
2911 else
2912 ctrl |= DXEPCTL_SETEVENFR;
2913
2914 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2915 }
2916 }
2917
2918 while (dwc2_gadget_target_frame_elapsed(ep)) {
2919 hs_req = get_ep_head(ep);
2920 if (hs_req) {
2921 hs_req->req.frame_number = ep->target_frame;
2922 hs_req->req.actual = 0;
2923 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2924 }
2925
2926 dwc2_gadget_incr_frame_num(ep);
2927 /* Update current frame number value. */
2928 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2929 }
2930
2931 if (!ep->req)
2932 dwc2_gadget_start_next_request(ep);
2933
2934}
2935
2936static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2937 struct dwc2_hsotg_ep *hs_ep);
2938
2939/**
2940 * dwc2_gadget_handle_nak - handle NAK interrupt
2941 * @hs_ep: The endpoint on which interrupt is asserted.
2942 *
2943 * This is starting point for ISOC-IN transfer, synchronization done with
2944 * first IN token received from host while corresponding EP is disabled.
2945 *
2946 * Device does not know when first one token will arrive from host. On first
2947 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2948 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2949 * sent in response to that as there was no data in FIFO. SW is basing on this
2950 * interrupt to obtain frame in which token has come and then based on the
2951 * interval calculates next frame for transfer.
2952 */
2953static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2954{
2955 struct dwc2_hsotg *hsotg = hs_ep->parent;
2956 struct dwc2_hsotg_req *hs_req;
2957 int dir_in = hs_ep->dir_in;
2958 u32 ctrl;
2959
2960 if (!dir_in || !hs_ep->isochronous)
2961 return;
2962
2963 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2964
2965 if (using_desc_dma(hsotg)) {
2966 hs_ep->target_frame = hsotg->frame_number;
2967 dwc2_gadget_incr_frame_num(hs_ep);
2968
2969 /* In service interval mode target_frame must
2970 * be set to last (u)frame of the service interval.
2971 */
2972 if (hsotg->params.service_interval) {
2973 /* Set target_frame to the first (u)frame of
2974 * the service interval
2975 */
2976 hs_ep->target_frame &= ~hs_ep->interval + 1;
2977
2978 /* Set target_frame to the last (u)frame of
2979 * the service interval
2980 */
2981 dwc2_gadget_incr_frame_num(hs_ep);
2982 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2983 }
2984
2985 dwc2_gadget_start_isoc_ddma(hs_ep);
2986 return;
2987 }
2988
2989 hs_ep->target_frame = hsotg->frame_number;
2990 if (hs_ep->interval > 1) {
2991 u32 ctrl = dwc2_readl(hsotg,
2992 DIEPCTL(hs_ep->index));
2993 if (hs_ep->target_frame & 0x1)
2994 ctrl |= DXEPCTL_SETODDFR;
2995 else
2996 ctrl |= DXEPCTL_SETEVENFR;
2997
2998 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2999 }
3000 }
3001
3002 if (using_desc_dma(hsotg))
3003 return;
3004
3005 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3006 if (ctrl & DXEPCTL_EPENA)
3007 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3008 else
3009 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3010
3011 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3012 hs_req = get_ep_head(hs_ep);
3013 if (hs_req) {
3014 hs_req->req.frame_number = hs_ep->target_frame;
3015 hs_req->req.actual = 0;
3016 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3017 }
3018
3019 dwc2_gadget_incr_frame_num(hs_ep);
3020 /* Update current frame number value. */
3021 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3022 }
3023
3024 if (!hs_ep->req)
3025 dwc2_gadget_start_next_request(hs_ep);
3026}
3027
3028/**
3029 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3030 * @hsotg: The driver state
3031 * @idx: The index for the endpoint (0..15)
3032 * @dir_in: Set if this is an IN endpoint
3033 *
3034 * Process and clear any interrupt pending for an individual endpoint
3035 */
3036static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3037 int dir_in)
3038{
3039 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3040 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3041 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3042 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3043 u32 ints;
3044
3045 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3046
3047 /* Clear endpoint interrupts */
3048 dwc2_writel(hsotg, ints, epint_reg);
3049
3050 if (!hs_ep) {
3051 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3052 __func__, idx, dir_in ? "in" : "out");
3053 return;
3054 }
3055
3056 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3057 __func__, idx, dir_in ? "in" : "out", ints);
3058
3059 /* Don't process XferCompl interrupt if it is a setup packet */
3060 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3061 ints &= ~DXEPINT_XFERCOMPL;
3062
3063 /*
3064 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3065 * stage and xfercomplete was generated without SETUP phase done
3066 * interrupt. SW should parse received setup packet only after host's
3067 * exit from setup phase of control transfer.
3068 */
3069 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3070 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3071 ints &= ~DXEPINT_XFERCOMPL;
3072
3073 if (ints & DXEPINT_XFERCOMPL) {
3074 dev_dbg(hsotg->dev,
3075 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3076 __func__, dwc2_readl(hsotg, epctl_reg),
3077 dwc2_readl(hsotg, epsiz_reg));
3078
3079 /* In DDMA handle isochronous requests separately */
3080 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3081 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3082 } else if (dir_in) {
3083 /*
3084 * We get OutDone from the FIFO, so we only
3085 * need to look at completing IN requests here
3086 * if operating slave mode
3087 */
3088 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3089 dwc2_hsotg_complete_in(hsotg, hs_ep);
3090
3091 if (idx == 0 && !hs_ep->req)
3092 dwc2_hsotg_enqueue_setup(hsotg);
3093 } else if (using_dma(hsotg)) {
3094 /*
3095 * We're using DMA, we need to fire an OutDone here
3096 * as we ignore the RXFIFO.
3097 */
3098 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3099 dwc2_hsotg_handle_outdone(hsotg, idx);
3100 }
3101 }
3102
3103 if (ints & DXEPINT_EPDISBLD)
3104 dwc2_gadget_handle_ep_disabled(hs_ep);
3105
3106 if (ints & DXEPINT_OUTTKNEPDIS)
3107 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3108
3109 if (ints & DXEPINT_NAKINTRPT)
3110 dwc2_gadget_handle_nak(hs_ep);
3111
3112 if (ints & DXEPINT_AHBERR)
3113 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3114
3115 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3116 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3117
3118 if (using_dma(hsotg) && idx == 0) {
3119 /*
3120 * this is the notification we've received a
3121 * setup packet. In non-DMA mode we'd get this
3122 * from the RXFIFO, instead we need to process
3123 * the setup here.
3124 */
3125
3126 if (dir_in)
3127 WARN_ON_ONCE(1);
3128 else
3129 dwc2_hsotg_handle_outdone(hsotg, 0);
3130 }
3131 }
3132
3133 if (ints & DXEPINT_STSPHSERCVD) {
3134 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3135
3136 /* Safety check EP0 state when STSPHSERCVD asserted */
3137 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3138 /* Move to STATUS IN for DDMA */
3139 if (using_desc_dma(hsotg)) {
3140 if (!hsotg->delayed_status)
3141 dwc2_hsotg_ep0_zlp(hsotg, true);
3142 else
3143 /* In case of 3 stage Control Write with delayed
3144 * status, when Status IN transfer started
3145 * before STSPHSERCVD asserted, NAKSTS bit not
3146 * cleared by CNAK in dwc2_hsotg_start_req()
3147 * function. Clear now NAKSTS to allow complete
3148 * transfer.
3149 */
3150 dwc2_set_bit(hsotg, DIEPCTL(0),
3151 DXEPCTL_CNAK);
3152 }
3153 }
3154
3155 }
3156
3157 if (ints & DXEPINT_BACK2BACKSETUP)
3158 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3159
3160 if (ints & DXEPINT_BNAINTR) {
3161 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3162 if (hs_ep->isochronous)
3163 dwc2_gadget_handle_isoc_bna(hs_ep);
3164 }
3165
3166 if (dir_in && !hs_ep->isochronous) {
3167 /* not sure if this is important, but we'll clear it anyway */
3168 if (ints & DXEPINT_INTKNTXFEMP) {
3169 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3170 __func__, idx);
3171 }
3172
3173 /* this probably means something bad is happening */
3174 if (ints & DXEPINT_INTKNEPMIS) {
3175 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3176 __func__, idx);
3177 }
3178
3179 /* FIFO has space or is empty (see GAHBCFG) */
3180 if (hsotg->dedicated_fifos &&
3181 ints & DXEPINT_TXFEMP) {
3182 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3183 __func__, idx);
3184 if (!using_dma(hsotg))
3185 dwc2_hsotg_trytx(hsotg, hs_ep);
3186 }
3187 }
3188}
3189
3190/**
3191 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3192 * @hsotg: The device state.
3193 *
3194 * Handle updating the device settings after the enumeration phase has
3195 * been completed.
3196 */
3197static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3198{
3199 u32 dsts = dwc2_readl(hsotg, DSTS);
3200 int ep0_mps = 0, ep_mps = 8;
3201
3202 /*
3203 * This should signal the finish of the enumeration phase
3204 * of the USB handshaking, so we should now know what rate
3205 * we connected at.
3206 */
3207
3208 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3209
3210 /*
3211 * note, since we're limited by the size of transfer on EP0, and
3212 * it seems IN transfers must be a even number of packets we do
3213 * not advertise a 64byte MPS on EP0.
3214 */
3215
3216 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3217 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3218 case DSTS_ENUMSPD_FS:
3219 case DSTS_ENUMSPD_FS48:
3220 hsotg->gadget.speed = USB_SPEED_FULL;
3221 ep0_mps = EP0_MPS_LIMIT;
3222 ep_mps = 1023;
3223 break;
3224
3225 case DSTS_ENUMSPD_HS:
3226 hsotg->gadget.speed = USB_SPEED_HIGH;
3227 ep0_mps = EP0_MPS_LIMIT;
3228 ep_mps = 1024;
3229 break;
3230
3231 case DSTS_ENUMSPD_LS:
3232 hsotg->gadget.speed = USB_SPEED_LOW;
3233 ep0_mps = 8;
3234 ep_mps = 8;
3235 /*
3236 * note, we don't actually support LS in this driver at the
3237 * moment, and the documentation seems to imply that it isn't
3238 * supported by the PHYs on some of the devices.
3239 */
3240 break;
3241 }
3242 dev_info(hsotg->dev, "new device is %s\n",
3243 usb_speed_string(hsotg->gadget.speed));
3244
3245 /*
3246 * we should now know the maximum packet size for an
3247 * endpoint, so set the endpoints to a default value.
3248 */
3249
3250 if (ep0_mps) {
3251 int i;
3252 /* Initialize ep0 for both in and out directions */
3253 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3254 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3255 for (i = 1; i < hsotg->num_of_eps; i++) {
3256 if (hsotg->eps_in[i])
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3258 0, 1);
3259 if (hsotg->eps_out[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3261 0, 0);
3262 }
3263 }
3264
3265 /* ensure after enumeration our EP0 is active */
3266
3267 dwc2_hsotg_enqueue_setup(hsotg);
3268
3269 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3270 dwc2_readl(hsotg, DIEPCTL0),
3271 dwc2_readl(hsotg, DOEPCTL0));
3272}
3273
3274/**
3275 * kill_all_requests - remove all requests from the endpoint's queue
3276 * @hsotg: The device state.
3277 * @ep: The endpoint the requests may be on.
3278 * @result: The result code to use.
3279 *
3280 * Go through the requests on the given endpoint and mark them
3281 * completed with the given result code.
3282 */
3283static void kill_all_requests(struct dwc2_hsotg *hsotg,
3284 struct dwc2_hsotg_ep *ep,
3285 int result)
3286{
3287 unsigned int size;
3288
3289 ep->req = NULL;
3290
3291 while (!list_empty(&ep->queue)) {
3292 struct dwc2_hsotg_req *req = get_ep_head(ep);
3293
3294 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3295 }
3296
3297 if (!hsotg->dedicated_fifos)
3298 return;
3299 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3300 if (size < ep->fifo_size)
3301 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3302}
3303
3304/**
3305 * dwc2_hsotg_disconnect - disconnect service
3306 * @hsotg: The device state.
3307 *
3308 * The device has been disconnected. Remove all current
3309 * transactions and signal the gadget driver that this
3310 * has happened.
3311 */
3312void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3313{
3314 unsigned int ep;
3315
3316 if (!hsotg->connected)
3317 return;
3318
3319 hsotg->connected = 0;
3320 hsotg->test_mode = 0;
3321
3322 /* all endpoints should be shutdown */
3323 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3324 if (hsotg->eps_in[ep])
3325 kill_all_requests(hsotg, hsotg->eps_in[ep],
3326 -ESHUTDOWN);
3327 if (hsotg->eps_out[ep])
3328 kill_all_requests(hsotg, hsotg->eps_out[ep],
3329 -ESHUTDOWN);
3330 }
3331
3332 call_gadget(hsotg, disconnect);
3333 hsotg->lx_state = DWC2_L3;
3334
3335 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3336}
3337
3338/**
3339 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3340 * @hsotg: The device state:
3341 * @periodic: True if this is a periodic FIFO interrupt
3342 */
3343static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3344{
3345 struct dwc2_hsotg_ep *ep;
3346 int epno, ret;
3347
3348 /* look through for any more data to transmit */
3349 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3350 ep = index_to_ep(hsotg, epno, 1);
3351
3352 if (!ep)
3353 continue;
3354
3355 if (!ep->dir_in)
3356 continue;
3357
3358 if ((periodic && !ep->periodic) ||
3359 (!periodic && ep->periodic))
3360 continue;
3361
3362 ret = dwc2_hsotg_trytx(hsotg, ep);
3363 if (ret < 0)
3364 break;
3365 }
3366}
3367
3368/* IRQ flags which will trigger a retry around the IRQ loop */
3369#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3370 GINTSTS_PTXFEMP | \
3371 GINTSTS_RXFLVL)
3372
3373static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3374/**
3375 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3376 * @hsotg: The device state
3377 * @is_usb_reset: Usb resetting flag
3378 *
3379 * Issue a soft reset to the core, and await the core finishing it.
3380 */
3381void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3382 bool is_usb_reset)
3383{
3384 u32 intmsk;
3385 u32 val;
3386 u32 usbcfg;
3387 u32 dcfg = 0;
3388 int ep;
3389
3390 /* Kill any ep0 requests as controller will be reinitialized */
3391 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3392
3393 if (!is_usb_reset) {
3394 if (dwc2_core_reset(hsotg, true))
3395 return;
3396 } else {
3397 /* all endpoints should be shutdown */
3398 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3399 if (hsotg->eps_in[ep])
3400 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3401 if (hsotg->eps_out[ep])
3402 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3403 }
3404 }
3405
3406 /*
3407 * we must now enable ep0 ready for host detection and then
3408 * set configuration.
3409 */
3410
3411 /* keep other bits untouched (so e.g. forced modes are not lost) */
3412 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3413 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3414 usbcfg |= GUSBCFG_TOUTCAL(7);
3415
3416 /* remove the HNP/SRP and set the PHY */
3417 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3418 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3419
3420 dwc2_phy_init(hsotg, true);
3421
3422 dwc2_hsotg_init_fifo(hsotg);
3423
3424 if (!is_usb_reset)
3425 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3426
3427 dcfg |= DCFG_EPMISCNT(1);
3428
3429 switch (hsotg->params.speed) {
3430 case DWC2_SPEED_PARAM_LOW:
3431 dcfg |= DCFG_DEVSPD_LS;
3432 break;
3433 case DWC2_SPEED_PARAM_FULL:
3434 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3435 dcfg |= DCFG_DEVSPD_FS48;
3436 else
3437 dcfg |= DCFG_DEVSPD_FS;
3438 break;
3439 default:
3440 dcfg |= DCFG_DEVSPD_HS;
3441 }
3442
3443 if (hsotg->params.ipg_isoc_en)
3444 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3445
3446 dwc2_writel(hsotg, dcfg, DCFG);
3447
3448 /* Clear any pending OTG interrupts */
3449 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3450
3451 /* Clear any pending interrupts */
3452 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3453 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3454 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3455 GINTSTS_USBRST | GINTSTS_RESETDET |
3456 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3457 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3458 GINTSTS_LPMTRANRCVD;
3459
3460 if (!using_desc_dma(hsotg))
3461 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3462
3463 if (!hsotg->params.external_id_pin_ctl)
3464 intmsk |= GINTSTS_CONIDSTSCHNG;
3465
3466 dwc2_writel(hsotg, intmsk, GINTMSK);
3467
3468 if (using_dma(hsotg)) {
3469 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3470 hsotg->params.ahbcfg,
3471 GAHBCFG);
3472
3473 /* Set DDMA mode support in the core if needed */
3474 if (using_desc_dma(hsotg))
3475 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3476
3477 } else {
3478 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3479 (GAHBCFG_NP_TXF_EMP_LVL |
3480 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3481 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3482 }
3483
3484 /*
3485 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3486 * when we have no data to transfer. Otherwise we get being flooded by
3487 * interrupts.
3488 */
3489
3490 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3491 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3492 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3493 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3494 DIEPMSK);
3495
3496 /*
3497 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3498 * DMA mode we may need this and StsPhseRcvd.
3499 */
3500 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3501 DOEPMSK_STSPHSERCVDMSK) : 0) |
3502 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3503 DOEPMSK_SETUPMSK,
3504 DOEPMSK);
3505
3506 /* Enable BNA interrupt for DDMA */
3507 if (using_desc_dma(hsotg)) {
3508 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3509 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3510 }
3511
3512 /* Enable Service Interval mode if supported */
3513 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3514 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3515
3516 dwc2_writel(hsotg, 0, DAINTMSK);
3517
3518 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3519 dwc2_readl(hsotg, DIEPCTL0),
3520 dwc2_readl(hsotg, DOEPCTL0));
3521
3522 /* enable in and out endpoint interrupts */
3523 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3524
3525 /*
3526 * Enable the RXFIFO when in slave mode, as this is how we collect
3527 * the data. In DMA mode, we get events from the FIFO but also
3528 * things we cannot process, so do not use it.
3529 */
3530 if (!using_dma(hsotg))
3531 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3532
3533 /* Enable interrupts for EP0 in and out */
3534 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3535 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3536
3537 if (!is_usb_reset) {
3538 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3539 udelay(10); /* see openiboot */
3540 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3541 }
3542
3543 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3544
3545 /*
3546 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3547 * writing to the EPCTL register..
3548 */
3549
3550 /* set to read 1 8byte packet */
3551 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3552 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3553
3554 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3555 DXEPCTL_CNAK | DXEPCTL_EPENA |
3556 DXEPCTL_USBACTEP,
3557 DOEPCTL0);
3558
3559 /* enable, but don't activate EP0in */
3560 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3561 DXEPCTL_USBACTEP, DIEPCTL0);
3562
3563 /* clear global NAKs */
3564 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3565 if (!is_usb_reset)
3566 val |= DCTL_SFTDISCON;
3567 dwc2_set_bit(hsotg, DCTL, val);
3568
3569 /* configure the core to support LPM */
3570 dwc2_gadget_init_lpm(hsotg);
3571
3572 /* program GREFCLK register if needed */
3573 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3574 dwc2_gadget_program_ref_clk(hsotg);
3575
3576 /* must be at-least 3ms to allow bus to see disconnect */
3577 mdelay(3);
3578
3579 hsotg->lx_state = DWC2_L0;
3580
3581 dwc2_hsotg_enqueue_setup(hsotg);
3582
3583 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3584 dwc2_readl(hsotg, DIEPCTL0),
3585 dwc2_readl(hsotg, DOEPCTL0));
3586}
3587
3588void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3589{
3590 /* set the soft-disconnect bit */
3591 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3592}
3593
3594void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3595{
3596 /* remove the soft-disconnect and let's go */
3597 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3598 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3599}
3600
3601/**
3602 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3603 * @hsotg: The device state:
3604 *
3605 * This interrupt indicates one of the following conditions occurred while
3606 * transmitting an ISOC transaction.
3607 * - Corrupted IN Token for ISOC EP.
3608 * - Packet not complete in FIFO.
3609 *
3610 * The following actions will be taken:
3611 * - Determine the EP
3612 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3613 */
3614static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3615{
3616 struct dwc2_hsotg_ep *hs_ep;
3617 u32 epctrl;
3618 u32 daintmsk;
3619 u32 idx;
3620
3621 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3622
3623 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3624
3625 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3626 hs_ep = hsotg->eps_in[idx];
3627 /* Proceed only unmasked ISOC EPs */
3628 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3629 continue;
3630
3631 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3632 if ((epctrl & DXEPCTL_EPENA) &&
3633 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3634 epctrl |= DXEPCTL_SNAK;
3635 epctrl |= DXEPCTL_EPDIS;
3636 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3637 }
3638 }
3639
3640 /* Clear interrupt */
3641 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3642}
3643
3644/**
3645 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3646 * @hsotg: The device state:
3647 *
3648 * This interrupt indicates one of the following conditions occurred while
3649 * transmitting an ISOC transaction.
3650 * - Corrupted OUT Token for ISOC EP.
3651 * - Packet not complete in FIFO.
3652 *
3653 * The following actions will be taken:
3654 * - Determine the EP
3655 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3656 */
3657static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3658{
3659 u32 gintsts;
3660 u32 gintmsk;
3661 u32 daintmsk;
3662 u32 epctrl;
3663 struct dwc2_hsotg_ep *hs_ep;
3664 int idx;
3665
3666 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3667
3668 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3669 daintmsk >>= DAINT_OUTEP_SHIFT;
3670
3671 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3672 hs_ep = hsotg->eps_out[idx];
3673 /* Proceed only unmasked ISOC EPs */
3674 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3675 continue;
3676
3677 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3678 if ((epctrl & DXEPCTL_EPENA) &&
3679 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3680 /* Unmask GOUTNAKEFF interrupt */
3681 gintmsk = dwc2_readl(hsotg, GINTMSK);
3682 gintmsk |= GINTSTS_GOUTNAKEFF;
3683 dwc2_writel(hsotg, gintmsk, GINTMSK);
3684
3685 gintsts = dwc2_readl(hsotg, GINTSTS);
3686 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3687 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3688 break;
3689 }
3690 }
3691 }
3692
3693 /* Clear interrupt */
3694 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3695}
3696
3697/**
3698 * dwc2_hsotg_irq - handle device interrupt
3699 * @irq: The IRQ number triggered
3700 * @pw: The pw value when registered the handler.
3701 */
3702static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3703{
3704 struct dwc2_hsotg *hsotg = pw;
3705 int retry_count = 8;
3706 u32 gintsts;
3707 u32 gintmsk;
3708
3709 if (!dwc2_is_device_mode(hsotg))
3710 return IRQ_NONE;
3711
3712 spin_lock(&hsotg->lock);
3713irq_retry:
3714 gintsts = dwc2_readl(hsotg, GINTSTS);
3715 gintmsk = dwc2_readl(hsotg, GINTMSK);
3716
3717 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3718 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3719
3720 gintsts &= gintmsk;
3721
3722 if (gintsts & GINTSTS_RESETDET) {
3723 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3724
3725 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3726
3727 /* This event must be used only if controller is suspended */
3728 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3729 dwc2_exit_partial_power_down(hsotg, 0, true);
3730
3731 hsotg->lx_state = DWC2_L0;
3732 }
3733
3734 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3735 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3736 u32 connected = hsotg->connected;
3737
3738 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3739 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3740 dwc2_readl(hsotg, GNPTXSTS));
3741
3742 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3743
3744 /* Report disconnection if it is not already done. */
3745 dwc2_hsotg_disconnect(hsotg);
3746
3747 /* Reset device address to zero */
3748 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3749
3750 if (usb_status & GOTGCTL_BSESVLD && connected)
3751 dwc2_hsotg_core_init_disconnected(hsotg, true);
3752 }
3753
3754 if (gintsts & GINTSTS_ENUMDONE) {
3755 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3756
3757 dwc2_hsotg_irq_enumdone(hsotg);
3758 }
3759
3760 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3761 u32 daint = dwc2_readl(hsotg, DAINT);
3762 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3763 u32 daint_out, daint_in;
3764 int ep;
3765
3766 daint &= daintmsk;
3767 daint_out = daint >> DAINT_OUTEP_SHIFT;
3768 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3769
3770 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3771
3772 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3773 ep++, daint_out >>= 1) {
3774 if (daint_out & 1)
3775 dwc2_hsotg_epint(hsotg, ep, 0);
3776 }
3777
3778 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3779 ep++, daint_in >>= 1) {
3780 if (daint_in & 1)
3781 dwc2_hsotg_epint(hsotg, ep, 1);
3782 }
3783 }
3784
3785 /* check both FIFOs */
3786
3787 if (gintsts & GINTSTS_NPTXFEMP) {
3788 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3789
3790 /*
3791 * Disable the interrupt to stop it happening again
3792 * unless one of these endpoint routines decides that
3793 * it needs re-enabling
3794 */
3795
3796 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3797 dwc2_hsotg_irq_fifoempty(hsotg, false);
3798 }
3799
3800 if (gintsts & GINTSTS_PTXFEMP) {
3801 dev_dbg(hsotg->dev, "PTxFEmp\n");
3802
3803 /* See note in GINTSTS_NPTxFEmp */
3804
3805 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3806 dwc2_hsotg_irq_fifoempty(hsotg, true);
3807 }
3808
3809 if (gintsts & GINTSTS_RXFLVL) {
3810 /*
3811 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3812 * we need to retry dwc2_hsotg_handle_rx if this is still
3813 * set.
3814 */
3815
3816 dwc2_hsotg_handle_rx(hsotg);
3817 }
3818
3819 if (gintsts & GINTSTS_ERLYSUSP) {
3820 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3821 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3822 }
3823
3824 /*
3825 * these next two seem to crop-up occasionally causing the core
3826 * to shutdown the USB transfer, so try clearing them and logging
3827 * the occurrence.
3828 */
3829
3830 if (gintsts & GINTSTS_GOUTNAKEFF) {
3831 u8 idx;
3832 u32 epctrl;
3833 u32 gintmsk;
3834 u32 daintmsk;
3835 struct dwc2_hsotg_ep *hs_ep;
3836
3837 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3838 daintmsk >>= DAINT_OUTEP_SHIFT;
3839 /* Mask this interrupt */
3840 gintmsk = dwc2_readl(hsotg, GINTMSK);
3841 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3842 dwc2_writel(hsotg, gintmsk, GINTMSK);
3843
3844 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3845 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3846 hs_ep = hsotg->eps_out[idx];
3847 /* Proceed only unmasked ISOC EPs */
3848 if (BIT(idx) & ~daintmsk)
3849 continue;
3850
3851 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3852
3853 //ISOC Ep's only
3854 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3855 epctrl |= DXEPCTL_SNAK;
3856 epctrl |= DXEPCTL_EPDIS;
3857 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3858 continue;
3859 }
3860
3861 //Non-ISOC EP's
3862 if (hs_ep->halted) {
3863 if (!(epctrl & DXEPCTL_EPENA))
3864 epctrl |= DXEPCTL_EPENA;
3865 epctrl |= DXEPCTL_EPDIS;
3866 epctrl |= DXEPCTL_STALL;
3867 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3868 }
3869 }
3870
3871 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3872 }
3873
3874 if (gintsts & GINTSTS_GINNAKEFF) {
3875 dev_info(hsotg->dev, "GINNakEff triggered\n");
3876
3877 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3878
3879 dwc2_hsotg_dump(hsotg);
3880 }
3881
3882 if (gintsts & GINTSTS_INCOMPL_SOIN)
3883 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3884
3885 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3886 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3887
3888 /*
3889 * if we've had fifo events, we should try and go around the
3890 * loop again to see if there's any point in returning yet.
3891 */
3892
3893 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3894 goto irq_retry;
3895
3896 /* Check WKUP_ALERT interrupt*/
3897 if (hsotg->params.service_interval)
3898 dwc2_gadget_wkup_alert_handler(hsotg);
3899
3900 spin_unlock(&hsotg->lock);
3901
3902 return IRQ_HANDLED;
3903}
3904
3905static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3906 struct dwc2_hsotg_ep *hs_ep)
3907{
3908 u32 epctrl_reg;
3909 u32 epint_reg;
3910
3911 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3912 DOEPCTL(hs_ep->index);
3913 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3914 DOEPINT(hs_ep->index);
3915
3916 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3917 hs_ep->name);
3918
3919 if (hs_ep->dir_in) {
3920 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3921 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3922 /* Wait for Nak effect */
3923 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3924 DXEPINT_INEPNAKEFF, 100))
3925 dev_warn(hsotg->dev,
3926 "%s: timeout DIEPINT.NAKEFF\n",
3927 __func__);
3928 } else {
3929 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3930 /* Wait for Nak effect */
3931 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3932 GINTSTS_GINNAKEFF, 100))
3933 dev_warn(hsotg->dev,
3934 "%s: timeout GINTSTS.GINNAKEFF\n",
3935 __func__);
3936 }
3937 } else {
3938 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3939 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3940
3941 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3942 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3943
3944 if (!using_dma(hsotg)) {
3945 /* Wait for GINTSTS_RXFLVL interrupt */
3946 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3947 GINTSTS_RXFLVL, 100)) {
3948 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3949 __func__);
3950 } else {
3951 /*
3952 * Pop GLOBAL OUT NAK status packet from RxFIFO
3953 * to assert GOUTNAKEFF interrupt
3954 */
3955 dwc2_readl(hsotg, GRXSTSP);
3956 }
3957 }
3958
3959 /* Wait for global nak to take effect */
3960 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3961 GINTSTS_GOUTNAKEFF, 100))
3962 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3963 __func__);
3964 }
3965
3966 /* Disable ep */
3967 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3968
3969 /* Wait for ep to be disabled */
3970 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3971 dev_warn(hsotg->dev,
3972 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3973
3974 /* Clear EPDISBLD interrupt */
3975 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3976
3977 if (hs_ep->dir_in) {
3978 unsigned short fifo_index;
3979
3980 if (hsotg->dedicated_fifos || hs_ep->periodic)
3981 fifo_index = hs_ep->fifo_index;
3982 else
3983 fifo_index = 0;
3984
3985 /* Flush TX FIFO */
3986 dwc2_flush_tx_fifo(hsotg, fifo_index);
3987
3988 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3989 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3990 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3991
3992 } else {
3993 /* Remove global NAKs */
3994 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3995 }
3996}
3997
3998/**
3999 * dwc2_hsotg_ep_enable - enable the given endpoint
4000 * @ep: The USB endpint to configure
4001 * @desc: The USB endpoint descriptor to configure with.
4002 *
4003 * This is called from the USB gadget code's usb_ep_enable().
4004 */
4005static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4006 const struct usb_endpoint_descriptor *desc)
4007{
4008 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4009 struct dwc2_hsotg *hsotg = hs_ep->parent;
4010 unsigned long flags;
4011 unsigned int index = hs_ep->index;
4012 u32 epctrl_reg;
4013 u32 epctrl;
4014 u32 mps;
4015 u32 mc;
4016 u32 mask;
4017 unsigned int dir_in;
4018 unsigned int i, val, size;
4019 int ret = 0;
4020 unsigned char ep_type;
4021 int desc_num;
4022
4023 dev_dbg(hsotg->dev,
4024 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4025 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4026 desc->wMaxPacketSize, desc->bInterval);
4027
4028 /* not to be called for EP0 */
4029 if (index == 0) {
4030 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4031 return -EINVAL;
4032 }
4033
4034 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4035 if (dir_in != hs_ep->dir_in) {
4036 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4037 return -EINVAL;
4038 }
4039
4040 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4041 mps = usb_endpoint_maxp(desc);
4042 mc = usb_endpoint_maxp_mult(desc);
4043
4044 /* ISOC IN in DDMA supported bInterval up to 10 */
4045 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4046 dir_in && desc->bInterval > 10) {
4047 dev_err(hsotg->dev,
4048 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4049 return -EINVAL;
4050 }
4051
4052 /* High bandwidth ISOC OUT in DDMA not supported */
4053 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4054 !dir_in && mc > 1) {
4055 dev_err(hsotg->dev,
4056 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4057 return -EINVAL;
4058 }
4059
4060 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4061
4062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4063 epctrl = dwc2_readl(hsotg, epctrl_reg);
4064
4065 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4066 __func__, epctrl, epctrl_reg);
4067
4068 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4069 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4070 else
4071 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4072
4073 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4074 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4075 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4076 desc_num * sizeof(struct dwc2_dma_desc),
4077 &hs_ep->desc_list_dma, GFP_ATOMIC);
4078 if (!hs_ep->desc_list) {
4079 ret = -ENOMEM;
4080 goto error2;
4081 }
4082 }
4083
4084 spin_lock_irqsave(&hsotg->lock, flags);
4085
4086 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4087 epctrl |= DXEPCTL_MPS(mps);
4088
4089 /*
4090 * mark the endpoint as active, otherwise the core may ignore
4091 * transactions entirely for this endpoint
4092 */
4093 epctrl |= DXEPCTL_USBACTEP;
4094
4095 /* update the endpoint state */
4096 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4097
4098 /* default, set to non-periodic */
4099 hs_ep->isochronous = 0;
4100 hs_ep->periodic = 0;
4101 hs_ep->halted = 0;
4102 hs_ep->wedged = 0;
4103 hs_ep->interval = desc->bInterval;
4104
4105 switch (ep_type) {
4106 case USB_ENDPOINT_XFER_ISOC:
4107 epctrl |= DXEPCTL_EPTYPE_ISO;
4108 epctrl |= DXEPCTL_SETEVENFR;
4109 hs_ep->isochronous = 1;
4110 hs_ep->interval = 1 << (desc->bInterval - 1);
4111 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4112 hs_ep->next_desc = 0;
4113 hs_ep->compl_desc = 0;
4114 if (dir_in) {
4115 hs_ep->periodic = 1;
4116 mask = dwc2_readl(hsotg, DIEPMSK);
4117 mask |= DIEPMSK_NAKMSK;
4118 dwc2_writel(hsotg, mask, DIEPMSK);
4119 } else {
4120 epctrl |= DXEPCTL_SNAK;
4121 mask = dwc2_readl(hsotg, DOEPMSK);
4122 mask |= DOEPMSK_OUTTKNEPDISMSK;
4123 dwc2_writel(hsotg, mask, DOEPMSK);
4124 }
4125 break;
4126
4127 case USB_ENDPOINT_XFER_BULK:
4128 epctrl |= DXEPCTL_EPTYPE_BULK;
4129 break;
4130
4131 case USB_ENDPOINT_XFER_INT:
4132 if (dir_in)
4133 hs_ep->periodic = 1;
4134
4135 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4136 hs_ep->interval = 1 << (desc->bInterval - 1);
4137
4138 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4139 break;
4140
4141 case USB_ENDPOINT_XFER_CONTROL:
4142 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4143 break;
4144 }
4145
4146 /*
4147 * if the hardware has dedicated fifos, we must give each IN EP
4148 * a unique tx-fifo even if it is non-periodic.
4149 */
4150 if (dir_in && hsotg->dedicated_fifos) {
4151 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4152 u32 fifo_index = 0;
4153 u32 fifo_size = UINT_MAX;
4154
4155 size = hs_ep->ep.maxpacket * hs_ep->mc;
4156 for (i = 1; i <= fifo_count; ++i) {
4157 if (hsotg->fifo_map & (1 << i))
4158 continue;
4159 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4160 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4161 if (val < size)
4162 continue;
4163 /* Search for smallest acceptable fifo */
4164 if (val < fifo_size) {
4165 fifo_size = val;
4166 fifo_index = i;
4167 }
4168 }
4169 if (!fifo_index) {
4170 dev_err(hsotg->dev,
4171 "%s: No suitable fifo found\n", __func__);
4172 ret = -ENOMEM;
4173 goto error1;
4174 }
4175 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4176 hsotg->fifo_map |= 1 << fifo_index;
4177 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4178 hs_ep->fifo_index = fifo_index;
4179 hs_ep->fifo_size = fifo_size;
4180 }
4181
4182 /* for non control endpoints, set PID to D0 */
4183 if (index && !hs_ep->isochronous)
4184 epctrl |= DXEPCTL_SETD0PID;
4185
4186 /* WA for Full speed ISOC IN in DDMA mode.
4187 * By Clear NAK status of EP, core will send ZLP
4188 * to IN token and assert NAK interrupt relying
4189 * on TxFIFO status only
4190 */
4191
4192 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4193 hs_ep->isochronous && dir_in) {
4194 /* The WA applies only to core versions from 2.72a
4195 * to 4.00a (including both). Also for FS_IOT_1.00a
4196 * and HS_IOT_1.00a.
4197 */
4198 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4199
4200 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4201 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4202 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4203 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4204 epctrl |= DXEPCTL_CNAK;
4205 }
4206
4207 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4208 __func__, epctrl);
4209
4210 dwc2_writel(hsotg, epctrl, epctrl_reg);
4211 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4212 __func__, dwc2_readl(hsotg, epctrl_reg));
4213
4214 /* enable the endpoint interrupt */
4215 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4216
4217error1:
4218 spin_unlock_irqrestore(&hsotg->lock, flags);
4219
4220error2:
4221 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4222 dmam_free_coherent(hsotg->dev, desc_num *
4223 sizeof(struct dwc2_dma_desc),
4224 hs_ep->desc_list, hs_ep->desc_list_dma);
4225 hs_ep->desc_list = NULL;
4226 }
4227
4228 return ret;
4229}
4230
4231/**
4232 * dwc2_hsotg_ep_disable - disable given endpoint
4233 * @ep: The endpoint to disable.
4234 */
4235static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4236{
4237 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4238 struct dwc2_hsotg *hsotg = hs_ep->parent;
4239 int dir_in = hs_ep->dir_in;
4240 int index = hs_ep->index;
4241 u32 epctrl_reg;
4242 u32 ctrl;
4243
4244 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4245
4246 if (ep == &hsotg->eps_out[0]->ep) {
4247 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4248 return -EINVAL;
4249 }
4250
4251 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4252 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4253 return -EINVAL;
4254 }
4255
4256 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4257
4258 ctrl = dwc2_readl(hsotg, epctrl_reg);
4259
4260 if (ctrl & DXEPCTL_EPENA)
4261 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4262
4263 ctrl &= ~DXEPCTL_EPENA;
4264 ctrl &= ~DXEPCTL_USBACTEP;
4265 ctrl |= DXEPCTL_SNAK;
4266
4267 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4268 dwc2_writel(hsotg, ctrl, epctrl_reg);
4269
4270 /* disable endpoint interrupts */
4271 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4272
4273 /* terminate all requests with shutdown */
4274 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4275
4276 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4277 hs_ep->fifo_index = 0;
4278 hs_ep->fifo_size = 0;
4279
4280 return 0;
4281}
4282
4283static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4284{
4285 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4286 struct dwc2_hsotg *hsotg = hs_ep->parent;
4287 unsigned long flags;
4288 int ret;
4289
4290 spin_lock_irqsave(&hsotg->lock, flags);
4291 ret = dwc2_hsotg_ep_disable(ep);
4292 spin_unlock_irqrestore(&hsotg->lock, flags);
4293 return ret;
4294}
4295
4296/**
4297 * on_list - check request is on the given endpoint
4298 * @ep: The endpoint to check.
4299 * @test: The request to test if it is on the endpoint.
4300 */
4301static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4302{
4303 struct dwc2_hsotg_req *req, *treq;
4304
4305 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4306 if (req == test)
4307 return true;
4308 }
4309
4310 return false;
4311}
4312
4313/**
4314 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4315 * @ep: The endpoint to dequeue.
4316 * @req: The request to be removed from a queue.
4317 */
4318static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4319{
4320 struct dwc2_hsotg_req *hs_req = our_req(req);
4321 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4322 struct dwc2_hsotg *hs = hs_ep->parent;
4323 unsigned long flags;
4324
4325 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4326
4327 spin_lock_irqsave(&hs->lock, flags);
4328
4329 if (!on_list(hs_ep, hs_req)) {
4330 spin_unlock_irqrestore(&hs->lock, flags);
4331 return -EINVAL;
4332 }
4333
4334 /* Dequeue already started request */
4335 if (req == &hs_ep->req->req)
4336 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4337
4338 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4339 spin_unlock_irqrestore(&hs->lock, flags);
4340
4341 return 0;
4342}
4343
4344/**
4345 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4346 * @ep: The endpoint to be wedged.
4347 *
4348 */
4349static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4350{
4351 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4352 struct dwc2_hsotg *hs = hs_ep->parent;
4353
4354 unsigned long flags;
4355 int ret;
4356
4357 spin_lock_irqsave(&hs->lock, flags);
4358 hs_ep->wedged = 1;
4359 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4360 spin_unlock_irqrestore(&hs->lock, flags);
4361
4362 return ret;
4363}
4364
4365/**
4366 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4367 * @ep: The endpoint to set halt.
4368 * @value: Set or unset the halt.
4369 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4370 * the endpoint is busy processing requests.
4371 *
4372 * We need to stall the endpoint immediately if request comes from set_feature
4373 * protocol command handler.
4374 */
4375static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4376{
4377 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4378 struct dwc2_hsotg *hs = hs_ep->parent;
4379 int index = hs_ep->index;
4380 u32 epreg;
4381 u32 epctl;
4382 u32 xfertype;
4383
4384 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4385
4386 if (index == 0) {
4387 if (value)
4388 dwc2_hsotg_stall_ep0(hs);
4389 else
4390 dev_warn(hs->dev,
4391 "%s: can't clear halt on ep0\n", __func__);
4392 return 0;
4393 }
4394
4395 if (hs_ep->isochronous) {
4396 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4397 return -EINVAL;
4398 }
4399
4400 if (!now && value && !list_empty(&hs_ep->queue)) {
4401 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4402 ep->name);
4403 return -EAGAIN;
4404 }
4405
4406 if (hs_ep->dir_in) {
4407 epreg = DIEPCTL(index);
4408 epctl = dwc2_readl(hs, epreg);
4409
4410 if (value) {
4411 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4412 if (epctl & DXEPCTL_EPENA)
4413 epctl |= DXEPCTL_EPDIS;
4414 } else {
4415 epctl &= ~DXEPCTL_STALL;
4416 hs_ep->wedged = 0;
4417 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4418 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4419 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4420 epctl |= DXEPCTL_SETD0PID;
4421 }
4422 dwc2_writel(hs, epctl, epreg);
4423 } else {
4424 epreg = DOEPCTL(index);
4425 epctl = dwc2_readl(hs, epreg);
4426
4427 if (value) {
4428 /* Unmask GOUTNAKEFF interrupt */
4429 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4430
4431 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4432 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4433 // STALL bit will be set in GOUTNAKEFF interrupt handler
4434 } else {
4435 epctl &= ~DXEPCTL_STALL;
4436 hs_ep->wedged = 0;
4437 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4438 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4439 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4440 epctl |= DXEPCTL_SETD0PID;
4441 dwc2_writel(hs, epctl, epreg);
4442 }
4443 }
4444
4445 hs_ep->halted = value;
4446 return 0;
4447}
4448
4449/**
4450 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4451 * @ep: The endpoint to set halt.
4452 * @value: Set or unset the halt.
4453 */
4454static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4455{
4456 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4457 struct dwc2_hsotg *hs = hs_ep->parent;
4458 unsigned long flags;
4459 int ret;
4460
4461 spin_lock_irqsave(&hs->lock, flags);
4462 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4463 spin_unlock_irqrestore(&hs->lock, flags);
4464
4465 return ret;
4466}
4467
4468static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4469 .enable = dwc2_hsotg_ep_enable,
4470 .disable = dwc2_hsotg_ep_disable_lock,
4471 .alloc_request = dwc2_hsotg_ep_alloc_request,
4472 .free_request = dwc2_hsotg_ep_free_request,
4473 .queue = dwc2_hsotg_ep_queue_lock,
4474 .dequeue = dwc2_hsotg_ep_dequeue,
4475 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4476 .set_wedge = dwc2_gadget_ep_set_wedge,
4477 /* note, don't believe we have any call for the fifo routines */
4478};
4479
4480/**
4481 * dwc2_hsotg_init - initialize the usb core
4482 * @hsotg: The driver state
4483 */
4484static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4485{
4486 /* unmask subset of endpoint interrupts */
4487
4488 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4489 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4490 DIEPMSK);
4491
4492 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4493 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4494 DOEPMSK);
4495
4496 dwc2_writel(hsotg, 0, DAINTMSK);
4497
4498 /* Be in disconnected state until gadget is registered */
4499 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4500
4501 /* setup fifos */
4502
4503 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4504 dwc2_readl(hsotg, GRXFSIZ),
4505 dwc2_readl(hsotg, GNPTXFSIZ));
4506
4507 dwc2_hsotg_init_fifo(hsotg);
4508
4509 if (using_dma(hsotg))
4510 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4511}
4512
4513/**
4514 * dwc2_hsotg_udc_start - prepare the udc for work
4515 * @gadget: The usb gadget state
4516 * @driver: The usb gadget driver
4517 *
4518 * Perform initialization to prepare udc device and driver
4519 * to work.
4520 */
4521static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4522 struct usb_gadget_driver *driver)
4523{
4524 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4525 unsigned long flags;
4526 int ret;
4527
4528 if (!hsotg) {
4529 pr_err("%s: called with no device\n", __func__);
4530 return -ENODEV;
4531 }
4532
4533 if (!driver) {
4534 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4535 return -EINVAL;
4536 }
4537
4538 if (driver->max_speed < USB_SPEED_FULL)
4539 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4540
4541 if (!driver->setup) {
4542 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4543 return -EINVAL;
4544 }
4545
4546 WARN_ON(hsotg->driver);
4547
4548 hsotg->driver = driver;
4549 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4550 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4551
4552 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL ||
4553 (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg))) {
4554 ret = dwc2_lowlevel_hw_enable(hsotg);
4555 if (ret)
4556 goto err;
4557 }
4558
4559 if (!IS_ERR_OR_NULL(hsotg->uphy))
4560 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4561
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 if (dwc2_hw_is_device(hsotg)) {
4564 dwc2_hsotg_init(hsotg);
4565 dwc2_hsotg_core_init_disconnected(hsotg, false);
4566 }
4567
4568 hsotg->enabled = 0;
4569 spin_unlock_irqrestore(&hsotg->lock, flags);
4570
4571 gadget->sg_supported = using_desc_dma(hsotg);
4572 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4573
4574 return 0;
4575
4576err:
4577 hsotg->driver = NULL;
4578 return ret;
4579}
4580
4581/**
4582 * dwc2_hsotg_udc_stop - stop the udc
4583 * @gadget: The usb gadget state
4584 *
4585 * Stop udc hw block and stay tunned for future transmissions
4586 */
4587static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4588{
4589 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4590 unsigned long flags;
4591 int ep;
4592
4593 if (!hsotg)
4594 return -ENODEV;
4595
4596 /* all endpoints should be shutdown */
4597 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4598 if (hsotg->eps_in[ep])
4599 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4600 if (hsotg->eps_out[ep])
4601 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4602 }
4603
4604 spin_lock_irqsave(&hsotg->lock, flags);
4605
4606 hsotg->driver = NULL;
4607 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4608 hsotg->enabled = 0;
4609
4610 spin_unlock_irqrestore(&hsotg->lock, flags);
4611
4612 if (!IS_ERR_OR_NULL(hsotg->uphy))
4613 otg_set_peripheral(hsotg->uphy->otg, NULL);
4614
4615 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL ||
4616 (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)))
4617 dwc2_lowlevel_hw_disable(hsotg);
4618
4619 return 0;
4620}
4621
4622/**
4623 * dwc2_hsotg_gadget_getframe - read the frame number
4624 * @gadget: The usb gadget state
4625 *
4626 * Read the {micro} frame number
4627 */
4628static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4629{
4630 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4631}
4632
4633/**
4634 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4635 * @gadget: The usb gadget state
4636 * @is_selfpowered: Whether the device is self-powered
4637 *
4638 * Set if the device is self or bus powered.
4639 */
4640static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4641 int is_selfpowered)
4642{
4643 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4644 unsigned long flags;
4645
4646 spin_lock_irqsave(&hsotg->lock, flags);
4647 gadget->is_selfpowered = !!is_selfpowered;
4648 spin_unlock_irqrestore(&hsotg->lock, flags);
4649
4650 return 0;
4651}
4652
4653/**
4654 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4655 * @gadget: The usb gadget state
4656 * @is_on: Current state of the USB PHY
4657 *
4658 * Connect/Disconnect the USB PHY pullup
4659 */
4660static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4661{
4662 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4663 unsigned long flags;
4664
4665 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4666 hsotg->op_state);
4667
4668 /* Don't modify pullup state while in host mode */
4669 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4670 hsotg->enabled = is_on;
4671 return 0;
4672 }
4673
4674 spin_lock_irqsave(&hsotg->lock, flags);
4675 if (is_on) {
4676 hsotg->enabled = 1;
4677 dwc2_hsotg_core_init_disconnected(hsotg, false);
4678 /* Enable ACG feature in device mode,if supported */
4679 dwc2_enable_acg(hsotg);
4680 dwc2_hsotg_core_connect(hsotg);
4681 } else {
4682 dwc2_hsotg_core_disconnect(hsotg);
4683 dwc2_hsotg_disconnect(hsotg);
4684 hsotg->enabled = 0;
4685 }
4686
4687 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4688 spin_unlock_irqrestore(&hsotg->lock, flags);
4689
4690 return 0;
4691}
4692
4693static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4694{
4695 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4696 unsigned long flags;
4697
4698 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4699 spin_lock_irqsave(&hsotg->lock, flags);
4700
4701 /*
4702 * If controller is in partial power down state, it must exit from
4703 * that state before being initialized / de-initialized
4704 */
4705 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4706 /*
4707 * No need to check the return value as
4708 * registers are not being restored.
4709 */
4710 dwc2_exit_partial_power_down(hsotg, 0, false);
4711
4712 if (is_active) {
4713 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4714
4715 dwc2_hsotg_core_init_disconnected(hsotg, false);
4716 if (hsotg->enabled) {
4717 /* Enable ACG feature in device mode,if supported */
4718 dwc2_enable_acg(hsotg);
4719 dwc2_hsotg_core_connect(hsotg);
4720 }
4721 } else {
4722 dwc2_hsotg_core_disconnect(hsotg);
4723 dwc2_hsotg_disconnect(hsotg);
4724 }
4725
4726 spin_unlock_irqrestore(&hsotg->lock, flags);
4727 return 0;
4728}
4729
4730/**
4731 * dwc2_hsotg_vbus_draw - report bMaxPower field
4732 * @gadget: The usb gadget state
4733 * @mA: Amount of current
4734 *
4735 * Report how much power the device may consume to the phy.
4736 */
4737static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4738{
4739 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4740
4741 if (IS_ERR_OR_NULL(hsotg->uphy))
4742 return -ENOTSUPP;
4743 return usb_phy_set_power(hsotg->uphy, mA);
4744}
4745
4746static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4747{
4748 struct dwc2_hsotg *hsotg = to_hsotg(g);
4749 unsigned long flags;
4750
4751 spin_lock_irqsave(&hsotg->lock, flags);
4752 switch (speed) {
4753 case USB_SPEED_HIGH:
4754 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4755 break;
4756 case USB_SPEED_FULL:
4757 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4758 break;
4759 case USB_SPEED_LOW:
4760 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4761 break;
4762 default:
4763 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4764 }
4765 spin_unlock_irqrestore(&hsotg->lock, flags);
4766}
4767
4768static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4769 .get_frame = dwc2_hsotg_gadget_getframe,
4770 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4771 .udc_start = dwc2_hsotg_udc_start,
4772 .udc_stop = dwc2_hsotg_udc_stop,
4773 .pullup = dwc2_hsotg_pullup,
4774 .udc_set_speed = dwc2_gadget_set_speed,
4775 .vbus_session = dwc2_hsotg_vbus_session,
4776 .vbus_draw = dwc2_hsotg_vbus_draw,
4777};
4778
4779/**
4780 * dwc2_hsotg_initep - initialise a single endpoint
4781 * @hsotg: The device state.
4782 * @hs_ep: The endpoint to be initialised.
4783 * @epnum: The endpoint number
4784 * @dir_in: True if direction is in.
4785 *
4786 * Initialise the given endpoint (as part of the probe and device state
4787 * creation) to give to the gadget driver. Setup the endpoint name, any
4788 * direction information and other state that may be required.
4789 */
4790static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4791 struct dwc2_hsotg_ep *hs_ep,
4792 int epnum,
4793 bool dir_in)
4794{
4795 char *dir;
4796
4797 if (epnum == 0)
4798 dir = "";
4799 else if (dir_in)
4800 dir = "in";
4801 else
4802 dir = "out";
4803
4804 hs_ep->dir_in = dir_in;
4805 hs_ep->index = epnum;
4806
4807 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4808
4809 INIT_LIST_HEAD(&hs_ep->queue);
4810 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4811
4812 /* add to the list of endpoints known by the gadget driver */
4813 if (epnum)
4814 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4815
4816 hs_ep->parent = hsotg;
4817 hs_ep->ep.name = hs_ep->name;
4818
4819 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4820 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4821 else
4822 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4823 epnum ? 1024 : EP0_MPS_LIMIT);
4824 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4825
4826 if (epnum == 0) {
4827 hs_ep->ep.caps.type_control = true;
4828 } else {
4829 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4830 hs_ep->ep.caps.type_iso = true;
4831 hs_ep->ep.caps.type_bulk = true;
4832 }
4833 hs_ep->ep.caps.type_int = true;
4834 }
4835
4836 if (dir_in)
4837 hs_ep->ep.caps.dir_in = true;
4838 else
4839 hs_ep->ep.caps.dir_out = true;
4840
4841 /*
4842 * if we're using dma, we need to set the next-endpoint pointer
4843 * to be something valid.
4844 */
4845
4846 if (using_dma(hsotg)) {
4847 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4848
4849 if (dir_in)
4850 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4851 else
4852 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4853 }
4854}
4855
4856/**
4857 * dwc2_hsotg_hw_cfg - read HW configuration registers
4858 * @hsotg: Programming view of the DWC_otg controller
4859 *
4860 * Read the USB core HW configuration registers
4861 */
4862static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4863{
4864 u32 cfg;
4865 u32 ep_type;
4866 u32 i;
4867
4868 /* check hardware configuration */
4869
4870 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4871
4872 /* Add ep0 */
4873 hsotg->num_of_eps++;
4874
4875 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4876 sizeof(struct dwc2_hsotg_ep),
4877 GFP_KERNEL);
4878 if (!hsotg->eps_in[0])
4879 return -ENOMEM;
4880 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4881 hsotg->eps_out[0] = hsotg->eps_in[0];
4882
4883 cfg = hsotg->hw_params.dev_ep_dirs;
4884 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4885 ep_type = cfg & 3;
4886 /* Direction in or both */
4887 if (!(ep_type & 2)) {
4888 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4889 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4890 if (!hsotg->eps_in[i])
4891 return -ENOMEM;
4892 }
4893 /* Direction out or both */
4894 if (!(ep_type & 1)) {
4895 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4896 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4897 if (!hsotg->eps_out[i])
4898 return -ENOMEM;
4899 }
4900 }
4901
4902 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4903 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4904
4905 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4906 hsotg->num_of_eps,
4907 hsotg->dedicated_fifos ? "dedicated" : "shared",
4908 hsotg->fifo_mem);
4909 return 0;
4910}
4911
4912/**
4913 * dwc2_hsotg_dump - dump state of the udc
4914 * @hsotg: Programming view of the DWC_otg controller
4915 *
4916 */
4917static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4918{
4919#ifdef DEBUG
4920 struct device *dev = hsotg->dev;
4921 u32 val;
4922 int idx;
4923
4924 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4925 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4926 dwc2_readl(hsotg, DIEPMSK));
4927
4928 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4929 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4930
4931 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4932 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4933
4934 /* show periodic fifo settings */
4935
4936 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4937 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4938 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4939 val >> FIFOSIZE_DEPTH_SHIFT,
4940 val & FIFOSIZE_STARTADDR_MASK);
4941 }
4942
4943 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4944 dev_info(dev,
4945 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4946 dwc2_readl(hsotg, DIEPCTL(idx)),
4947 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4948 dwc2_readl(hsotg, DIEPDMA(idx)));
4949
4950 val = dwc2_readl(hsotg, DOEPCTL(idx));
4951 dev_info(dev,
4952 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4953 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4954 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4955 dwc2_readl(hsotg, DOEPDMA(idx)));
4956 }
4957
4958 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4959 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4960#endif
4961}
4962
4963/**
4964 * dwc2_gadget_init - init function for gadget
4965 * @hsotg: Programming view of the DWC_otg controller
4966 *
4967 */
4968int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4969{
4970 struct device *dev = hsotg->dev;
4971 int epnum;
4972 int ret;
4973
4974 /* Dump fifo information */
4975 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4976 hsotg->params.g_np_tx_fifo_size);
4977 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4978
4979 switch (hsotg->params.speed) {
4980 case DWC2_SPEED_PARAM_LOW:
4981 hsotg->gadget.max_speed = USB_SPEED_LOW;
4982 break;
4983 case DWC2_SPEED_PARAM_FULL:
4984 hsotg->gadget.max_speed = USB_SPEED_FULL;
4985 break;
4986 default:
4987 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4988 break;
4989 }
4990
4991 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4992 hsotg->gadget.name = dev_name(dev);
4993 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
4994 hsotg->remote_wakeup_allowed = 0;
4995
4996 if (hsotg->params.lpm)
4997 hsotg->gadget.lpm_capable = true;
4998
4999 if (hsotg->dr_mode == USB_DR_MODE_OTG)
5000 hsotg->gadget.is_otg = 1;
5001 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5002 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5003
5004 ret = dwc2_hsotg_hw_cfg(hsotg);
5005 if (ret) {
5006 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5007 return ret;
5008 }
5009
5010 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5011 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5012 if (!hsotg->ctrl_buff)
5013 return -ENOMEM;
5014
5015 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5016 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5017 if (!hsotg->ep0_buff)
5018 return -ENOMEM;
5019
5020 if (using_desc_dma(hsotg)) {
5021 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5022 if (ret < 0)
5023 return ret;
5024 }
5025
5026 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5027 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5028 if (ret < 0) {
5029 dev_err(dev, "cannot claim IRQ for gadget\n");
5030 return ret;
5031 }
5032
5033 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5034
5035 if (hsotg->num_of_eps == 0) {
5036 dev_err(dev, "wrong number of EPs (zero)\n");
5037 return -EINVAL;
5038 }
5039
5040 /* setup endpoint information */
5041
5042 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5043 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5044
5045 /* allocate EP0 request */
5046
5047 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5048 GFP_KERNEL);
5049 if (!hsotg->ctrl_req) {
5050 dev_err(dev, "failed to allocate ctrl req\n");
5051 return -ENOMEM;
5052 }
5053
5054 /* initialise the endpoints now the core has been initialised */
5055 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5056 if (hsotg->eps_in[epnum])
5057 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5058 epnum, 1);
5059 if (hsotg->eps_out[epnum])
5060 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5061 epnum, 0);
5062 }
5063
5064 dwc2_hsotg_dump(hsotg);
5065
5066 return 0;
5067}
5068
5069/**
5070 * dwc2_hsotg_remove - remove function for hsotg driver
5071 * @hsotg: Programming view of the DWC_otg controller
5072 *
5073 */
5074int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5075{
5076 usb_del_gadget_udc(&hsotg->gadget);
5077 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5078
5079 return 0;
5080}
5081
5082int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5083{
5084 unsigned long flags;
5085
5086 if (hsotg->lx_state != DWC2_L0)
5087 return 0;
5088
5089 if (hsotg->driver) {
5090 int ep;
5091
5092 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5093 hsotg->driver->driver.name);
5094
5095 spin_lock_irqsave(&hsotg->lock, flags);
5096 if (hsotg->enabled)
5097 dwc2_hsotg_core_disconnect(hsotg);
5098 dwc2_hsotg_disconnect(hsotg);
5099 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5100 spin_unlock_irqrestore(&hsotg->lock, flags);
5101
5102 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5103 if (hsotg->eps_in[ep])
5104 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5105 if (hsotg->eps_out[ep])
5106 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5107 }
5108 }
5109
5110 return 0;
5111}
5112
5113int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5114{
5115 unsigned long flags;
5116
5117 if (hsotg->lx_state == DWC2_L2)
5118 return 0;
5119
5120 if (hsotg->driver) {
5121 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5122 hsotg->driver->driver.name);
5123
5124 spin_lock_irqsave(&hsotg->lock, flags);
5125 dwc2_hsotg_core_init_disconnected(hsotg, false);
5126 if (hsotg->enabled) {
5127 /* Enable ACG feature in device mode,if supported */
5128 dwc2_enable_acg(hsotg);
5129 dwc2_hsotg_core_connect(hsotg);
5130 }
5131 spin_unlock_irqrestore(&hsotg->lock, flags);
5132 }
5133
5134 return 0;
5135}
5136
5137/**
5138 * dwc2_backup_device_registers() - Backup controller device registers.
5139 * When suspending usb bus, registers needs to be backuped
5140 * if controller power is disabled once suspended.
5141 *
5142 * @hsotg: Programming view of the DWC_otg controller
5143 */
5144int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5145{
5146 struct dwc2_dregs_backup *dr;
5147 int i;
5148
5149 dev_dbg(hsotg->dev, "%s\n", __func__);
5150
5151 /* Backup dev regs */
5152 dr = &hsotg->dr_backup;
5153
5154 dr->dcfg = dwc2_readl(hsotg, DCFG);
5155 dr->dctl = dwc2_readl(hsotg, DCTL);
5156 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5157 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5158 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5159
5160 for (i = 0; i < hsotg->num_of_eps; i++) {
5161 /* Backup IN EPs */
5162 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5163
5164 /* Ensure DATA PID is correctly configured */
5165 if (dr->diepctl[i] & DXEPCTL_DPID)
5166 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5167 else
5168 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5169
5170 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5171 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5172
5173 /* Backup OUT EPs */
5174 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5175
5176 /* Ensure DATA PID is correctly configured */
5177 if (dr->doepctl[i] & DXEPCTL_DPID)
5178 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5179 else
5180 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5181
5182 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5183 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5184 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5185 }
5186 dr->valid = true;
5187 return 0;
5188}
5189
5190/**
5191 * dwc2_restore_device_registers() - Restore controller device registers.
5192 * When resuming usb bus, device registers needs to be restored
5193 * if controller power were disabled.
5194 *
5195 * @hsotg: Programming view of the DWC_otg controller
5196 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5197 *
5198 * Return: 0 if successful, negative error code otherwise
5199 */
5200int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5201{
5202 struct dwc2_dregs_backup *dr;
5203 int i;
5204
5205 dev_dbg(hsotg->dev, "%s\n", __func__);
5206
5207 /* Restore dev regs */
5208 dr = &hsotg->dr_backup;
5209 if (!dr->valid) {
5210 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5211 __func__);
5212 return -EINVAL;
5213 }
5214 dr->valid = false;
5215
5216 if (!remote_wakeup)
5217 dwc2_writel(hsotg, dr->dctl, DCTL);
5218
5219 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5220 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5221 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5222
5223 for (i = 0; i < hsotg->num_of_eps; i++) {
5224 /* Restore IN EPs */
5225 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5226 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5227 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5228 /** WA for enabled EPx's IN in DDMA mode. On entering to
5229 * hibernation wrong value read and saved from DIEPDMAx,
5230 * as result BNA interrupt asserted on hibernation exit
5231 * by restoring from saved area.
5232 */
5233 if (using_desc_dma(hsotg) &&
5234 (dr->diepctl[i] & DXEPCTL_EPENA))
5235 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5236 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5237 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5238 /* Restore OUT EPs */
5239 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5240 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5241 * hibernation wrong value read and saved from DOEPDMAx,
5242 * as result BNA interrupt asserted on hibernation exit
5243 * by restoring from saved area.
5244 */
5245 if (using_desc_dma(hsotg) &&
5246 (dr->doepctl[i] & DXEPCTL_EPENA))
5247 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5248 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5249 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5250 }
5251
5252 return 0;
5253}
5254
5255/**
5256 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5257 *
5258 * @hsotg: Programming view of DWC_otg controller
5259 *
5260 */
5261void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5262{
5263 u32 val;
5264
5265 if (!hsotg->params.lpm)
5266 return;
5267
5268 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5269 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5270 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5271 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5272 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5273 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5274 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5275 dwc2_writel(hsotg, val, GLPMCFG);
5276 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5277
5278 /* Unmask WKUP_ALERT Interrupt */
5279 if (hsotg->params.service_interval)
5280 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5281}
5282
5283/**
5284 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5285 *
5286 * @hsotg: Programming view of DWC_otg controller
5287 *
5288 */
5289void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5290{
5291 u32 val = 0;
5292
5293 val |= GREFCLK_REF_CLK_MODE;
5294 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5295 val |= hsotg->params.sof_cnt_wkup_alert <<
5296 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5297
5298 dwc2_writel(hsotg, val, GREFCLK);
5299 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5300}
5301
5302/**
5303 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5304 *
5305 * @hsotg: Programming view of the DWC_otg controller
5306 *
5307 * Return non-zero if failed to enter to hibernation.
5308 */
5309int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5310{
5311 u32 gpwrdn;
5312 int ret = 0;
5313
5314 /* Change to L2(suspend) state */
5315 hsotg->lx_state = DWC2_L2;
5316 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5317 ret = dwc2_backup_global_registers(hsotg);
5318 if (ret) {
5319 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5320 __func__);
5321 return ret;
5322 }
5323 ret = dwc2_backup_device_registers(hsotg);
5324 if (ret) {
5325 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5326 __func__);
5327 return ret;
5328 }
5329
5330 gpwrdn = GPWRDN_PWRDNRSTN;
5331 gpwrdn |= GPWRDN_PMUACTV;
5332 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5333 udelay(10);
5334
5335 /* Set flag to indicate that we are in hibernation */
5336 hsotg->hibernated = 1;
5337
5338 /* Enable interrupts from wake up logic */
5339 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5340 gpwrdn |= GPWRDN_PMUINTSEL;
5341 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5342 udelay(10);
5343
5344 /* Unmask device mode interrupts in GPWRDN */
5345 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5346 gpwrdn |= GPWRDN_RST_DET_MSK;
5347 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5348 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5349 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5350 udelay(10);
5351
5352 /* Enable Power Down Clamp */
5353 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5354 gpwrdn |= GPWRDN_PWRDNCLMP;
5355 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5356 udelay(10);
5357
5358 /* Switch off VDD */
5359 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5360 gpwrdn |= GPWRDN_PWRDNSWTCH;
5361 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5362 udelay(10);
5363
5364 /* Save gpwrdn register for further usage if stschng interrupt */
5365 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5366 dev_dbg(hsotg->dev, "Hibernation completed\n");
5367
5368 return ret;
5369}
5370
5371/**
5372 * dwc2_gadget_exit_hibernation()
5373 * This function is for exiting from Device mode hibernation by host initiated
5374 * resume/reset and device initiated remote-wakeup.
5375 *
5376 * @hsotg: Programming view of the DWC_otg controller
5377 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5378 * @reset: indicates whether resume is initiated by Reset.
5379 *
5380 * Return non-zero if failed to exit from hibernation.
5381 */
5382int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5383 int rem_wakeup, int reset)
5384{
5385 u32 pcgcctl;
5386 u32 gpwrdn;
5387 u32 dctl;
5388 int ret = 0;
5389 struct dwc2_gregs_backup *gr;
5390 struct dwc2_dregs_backup *dr;
5391
5392 gr = &hsotg->gr_backup;
5393 dr = &hsotg->dr_backup;
5394
5395 if (!hsotg->hibernated) {
5396 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5397 return 1;
5398 }
5399 dev_dbg(hsotg->dev,
5400 "%s: called with rem_wakeup = %d reset = %d\n",
5401 __func__, rem_wakeup, reset);
5402
5403 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5404
5405 if (!reset) {
5406 /* Clear all pending interupts */
5407 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5408 }
5409
5410 /* De-assert Restore */
5411 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5412 gpwrdn &= ~GPWRDN_RESTORE;
5413 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5414 udelay(10);
5415
5416 if (!rem_wakeup) {
5417 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5418 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5419 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5420 }
5421
5422 /* Restore GUSBCFG, DCFG and DCTL */
5423 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5424 dwc2_writel(hsotg, dr->dcfg, DCFG);
5425 dwc2_writel(hsotg, dr->dctl, DCTL);
5426
5427 /* On USB Reset, reset device address to zero */
5428 if (reset)
5429 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5430
5431 /* De-assert Wakeup Logic */
5432 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5433 gpwrdn &= ~GPWRDN_PMUACTV;
5434 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5435
5436 if (rem_wakeup) {
5437 udelay(10);
5438 /* Start Remote Wakeup Signaling */
5439 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5440 } else {
5441 udelay(50);
5442 /* Set Device programming done bit */
5443 dctl = dwc2_readl(hsotg, DCTL);
5444 dctl |= DCTL_PWRONPRGDONE;
5445 dwc2_writel(hsotg, dctl, DCTL);
5446 }
5447 /* Wait for interrupts which must be cleared */
5448 mdelay(2);
5449 /* Clear all pending interupts */
5450 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5451
5452 /* Restore global registers */
5453 ret = dwc2_restore_global_registers(hsotg);
5454 if (ret) {
5455 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5456 __func__);
5457 return ret;
5458 }
5459
5460 /* Restore device registers */
5461 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5462 if (ret) {
5463 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5464 __func__);
5465 return ret;
5466 }
5467
5468 if (rem_wakeup) {
5469 mdelay(10);
5470 dctl = dwc2_readl(hsotg, DCTL);
5471 dctl &= ~DCTL_RMTWKUPSIG;
5472 dwc2_writel(hsotg, dctl, DCTL);
5473 }
5474
5475 hsotg->hibernated = 0;
5476 hsotg->lx_state = DWC2_L0;
5477 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5478
5479 return ret;
5480}
5481
5482/**
5483 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5484 * power down.
5485 *
5486 * @hsotg: Programming view of the DWC_otg controller
5487 *
5488 * Return: non-zero if failed to enter device partial power down.
5489 *
5490 * This function is for entering device mode partial power down.
5491 */
5492int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5493{
5494 u32 pcgcctl;
5495 int ret = 0;
5496
5497 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5498
5499 /* Backup all registers */
5500 ret = dwc2_backup_global_registers(hsotg);
5501 if (ret) {
5502 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5503 __func__);
5504 return ret;
5505 }
5506
5507 ret = dwc2_backup_device_registers(hsotg);
5508 if (ret) {
5509 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5510 __func__);
5511 return ret;
5512 }
5513
5514 /*
5515 * Clear any pending interrupts since dwc2 will not be able to
5516 * clear them after entering partial_power_down.
5517 */
5518 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5519
5520 /* Put the controller in low power state */
5521 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5522
5523 pcgcctl |= PCGCTL_PWRCLMP;
5524 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5525 udelay(5);
5526
5527 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5528 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5529 udelay(5);
5530
5531 pcgcctl |= PCGCTL_STOPPCLK;
5532 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5533
5534 /* Set in_ppd flag to 1 as here core enters suspend. */
5535 hsotg->in_ppd = 1;
5536 hsotg->lx_state = DWC2_L2;
5537
5538 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5539
5540 return ret;
5541}
5542
5543/*
5544 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5545 * power down.
5546 *
5547 * @hsotg: Programming view of the DWC_otg controller
5548 * @restore: indicates whether need to restore the registers or not.
5549 *
5550 * Return: non-zero if failed to exit device partial power down.
5551 *
5552 * This function is for exiting from device mode partial power down.
5553 */
5554int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5555 bool restore)
5556{
5557 u32 pcgcctl;
5558 u32 dctl;
5559 struct dwc2_dregs_backup *dr;
5560 int ret = 0;
5561
5562 dr = &hsotg->dr_backup;
5563
5564 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5565
5566 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5567 pcgcctl &= ~PCGCTL_STOPPCLK;
5568 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5569
5570 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5571 pcgcctl &= ~PCGCTL_PWRCLMP;
5572 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5573
5574 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5575 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5576 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577
5578 udelay(100);
5579 if (restore) {
5580 ret = dwc2_restore_global_registers(hsotg);
5581 if (ret) {
5582 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5583 __func__);
5584 return ret;
5585 }
5586 /* Restore DCFG */
5587 dwc2_writel(hsotg, dr->dcfg, DCFG);
5588
5589 ret = dwc2_restore_device_registers(hsotg, 0);
5590 if (ret) {
5591 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5592 __func__);
5593 return ret;
5594 }
5595 }
5596
5597 /* Set the Power-On Programming done bit */
5598 dctl = dwc2_readl(hsotg, DCTL);
5599 dctl |= DCTL_PWRONPRGDONE;
5600 dwc2_writel(hsotg, dctl, DCTL);
5601
5602 /* Set in_ppd flag to 0 as here core exits from suspend. */
5603 hsotg->in_ppd = 0;
5604 hsotg->lx_state = DWC2_L0;
5605
5606 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5607 return ret;
5608}
5609
5610/**
5611 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5612 *
5613 * @hsotg: Programming view of the DWC_otg controller
5614 *
5615 * Return: non-zero if failed to enter device partial power down.
5616 *
5617 * This function is for entering device mode clock gating.
5618 */
5619void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5620{
5621 u32 pcgctl;
5622
5623 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5624
5625 /* Set the Phy Clock bit as suspend is received. */
5626 pcgctl = dwc2_readl(hsotg, PCGCTL);
5627 pcgctl |= PCGCTL_STOPPCLK;
5628 dwc2_writel(hsotg, pcgctl, PCGCTL);
5629 udelay(5);
5630
5631 /* Set the Gate hclk as suspend is received. */
5632 pcgctl = dwc2_readl(hsotg, PCGCTL);
5633 pcgctl |= PCGCTL_GATEHCLK;
5634 dwc2_writel(hsotg, pcgctl, PCGCTL);
5635 udelay(5);
5636
5637 hsotg->lx_state = DWC2_L2;
5638 hsotg->bus_suspended = true;
5639}
5640
5641/*
5642 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5643 *
5644 * @hsotg: Programming view of the DWC_otg controller
5645 * @rem_wakeup: indicates whether remote wake up is enabled.
5646 *
5647 * This function is for exiting from device mode clock gating.
5648 */
5649void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5650{
5651 u32 pcgctl;
5652 u32 dctl;
5653
5654 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5655
5656 /* Clear the Gate hclk. */
5657 pcgctl = dwc2_readl(hsotg, PCGCTL);
5658 pcgctl &= ~PCGCTL_GATEHCLK;
5659 dwc2_writel(hsotg, pcgctl, PCGCTL);
5660 udelay(5);
5661
5662 /* Phy Clock bit. */
5663 pcgctl = dwc2_readl(hsotg, PCGCTL);
5664 pcgctl &= ~PCGCTL_STOPPCLK;
5665 dwc2_writel(hsotg, pcgctl, PCGCTL);
5666 udelay(5);
5667
5668 if (rem_wakeup) {
5669 /* Set Remote Wakeup Signaling */
5670 dctl = dwc2_readl(hsotg, DCTL);
5671 dctl |= DCTL_RMTWKUPSIG;
5672 dwc2_writel(hsotg, dctl, DCTL);
5673 }
5674
5675 /* Change to L0 state */
5676 call_gadget(hsotg, resume);
5677 hsotg->lx_state = DWC2_L0;
5678 hsotg->bus_suspended = false;
5679}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/mutex.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/of_platform.h>
26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
29#include <linux/usb/phy.h>
30#include <linux/usb/composite.h>
31
32
33#include "core.h"
34#include "hw.h"
35
36/* conversion functions */
37static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38{
39 return container_of(req, struct dwc2_hsotg_req, req);
40}
41
42static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43{
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
45}
46
47static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48{
49 return container_of(gadget, struct dwc2_hsotg, gadget);
50}
51
52static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53{
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55}
56
57static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58{
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60}
61
62static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
64{
65 if (dir_in)
66 return hsotg->eps_in[ep_index];
67 else
68 return hsotg->eps_out[ep_index];
69}
70
71/* forward declaration of functions */
72static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73
74/**
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
77 *
78 * Return true if we're using DMA.
79 *
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
84 * not 32bit aligned.
85 *
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
90 *
91 * g_using_dma is set depending on dts flag.
92 */
93static inline bool using_dma(struct dwc2_hsotg *hsotg)
94{
95 return hsotg->params.g_dma;
96}
97
98/*
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
101 *
102 * Return true if we're using descriptor DMA.
103 */
104static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105{
106 return hsotg->params.g_dma_desc;
107}
108
109/**
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
112 *
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 */
116static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117{
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
120
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
122 limit >>= 3;
123
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
128 } else {
129 hs_ep->frame_overrun = false;
130 }
131}
132
133/**
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * by one.
136 * @hs_ep: The endpoint.
137 *
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
141 *
142 */
143static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144{
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
147
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
149 limit >>= 3;
150
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
153 else
154 hs_ep->target_frame = limit;
155}
156
157/**
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
161 */
162static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163{
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
165 u32 new_gsintmsk;
166
167 new_gsintmsk = gsintmsk | ints;
168
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
172 }
173}
174
175/**
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
179 */
180static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181{
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
183 u32 new_gsintmsk;
184
185 new_gsintmsk = gsintmsk & ~ints;
186
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
189}
190
191/**
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
197 *
198 * Set or clear the mask for an individual endpoint's interrupt
199 * request.
200 */
201static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
203 unsigned int en)
204{
205 unsigned long flags;
206 u32 bit = 1 << ep;
207 u32 daint;
208
209 if (!dir_in)
210 bit <<= 16;
211
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
214 if (en)
215 daint |= bit;
216 else
217 daint &= ~bit;
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
220}
221
222/**
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 *
225 * @hsotg: Programming view of the DWC_otg controller
226 */
227int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228{
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
232 else
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
235}
236
237/**
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
240 *
241 * @hsotg: Programming view of the DWC_otg controller
242 */
243int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
244{
245 int addr;
246 int tx_addr_max;
247 u32 np_tx_fifo_size;
248
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
251
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
254
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
257 return 0;
258
259 return tx_addr_max - addr;
260}
261
262/**
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 *
265 * @hsotg: Programming view of the DWC_otg controller
266 *
267 */
268static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
269{
270 u32 gintsts2;
271 u32 gintmsk2;
272
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
276
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
281 }
282}
283
284/**
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
286 * TX FIFOs
287 *
288 * @hsotg: Programming view of the DWC_otg controller
289 */
290int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
291{
292 int tx_fifo_count;
293 int tx_fifo_depth;
294
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
298
299 if (!tx_fifo_count)
300 return tx_fifo_depth;
301 else
302 return tx_fifo_depth / tx_fifo_count;
303}
304
305/**
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
308 */
309static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
310{
311 unsigned int ep;
312 unsigned int addr;
313 int timeout;
314
315 u32 val;
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
320 hsotg->fifo_map = 0;
321
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
327 GNPTXFSIZ);
328
329 /*
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
333 * known values.
334 */
335
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
338
339 /*
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
342 * given endpoint.
343 */
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
345 if (!txfsz[ep])
346 continue;
347 val = addr;
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
351 addr += txfsz[ep];
352
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
355 }
356
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
359 GDFIFOCFG);
360 /*
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
363 */
364
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
367
368 /* wait until the fifos are both flushed */
369 timeout = 100;
370 while (1) {
371 val = dwc2_readl(hsotg, GRSTCTL);
372
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
374 break;
375
376 if (--timeout == 0) {
377 dev_err(hsotg->dev,
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
379 __func__, val);
380 break;
381 }
382
383 udelay(1);
384 }
385
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
387}
388
389/**
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
393 *
394 * Allocate a new USB request structure appropriate for the specified endpoint
395 */
396static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
397 gfp_t flags)
398{
399 struct dwc2_hsotg_req *req;
400
401 req = kzalloc(sizeof(*req), flags);
402 if (!req)
403 return NULL;
404
405 INIT_LIST_HEAD(&req->queue);
406
407 return &req->req;
408}
409
410/**
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
413 *
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
416 */
417static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418{
419 return hs_ep->periodic;
420}
421
422/**
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
427 *
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
430 */
431static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
434{
435 struct usb_request *req = &hs_req->req;
436
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
438}
439
440/*
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
444 *
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
447 */
448static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449{
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
454 GFP_KERNEL);
455 if (!hsotg->setup_desc[0])
456 goto fail;
457
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
462 GFP_KERNEL);
463 if (!hsotg->setup_desc[1])
464 goto fail;
465
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
470 GFP_KERNEL);
471 if (!hsotg->ctrl_in_desc)
472 goto fail;
473
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
478 GFP_KERNEL);
479 if (!hsotg->ctrl_out_desc)
480 goto fail;
481
482 return 0;
483
484fail:
485 return -ENOMEM;
486}
487
488/**
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
493 *
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
497 * write the data.
498 *
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 *
502 * This routine is only needed for PIO
503 */
504static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
507{
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
512 void *data;
513 int can_write;
514 int pkt_round;
515 int max_transfer;
516
517 to_write -= (buf_pos - hs_ep->last_load);
518
519 /* if there's nothing to write, get out early */
520 if (to_write == 0)
521 return 0;
522
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
525 int size_left;
526 int size_done;
527
528 /*
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
531 */
532
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
534
535 /*
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
538 */
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
541 return -ENOSPC;
542 }
543
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 __func__, size_left,
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
550
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
555
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
559
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
562 return -ENOSPC;
563 }
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
567
568 can_write &= 0xffff;
569 can_write *= 4;
570 } else {
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 dev_dbg(hsotg->dev,
573 "%s: no queue slots available (0x%08x)\n",
574 __func__, gnptxsts);
575
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
577 return -ENOSPC;
578 }
579
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
582 }
583
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
588
589 /*
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
593 */
594 if (can_write > 512 && !periodic)
595 can_write = 512;
596
597 /*
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
600 * doing it.
601 */
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
604
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
609 GINTSTS_NPTXFEMP);
610 }
611
612 /* see if we can write data */
613
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
617
618 /*
619 * Round the write down to an
620 * exact number of packets.
621 *
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
624 */
625
626 if (pkt_round)
627 to_write -= pkt_round;
628
629 /*
630 * enable correct FIFO interrupt to alert us when there
631 * is more room left.
632 */
633
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
638 GINTSTS_NPTXFEMP);
639 }
640
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
643
644 if (to_write <= 0)
645 return -ENOSPC;
646
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
649
650 if (periodic)
651 hs_ep->fifo_load += to_write;
652
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
655
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657
658 return (to_write >= can_write) ? -ENOSPC : 0;
659}
660
661/**
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
664 *
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
667 */
668static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669{
670 int index = hs_ep->index;
671 unsigned int maxsize;
672 unsigned int maxpkt;
673
674 if (index != 0) {
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
677 } else {
678 maxsize = 64 + 64;
679 if (hs_ep->dir_in)
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
681 else
682 maxpkt = 2;
683 }
684
685 /* we made the constant loading easier above by using +1 */
686 maxpkt--;
687 maxsize--;
688
689 /*
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
692 */
693
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
696
697 return maxsize;
698}
699
700/**
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
703 *
704 * Return the current frame number
705 */
706static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
707{
708 u32 dsts;
709
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
713
714 return dsts;
715}
716
717/**
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
721 *
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
725 */
726static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727{
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
733
734 if (is_isoc)
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
738 else
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740
741 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (hs_ep->index)
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
745
746 return maxsize;
747}
748
749/*
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
753 *
754 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * characteristics.
756 * DMA descriptor transfer bytes limit depends on EP type:
757 * Control out - MPS,
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
763 *
764 * Selects corresponding mask for RX/TX bytes as well.
765 */
766static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767{
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
771 u32 desc_size = 0;
772
773 if (!hs_ep->index && !dir_in) {
774 desc_size = mps;
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
777 if (dir_in) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 } else {
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
783 }
784 } else {
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
787
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
790 }
791
792 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (hs_ep->index)
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 desc_size = mps;
796 *mask = DEV_DMA_NBYTES_MASK;
797 }
798
799 return desc_size;
800}
801
802static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
804 dma_addr_t dma_buff,
805 unsigned int len,
806 bool true_last)
807{
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
810 u32 maxsize = 0;
811 u32 offset = 0;
812 u32 mask = 0;
813 int i;
814
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
819 if (len == 0)
820 hs_ep->desc_count = 1;
821
822 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status = 0;
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
826
827 if (len > maxsize) {
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830
831 (*desc)->status |=
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
834
835 len -= maxsize;
836 offset += maxsize;
837 } else {
838 if (true_last)
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
840
841 if (dir_in)
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
844 DEV_DMA_SHORT : 0);
845
846 (*desc)->status |=
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
849 }
850
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
854 (*desc)++;
855 }
856}
857
858/*
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
864 *
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
867 */
868static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
869 dma_addr_t dma_buff,
870 unsigned int len)
871{
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
875 int i;
876 u8 desc_count = 0;
877
878 if (hs_ep->req)
879 ureq = &hs_ep->req->req;
880
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
885 return;
886 }
887
888 /* DMA sg buffer */
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 sg_is_last(sg));
893 desc_count += hs_ep->desc_count;
894 }
895
896 hs_ep->desc_count = desc_count;
897}
898
899/*
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
904 *
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
908 * status.
909 */
910static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
912{
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
915 u32 index;
916 u32 mask = 0;
917 u8 pid = 0;
918
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
920
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
923
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
928 return 1;
929 }
930
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
937
938 desc->status = 0;
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
944
945 if (hs_ep->dir_in) {
946 if (len)
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
948 else
949 pid = 1;
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
953 DEV_DMA_SHORT : 0) |
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
957 }
958
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961
962 /* Increment frame number by interval for IN */
963 if (hs_ep->dir_in)
964 dwc2_gadget_incr_frame_num(hs_ep);
965
966 /* Update index of last configured entry in the chain */
967 hs_ep->next_desc++;
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
970
971 return 0;
972}
973
974/*
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
977 *
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
980 */
981static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982{
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
986 int ret;
987 int i;
988 u32 dma_reg;
989 u32 depctl;
990 u32 ctrl;
991 struct dwc2_dma_desc *desc;
992
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
996 return;
997 }
998
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1002 desc->status = 0;
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1005 }
1006
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1010
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1014 }
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1017 if (ret)
1018 break;
1019 }
1020
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1031}
1032
1033static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1037 int result);
1038
1039/**
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1045 *
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1048 */
1049static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1052 bool continuing)
1053{
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1057 u32 epctrl_reg;
1058 u32 epsize_reg;
1059 u32 epsize;
1060 u32 ctrl;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1065
1066 if (index != 0) {
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1069 WARN_ON(1);
1070 return;
1071 } else if (hs_ep->req != hs_req && continuing) {
1072 dev_err(hsotg->dev,
1073 "%s: continue different req\n", __func__);
1074 WARN_ON(1);
1075 return;
1076 }
1077 }
1078
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1086
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1092 return;
1093 }
1094
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1098
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1101 else
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1106
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1109
1110 /* round down to multiple of packets */
1111 if (round)
1112 maxreq -= round;
1113
1114 length = maxreq;
1115 }
1116
1117 if (length)
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 else
1120 packets = 1; /* send one packet if length is zero. */
1121
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1125 else
1126 epsize = DXEPTSIZ_MC(1);
1127 else
1128 epsize = 0;
1129
1130 /*
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 */
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1139 }
1140
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1143
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1149
1150 if (using_desc_dma(hsotg)) {
1151 u32 offset = 0;
1152 u32 mps = hs_ep->ep.maxpacket;
1153
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1155 if (!dir_in) {
1156 if (!index)
1157 length = mps;
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1160 }
1161
1162 if (continuing)
1163 offset = ureq->actual;
1164
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1167 length);
1168
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 } else {
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1177
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 /*
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1182 */
1183
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1188 }
1189 }
1190
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1196 else
1197 ctrl |= DXEPCTL_SETEVENFR;
1198 }
1199 ctrl |= DXEPCTL_CNAK;
1200 } else {
1201 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1202 return;
1203 }
1204 }
1205
1206 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1207
1208 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1209
1210 /* For Setup request do not clear NAK */
1211 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1212 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1213
1214 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1215 dwc2_writel(hsotg, ctrl, epctrl_reg);
1216
1217 /*
1218 * set these, it seems that DMA support increments past the end
1219 * of the packet buffer so we need to calculate the length from
1220 * this information.
1221 */
1222 hs_ep->size_loaded = length;
1223 hs_ep->last_load = ureq->actual;
1224
1225 if (dir_in && !using_dma(hsotg)) {
1226 /* set these anyway, we may need them for non-periodic in */
1227 hs_ep->fifo_load = 0;
1228
1229 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1230 }
1231
1232 /*
1233 * Note, trying to clear the NAK here causes problems with transmit
1234 * on the S3C6400 ending up with the TXFIFO becoming full.
1235 */
1236
1237 /* check ep is enabled */
1238 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1239 dev_dbg(hsotg->dev,
1240 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1241 index, dwc2_readl(hsotg, epctrl_reg));
1242
1243 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1244 __func__, dwc2_readl(hsotg, epctrl_reg));
1245
1246 /* enable ep interrupts */
1247 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1248}
1249
1250/**
1251 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1252 * @hsotg: The device state.
1253 * @hs_ep: The endpoint the request is on.
1254 * @req: The request being processed.
1255 *
1256 * We've been asked to queue a request, so ensure that the memory buffer
1257 * is correctly setup for DMA. If we've been passed an extant DMA address
1258 * then ensure the buffer has been synced to memory. If our buffer has no
1259 * DMA memory, then we map the memory and mark our request to allow us to
1260 * cleanup on completion.
1261 */
1262static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1263 struct dwc2_hsotg_ep *hs_ep,
1264 struct usb_request *req)
1265{
1266 int ret;
1267
1268 hs_ep->map_dir = hs_ep->dir_in;
1269 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1270 if (ret)
1271 goto dma_error;
1272
1273 return 0;
1274
1275dma_error:
1276 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1277 __func__, req->buf, req->length);
1278
1279 return -EIO;
1280}
1281
1282static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1283 struct dwc2_hsotg_ep *hs_ep,
1284 struct dwc2_hsotg_req *hs_req)
1285{
1286 void *req_buf = hs_req->req.buf;
1287
1288 /* If dma is not being used or buffer is aligned */
1289 if (!using_dma(hsotg) || !((long)req_buf & 3))
1290 return 0;
1291
1292 WARN_ON(hs_req->saved_req_buf);
1293
1294 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1295 hs_ep->ep.name, req_buf, hs_req->req.length);
1296
1297 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1298 if (!hs_req->req.buf) {
1299 hs_req->req.buf = req_buf;
1300 dev_err(hsotg->dev,
1301 "%s: unable to allocate memory for bounce buffer\n",
1302 __func__);
1303 return -ENOMEM;
1304 }
1305
1306 /* Save actual buffer */
1307 hs_req->saved_req_buf = req_buf;
1308
1309 if (hs_ep->dir_in)
1310 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1311 return 0;
1312}
1313
1314static void
1315dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1316 struct dwc2_hsotg_ep *hs_ep,
1317 struct dwc2_hsotg_req *hs_req)
1318{
1319 /* If dma is not being used or buffer was aligned */
1320 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1321 return;
1322
1323 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1324 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1325
1326 /* Copy data from bounce buffer on successful out transfer */
1327 if (!hs_ep->dir_in && !hs_req->req.status)
1328 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1329 hs_req->req.actual);
1330
1331 /* Free bounce buffer */
1332 kfree(hs_req->req.buf);
1333
1334 hs_req->req.buf = hs_req->saved_req_buf;
1335 hs_req->saved_req_buf = NULL;
1336}
1337
1338/**
1339 * dwc2_gadget_target_frame_elapsed - Checks target frame
1340 * @hs_ep: The driver endpoint to check
1341 *
1342 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1343 * corresponding transfer.
1344 */
1345static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1346{
1347 struct dwc2_hsotg *hsotg = hs_ep->parent;
1348 u32 target_frame = hs_ep->target_frame;
1349 u32 current_frame = hsotg->frame_number;
1350 bool frame_overrun = hs_ep->frame_overrun;
1351 u16 limit = DSTS_SOFFN_LIMIT;
1352
1353 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1354 limit >>= 3;
1355
1356 if (!frame_overrun && current_frame >= target_frame)
1357 return true;
1358
1359 if (frame_overrun && current_frame >= target_frame &&
1360 ((current_frame - target_frame) < limit / 2))
1361 return true;
1362
1363 return false;
1364}
1365
1366/*
1367 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1368 * @hsotg: The driver state
1369 * @hs_ep: the ep descriptor chain is for
1370 *
1371 * Called to update EP0 structure's pointers depend on stage of
1372 * control transfer.
1373 */
1374static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1375 struct dwc2_hsotg_ep *hs_ep)
1376{
1377 switch (hsotg->ep0_state) {
1378 case DWC2_EP0_SETUP:
1379 case DWC2_EP0_STATUS_OUT:
1380 hs_ep->desc_list = hsotg->setup_desc[0];
1381 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1382 break;
1383 case DWC2_EP0_DATA_IN:
1384 case DWC2_EP0_STATUS_IN:
1385 hs_ep->desc_list = hsotg->ctrl_in_desc;
1386 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1387 break;
1388 case DWC2_EP0_DATA_OUT:
1389 hs_ep->desc_list = hsotg->ctrl_out_desc;
1390 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1391 break;
1392 default:
1393 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1394 hsotg->ep0_state);
1395 return -EINVAL;
1396 }
1397
1398 return 0;
1399}
1400
1401static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1402 gfp_t gfp_flags)
1403{
1404 struct dwc2_hsotg_req *hs_req = our_req(req);
1405 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1406 struct dwc2_hsotg *hs = hs_ep->parent;
1407 bool first;
1408 int ret;
1409 u32 maxsize = 0;
1410 u32 mask = 0;
1411
1412
1413 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1414 ep->name, req, req->length, req->buf, req->no_interrupt,
1415 req->zero, req->short_not_ok);
1416
1417 /* Prevent new request submission when controller is suspended */
1418 if (hs->lx_state != DWC2_L0) {
1419 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1420 __func__);
1421 return -EAGAIN;
1422 }
1423
1424 /* initialise status of the request */
1425 INIT_LIST_HEAD(&hs_req->queue);
1426 req->actual = 0;
1427 req->status = -EINPROGRESS;
1428
1429 /* Don't queue ISOC request if length greater than mps*mc */
1430 if (hs_ep->isochronous &&
1431 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1432 dev_err(hs->dev, "req length > maxpacket*mc\n");
1433 return -EINVAL;
1434 }
1435
1436 /* In DDMA mode for ISOC's don't queue request if length greater
1437 * than descriptor limits.
1438 */
1439 if (using_desc_dma(hs) && hs_ep->isochronous) {
1440 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1441 if (hs_ep->dir_in && req->length > maxsize) {
1442 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1443 req->length, maxsize);
1444 return -EINVAL;
1445 }
1446
1447 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1448 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1449 req->length, hs_ep->ep.maxpacket);
1450 return -EINVAL;
1451 }
1452 }
1453
1454 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1455 if (ret)
1456 return ret;
1457
1458 /* if we're using DMA, sync the buffers as necessary */
1459 if (using_dma(hs)) {
1460 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1461 if (ret)
1462 return ret;
1463 }
1464 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1465 if (using_desc_dma(hs) && !hs_ep->index) {
1466 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1467 if (ret)
1468 return ret;
1469 }
1470
1471 first = list_empty(&hs_ep->queue);
1472 list_add_tail(&hs_req->queue, &hs_ep->queue);
1473
1474 /*
1475 * Handle DDMA isochronous transfers separately - just add new entry
1476 * to the descriptor chain.
1477 * Transfer will be started once SW gets either one of NAK or
1478 * OutTknEpDis interrupts.
1479 */
1480 if (using_desc_dma(hs) && hs_ep->isochronous) {
1481 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1482 dma_addr_t dma_addr = hs_req->req.dma;
1483
1484 if (hs_req->req.num_sgs) {
1485 WARN_ON(hs_req->req.num_sgs > 1);
1486 dma_addr = sg_dma_address(hs_req->req.sg);
1487 }
1488 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1489 hs_req->req.length);
1490 }
1491 return 0;
1492 }
1493
1494 /* Change EP direction if status phase request is after data out */
1495 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1496 hs->ep0_state == DWC2_EP0_DATA_OUT)
1497 hs_ep->dir_in = 1;
1498
1499 if (first) {
1500 if (!hs_ep->isochronous) {
1501 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1502 return 0;
1503 }
1504
1505 /* Update current frame number value. */
1506 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1507 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1508 dwc2_gadget_incr_frame_num(hs_ep);
1509 /* Update current frame number value once more as it
1510 * changes here.
1511 */
1512 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1513 }
1514
1515 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1516 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1517 }
1518 return 0;
1519}
1520
1521static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1522 gfp_t gfp_flags)
1523{
1524 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1525 struct dwc2_hsotg *hs = hs_ep->parent;
1526 unsigned long flags;
1527 int ret;
1528
1529 spin_lock_irqsave(&hs->lock, flags);
1530 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1531 spin_unlock_irqrestore(&hs->lock, flags);
1532
1533 return ret;
1534}
1535
1536static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1537 struct usb_request *req)
1538{
1539 struct dwc2_hsotg_req *hs_req = our_req(req);
1540
1541 kfree(hs_req);
1542}
1543
1544/**
1545 * dwc2_hsotg_complete_oursetup - setup completion callback
1546 * @ep: The endpoint the request was on.
1547 * @req: The request completed.
1548 *
1549 * Called on completion of any requests the driver itself
1550 * submitted that need cleaning up.
1551 */
1552static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1553 struct usb_request *req)
1554{
1555 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1556 struct dwc2_hsotg *hsotg = hs_ep->parent;
1557
1558 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1559
1560 dwc2_hsotg_ep_free_request(ep, req);
1561}
1562
1563/**
1564 * ep_from_windex - convert control wIndex value to endpoint
1565 * @hsotg: The driver state.
1566 * @windex: The control request wIndex field (in host order).
1567 *
1568 * Convert the given wIndex into a pointer to an driver endpoint
1569 * structure, or return NULL if it is not a valid endpoint.
1570 */
1571static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1572 u32 windex)
1573{
1574 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1575 int idx = windex & 0x7F;
1576
1577 if (windex >= 0x100)
1578 return NULL;
1579
1580 if (idx > hsotg->num_of_eps)
1581 return NULL;
1582
1583 return index_to_ep(hsotg, idx, dir);
1584}
1585
1586/**
1587 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1588 * @hsotg: The driver state.
1589 * @testmode: requested usb test mode
1590 * Enable usb Test Mode requested by the Host.
1591 */
1592int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1593{
1594 int dctl = dwc2_readl(hsotg, DCTL);
1595
1596 dctl &= ~DCTL_TSTCTL_MASK;
1597 switch (testmode) {
1598 case USB_TEST_J:
1599 case USB_TEST_K:
1600 case USB_TEST_SE0_NAK:
1601 case USB_TEST_PACKET:
1602 case USB_TEST_FORCE_ENABLE:
1603 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1604 break;
1605 default:
1606 return -EINVAL;
1607 }
1608 dwc2_writel(hsotg, dctl, DCTL);
1609 return 0;
1610}
1611
1612/**
1613 * dwc2_hsotg_send_reply - send reply to control request
1614 * @hsotg: The device state
1615 * @ep: Endpoint 0
1616 * @buff: Buffer for request
1617 * @length: Length of reply.
1618 *
1619 * Create a request and queue it on the given endpoint. This is useful as
1620 * an internal method of sending replies to certain control requests, etc.
1621 */
1622static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1623 struct dwc2_hsotg_ep *ep,
1624 void *buff,
1625 int length)
1626{
1627 struct usb_request *req;
1628 int ret;
1629
1630 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1631
1632 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1633 hsotg->ep0_reply = req;
1634 if (!req) {
1635 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1636 return -ENOMEM;
1637 }
1638
1639 req->buf = hsotg->ep0_buff;
1640 req->length = length;
1641 /*
1642 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1643 * STATUS stage.
1644 */
1645 req->zero = 0;
1646 req->complete = dwc2_hsotg_complete_oursetup;
1647
1648 if (length)
1649 memcpy(req->buf, buff, length);
1650
1651 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1652 if (ret) {
1653 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1654 return ret;
1655 }
1656
1657 return 0;
1658}
1659
1660/**
1661 * dwc2_hsotg_process_req_status - process request GET_STATUS
1662 * @hsotg: The device state
1663 * @ctrl: USB control request
1664 */
1665static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1666 struct usb_ctrlrequest *ctrl)
1667{
1668 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1669 struct dwc2_hsotg_ep *ep;
1670 __le16 reply;
1671 u16 status;
1672 int ret;
1673
1674 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1675
1676 if (!ep0->dir_in) {
1677 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1678 return -EINVAL;
1679 }
1680
1681 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1682 case USB_RECIP_DEVICE:
1683 status = hsotg->gadget.is_selfpowered <<
1684 USB_DEVICE_SELF_POWERED;
1685 status |= hsotg->remote_wakeup_allowed <<
1686 USB_DEVICE_REMOTE_WAKEUP;
1687 reply = cpu_to_le16(status);
1688 break;
1689
1690 case USB_RECIP_INTERFACE:
1691 /* currently, the data result should be zero */
1692 reply = cpu_to_le16(0);
1693 break;
1694
1695 case USB_RECIP_ENDPOINT:
1696 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1697 if (!ep)
1698 return -ENOENT;
1699
1700 reply = cpu_to_le16(ep->halted ? 1 : 0);
1701 break;
1702
1703 default:
1704 return 0;
1705 }
1706
1707 if (le16_to_cpu(ctrl->wLength) != 2)
1708 return -EINVAL;
1709
1710 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1711 if (ret) {
1712 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1713 return ret;
1714 }
1715
1716 return 1;
1717}
1718
1719static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1720
1721/**
1722 * get_ep_head - return the first request on the endpoint
1723 * @hs_ep: The controller endpoint to get
1724 *
1725 * Get the first request on the endpoint.
1726 */
1727static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1728{
1729 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1730 queue);
1731}
1732
1733/**
1734 * dwc2_gadget_start_next_request - Starts next request from ep queue
1735 * @hs_ep: Endpoint structure
1736 *
1737 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1738 * in its handler. Hence we need to unmask it here to be able to do
1739 * resynchronization.
1740 */
1741static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1742{
1743 struct dwc2_hsotg *hsotg = hs_ep->parent;
1744 int dir_in = hs_ep->dir_in;
1745 struct dwc2_hsotg_req *hs_req;
1746
1747 if (!list_empty(&hs_ep->queue)) {
1748 hs_req = get_ep_head(hs_ep);
1749 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1750 return;
1751 }
1752 if (!hs_ep->isochronous)
1753 return;
1754
1755 if (dir_in) {
1756 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1757 __func__);
1758 } else {
1759 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1760 __func__);
1761 }
1762}
1763
1764/**
1765 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1766 * @hsotg: The device state
1767 * @ctrl: USB control request
1768 */
1769static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1770 struct usb_ctrlrequest *ctrl)
1771{
1772 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1773 struct dwc2_hsotg_req *hs_req;
1774 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1775 struct dwc2_hsotg_ep *ep;
1776 int ret;
1777 bool halted;
1778 u32 recip;
1779 u32 wValue;
1780 u32 wIndex;
1781
1782 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1783 __func__, set ? "SET" : "CLEAR");
1784
1785 wValue = le16_to_cpu(ctrl->wValue);
1786 wIndex = le16_to_cpu(ctrl->wIndex);
1787 recip = ctrl->bRequestType & USB_RECIP_MASK;
1788
1789 switch (recip) {
1790 case USB_RECIP_DEVICE:
1791 switch (wValue) {
1792 case USB_DEVICE_REMOTE_WAKEUP:
1793 if (set)
1794 hsotg->remote_wakeup_allowed = 1;
1795 else
1796 hsotg->remote_wakeup_allowed = 0;
1797 break;
1798
1799 case USB_DEVICE_TEST_MODE:
1800 if ((wIndex & 0xff) != 0)
1801 return -EINVAL;
1802 if (!set)
1803 return -EINVAL;
1804
1805 hsotg->test_mode = wIndex >> 8;
1806 break;
1807 default:
1808 return -ENOENT;
1809 }
1810
1811 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1812 if (ret) {
1813 dev_err(hsotg->dev,
1814 "%s: failed to send reply\n", __func__);
1815 return ret;
1816 }
1817 break;
1818
1819 case USB_RECIP_ENDPOINT:
1820 ep = ep_from_windex(hsotg, wIndex);
1821 if (!ep) {
1822 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1823 __func__, wIndex);
1824 return -ENOENT;
1825 }
1826
1827 switch (wValue) {
1828 case USB_ENDPOINT_HALT:
1829 halted = ep->halted;
1830
1831 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1832
1833 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1834 if (ret) {
1835 dev_err(hsotg->dev,
1836 "%s: failed to send reply\n", __func__);
1837 return ret;
1838 }
1839
1840 /*
1841 * we have to complete all requests for ep if it was
1842 * halted, and the halt was cleared by CLEAR_FEATURE
1843 */
1844
1845 if (!set && halted) {
1846 /*
1847 * If we have request in progress,
1848 * then complete it
1849 */
1850 if (ep->req) {
1851 hs_req = ep->req;
1852 ep->req = NULL;
1853 list_del_init(&hs_req->queue);
1854 if (hs_req->req.complete) {
1855 spin_unlock(&hsotg->lock);
1856 usb_gadget_giveback_request(
1857 &ep->ep, &hs_req->req);
1858 spin_lock(&hsotg->lock);
1859 }
1860 }
1861
1862 /* If we have pending request, then start it */
1863 if (!ep->req)
1864 dwc2_gadget_start_next_request(ep);
1865 }
1866
1867 break;
1868
1869 default:
1870 return -ENOENT;
1871 }
1872 break;
1873 default:
1874 return -ENOENT;
1875 }
1876 return 1;
1877}
1878
1879static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1880
1881/**
1882 * dwc2_hsotg_stall_ep0 - stall ep0
1883 * @hsotg: The device state
1884 *
1885 * Set stall for ep0 as response for setup request.
1886 */
1887static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1888{
1889 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1890 u32 reg;
1891 u32 ctrl;
1892
1893 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1894 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1895
1896 /*
1897 * DxEPCTL_Stall will be cleared by EP once it has
1898 * taken effect, so no need to clear later.
1899 */
1900
1901 ctrl = dwc2_readl(hsotg, reg);
1902 ctrl |= DXEPCTL_STALL;
1903 ctrl |= DXEPCTL_CNAK;
1904 dwc2_writel(hsotg, ctrl, reg);
1905
1906 dev_dbg(hsotg->dev,
1907 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1908 ctrl, reg, dwc2_readl(hsotg, reg));
1909
1910 /*
1911 * complete won't be called, so we enqueue
1912 * setup request here
1913 */
1914 dwc2_hsotg_enqueue_setup(hsotg);
1915}
1916
1917/**
1918 * dwc2_hsotg_process_control - process a control request
1919 * @hsotg: The device state
1920 * @ctrl: The control request received
1921 *
1922 * The controller has received the SETUP phase of a control request, and
1923 * needs to work out what to do next (and whether to pass it on to the
1924 * gadget driver).
1925 */
1926static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1927 struct usb_ctrlrequest *ctrl)
1928{
1929 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1930 int ret = 0;
1931 u32 dcfg;
1932
1933 dev_dbg(hsotg->dev,
1934 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1935 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1936 ctrl->wIndex, ctrl->wLength);
1937
1938 if (ctrl->wLength == 0) {
1939 ep0->dir_in = 1;
1940 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1941 } else if (ctrl->bRequestType & USB_DIR_IN) {
1942 ep0->dir_in = 1;
1943 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1944 } else {
1945 ep0->dir_in = 0;
1946 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1947 }
1948
1949 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1950 switch (ctrl->bRequest) {
1951 case USB_REQ_SET_ADDRESS:
1952 hsotg->connected = 1;
1953 dcfg = dwc2_readl(hsotg, DCFG);
1954 dcfg &= ~DCFG_DEVADDR_MASK;
1955 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1956 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1957 dwc2_writel(hsotg, dcfg, DCFG);
1958
1959 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1960
1961 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1962 return;
1963
1964 case USB_REQ_GET_STATUS:
1965 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1966 break;
1967
1968 case USB_REQ_CLEAR_FEATURE:
1969 case USB_REQ_SET_FEATURE:
1970 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1971 break;
1972 }
1973 }
1974
1975 /* as a fallback, try delivering it to the driver to deal with */
1976
1977 if (ret == 0 && hsotg->driver) {
1978 spin_unlock(&hsotg->lock);
1979 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1980 spin_lock(&hsotg->lock);
1981 if (ret < 0)
1982 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1983 }
1984
1985 hsotg->delayed_status = false;
1986 if (ret == USB_GADGET_DELAYED_STATUS)
1987 hsotg->delayed_status = true;
1988
1989 /*
1990 * the request is either unhandlable, or is not formatted correctly
1991 * so respond with a STALL for the status stage to indicate failure.
1992 */
1993
1994 if (ret < 0)
1995 dwc2_hsotg_stall_ep0(hsotg);
1996}
1997
1998/**
1999 * dwc2_hsotg_complete_setup - completion of a setup transfer
2000 * @ep: The endpoint the request was on.
2001 * @req: The request completed.
2002 *
2003 * Called on completion of any requests the driver itself submitted for
2004 * EP0 setup packets
2005 */
2006static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2007 struct usb_request *req)
2008{
2009 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2010 struct dwc2_hsotg *hsotg = hs_ep->parent;
2011
2012 if (req->status < 0) {
2013 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2014 return;
2015 }
2016
2017 spin_lock(&hsotg->lock);
2018 if (req->actual == 0)
2019 dwc2_hsotg_enqueue_setup(hsotg);
2020 else
2021 dwc2_hsotg_process_control(hsotg, req->buf);
2022 spin_unlock(&hsotg->lock);
2023}
2024
2025/**
2026 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2027 * @hsotg: The device state.
2028 *
2029 * Enqueue a request on EP0 if necessary to received any SETUP packets
2030 * received from the host.
2031 */
2032static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2033{
2034 struct usb_request *req = hsotg->ctrl_req;
2035 struct dwc2_hsotg_req *hs_req = our_req(req);
2036 int ret;
2037
2038 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2039
2040 req->zero = 0;
2041 req->length = 8;
2042 req->buf = hsotg->ctrl_buff;
2043 req->complete = dwc2_hsotg_complete_setup;
2044
2045 if (!list_empty(&hs_req->queue)) {
2046 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2047 return;
2048 }
2049
2050 hsotg->eps_out[0]->dir_in = 0;
2051 hsotg->eps_out[0]->send_zlp = 0;
2052 hsotg->ep0_state = DWC2_EP0_SETUP;
2053
2054 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2055 if (ret < 0) {
2056 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2057 /*
2058 * Don't think there's much we can do other than watch the
2059 * driver fail.
2060 */
2061 }
2062}
2063
2064static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2065 struct dwc2_hsotg_ep *hs_ep)
2066{
2067 u32 ctrl;
2068 u8 index = hs_ep->index;
2069 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2070 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2071
2072 if (hs_ep->dir_in)
2073 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2074 index);
2075 else
2076 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2077 index);
2078 if (using_desc_dma(hsotg)) {
2079 /* Not specific buffer needed for ep0 ZLP */
2080 dma_addr_t dma = hs_ep->desc_list_dma;
2081
2082 if (!index)
2083 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2084
2085 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2086 } else {
2087 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2088 DXEPTSIZ_XFERSIZE(0),
2089 epsiz_reg);
2090 }
2091
2092 ctrl = dwc2_readl(hsotg, epctl_reg);
2093 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2094 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2095 ctrl |= DXEPCTL_USBACTEP;
2096 dwc2_writel(hsotg, ctrl, epctl_reg);
2097}
2098
2099/**
2100 * dwc2_hsotg_complete_request - complete a request given to us
2101 * @hsotg: The device state.
2102 * @hs_ep: The endpoint the request was on.
2103 * @hs_req: The request to complete.
2104 * @result: The result code (0 => Ok, otherwise errno)
2105 *
2106 * The given request has finished, so call the necessary completion
2107 * if it has one and then look to see if we can start a new request
2108 * on the endpoint.
2109 *
2110 * Note, expects the ep to already be locked as appropriate.
2111 */
2112static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2113 struct dwc2_hsotg_ep *hs_ep,
2114 struct dwc2_hsotg_req *hs_req,
2115 int result)
2116{
2117 if (!hs_req) {
2118 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2119 return;
2120 }
2121
2122 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2123 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2124
2125 /*
2126 * only replace the status if we've not already set an error
2127 * from a previous transaction
2128 */
2129
2130 if (hs_req->req.status == -EINPROGRESS)
2131 hs_req->req.status = result;
2132
2133 if (using_dma(hsotg))
2134 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2135
2136 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2137
2138 hs_ep->req = NULL;
2139 list_del_init(&hs_req->queue);
2140
2141 /*
2142 * call the complete request with the locks off, just in case the
2143 * request tries to queue more work for this endpoint.
2144 */
2145
2146 if (hs_req->req.complete) {
2147 spin_unlock(&hsotg->lock);
2148 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2149 spin_lock(&hsotg->lock);
2150 }
2151
2152 /* In DDMA don't need to proceed to starting of next ISOC request */
2153 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2154 return;
2155
2156 /*
2157 * Look to see if there is anything else to do. Note, the completion
2158 * of the previous request may have caused a new request to be started
2159 * so be careful when doing this.
2160 */
2161
2162 if (!hs_ep->req && result >= 0)
2163 dwc2_gadget_start_next_request(hs_ep);
2164}
2165
2166/*
2167 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2168 * @hs_ep: The endpoint the request was on.
2169 *
2170 * Get first request from the ep queue, determine descriptor on which complete
2171 * happened. SW discovers which descriptor currently in use by HW, adjusts
2172 * dma_address and calculates index of completed descriptor based on the value
2173 * of DEPDMA register. Update actual length of request, giveback to gadget.
2174 */
2175static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2176{
2177 struct dwc2_hsotg *hsotg = hs_ep->parent;
2178 struct dwc2_hsotg_req *hs_req;
2179 struct usb_request *ureq;
2180 u32 desc_sts;
2181 u32 mask;
2182
2183 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2184
2185 /* Process only descriptors with buffer status set to DMA done */
2186 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2187 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2188
2189 hs_req = get_ep_head(hs_ep);
2190 if (!hs_req) {
2191 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2192 return;
2193 }
2194 ureq = &hs_req->req;
2195
2196 /* Check completion status */
2197 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2198 DEV_DMA_STS_SUCC) {
2199 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2200 DEV_DMA_ISOC_RX_NBYTES_MASK;
2201 ureq->actual = ureq->length - ((desc_sts & mask) >>
2202 DEV_DMA_ISOC_NBYTES_SHIFT);
2203
2204 /* Adjust actual len for ISOC Out if len is
2205 * not align of 4
2206 */
2207 if (!hs_ep->dir_in && ureq->length & 0x3)
2208 ureq->actual += 4 - (ureq->length & 0x3);
2209
2210 /* Set actual frame number for completed transfers */
2211 ureq->frame_number =
2212 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2213 DEV_DMA_ISOC_FRNUM_SHIFT;
2214 }
2215
2216 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2217
2218 hs_ep->compl_desc++;
2219 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2220 hs_ep->compl_desc = 0;
2221 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2222 }
2223}
2224
2225/*
2226 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2227 * @hs_ep: The isochronous endpoint.
2228 *
2229 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2230 * interrupt. Reset target frame and next_desc to allow to start
2231 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2232 * interrupt for OUT direction.
2233 */
2234static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2235{
2236 struct dwc2_hsotg *hsotg = hs_ep->parent;
2237
2238 if (!hs_ep->dir_in)
2239 dwc2_flush_rx_fifo(hsotg);
2240 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2241
2242 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2243 hs_ep->next_desc = 0;
2244 hs_ep->compl_desc = 0;
2245}
2246
2247/**
2248 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2249 * @hsotg: The device state.
2250 * @ep_idx: The endpoint index for the data
2251 * @size: The size of data in the fifo, in bytes
2252 *
2253 * The FIFO status shows there is data to read from the FIFO for a given
2254 * endpoint, so sort out whether we need to read the data into a request
2255 * that has been made for that endpoint.
2256 */
2257static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2258{
2259 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2260 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2261 int to_read;
2262 int max_req;
2263 int read_ptr;
2264
2265 if (!hs_req) {
2266 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2267 int ptr;
2268
2269 dev_dbg(hsotg->dev,
2270 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2271 __func__, size, ep_idx, epctl);
2272
2273 /* dump the data from the FIFO, we've nothing we can do */
2274 for (ptr = 0; ptr < size; ptr += 4)
2275 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2276
2277 return;
2278 }
2279
2280 to_read = size;
2281 read_ptr = hs_req->req.actual;
2282 max_req = hs_req->req.length - read_ptr;
2283
2284 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2285 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2286
2287 if (to_read > max_req) {
2288 /*
2289 * more data appeared than we where willing
2290 * to deal with in this request.
2291 */
2292
2293 /* currently we don't deal this */
2294 WARN_ON_ONCE(1);
2295 }
2296
2297 hs_ep->total_data += to_read;
2298 hs_req->req.actual += to_read;
2299 to_read = DIV_ROUND_UP(to_read, 4);
2300
2301 /*
2302 * note, we might over-write the buffer end by 3 bytes depending on
2303 * alignment of the data.
2304 */
2305 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2306 hs_req->req.buf + read_ptr, to_read);
2307}
2308
2309/**
2310 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2311 * @hsotg: The device instance
2312 * @dir_in: If IN zlp
2313 *
2314 * Generate a zero-length IN packet request for terminating a SETUP
2315 * transaction.
2316 *
2317 * Note, since we don't write any data to the TxFIFO, then it is
2318 * currently believed that we do not need to wait for any space in
2319 * the TxFIFO.
2320 */
2321static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2322{
2323 /* eps_out[0] is used in both directions */
2324 hsotg->eps_out[0]->dir_in = dir_in;
2325 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2326
2327 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2328}
2329
2330/*
2331 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2332 * @hs_ep - The endpoint on which transfer went
2333 *
2334 * Iterate over endpoints descriptor chain and get info on bytes remained
2335 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2336 */
2337static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2338{
2339 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2340 struct dwc2_hsotg *hsotg = hs_ep->parent;
2341 unsigned int bytes_rem = 0;
2342 unsigned int bytes_rem_correction = 0;
2343 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2344 int i;
2345 u32 status;
2346 u32 mps = hs_ep->ep.maxpacket;
2347 int dir_in = hs_ep->dir_in;
2348
2349 if (!desc)
2350 return -EINVAL;
2351
2352 /* Interrupt OUT EP with mps not multiple of 4 */
2353 if (hs_ep->index)
2354 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2355 bytes_rem_correction = 4 - (mps % 4);
2356
2357 for (i = 0; i < hs_ep->desc_count; ++i) {
2358 status = desc->status;
2359 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2360 bytes_rem -= bytes_rem_correction;
2361
2362 if (status & DEV_DMA_STS_MASK)
2363 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2364 i, status & DEV_DMA_STS_MASK);
2365
2366 if (status & DEV_DMA_L)
2367 break;
2368
2369 desc++;
2370 }
2371
2372 return bytes_rem;
2373}
2374
2375/**
2376 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2377 * @hsotg: The device instance
2378 * @epnum: The endpoint received from
2379 *
2380 * The RXFIFO has delivered an OutDone event, which means that the data
2381 * transfer for an OUT endpoint has been completed, either by a short
2382 * packet or by the finish of a transfer.
2383 */
2384static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2385{
2386 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2387 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2388 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2389 struct usb_request *req = &hs_req->req;
2390 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2391 int result = 0;
2392
2393 if (!hs_req) {
2394 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2395 return;
2396 }
2397
2398 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2399 dev_dbg(hsotg->dev, "zlp packet received\n");
2400 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2401 dwc2_hsotg_enqueue_setup(hsotg);
2402 return;
2403 }
2404
2405 if (using_desc_dma(hsotg))
2406 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2407
2408 if (using_dma(hsotg)) {
2409 unsigned int size_done;
2410
2411 /*
2412 * Calculate the size of the transfer by checking how much
2413 * is left in the endpoint size register and then working it
2414 * out from the amount we loaded for the transfer.
2415 *
2416 * We need to do this as DMA pointers are always 32bit aligned
2417 * so may overshoot/undershoot the transfer.
2418 */
2419
2420 size_done = hs_ep->size_loaded - size_left;
2421 size_done += hs_ep->last_load;
2422
2423 req->actual = size_done;
2424 }
2425
2426 /* if there is more request to do, schedule new transfer */
2427 if (req->actual < req->length && size_left == 0) {
2428 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2429 return;
2430 }
2431
2432 if (req->actual < req->length && req->short_not_ok) {
2433 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2434 __func__, req->actual, req->length);
2435
2436 /*
2437 * todo - what should we return here? there's no one else
2438 * even bothering to check the status.
2439 */
2440 }
2441
2442 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2443 if (!using_desc_dma(hsotg) && epnum == 0 &&
2444 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2445 /* Move to STATUS IN */
2446 if (!hsotg->delayed_status)
2447 dwc2_hsotg_ep0_zlp(hsotg, true);
2448 }
2449
2450 /* Set actual frame number for completed transfers */
2451 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2452 req->frame_number = hs_ep->target_frame;
2453 dwc2_gadget_incr_frame_num(hs_ep);
2454 }
2455
2456 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2457}
2458
2459/**
2460 * dwc2_hsotg_handle_rx - RX FIFO has data
2461 * @hsotg: The device instance
2462 *
2463 * The IRQ handler has detected that the RX FIFO has some data in it
2464 * that requires processing, so find out what is in there and do the
2465 * appropriate read.
2466 *
2467 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2468 * chunks, so if you have x packets received on an endpoint you'll get x
2469 * FIFO events delivered, each with a packet's worth of data in it.
2470 *
2471 * When using DMA, we should not be processing events from the RXFIFO
2472 * as the actual data should be sent to the memory directly and we turn
2473 * on the completion interrupts to get notifications of transfer completion.
2474 */
2475static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2476{
2477 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2478 u32 epnum, status, size;
2479
2480 WARN_ON(using_dma(hsotg));
2481
2482 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2483 status = grxstsr & GRXSTS_PKTSTS_MASK;
2484
2485 size = grxstsr & GRXSTS_BYTECNT_MASK;
2486 size >>= GRXSTS_BYTECNT_SHIFT;
2487
2488 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2489 __func__, grxstsr, size, epnum);
2490
2491 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2492 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2493 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2494 break;
2495
2496 case GRXSTS_PKTSTS_OUTDONE:
2497 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2498 dwc2_hsotg_read_frameno(hsotg));
2499
2500 if (!using_dma(hsotg))
2501 dwc2_hsotg_handle_outdone(hsotg, epnum);
2502 break;
2503
2504 case GRXSTS_PKTSTS_SETUPDONE:
2505 dev_dbg(hsotg->dev,
2506 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2507 dwc2_hsotg_read_frameno(hsotg),
2508 dwc2_readl(hsotg, DOEPCTL(0)));
2509 /*
2510 * Call dwc2_hsotg_handle_outdone here if it was not called from
2511 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2512 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2513 */
2514 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2515 dwc2_hsotg_handle_outdone(hsotg, epnum);
2516 break;
2517
2518 case GRXSTS_PKTSTS_OUTRX:
2519 dwc2_hsotg_rx_data(hsotg, epnum, size);
2520 break;
2521
2522 case GRXSTS_PKTSTS_SETUPRX:
2523 dev_dbg(hsotg->dev,
2524 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2525 dwc2_hsotg_read_frameno(hsotg),
2526 dwc2_readl(hsotg, DOEPCTL(0)));
2527
2528 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2529
2530 dwc2_hsotg_rx_data(hsotg, epnum, size);
2531 break;
2532
2533 default:
2534 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2535 __func__, grxstsr);
2536
2537 dwc2_hsotg_dump(hsotg);
2538 break;
2539 }
2540}
2541
2542/**
2543 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2544 * @mps: The maximum packet size in bytes.
2545 */
2546static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2547{
2548 switch (mps) {
2549 case 64:
2550 return D0EPCTL_MPS_64;
2551 case 32:
2552 return D0EPCTL_MPS_32;
2553 case 16:
2554 return D0EPCTL_MPS_16;
2555 case 8:
2556 return D0EPCTL_MPS_8;
2557 }
2558
2559 /* bad max packet size, warn and return invalid result */
2560 WARN_ON(1);
2561 return (u32)-1;
2562}
2563
2564/**
2565 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2566 * @hsotg: The driver state.
2567 * @ep: The index number of the endpoint
2568 * @mps: The maximum packet size in bytes
2569 * @mc: The multicount value
2570 * @dir_in: True if direction is in.
2571 *
2572 * Configure the maximum packet size for the given endpoint, updating
2573 * the hardware control registers to reflect this.
2574 */
2575static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2576 unsigned int ep, unsigned int mps,
2577 unsigned int mc, unsigned int dir_in)
2578{
2579 struct dwc2_hsotg_ep *hs_ep;
2580 u32 reg;
2581
2582 hs_ep = index_to_ep(hsotg, ep, dir_in);
2583 if (!hs_ep)
2584 return;
2585
2586 if (ep == 0) {
2587 u32 mps_bytes = mps;
2588
2589 /* EP0 is a special case */
2590 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2591 if (mps > 3)
2592 goto bad_mps;
2593 hs_ep->ep.maxpacket = mps_bytes;
2594 hs_ep->mc = 1;
2595 } else {
2596 if (mps > 1024)
2597 goto bad_mps;
2598 hs_ep->mc = mc;
2599 if (mc > 3)
2600 goto bad_mps;
2601 hs_ep->ep.maxpacket = mps;
2602 }
2603
2604 if (dir_in) {
2605 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2606 reg &= ~DXEPCTL_MPS_MASK;
2607 reg |= mps;
2608 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2609 } else {
2610 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2611 reg &= ~DXEPCTL_MPS_MASK;
2612 reg |= mps;
2613 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2614 }
2615
2616 return;
2617
2618bad_mps:
2619 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2620}
2621
2622/**
2623 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2624 * @hsotg: The driver state
2625 * @idx: The index for the endpoint (0..15)
2626 */
2627static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2628{
2629 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2630 GRSTCTL);
2631
2632 /* wait until the fifo is flushed */
2633 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2634 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2635 __func__);
2636}
2637
2638/**
2639 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2640 * @hsotg: The driver state
2641 * @hs_ep: The driver endpoint to check.
2642 *
2643 * Check to see if there is a request that has data to send, and if so
2644 * make an attempt to write data into the FIFO.
2645 */
2646static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2647 struct dwc2_hsotg_ep *hs_ep)
2648{
2649 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2650
2651 if (!hs_ep->dir_in || !hs_req) {
2652 /**
2653 * if request is not enqueued, we disable interrupts
2654 * for endpoints, excepting ep0
2655 */
2656 if (hs_ep->index != 0)
2657 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2658 hs_ep->dir_in, 0);
2659 return 0;
2660 }
2661
2662 if (hs_req->req.actual < hs_req->req.length) {
2663 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2664 hs_ep->index);
2665 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2666 }
2667
2668 return 0;
2669}
2670
2671/**
2672 * dwc2_hsotg_complete_in - complete IN transfer
2673 * @hsotg: The device state.
2674 * @hs_ep: The endpoint that has just completed.
2675 *
2676 * An IN transfer has been completed, update the transfer's state and then
2677 * call the relevant completion routines.
2678 */
2679static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2680 struct dwc2_hsotg_ep *hs_ep)
2681{
2682 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2683 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2684 int size_left, size_done;
2685
2686 if (!hs_req) {
2687 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2688 return;
2689 }
2690
2691 /* Finish ZLP handling for IN EP0 transactions */
2692 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2693 dev_dbg(hsotg->dev, "zlp packet sent\n");
2694
2695 /*
2696 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2697 * changed to IN. Change back to complete OUT transfer request
2698 */
2699 hs_ep->dir_in = 0;
2700
2701 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2702 if (hsotg->test_mode) {
2703 int ret;
2704
2705 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2706 if (ret < 0) {
2707 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2708 hsotg->test_mode);
2709 dwc2_hsotg_stall_ep0(hsotg);
2710 return;
2711 }
2712 }
2713 dwc2_hsotg_enqueue_setup(hsotg);
2714 return;
2715 }
2716
2717 /*
2718 * Calculate the size of the transfer by checking how much is left
2719 * in the endpoint size register and then working it out from
2720 * the amount we loaded for the transfer.
2721 *
2722 * We do this even for DMA, as the transfer may have incremented
2723 * past the end of the buffer (DMA transfers are always 32bit
2724 * aligned).
2725 */
2726 if (using_desc_dma(hsotg)) {
2727 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2728 if (size_left < 0)
2729 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2730 size_left);
2731 } else {
2732 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2733 }
2734
2735 size_done = hs_ep->size_loaded - size_left;
2736 size_done += hs_ep->last_load;
2737
2738 if (hs_req->req.actual != size_done)
2739 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2740 __func__, hs_req->req.actual, size_done);
2741
2742 hs_req->req.actual = size_done;
2743 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2744 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2745
2746 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2747 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2748 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2749 return;
2750 }
2751
2752 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2753 if (hs_ep->send_zlp) {
2754 hs_ep->send_zlp = 0;
2755 if (!using_desc_dma(hsotg)) {
2756 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2757 /* transfer will be completed on next complete interrupt */
2758 return;
2759 }
2760 }
2761
2762 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2763 /* Move to STATUS OUT */
2764 dwc2_hsotg_ep0_zlp(hsotg, false);
2765 return;
2766 }
2767
2768 /* Set actual frame number for completed transfers */
2769 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2770 hs_req->req.frame_number = hs_ep->target_frame;
2771 dwc2_gadget_incr_frame_num(hs_ep);
2772 }
2773
2774 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2775}
2776
2777/**
2778 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2779 * @hsotg: The device state.
2780 * @idx: Index of ep.
2781 * @dir_in: Endpoint direction 1-in 0-out.
2782 *
2783 * Reads for endpoint with given index and direction, by masking
2784 * epint_reg with coresponding mask.
2785 */
2786static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2787 unsigned int idx, int dir_in)
2788{
2789 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2790 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2791 u32 ints;
2792 u32 mask;
2793 u32 diepempmsk;
2794
2795 mask = dwc2_readl(hsotg, epmsk_reg);
2796 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2797 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2798 mask |= DXEPINT_SETUP_RCVD;
2799
2800 ints = dwc2_readl(hsotg, epint_reg);
2801 ints &= mask;
2802 return ints;
2803}
2804
2805/**
2806 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2807 * @hs_ep: The endpoint on which interrupt is asserted.
2808 *
2809 * This interrupt indicates that the endpoint has been disabled per the
2810 * application's request.
2811 *
2812 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2813 * in case of ISOC completes current request.
2814 *
2815 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2816 * request starts it.
2817 */
2818static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2819{
2820 struct dwc2_hsotg *hsotg = hs_ep->parent;
2821 struct dwc2_hsotg_req *hs_req;
2822 unsigned char idx = hs_ep->index;
2823 int dir_in = hs_ep->dir_in;
2824 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2825 int dctl = dwc2_readl(hsotg, DCTL);
2826
2827 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2828
2829 if (dir_in) {
2830 int epctl = dwc2_readl(hsotg, epctl_reg);
2831
2832 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2833
2834 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2835 int dctl = dwc2_readl(hsotg, DCTL);
2836
2837 dctl |= DCTL_CGNPINNAK;
2838 dwc2_writel(hsotg, dctl, DCTL);
2839 }
2840 } else {
2841
2842 if (dctl & DCTL_GOUTNAKSTS) {
2843 dctl |= DCTL_CGOUTNAK;
2844 dwc2_writel(hsotg, dctl, DCTL);
2845 }
2846 }
2847
2848 if (!hs_ep->isochronous)
2849 return;
2850
2851 if (list_empty(&hs_ep->queue)) {
2852 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2853 __func__, hs_ep);
2854 return;
2855 }
2856
2857 do {
2858 hs_req = get_ep_head(hs_ep);
2859 if (hs_req)
2860 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2861 -ENODATA);
2862 dwc2_gadget_incr_frame_num(hs_ep);
2863 /* Update current frame number value. */
2864 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2865 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2866}
2867
2868/**
2869 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2870 * @ep: The endpoint on which interrupt is asserted.
2871 *
2872 * This is starting point for ISOC-OUT transfer, synchronization done with
2873 * first out token received from host while corresponding EP is disabled.
2874 *
2875 * Device does not know initial frame in which out token will come. For this
2876 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2877 * getting this interrupt SW starts calculation for next transfer frame.
2878 */
2879static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2880{
2881 struct dwc2_hsotg *hsotg = ep->parent;
2882 struct dwc2_hsotg_req *hs_req;
2883 int dir_in = ep->dir_in;
2884
2885 if (dir_in || !ep->isochronous)
2886 return;
2887
2888 if (using_desc_dma(hsotg)) {
2889 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2890 /* Start first ISO Out */
2891 ep->target_frame = hsotg->frame_number;
2892 dwc2_gadget_start_isoc_ddma(ep);
2893 }
2894 return;
2895 }
2896
2897 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2898 u32 ctrl;
2899
2900 ep->target_frame = hsotg->frame_number;
2901 if (ep->interval > 1) {
2902 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2903 if (ep->target_frame & 0x1)
2904 ctrl |= DXEPCTL_SETODDFR;
2905 else
2906 ctrl |= DXEPCTL_SETEVENFR;
2907
2908 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2909 }
2910 }
2911
2912 while (dwc2_gadget_target_frame_elapsed(ep)) {
2913 hs_req = get_ep_head(ep);
2914 if (hs_req)
2915 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2916
2917 dwc2_gadget_incr_frame_num(ep);
2918 /* Update current frame number value. */
2919 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2920 }
2921
2922 if (!ep->req)
2923 dwc2_gadget_start_next_request(ep);
2924
2925}
2926
2927static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2928 struct dwc2_hsotg_ep *hs_ep);
2929
2930/**
2931 * dwc2_gadget_handle_nak - handle NAK interrupt
2932 * @hs_ep: The endpoint on which interrupt is asserted.
2933 *
2934 * This is starting point for ISOC-IN transfer, synchronization done with
2935 * first IN token received from host while corresponding EP is disabled.
2936 *
2937 * Device does not know when first one token will arrive from host. On first
2938 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2939 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2940 * sent in response to that as there was no data in FIFO. SW is basing on this
2941 * interrupt to obtain frame in which token has come and then based on the
2942 * interval calculates next frame for transfer.
2943 */
2944static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2945{
2946 struct dwc2_hsotg *hsotg = hs_ep->parent;
2947 struct dwc2_hsotg_req *hs_req;
2948 int dir_in = hs_ep->dir_in;
2949 u32 ctrl;
2950
2951 if (!dir_in || !hs_ep->isochronous)
2952 return;
2953
2954 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2955
2956 if (using_desc_dma(hsotg)) {
2957 hs_ep->target_frame = hsotg->frame_number;
2958 dwc2_gadget_incr_frame_num(hs_ep);
2959
2960 /* In service interval mode target_frame must
2961 * be set to last (u)frame of the service interval.
2962 */
2963 if (hsotg->params.service_interval) {
2964 /* Set target_frame to the first (u)frame of
2965 * the service interval
2966 */
2967 hs_ep->target_frame &= ~hs_ep->interval + 1;
2968
2969 /* Set target_frame to the last (u)frame of
2970 * the service interval
2971 */
2972 dwc2_gadget_incr_frame_num(hs_ep);
2973 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2974 }
2975
2976 dwc2_gadget_start_isoc_ddma(hs_ep);
2977 return;
2978 }
2979
2980 hs_ep->target_frame = hsotg->frame_number;
2981 if (hs_ep->interval > 1) {
2982 u32 ctrl = dwc2_readl(hsotg,
2983 DIEPCTL(hs_ep->index));
2984 if (hs_ep->target_frame & 0x1)
2985 ctrl |= DXEPCTL_SETODDFR;
2986 else
2987 ctrl |= DXEPCTL_SETEVENFR;
2988
2989 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2990 }
2991 }
2992
2993 if (using_desc_dma(hsotg))
2994 return;
2995
2996 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
2997 if (ctrl & DXEPCTL_EPENA)
2998 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
2999 else
3000 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3001
3002 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3003 hs_req = get_ep_head(hs_ep);
3004 if (hs_req)
3005 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3006
3007 dwc2_gadget_incr_frame_num(hs_ep);
3008 /* Update current frame number value. */
3009 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3010 }
3011
3012 if (!hs_ep->req)
3013 dwc2_gadget_start_next_request(hs_ep);
3014}
3015
3016/**
3017 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3018 * @hsotg: The driver state
3019 * @idx: The index for the endpoint (0..15)
3020 * @dir_in: Set if this is an IN endpoint
3021 *
3022 * Process and clear any interrupt pending for an individual endpoint
3023 */
3024static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3025 int dir_in)
3026{
3027 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3028 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3029 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3030 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3031 u32 ints;
3032
3033 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3034
3035 /* Clear endpoint interrupts */
3036 dwc2_writel(hsotg, ints, epint_reg);
3037
3038 if (!hs_ep) {
3039 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3040 __func__, idx, dir_in ? "in" : "out");
3041 return;
3042 }
3043
3044 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3045 __func__, idx, dir_in ? "in" : "out", ints);
3046
3047 /* Don't process XferCompl interrupt if it is a setup packet */
3048 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3049 ints &= ~DXEPINT_XFERCOMPL;
3050
3051 /*
3052 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3053 * stage and xfercomplete was generated without SETUP phase done
3054 * interrupt. SW should parse received setup packet only after host's
3055 * exit from setup phase of control transfer.
3056 */
3057 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3058 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3059 ints &= ~DXEPINT_XFERCOMPL;
3060
3061 if (ints & DXEPINT_XFERCOMPL) {
3062 dev_dbg(hsotg->dev,
3063 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3064 __func__, dwc2_readl(hsotg, epctl_reg),
3065 dwc2_readl(hsotg, epsiz_reg));
3066
3067 /* In DDMA handle isochronous requests separately */
3068 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3069 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3070 } else if (dir_in) {
3071 /*
3072 * We get OutDone from the FIFO, so we only
3073 * need to look at completing IN requests here
3074 * if operating slave mode
3075 */
3076 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3077 dwc2_hsotg_complete_in(hsotg, hs_ep);
3078
3079 if (idx == 0 && !hs_ep->req)
3080 dwc2_hsotg_enqueue_setup(hsotg);
3081 } else if (using_dma(hsotg)) {
3082 /*
3083 * We're using DMA, we need to fire an OutDone here
3084 * as we ignore the RXFIFO.
3085 */
3086 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3087 dwc2_hsotg_handle_outdone(hsotg, idx);
3088 }
3089 }
3090
3091 if (ints & DXEPINT_EPDISBLD)
3092 dwc2_gadget_handle_ep_disabled(hs_ep);
3093
3094 if (ints & DXEPINT_OUTTKNEPDIS)
3095 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3096
3097 if (ints & DXEPINT_NAKINTRPT)
3098 dwc2_gadget_handle_nak(hs_ep);
3099
3100 if (ints & DXEPINT_AHBERR)
3101 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3102
3103 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3104 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3105
3106 if (using_dma(hsotg) && idx == 0) {
3107 /*
3108 * this is the notification we've received a
3109 * setup packet. In non-DMA mode we'd get this
3110 * from the RXFIFO, instead we need to process
3111 * the setup here.
3112 */
3113
3114 if (dir_in)
3115 WARN_ON_ONCE(1);
3116 else
3117 dwc2_hsotg_handle_outdone(hsotg, 0);
3118 }
3119 }
3120
3121 if (ints & DXEPINT_STSPHSERCVD) {
3122 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3123
3124 /* Safety check EP0 state when STSPHSERCVD asserted */
3125 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3126 /* Move to STATUS IN for DDMA */
3127 if (using_desc_dma(hsotg)) {
3128 if (!hsotg->delayed_status)
3129 dwc2_hsotg_ep0_zlp(hsotg, true);
3130 else
3131 /* In case of 3 stage Control Write with delayed
3132 * status, when Status IN transfer started
3133 * before STSPHSERCVD asserted, NAKSTS bit not
3134 * cleared by CNAK in dwc2_hsotg_start_req()
3135 * function. Clear now NAKSTS to allow complete
3136 * transfer.
3137 */
3138 dwc2_set_bit(hsotg, DIEPCTL(0),
3139 DXEPCTL_CNAK);
3140 }
3141 }
3142
3143 }
3144
3145 if (ints & DXEPINT_BACK2BACKSETUP)
3146 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3147
3148 if (ints & DXEPINT_BNAINTR) {
3149 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3150 if (hs_ep->isochronous)
3151 dwc2_gadget_handle_isoc_bna(hs_ep);
3152 }
3153
3154 if (dir_in && !hs_ep->isochronous) {
3155 /* not sure if this is important, but we'll clear it anyway */
3156 if (ints & DXEPINT_INTKNTXFEMP) {
3157 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3158 __func__, idx);
3159 }
3160
3161 /* this probably means something bad is happening */
3162 if (ints & DXEPINT_INTKNEPMIS) {
3163 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3164 __func__, idx);
3165 }
3166
3167 /* FIFO has space or is empty (see GAHBCFG) */
3168 if (hsotg->dedicated_fifos &&
3169 ints & DXEPINT_TXFEMP) {
3170 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3171 __func__, idx);
3172 if (!using_dma(hsotg))
3173 dwc2_hsotg_trytx(hsotg, hs_ep);
3174 }
3175 }
3176}
3177
3178/**
3179 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3180 * @hsotg: The device state.
3181 *
3182 * Handle updating the device settings after the enumeration phase has
3183 * been completed.
3184 */
3185static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3186{
3187 u32 dsts = dwc2_readl(hsotg, DSTS);
3188 int ep0_mps = 0, ep_mps = 8;
3189
3190 /*
3191 * This should signal the finish of the enumeration phase
3192 * of the USB handshaking, so we should now know what rate
3193 * we connected at.
3194 */
3195
3196 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3197
3198 /*
3199 * note, since we're limited by the size of transfer on EP0, and
3200 * it seems IN transfers must be a even number of packets we do
3201 * not advertise a 64byte MPS on EP0.
3202 */
3203
3204 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3205 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3206 case DSTS_ENUMSPD_FS:
3207 case DSTS_ENUMSPD_FS48:
3208 hsotg->gadget.speed = USB_SPEED_FULL;
3209 ep0_mps = EP0_MPS_LIMIT;
3210 ep_mps = 1023;
3211 break;
3212
3213 case DSTS_ENUMSPD_HS:
3214 hsotg->gadget.speed = USB_SPEED_HIGH;
3215 ep0_mps = EP0_MPS_LIMIT;
3216 ep_mps = 1024;
3217 break;
3218
3219 case DSTS_ENUMSPD_LS:
3220 hsotg->gadget.speed = USB_SPEED_LOW;
3221 ep0_mps = 8;
3222 ep_mps = 8;
3223 /*
3224 * note, we don't actually support LS in this driver at the
3225 * moment, and the documentation seems to imply that it isn't
3226 * supported by the PHYs on some of the devices.
3227 */
3228 break;
3229 }
3230 dev_info(hsotg->dev, "new device is %s\n",
3231 usb_speed_string(hsotg->gadget.speed));
3232
3233 /*
3234 * we should now know the maximum packet size for an
3235 * endpoint, so set the endpoints to a default value.
3236 */
3237
3238 if (ep0_mps) {
3239 int i;
3240 /* Initialize ep0 for both in and out directions */
3241 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3242 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3243 for (i = 1; i < hsotg->num_of_eps; i++) {
3244 if (hsotg->eps_in[i])
3245 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3246 0, 1);
3247 if (hsotg->eps_out[i])
3248 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3249 0, 0);
3250 }
3251 }
3252
3253 /* ensure after enumeration our EP0 is active */
3254
3255 dwc2_hsotg_enqueue_setup(hsotg);
3256
3257 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3258 dwc2_readl(hsotg, DIEPCTL0),
3259 dwc2_readl(hsotg, DOEPCTL0));
3260}
3261
3262/**
3263 * kill_all_requests - remove all requests from the endpoint's queue
3264 * @hsotg: The device state.
3265 * @ep: The endpoint the requests may be on.
3266 * @result: The result code to use.
3267 *
3268 * Go through the requests on the given endpoint and mark them
3269 * completed with the given result code.
3270 */
3271static void kill_all_requests(struct dwc2_hsotg *hsotg,
3272 struct dwc2_hsotg_ep *ep,
3273 int result)
3274{
3275 unsigned int size;
3276
3277 ep->req = NULL;
3278
3279 while (!list_empty(&ep->queue)) {
3280 struct dwc2_hsotg_req *req = get_ep_head(ep);
3281
3282 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3283 }
3284
3285 if (!hsotg->dedicated_fifos)
3286 return;
3287 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3288 if (size < ep->fifo_size)
3289 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3290}
3291
3292/**
3293 * dwc2_hsotg_disconnect - disconnect service
3294 * @hsotg: The device state.
3295 *
3296 * The device has been disconnected. Remove all current
3297 * transactions and signal the gadget driver that this
3298 * has happened.
3299 */
3300void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3301{
3302 unsigned int ep;
3303
3304 if (!hsotg->connected)
3305 return;
3306
3307 hsotg->connected = 0;
3308 hsotg->test_mode = 0;
3309
3310 /* all endpoints should be shutdown */
3311 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3312 if (hsotg->eps_in[ep])
3313 kill_all_requests(hsotg, hsotg->eps_in[ep],
3314 -ESHUTDOWN);
3315 if (hsotg->eps_out[ep])
3316 kill_all_requests(hsotg, hsotg->eps_out[ep],
3317 -ESHUTDOWN);
3318 }
3319
3320 call_gadget(hsotg, disconnect);
3321 hsotg->lx_state = DWC2_L3;
3322
3323 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3324}
3325
3326/**
3327 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3328 * @hsotg: The device state:
3329 * @periodic: True if this is a periodic FIFO interrupt
3330 */
3331static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3332{
3333 struct dwc2_hsotg_ep *ep;
3334 int epno, ret;
3335
3336 /* look through for any more data to transmit */
3337 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3338 ep = index_to_ep(hsotg, epno, 1);
3339
3340 if (!ep)
3341 continue;
3342
3343 if (!ep->dir_in)
3344 continue;
3345
3346 if ((periodic && !ep->periodic) ||
3347 (!periodic && ep->periodic))
3348 continue;
3349
3350 ret = dwc2_hsotg_trytx(hsotg, ep);
3351 if (ret < 0)
3352 break;
3353 }
3354}
3355
3356/* IRQ flags which will trigger a retry around the IRQ loop */
3357#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3358 GINTSTS_PTXFEMP | \
3359 GINTSTS_RXFLVL)
3360
3361static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3362/**
3363 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3364 * @hsotg: The device state
3365 * @is_usb_reset: Usb resetting flag
3366 *
3367 * Issue a soft reset to the core, and await the core finishing it.
3368 */
3369void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3370 bool is_usb_reset)
3371{
3372 u32 intmsk;
3373 u32 val;
3374 u32 usbcfg;
3375 u32 dcfg = 0;
3376 int ep;
3377
3378 /* Kill any ep0 requests as controller will be reinitialized */
3379 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3380
3381 if (!is_usb_reset) {
3382 if (dwc2_core_reset(hsotg, true))
3383 return;
3384 } else {
3385 /* all endpoints should be shutdown */
3386 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3387 if (hsotg->eps_in[ep])
3388 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3389 if (hsotg->eps_out[ep])
3390 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3391 }
3392 }
3393
3394 /*
3395 * we must now enable ep0 ready for host detection and then
3396 * set configuration.
3397 */
3398
3399 /* keep other bits untouched (so e.g. forced modes are not lost) */
3400 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3401 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3402 usbcfg |= GUSBCFG_TOUTCAL(7);
3403
3404 /* remove the HNP/SRP and set the PHY */
3405 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3406 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3407
3408 dwc2_phy_init(hsotg, true);
3409
3410 dwc2_hsotg_init_fifo(hsotg);
3411
3412 if (!is_usb_reset)
3413 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3414
3415 dcfg |= DCFG_EPMISCNT(1);
3416
3417 switch (hsotg->params.speed) {
3418 case DWC2_SPEED_PARAM_LOW:
3419 dcfg |= DCFG_DEVSPD_LS;
3420 break;
3421 case DWC2_SPEED_PARAM_FULL:
3422 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3423 dcfg |= DCFG_DEVSPD_FS48;
3424 else
3425 dcfg |= DCFG_DEVSPD_FS;
3426 break;
3427 default:
3428 dcfg |= DCFG_DEVSPD_HS;
3429 }
3430
3431 if (hsotg->params.ipg_isoc_en)
3432 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3433
3434 dwc2_writel(hsotg, dcfg, DCFG);
3435
3436 /* Clear any pending OTG interrupts */
3437 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3438
3439 /* Clear any pending interrupts */
3440 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3441 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3442 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3443 GINTSTS_USBRST | GINTSTS_RESETDET |
3444 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3445 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3446 GINTSTS_LPMTRANRCVD;
3447
3448 if (!using_desc_dma(hsotg))
3449 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3450
3451 if (!hsotg->params.external_id_pin_ctl)
3452 intmsk |= GINTSTS_CONIDSTSCHNG;
3453
3454 dwc2_writel(hsotg, intmsk, GINTMSK);
3455
3456 if (using_dma(hsotg)) {
3457 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3458 hsotg->params.ahbcfg,
3459 GAHBCFG);
3460
3461 /* Set DDMA mode support in the core if needed */
3462 if (using_desc_dma(hsotg))
3463 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3464
3465 } else {
3466 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3467 (GAHBCFG_NP_TXF_EMP_LVL |
3468 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3469 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3470 }
3471
3472 /*
3473 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3474 * when we have no data to transfer. Otherwise we get being flooded by
3475 * interrupts.
3476 */
3477
3478 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3479 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3480 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3481 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3482 DIEPMSK);
3483
3484 /*
3485 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3486 * DMA mode we may need this and StsPhseRcvd.
3487 */
3488 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3489 DOEPMSK_STSPHSERCVDMSK) : 0) |
3490 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3491 DOEPMSK_SETUPMSK,
3492 DOEPMSK);
3493
3494 /* Enable BNA interrupt for DDMA */
3495 if (using_desc_dma(hsotg)) {
3496 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3497 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3498 }
3499
3500 /* Enable Service Interval mode if supported */
3501 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3502 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3503
3504 dwc2_writel(hsotg, 0, DAINTMSK);
3505
3506 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3507 dwc2_readl(hsotg, DIEPCTL0),
3508 dwc2_readl(hsotg, DOEPCTL0));
3509
3510 /* enable in and out endpoint interrupts */
3511 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3512
3513 /*
3514 * Enable the RXFIFO when in slave mode, as this is how we collect
3515 * the data. In DMA mode, we get events from the FIFO but also
3516 * things we cannot process, so do not use it.
3517 */
3518 if (!using_dma(hsotg))
3519 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3520
3521 /* Enable interrupts for EP0 in and out */
3522 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3523 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3524
3525 if (!is_usb_reset) {
3526 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3527 udelay(10); /* see openiboot */
3528 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3529 }
3530
3531 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3532
3533 /*
3534 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3535 * writing to the EPCTL register..
3536 */
3537
3538 /* set to read 1 8byte packet */
3539 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3540 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3541
3542 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3543 DXEPCTL_CNAK | DXEPCTL_EPENA |
3544 DXEPCTL_USBACTEP,
3545 DOEPCTL0);
3546
3547 /* enable, but don't activate EP0in */
3548 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3549 DXEPCTL_USBACTEP, DIEPCTL0);
3550
3551 /* clear global NAKs */
3552 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3553 if (!is_usb_reset)
3554 val |= DCTL_SFTDISCON;
3555 dwc2_set_bit(hsotg, DCTL, val);
3556
3557 /* configure the core to support LPM */
3558 dwc2_gadget_init_lpm(hsotg);
3559
3560 /* program GREFCLK register if needed */
3561 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3562 dwc2_gadget_program_ref_clk(hsotg);
3563
3564 /* must be at-least 3ms to allow bus to see disconnect */
3565 mdelay(3);
3566
3567 hsotg->lx_state = DWC2_L0;
3568
3569 dwc2_hsotg_enqueue_setup(hsotg);
3570
3571 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3572 dwc2_readl(hsotg, DIEPCTL0),
3573 dwc2_readl(hsotg, DOEPCTL0));
3574}
3575
3576void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3577{
3578 /* set the soft-disconnect bit */
3579 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3580}
3581
3582void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3583{
3584 /* remove the soft-disconnect and let's go */
3585 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3586}
3587
3588/**
3589 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3590 * @hsotg: The device state:
3591 *
3592 * This interrupt indicates one of the following conditions occurred while
3593 * transmitting an ISOC transaction.
3594 * - Corrupted IN Token for ISOC EP.
3595 * - Packet not complete in FIFO.
3596 *
3597 * The following actions will be taken:
3598 * - Determine the EP
3599 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3600 */
3601static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3602{
3603 struct dwc2_hsotg_ep *hs_ep;
3604 u32 epctrl;
3605 u32 daintmsk;
3606 u32 idx;
3607
3608 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3609
3610 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3611
3612 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3613 hs_ep = hsotg->eps_in[idx];
3614 /* Proceed only unmasked ISOC EPs */
3615 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3616 continue;
3617
3618 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3619 if ((epctrl & DXEPCTL_EPENA) &&
3620 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3621 epctrl |= DXEPCTL_SNAK;
3622 epctrl |= DXEPCTL_EPDIS;
3623 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3624 }
3625 }
3626
3627 /* Clear interrupt */
3628 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3629}
3630
3631/**
3632 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3633 * @hsotg: The device state:
3634 *
3635 * This interrupt indicates one of the following conditions occurred while
3636 * transmitting an ISOC transaction.
3637 * - Corrupted OUT Token for ISOC EP.
3638 * - Packet not complete in FIFO.
3639 *
3640 * The following actions will be taken:
3641 * - Determine the EP
3642 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3643 */
3644static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3645{
3646 u32 gintsts;
3647 u32 gintmsk;
3648 u32 daintmsk;
3649 u32 epctrl;
3650 struct dwc2_hsotg_ep *hs_ep;
3651 int idx;
3652
3653 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3654
3655 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3656 daintmsk >>= DAINT_OUTEP_SHIFT;
3657
3658 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3659 hs_ep = hsotg->eps_out[idx];
3660 /* Proceed only unmasked ISOC EPs */
3661 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3662 continue;
3663
3664 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3665 if ((epctrl & DXEPCTL_EPENA) &&
3666 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3667 /* Unmask GOUTNAKEFF interrupt */
3668 gintmsk = dwc2_readl(hsotg, GINTMSK);
3669 gintmsk |= GINTSTS_GOUTNAKEFF;
3670 dwc2_writel(hsotg, gintmsk, GINTMSK);
3671
3672 gintsts = dwc2_readl(hsotg, GINTSTS);
3673 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3674 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3675 break;
3676 }
3677 }
3678 }
3679
3680 /* Clear interrupt */
3681 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3682}
3683
3684/**
3685 * dwc2_hsotg_irq - handle device interrupt
3686 * @irq: The IRQ number triggered
3687 * @pw: The pw value when registered the handler.
3688 */
3689static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3690{
3691 struct dwc2_hsotg *hsotg = pw;
3692 int retry_count = 8;
3693 u32 gintsts;
3694 u32 gintmsk;
3695
3696 if (!dwc2_is_device_mode(hsotg))
3697 return IRQ_NONE;
3698
3699 spin_lock(&hsotg->lock);
3700irq_retry:
3701 gintsts = dwc2_readl(hsotg, GINTSTS);
3702 gintmsk = dwc2_readl(hsotg, GINTMSK);
3703
3704 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3705 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3706
3707 gintsts &= gintmsk;
3708
3709 if (gintsts & GINTSTS_RESETDET) {
3710 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3711
3712 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3713
3714 /* This event must be used only if controller is suspended */
3715 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3716 dwc2_exit_partial_power_down(hsotg, 0, true);
3717
3718 hsotg->lx_state = DWC2_L0;
3719 }
3720
3721 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3722 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3723 u32 connected = hsotg->connected;
3724
3725 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3726 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3727 dwc2_readl(hsotg, GNPTXSTS));
3728
3729 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3730
3731 /* Report disconnection if it is not already done. */
3732 dwc2_hsotg_disconnect(hsotg);
3733
3734 /* Reset device address to zero */
3735 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3736
3737 if (usb_status & GOTGCTL_BSESVLD && connected)
3738 dwc2_hsotg_core_init_disconnected(hsotg, true);
3739 }
3740
3741 if (gintsts & GINTSTS_ENUMDONE) {
3742 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3743
3744 dwc2_hsotg_irq_enumdone(hsotg);
3745 }
3746
3747 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3748 u32 daint = dwc2_readl(hsotg, DAINT);
3749 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3750 u32 daint_out, daint_in;
3751 int ep;
3752
3753 daint &= daintmsk;
3754 daint_out = daint >> DAINT_OUTEP_SHIFT;
3755 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3756
3757 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3758
3759 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3760 ep++, daint_out >>= 1) {
3761 if (daint_out & 1)
3762 dwc2_hsotg_epint(hsotg, ep, 0);
3763 }
3764
3765 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3766 ep++, daint_in >>= 1) {
3767 if (daint_in & 1)
3768 dwc2_hsotg_epint(hsotg, ep, 1);
3769 }
3770 }
3771
3772 /* check both FIFOs */
3773
3774 if (gintsts & GINTSTS_NPTXFEMP) {
3775 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3776
3777 /*
3778 * Disable the interrupt to stop it happening again
3779 * unless one of these endpoint routines decides that
3780 * it needs re-enabling
3781 */
3782
3783 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3784 dwc2_hsotg_irq_fifoempty(hsotg, false);
3785 }
3786
3787 if (gintsts & GINTSTS_PTXFEMP) {
3788 dev_dbg(hsotg->dev, "PTxFEmp\n");
3789
3790 /* See note in GINTSTS_NPTxFEmp */
3791
3792 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3793 dwc2_hsotg_irq_fifoempty(hsotg, true);
3794 }
3795
3796 if (gintsts & GINTSTS_RXFLVL) {
3797 /*
3798 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3799 * we need to retry dwc2_hsotg_handle_rx if this is still
3800 * set.
3801 */
3802
3803 dwc2_hsotg_handle_rx(hsotg);
3804 }
3805
3806 if (gintsts & GINTSTS_ERLYSUSP) {
3807 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3808 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3809 }
3810
3811 /*
3812 * these next two seem to crop-up occasionally causing the core
3813 * to shutdown the USB transfer, so try clearing them and logging
3814 * the occurrence.
3815 */
3816
3817 if (gintsts & GINTSTS_GOUTNAKEFF) {
3818 u8 idx;
3819 u32 epctrl;
3820 u32 gintmsk;
3821 u32 daintmsk;
3822 struct dwc2_hsotg_ep *hs_ep;
3823
3824 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3825 daintmsk >>= DAINT_OUTEP_SHIFT;
3826 /* Mask this interrupt */
3827 gintmsk = dwc2_readl(hsotg, GINTMSK);
3828 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3829 dwc2_writel(hsotg, gintmsk, GINTMSK);
3830
3831 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3832 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3833 hs_ep = hsotg->eps_out[idx];
3834 /* Proceed only unmasked ISOC EPs */
3835 if (BIT(idx) & ~daintmsk)
3836 continue;
3837
3838 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3839
3840 //ISOC Ep's only
3841 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3842 epctrl |= DXEPCTL_SNAK;
3843 epctrl |= DXEPCTL_EPDIS;
3844 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3845 continue;
3846 }
3847
3848 //Non-ISOC EP's
3849 if (hs_ep->halted) {
3850 if (!(epctrl & DXEPCTL_EPENA))
3851 epctrl |= DXEPCTL_EPENA;
3852 epctrl |= DXEPCTL_EPDIS;
3853 epctrl |= DXEPCTL_STALL;
3854 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3855 }
3856 }
3857
3858 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3859 }
3860
3861 if (gintsts & GINTSTS_GINNAKEFF) {
3862 dev_info(hsotg->dev, "GINNakEff triggered\n");
3863
3864 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3865
3866 dwc2_hsotg_dump(hsotg);
3867 }
3868
3869 if (gintsts & GINTSTS_INCOMPL_SOIN)
3870 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3871
3872 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3873 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3874
3875 /*
3876 * if we've had fifo events, we should try and go around the
3877 * loop again to see if there's any point in returning yet.
3878 */
3879
3880 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3881 goto irq_retry;
3882
3883 /* Check WKUP_ALERT interrupt*/
3884 if (hsotg->params.service_interval)
3885 dwc2_gadget_wkup_alert_handler(hsotg);
3886
3887 spin_unlock(&hsotg->lock);
3888
3889 return IRQ_HANDLED;
3890}
3891
3892static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3893 struct dwc2_hsotg_ep *hs_ep)
3894{
3895 u32 epctrl_reg;
3896 u32 epint_reg;
3897
3898 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3899 DOEPCTL(hs_ep->index);
3900 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3901 DOEPINT(hs_ep->index);
3902
3903 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3904 hs_ep->name);
3905
3906 if (hs_ep->dir_in) {
3907 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3908 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3909 /* Wait for Nak effect */
3910 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3911 DXEPINT_INEPNAKEFF, 100))
3912 dev_warn(hsotg->dev,
3913 "%s: timeout DIEPINT.NAKEFF\n",
3914 __func__);
3915 } else {
3916 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3917 /* Wait for Nak effect */
3918 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3919 GINTSTS_GINNAKEFF, 100))
3920 dev_warn(hsotg->dev,
3921 "%s: timeout GINTSTS.GINNAKEFF\n",
3922 __func__);
3923 }
3924 } else {
3925 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3926 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3927
3928 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3929 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3930
3931 if (!using_dma(hsotg)) {
3932 /* Wait for GINTSTS_RXFLVL interrupt */
3933 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3934 GINTSTS_RXFLVL, 100)) {
3935 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3936 __func__);
3937 } else {
3938 /*
3939 * Pop GLOBAL OUT NAK status packet from RxFIFO
3940 * to assert GOUTNAKEFF interrupt
3941 */
3942 dwc2_readl(hsotg, GRXSTSP);
3943 }
3944 }
3945
3946 /* Wait for global nak to take effect */
3947 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3948 GINTSTS_GOUTNAKEFF, 100))
3949 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3950 __func__);
3951 }
3952
3953 /* Disable ep */
3954 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3955
3956 /* Wait for ep to be disabled */
3957 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3958 dev_warn(hsotg->dev,
3959 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3960
3961 /* Clear EPDISBLD interrupt */
3962 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3963
3964 if (hs_ep->dir_in) {
3965 unsigned short fifo_index;
3966
3967 if (hsotg->dedicated_fifos || hs_ep->periodic)
3968 fifo_index = hs_ep->fifo_index;
3969 else
3970 fifo_index = 0;
3971
3972 /* Flush TX FIFO */
3973 dwc2_flush_tx_fifo(hsotg, fifo_index);
3974
3975 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3976 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3977 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3978
3979 } else {
3980 /* Remove global NAKs */
3981 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3982 }
3983}
3984
3985/**
3986 * dwc2_hsotg_ep_enable - enable the given endpoint
3987 * @ep: The USB endpint to configure
3988 * @desc: The USB endpoint descriptor to configure with.
3989 *
3990 * This is called from the USB gadget code's usb_ep_enable().
3991 */
3992static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3993 const struct usb_endpoint_descriptor *desc)
3994{
3995 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3996 struct dwc2_hsotg *hsotg = hs_ep->parent;
3997 unsigned long flags;
3998 unsigned int index = hs_ep->index;
3999 u32 epctrl_reg;
4000 u32 epctrl;
4001 u32 mps;
4002 u32 mc;
4003 u32 mask;
4004 unsigned int dir_in;
4005 unsigned int i, val, size;
4006 int ret = 0;
4007 unsigned char ep_type;
4008 int desc_num;
4009
4010 dev_dbg(hsotg->dev,
4011 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4012 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4013 desc->wMaxPacketSize, desc->bInterval);
4014
4015 /* not to be called for EP0 */
4016 if (index == 0) {
4017 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4018 return -EINVAL;
4019 }
4020
4021 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4022 if (dir_in != hs_ep->dir_in) {
4023 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4024 return -EINVAL;
4025 }
4026
4027 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4028 mps = usb_endpoint_maxp(desc);
4029 mc = usb_endpoint_maxp_mult(desc);
4030
4031 /* ISOC IN in DDMA supported bInterval up to 10 */
4032 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4033 dir_in && desc->bInterval > 10) {
4034 dev_err(hsotg->dev,
4035 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4036 return -EINVAL;
4037 }
4038
4039 /* High bandwidth ISOC OUT in DDMA not supported */
4040 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4041 !dir_in && mc > 1) {
4042 dev_err(hsotg->dev,
4043 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4044 return -EINVAL;
4045 }
4046
4047 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4048
4049 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4050 epctrl = dwc2_readl(hsotg, epctrl_reg);
4051
4052 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4053 __func__, epctrl, epctrl_reg);
4054
4055 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4056 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4057 else
4058 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4059
4060 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4061 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4062 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4063 desc_num * sizeof(struct dwc2_dma_desc),
4064 &hs_ep->desc_list_dma, GFP_ATOMIC);
4065 if (!hs_ep->desc_list) {
4066 ret = -ENOMEM;
4067 goto error2;
4068 }
4069 }
4070
4071 spin_lock_irqsave(&hsotg->lock, flags);
4072
4073 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4074 epctrl |= DXEPCTL_MPS(mps);
4075
4076 /*
4077 * mark the endpoint as active, otherwise the core may ignore
4078 * transactions entirely for this endpoint
4079 */
4080 epctrl |= DXEPCTL_USBACTEP;
4081
4082 /* update the endpoint state */
4083 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4084
4085 /* default, set to non-periodic */
4086 hs_ep->isochronous = 0;
4087 hs_ep->periodic = 0;
4088 hs_ep->halted = 0;
4089 hs_ep->interval = desc->bInterval;
4090
4091 switch (ep_type) {
4092 case USB_ENDPOINT_XFER_ISOC:
4093 epctrl |= DXEPCTL_EPTYPE_ISO;
4094 epctrl |= DXEPCTL_SETEVENFR;
4095 hs_ep->isochronous = 1;
4096 hs_ep->interval = 1 << (desc->bInterval - 1);
4097 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4098 hs_ep->next_desc = 0;
4099 hs_ep->compl_desc = 0;
4100 if (dir_in) {
4101 hs_ep->periodic = 1;
4102 mask = dwc2_readl(hsotg, DIEPMSK);
4103 mask |= DIEPMSK_NAKMSK;
4104 dwc2_writel(hsotg, mask, DIEPMSK);
4105 } else {
4106 epctrl |= DXEPCTL_SNAK;
4107 mask = dwc2_readl(hsotg, DOEPMSK);
4108 mask |= DOEPMSK_OUTTKNEPDISMSK;
4109 dwc2_writel(hsotg, mask, DOEPMSK);
4110 }
4111 break;
4112
4113 case USB_ENDPOINT_XFER_BULK:
4114 epctrl |= DXEPCTL_EPTYPE_BULK;
4115 break;
4116
4117 case USB_ENDPOINT_XFER_INT:
4118 if (dir_in)
4119 hs_ep->periodic = 1;
4120
4121 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4122 hs_ep->interval = 1 << (desc->bInterval - 1);
4123
4124 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4125 break;
4126
4127 case USB_ENDPOINT_XFER_CONTROL:
4128 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4129 break;
4130 }
4131
4132 /*
4133 * if the hardware has dedicated fifos, we must give each IN EP
4134 * a unique tx-fifo even if it is non-periodic.
4135 */
4136 if (dir_in && hsotg->dedicated_fifos) {
4137 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4138 u32 fifo_index = 0;
4139 u32 fifo_size = UINT_MAX;
4140
4141 size = hs_ep->ep.maxpacket * hs_ep->mc;
4142 for (i = 1; i <= fifo_count; ++i) {
4143 if (hsotg->fifo_map & (1 << i))
4144 continue;
4145 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4146 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4147 if (val < size)
4148 continue;
4149 /* Search for smallest acceptable fifo */
4150 if (val < fifo_size) {
4151 fifo_size = val;
4152 fifo_index = i;
4153 }
4154 }
4155 if (!fifo_index) {
4156 dev_err(hsotg->dev,
4157 "%s: No suitable fifo found\n", __func__);
4158 ret = -ENOMEM;
4159 goto error1;
4160 }
4161 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4162 hsotg->fifo_map |= 1 << fifo_index;
4163 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4164 hs_ep->fifo_index = fifo_index;
4165 hs_ep->fifo_size = fifo_size;
4166 }
4167
4168 /* for non control endpoints, set PID to D0 */
4169 if (index && !hs_ep->isochronous)
4170 epctrl |= DXEPCTL_SETD0PID;
4171
4172 /* WA for Full speed ISOC IN in DDMA mode.
4173 * By Clear NAK status of EP, core will send ZLP
4174 * to IN token and assert NAK interrupt relying
4175 * on TxFIFO status only
4176 */
4177
4178 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4179 hs_ep->isochronous && dir_in) {
4180 /* The WA applies only to core versions from 2.72a
4181 * to 4.00a (including both). Also for FS_IOT_1.00a
4182 * and HS_IOT_1.00a.
4183 */
4184 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4185
4186 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4187 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4188 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4189 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4190 epctrl |= DXEPCTL_CNAK;
4191 }
4192
4193 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4194 __func__, epctrl);
4195
4196 dwc2_writel(hsotg, epctrl, epctrl_reg);
4197 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4198 __func__, dwc2_readl(hsotg, epctrl_reg));
4199
4200 /* enable the endpoint interrupt */
4201 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4202
4203error1:
4204 spin_unlock_irqrestore(&hsotg->lock, flags);
4205
4206error2:
4207 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4208 dmam_free_coherent(hsotg->dev, desc_num *
4209 sizeof(struct dwc2_dma_desc),
4210 hs_ep->desc_list, hs_ep->desc_list_dma);
4211 hs_ep->desc_list = NULL;
4212 }
4213
4214 return ret;
4215}
4216
4217/**
4218 * dwc2_hsotg_ep_disable - disable given endpoint
4219 * @ep: The endpoint to disable.
4220 */
4221static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4222{
4223 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4224 struct dwc2_hsotg *hsotg = hs_ep->parent;
4225 int dir_in = hs_ep->dir_in;
4226 int index = hs_ep->index;
4227 u32 epctrl_reg;
4228 u32 ctrl;
4229
4230 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4231
4232 if (ep == &hsotg->eps_out[0]->ep) {
4233 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4234 return -EINVAL;
4235 }
4236
4237 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4238 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4239 return -EINVAL;
4240 }
4241
4242 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4243
4244 ctrl = dwc2_readl(hsotg, epctrl_reg);
4245
4246 if (ctrl & DXEPCTL_EPENA)
4247 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4248
4249 ctrl &= ~DXEPCTL_EPENA;
4250 ctrl &= ~DXEPCTL_USBACTEP;
4251 ctrl |= DXEPCTL_SNAK;
4252
4253 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4254 dwc2_writel(hsotg, ctrl, epctrl_reg);
4255
4256 /* disable endpoint interrupts */
4257 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4258
4259 /* terminate all requests with shutdown */
4260 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4261
4262 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4263 hs_ep->fifo_index = 0;
4264 hs_ep->fifo_size = 0;
4265
4266 return 0;
4267}
4268
4269static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4270{
4271 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4272 struct dwc2_hsotg *hsotg = hs_ep->parent;
4273 unsigned long flags;
4274 int ret;
4275
4276 spin_lock_irqsave(&hsotg->lock, flags);
4277 ret = dwc2_hsotg_ep_disable(ep);
4278 spin_unlock_irqrestore(&hsotg->lock, flags);
4279 return ret;
4280}
4281
4282/**
4283 * on_list - check request is on the given endpoint
4284 * @ep: The endpoint to check.
4285 * @test: The request to test if it is on the endpoint.
4286 */
4287static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4288{
4289 struct dwc2_hsotg_req *req, *treq;
4290
4291 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4292 if (req == test)
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
4299/**
4300 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4301 * @ep: The endpoint to dequeue.
4302 * @req: The request to be removed from a queue.
4303 */
4304static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4305{
4306 struct dwc2_hsotg_req *hs_req = our_req(req);
4307 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4308 struct dwc2_hsotg *hs = hs_ep->parent;
4309 unsigned long flags;
4310
4311 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4312
4313 spin_lock_irqsave(&hs->lock, flags);
4314
4315 if (!on_list(hs_ep, hs_req)) {
4316 spin_unlock_irqrestore(&hs->lock, flags);
4317 return -EINVAL;
4318 }
4319
4320 /* Dequeue already started request */
4321 if (req == &hs_ep->req->req)
4322 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4323
4324 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4325 spin_unlock_irqrestore(&hs->lock, flags);
4326
4327 return 0;
4328}
4329
4330/**
4331 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4332 * @ep: The endpoint to set halt.
4333 * @value: Set or unset the halt.
4334 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4335 * the endpoint is busy processing requests.
4336 *
4337 * We need to stall the endpoint immediately if request comes from set_feature
4338 * protocol command handler.
4339 */
4340static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4341{
4342 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4343 struct dwc2_hsotg *hs = hs_ep->parent;
4344 int index = hs_ep->index;
4345 u32 epreg;
4346 u32 epctl;
4347 u32 xfertype;
4348
4349 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4350
4351 if (index == 0) {
4352 if (value)
4353 dwc2_hsotg_stall_ep0(hs);
4354 else
4355 dev_warn(hs->dev,
4356 "%s: can't clear halt on ep0\n", __func__);
4357 return 0;
4358 }
4359
4360 if (hs_ep->isochronous) {
4361 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4362 return -EINVAL;
4363 }
4364
4365 if (!now && value && !list_empty(&hs_ep->queue)) {
4366 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4367 ep->name);
4368 return -EAGAIN;
4369 }
4370
4371 if (hs_ep->dir_in) {
4372 epreg = DIEPCTL(index);
4373 epctl = dwc2_readl(hs, epreg);
4374
4375 if (value) {
4376 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4377 if (epctl & DXEPCTL_EPENA)
4378 epctl |= DXEPCTL_EPDIS;
4379 } else {
4380 epctl &= ~DXEPCTL_STALL;
4381 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4382 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4383 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4384 epctl |= DXEPCTL_SETD0PID;
4385 }
4386 dwc2_writel(hs, epctl, epreg);
4387 } else {
4388 epreg = DOEPCTL(index);
4389 epctl = dwc2_readl(hs, epreg);
4390
4391 if (value) {
4392 /* Unmask GOUTNAKEFF interrupt */
4393 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4394
4395 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4396 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4397 // STALL bit will be set in GOUTNAKEFF interrupt handler
4398 } else {
4399 epctl &= ~DXEPCTL_STALL;
4400 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4401 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4402 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4403 epctl |= DXEPCTL_SETD0PID;
4404 dwc2_writel(hs, epctl, epreg);
4405 }
4406 }
4407
4408 hs_ep->halted = value;
4409 return 0;
4410}
4411
4412/**
4413 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4414 * @ep: The endpoint to set halt.
4415 * @value: Set or unset the halt.
4416 */
4417static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4418{
4419 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4420 struct dwc2_hsotg *hs = hs_ep->parent;
4421 unsigned long flags;
4422 int ret;
4423
4424 spin_lock_irqsave(&hs->lock, flags);
4425 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4426 spin_unlock_irqrestore(&hs->lock, flags);
4427
4428 return ret;
4429}
4430
4431static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4432 .enable = dwc2_hsotg_ep_enable,
4433 .disable = dwc2_hsotg_ep_disable_lock,
4434 .alloc_request = dwc2_hsotg_ep_alloc_request,
4435 .free_request = dwc2_hsotg_ep_free_request,
4436 .queue = dwc2_hsotg_ep_queue_lock,
4437 .dequeue = dwc2_hsotg_ep_dequeue,
4438 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4439 /* note, don't believe we have any call for the fifo routines */
4440};
4441
4442/**
4443 * dwc2_hsotg_init - initialize the usb core
4444 * @hsotg: The driver state
4445 */
4446static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4447{
4448 /* unmask subset of endpoint interrupts */
4449
4450 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4451 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4452 DIEPMSK);
4453
4454 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4455 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4456 DOEPMSK);
4457
4458 dwc2_writel(hsotg, 0, DAINTMSK);
4459
4460 /* Be in disconnected state until gadget is registered */
4461 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4462
4463 /* setup fifos */
4464
4465 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4466 dwc2_readl(hsotg, GRXFSIZ),
4467 dwc2_readl(hsotg, GNPTXFSIZ));
4468
4469 dwc2_hsotg_init_fifo(hsotg);
4470
4471 if (using_dma(hsotg))
4472 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4473}
4474
4475/**
4476 * dwc2_hsotg_udc_start - prepare the udc for work
4477 * @gadget: The usb gadget state
4478 * @driver: The usb gadget driver
4479 *
4480 * Perform initialization to prepare udc device and driver
4481 * to work.
4482 */
4483static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4484 struct usb_gadget_driver *driver)
4485{
4486 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4487 unsigned long flags;
4488 int ret;
4489
4490 if (!hsotg) {
4491 pr_err("%s: called with no device\n", __func__);
4492 return -ENODEV;
4493 }
4494
4495 if (!driver) {
4496 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4497 return -EINVAL;
4498 }
4499
4500 if (driver->max_speed < USB_SPEED_FULL)
4501 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4502
4503 if (!driver->setup) {
4504 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4505 return -EINVAL;
4506 }
4507
4508 WARN_ON(hsotg->driver);
4509
4510 driver->driver.bus = NULL;
4511 hsotg->driver = driver;
4512 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4513 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4514
4515 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4516 ret = dwc2_lowlevel_hw_enable(hsotg);
4517 if (ret)
4518 goto err;
4519 }
4520
4521 if (!IS_ERR_OR_NULL(hsotg->uphy))
4522 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4523
4524 spin_lock_irqsave(&hsotg->lock, flags);
4525 if (dwc2_hw_is_device(hsotg)) {
4526 dwc2_hsotg_init(hsotg);
4527 dwc2_hsotg_core_init_disconnected(hsotg, false);
4528 }
4529
4530 hsotg->enabled = 0;
4531 spin_unlock_irqrestore(&hsotg->lock, flags);
4532
4533 gadget->sg_supported = using_desc_dma(hsotg);
4534 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4535
4536 return 0;
4537
4538err:
4539 hsotg->driver = NULL;
4540 return ret;
4541}
4542
4543/**
4544 * dwc2_hsotg_udc_stop - stop the udc
4545 * @gadget: The usb gadget state
4546 *
4547 * Stop udc hw block and stay tunned for future transmissions
4548 */
4549static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4550{
4551 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4552 unsigned long flags;
4553 int ep;
4554
4555 if (!hsotg)
4556 return -ENODEV;
4557
4558 /* all endpoints should be shutdown */
4559 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4560 if (hsotg->eps_in[ep])
4561 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4562 if (hsotg->eps_out[ep])
4563 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4564 }
4565
4566 spin_lock_irqsave(&hsotg->lock, flags);
4567
4568 hsotg->driver = NULL;
4569 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4570 hsotg->enabled = 0;
4571
4572 spin_unlock_irqrestore(&hsotg->lock, flags);
4573
4574 if (!IS_ERR_OR_NULL(hsotg->uphy))
4575 otg_set_peripheral(hsotg->uphy->otg, NULL);
4576
4577 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4578 dwc2_lowlevel_hw_disable(hsotg);
4579
4580 return 0;
4581}
4582
4583/**
4584 * dwc2_hsotg_gadget_getframe - read the frame number
4585 * @gadget: The usb gadget state
4586 *
4587 * Read the {micro} frame number
4588 */
4589static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4590{
4591 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4592}
4593
4594/**
4595 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4596 * @gadget: The usb gadget state
4597 * @is_selfpowered: Whether the device is self-powered
4598 *
4599 * Set if the device is self or bus powered.
4600 */
4601static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4602 int is_selfpowered)
4603{
4604 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4605 unsigned long flags;
4606
4607 spin_lock_irqsave(&hsotg->lock, flags);
4608 gadget->is_selfpowered = !!is_selfpowered;
4609 spin_unlock_irqrestore(&hsotg->lock, flags);
4610
4611 return 0;
4612}
4613
4614/**
4615 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4616 * @gadget: The usb gadget state
4617 * @is_on: Current state of the USB PHY
4618 *
4619 * Connect/Disconnect the USB PHY pullup
4620 */
4621static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4622{
4623 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4624 unsigned long flags;
4625
4626 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4627 hsotg->op_state);
4628
4629 /* Don't modify pullup state while in host mode */
4630 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4631 hsotg->enabled = is_on;
4632 return 0;
4633 }
4634
4635 spin_lock_irqsave(&hsotg->lock, flags);
4636 if (is_on) {
4637 hsotg->enabled = 1;
4638 dwc2_hsotg_core_init_disconnected(hsotg, false);
4639 /* Enable ACG feature in device mode,if supported */
4640 dwc2_enable_acg(hsotg);
4641 dwc2_hsotg_core_connect(hsotg);
4642 } else {
4643 dwc2_hsotg_core_disconnect(hsotg);
4644 dwc2_hsotg_disconnect(hsotg);
4645 hsotg->enabled = 0;
4646 }
4647
4648 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4649 spin_unlock_irqrestore(&hsotg->lock, flags);
4650
4651 return 0;
4652}
4653
4654static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4655{
4656 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4657 unsigned long flags;
4658
4659 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4660 spin_lock_irqsave(&hsotg->lock, flags);
4661
4662 /*
4663 * If controller is in partial power down state, it must exit from
4664 * that state before being initialized / de-initialized
4665 */
4666 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4667 /*
4668 * No need to check the return value as
4669 * registers are not being restored.
4670 */
4671 dwc2_exit_partial_power_down(hsotg, 0, false);
4672
4673 if (is_active) {
4674 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4675
4676 dwc2_hsotg_core_init_disconnected(hsotg, false);
4677 if (hsotg->enabled) {
4678 /* Enable ACG feature in device mode,if supported */
4679 dwc2_enable_acg(hsotg);
4680 dwc2_hsotg_core_connect(hsotg);
4681 }
4682 } else {
4683 dwc2_hsotg_core_disconnect(hsotg);
4684 dwc2_hsotg_disconnect(hsotg);
4685 }
4686
4687 spin_unlock_irqrestore(&hsotg->lock, flags);
4688 return 0;
4689}
4690
4691/**
4692 * dwc2_hsotg_vbus_draw - report bMaxPower field
4693 * @gadget: The usb gadget state
4694 * @mA: Amount of current
4695 *
4696 * Report how much power the device may consume to the phy.
4697 */
4698static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4699{
4700 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4701
4702 if (IS_ERR_OR_NULL(hsotg->uphy))
4703 return -ENOTSUPP;
4704 return usb_phy_set_power(hsotg->uphy, mA);
4705}
4706
4707static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4708 .get_frame = dwc2_hsotg_gadget_getframe,
4709 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4710 .udc_start = dwc2_hsotg_udc_start,
4711 .udc_stop = dwc2_hsotg_udc_stop,
4712 .pullup = dwc2_hsotg_pullup,
4713 .vbus_session = dwc2_hsotg_vbus_session,
4714 .vbus_draw = dwc2_hsotg_vbus_draw,
4715};
4716
4717/**
4718 * dwc2_hsotg_initep - initialise a single endpoint
4719 * @hsotg: The device state.
4720 * @hs_ep: The endpoint to be initialised.
4721 * @epnum: The endpoint number
4722 * @dir_in: True if direction is in.
4723 *
4724 * Initialise the given endpoint (as part of the probe and device state
4725 * creation) to give to the gadget driver. Setup the endpoint name, any
4726 * direction information and other state that may be required.
4727 */
4728static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4729 struct dwc2_hsotg_ep *hs_ep,
4730 int epnum,
4731 bool dir_in)
4732{
4733 char *dir;
4734
4735 if (epnum == 0)
4736 dir = "";
4737 else if (dir_in)
4738 dir = "in";
4739 else
4740 dir = "out";
4741
4742 hs_ep->dir_in = dir_in;
4743 hs_ep->index = epnum;
4744
4745 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4746
4747 INIT_LIST_HEAD(&hs_ep->queue);
4748 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4749
4750 /* add to the list of endpoints known by the gadget driver */
4751 if (epnum)
4752 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4753
4754 hs_ep->parent = hsotg;
4755 hs_ep->ep.name = hs_ep->name;
4756
4757 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4758 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4759 else
4760 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4761 epnum ? 1024 : EP0_MPS_LIMIT);
4762 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4763
4764 if (epnum == 0) {
4765 hs_ep->ep.caps.type_control = true;
4766 } else {
4767 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4768 hs_ep->ep.caps.type_iso = true;
4769 hs_ep->ep.caps.type_bulk = true;
4770 }
4771 hs_ep->ep.caps.type_int = true;
4772 }
4773
4774 if (dir_in)
4775 hs_ep->ep.caps.dir_in = true;
4776 else
4777 hs_ep->ep.caps.dir_out = true;
4778
4779 /*
4780 * if we're using dma, we need to set the next-endpoint pointer
4781 * to be something valid.
4782 */
4783
4784 if (using_dma(hsotg)) {
4785 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4786
4787 if (dir_in)
4788 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4789 else
4790 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4791 }
4792}
4793
4794/**
4795 * dwc2_hsotg_hw_cfg - read HW configuration registers
4796 * @hsotg: Programming view of the DWC_otg controller
4797 *
4798 * Read the USB core HW configuration registers
4799 */
4800static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4801{
4802 u32 cfg;
4803 u32 ep_type;
4804 u32 i;
4805
4806 /* check hardware configuration */
4807
4808 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4809
4810 /* Add ep0 */
4811 hsotg->num_of_eps++;
4812
4813 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4814 sizeof(struct dwc2_hsotg_ep),
4815 GFP_KERNEL);
4816 if (!hsotg->eps_in[0])
4817 return -ENOMEM;
4818 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4819 hsotg->eps_out[0] = hsotg->eps_in[0];
4820
4821 cfg = hsotg->hw_params.dev_ep_dirs;
4822 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4823 ep_type = cfg & 3;
4824 /* Direction in or both */
4825 if (!(ep_type & 2)) {
4826 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4827 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4828 if (!hsotg->eps_in[i])
4829 return -ENOMEM;
4830 }
4831 /* Direction out or both */
4832 if (!(ep_type & 1)) {
4833 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4834 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4835 if (!hsotg->eps_out[i])
4836 return -ENOMEM;
4837 }
4838 }
4839
4840 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4841 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4842
4843 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4844 hsotg->num_of_eps,
4845 hsotg->dedicated_fifos ? "dedicated" : "shared",
4846 hsotg->fifo_mem);
4847 return 0;
4848}
4849
4850/**
4851 * dwc2_hsotg_dump - dump state of the udc
4852 * @hsotg: Programming view of the DWC_otg controller
4853 *
4854 */
4855static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4856{
4857#ifdef DEBUG
4858 struct device *dev = hsotg->dev;
4859 u32 val;
4860 int idx;
4861
4862 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4863 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4864 dwc2_readl(hsotg, DIEPMSK));
4865
4866 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4867 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4868
4869 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4870 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4871
4872 /* show periodic fifo settings */
4873
4874 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4875 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4876 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4877 val >> FIFOSIZE_DEPTH_SHIFT,
4878 val & FIFOSIZE_STARTADDR_MASK);
4879 }
4880
4881 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4882 dev_info(dev,
4883 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4884 dwc2_readl(hsotg, DIEPCTL(idx)),
4885 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4886 dwc2_readl(hsotg, DIEPDMA(idx)));
4887
4888 val = dwc2_readl(hsotg, DOEPCTL(idx));
4889 dev_info(dev,
4890 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4891 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4892 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4893 dwc2_readl(hsotg, DOEPDMA(idx)));
4894 }
4895
4896 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4897 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4898#endif
4899}
4900
4901/**
4902 * dwc2_gadget_init - init function for gadget
4903 * @hsotg: Programming view of the DWC_otg controller
4904 *
4905 */
4906int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4907{
4908 struct device *dev = hsotg->dev;
4909 int epnum;
4910 int ret;
4911
4912 /* Dump fifo information */
4913 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4914 hsotg->params.g_np_tx_fifo_size);
4915 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4916
4917 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4918 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4919 hsotg->gadget.name = dev_name(dev);
4920 hsotg->remote_wakeup_allowed = 0;
4921
4922 if (hsotg->params.lpm)
4923 hsotg->gadget.lpm_capable = true;
4924
4925 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4926 hsotg->gadget.is_otg = 1;
4927 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4928 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4929
4930 ret = dwc2_hsotg_hw_cfg(hsotg);
4931 if (ret) {
4932 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4933 return ret;
4934 }
4935
4936 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4937 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4938 if (!hsotg->ctrl_buff)
4939 return -ENOMEM;
4940
4941 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4942 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4943 if (!hsotg->ep0_buff)
4944 return -ENOMEM;
4945
4946 if (using_desc_dma(hsotg)) {
4947 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4948 if (ret < 0)
4949 return ret;
4950 }
4951
4952 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4953 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4954 if (ret < 0) {
4955 dev_err(dev, "cannot claim IRQ for gadget\n");
4956 return ret;
4957 }
4958
4959 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4960
4961 if (hsotg->num_of_eps == 0) {
4962 dev_err(dev, "wrong number of EPs (zero)\n");
4963 return -EINVAL;
4964 }
4965
4966 /* setup endpoint information */
4967
4968 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4969 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4970
4971 /* allocate EP0 request */
4972
4973 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4974 GFP_KERNEL);
4975 if (!hsotg->ctrl_req) {
4976 dev_err(dev, "failed to allocate ctrl req\n");
4977 return -ENOMEM;
4978 }
4979
4980 /* initialise the endpoints now the core has been initialised */
4981 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4982 if (hsotg->eps_in[epnum])
4983 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4984 epnum, 1);
4985 if (hsotg->eps_out[epnum])
4986 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4987 epnum, 0);
4988 }
4989
4990 dwc2_hsotg_dump(hsotg);
4991
4992 return 0;
4993}
4994
4995/**
4996 * dwc2_hsotg_remove - remove function for hsotg driver
4997 * @hsotg: Programming view of the DWC_otg controller
4998 *
4999 */
5000int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5001{
5002 usb_del_gadget_udc(&hsotg->gadget);
5003 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5004
5005 return 0;
5006}
5007
5008int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5009{
5010 unsigned long flags;
5011
5012 if (hsotg->lx_state != DWC2_L0)
5013 return 0;
5014
5015 if (hsotg->driver) {
5016 int ep;
5017
5018 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5019 hsotg->driver->driver.name);
5020
5021 spin_lock_irqsave(&hsotg->lock, flags);
5022 if (hsotg->enabled)
5023 dwc2_hsotg_core_disconnect(hsotg);
5024 dwc2_hsotg_disconnect(hsotg);
5025 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5026 spin_unlock_irqrestore(&hsotg->lock, flags);
5027
5028 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
5029 if (hsotg->eps_in[ep])
5030 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5031 if (hsotg->eps_out[ep])
5032 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5033 }
5034 }
5035
5036 return 0;
5037}
5038
5039int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5040{
5041 unsigned long flags;
5042
5043 if (hsotg->lx_state == DWC2_L2)
5044 return 0;
5045
5046 if (hsotg->driver) {
5047 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5048 hsotg->driver->driver.name);
5049
5050 spin_lock_irqsave(&hsotg->lock, flags);
5051 dwc2_hsotg_core_init_disconnected(hsotg, false);
5052 if (hsotg->enabled) {
5053 /* Enable ACG feature in device mode,if supported */
5054 dwc2_enable_acg(hsotg);
5055 dwc2_hsotg_core_connect(hsotg);
5056 }
5057 spin_unlock_irqrestore(&hsotg->lock, flags);
5058 }
5059
5060 return 0;
5061}
5062
5063/**
5064 * dwc2_backup_device_registers() - Backup controller device registers.
5065 * When suspending usb bus, registers needs to be backuped
5066 * if controller power is disabled once suspended.
5067 *
5068 * @hsotg: Programming view of the DWC_otg controller
5069 */
5070int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5071{
5072 struct dwc2_dregs_backup *dr;
5073 int i;
5074
5075 dev_dbg(hsotg->dev, "%s\n", __func__);
5076
5077 /* Backup dev regs */
5078 dr = &hsotg->dr_backup;
5079
5080 dr->dcfg = dwc2_readl(hsotg, DCFG);
5081 dr->dctl = dwc2_readl(hsotg, DCTL);
5082 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5083 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5084 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5085
5086 for (i = 0; i < hsotg->num_of_eps; i++) {
5087 /* Backup IN EPs */
5088 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5089
5090 /* Ensure DATA PID is correctly configured */
5091 if (dr->diepctl[i] & DXEPCTL_DPID)
5092 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5093 else
5094 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5095
5096 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5097 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5098
5099 /* Backup OUT EPs */
5100 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5101
5102 /* Ensure DATA PID is correctly configured */
5103 if (dr->doepctl[i] & DXEPCTL_DPID)
5104 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5105 else
5106 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5107
5108 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5109 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5110 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5111 }
5112 dr->valid = true;
5113 return 0;
5114}
5115
5116/**
5117 * dwc2_restore_device_registers() - Restore controller device registers.
5118 * When resuming usb bus, device registers needs to be restored
5119 * if controller power were disabled.
5120 *
5121 * @hsotg: Programming view of the DWC_otg controller
5122 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5123 *
5124 * Return: 0 if successful, negative error code otherwise
5125 */
5126int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5127{
5128 struct dwc2_dregs_backup *dr;
5129 int i;
5130
5131 dev_dbg(hsotg->dev, "%s\n", __func__);
5132
5133 /* Restore dev regs */
5134 dr = &hsotg->dr_backup;
5135 if (!dr->valid) {
5136 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5137 __func__);
5138 return -EINVAL;
5139 }
5140 dr->valid = false;
5141
5142 if (!remote_wakeup)
5143 dwc2_writel(hsotg, dr->dctl, DCTL);
5144
5145 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5146 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5147 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5148
5149 for (i = 0; i < hsotg->num_of_eps; i++) {
5150 /* Restore IN EPs */
5151 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5152 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5153 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5154 /** WA for enabled EPx's IN in DDMA mode. On entering to
5155 * hibernation wrong value read and saved from DIEPDMAx,
5156 * as result BNA interrupt asserted on hibernation exit
5157 * by restoring from saved area.
5158 */
5159 if (hsotg->params.g_dma_desc &&
5160 (dr->diepctl[i] & DXEPCTL_EPENA))
5161 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5162 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5163 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5164 /* Restore OUT EPs */
5165 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5166 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5167 * hibernation wrong value read and saved from DOEPDMAx,
5168 * as result BNA interrupt asserted on hibernation exit
5169 * by restoring from saved area.
5170 */
5171 if (hsotg->params.g_dma_desc &&
5172 (dr->doepctl[i] & DXEPCTL_EPENA))
5173 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5174 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5175 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5176 }
5177
5178 return 0;
5179}
5180
5181/**
5182 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5183 *
5184 * @hsotg: Programming view of DWC_otg controller
5185 *
5186 */
5187void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5188{
5189 u32 val;
5190
5191 if (!hsotg->params.lpm)
5192 return;
5193
5194 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5195 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5196 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5197 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5198 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5199 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5200 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5201 dwc2_writel(hsotg, val, GLPMCFG);
5202 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5203
5204 /* Unmask WKUP_ALERT Interrupt */
5205 if (hsotg->params.service_interval)
5206 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5207}
5208
5209/**
5210 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5211 *
5212 * @hsotg: Programming view of DWC_otg controller
5213 *
5214 */
5215void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5216{
5217 u32 val = 0;
5218
5219 val |= GREFCLK_REF_CLK_MODE;
5220 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5221 val |= hsotg->params.sof_cnt_wkup_alert <<
5222 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5223
5224 dwc2_writel(hsotg, val, GREFCLK);
5225 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5226}
5227
5228/**
5229 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5230 *
5231 * @hsotg: Programming view of the DWC_otg controller
5232 *
5233 * Return non-zero if failed to enter to hibernation.
5234 */
5235int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5236{
5237 u32 gpwrdn;
5238 int ret = 0;
5239
5240 /* Change to L2(suspend) state */
5241 hsotg->lx_state = DWC2_L2;
5242 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5243 ret = dwc2_backup_global_registers(hsotg);
5244 if (ret) {
5245 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5246 __func__);
5247 return ret;
5248 }
5249 ret = dwc2_backup_device_registers(hsotg);
5250 if (ret) {
5251 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5252 __func__);
5253 return ret;
5254 }
5255
5256 gpwrdn = GPWRDN_PWRDNRSTN;
5257 gpwrdn |= GPWRDN_PMUACTV;
5258 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5259 udelay(10);
5260
5261 /* Set flag to indicate that we are in hibernation */
5262 hsotg->hibernated = 1;
5263
5264 /* Enable interrupts from wake up logic */
5265 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5266 gpwrdn |= GPWRDN_PMUINTSEL;
5267 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5268 udelay(10);
5269
5270 /* Unmask device mode interrupts in GPWRDN */
5271 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5272 gpwrdn |= GPWRDN_RST_DET_MSK;
5273 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5274 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5275 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5276 udelay(10);
5277
5278 /* Enable Power Down Clamp */
5279 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5280 gpwrdn |= GPWRDN_PWRDNCLMP;
5281 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5282 udelay(10);
5283
5284 /* Switch off VDD */
5285 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5286 gpwrdn |= GPWRDN_PWRDNSWTCH;
5287 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5288 udelay(10);
5289
5290 /* Save gpwrdn register for further usage if stschng interrupt */
5291 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5292 dev_dbg(hsotg->dev, "Hibernation completed\n");
5293
5294 return ret;
5295}
5296
5297/**
5298 * dwc2_gadget_exit_hibernation()
5299 * This function is for exiting from Device mode hibernation by host initiated
5300 * resume/reset and device initiated remote-wakeup.
5301 *
5302 * @hsotg: Programming view of the DWC_otg controller
5303 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5304 * @reset: indicates whether resume is initiated by Reset.
5305 *
5306 * Return non-zero if failed to exit from hibernation.
5307 */
5308int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5309 int rem_wakeup, int reset)
5310{
5311 u32 pcgcctl;
5312 u32 gpwrdn;
5313 u32 dctl;
5314 int ret = 0;
5315 struct dwc2_gregs_backup *gr;
5316 struct dwc2_dregs_backup *dr;
5317
5318 gr = &hsotg->gr_backup;
5319 dr = &hsotg->dr_backup;
5320
5321 if (!hsotg->hibernated) {
5322 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5323 return 1;
5324 }
5325 dev_dbg(hsotg->dev,
5326 "%s: called with rem_wakeup = %d reset = %d\n",
5327 __func__, rem_wakeup, reset);
5328
5329 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5330
5331 if (!reset) {
5332 /* Clear all pending interupts */
5333 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5334 }
5335
5336 /* De-assert Restore */
5337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5338 gpwrdn &= ~GPWRDN_RESTORE;
5339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5340 udelay(10);
5341
5342 if (!rem_wakeup) {
5343 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5344 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5345 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5346 }
5347
5348 /* Restore GUSBCFG, DCFG and DCTL */
5349 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5350 dwc2_writel(hsotg, dr->dcfg, DCFG);
5351 dwc2_writel(hsotg, dr->dctl, DCTL);
5352
5353 /* On USB Reset, reset device address to zero */
5354 if (reset)
5355 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5356
5357 /* De-assert Wakeup Logic */
5358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5359 gpwrdn &= ~GPWRDN_PMUACTV;
5360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5361
5362 if (rem_wakeup) {
5363 udelay(10);
5364 /* Start Remote Wakeup Signaling */
5365 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5366 } else {
5367 udelay(50);
5368 /* Set Device programming done bit */
5369 dctl = dwc2_readl(hsotg, DCTL);
5370 dctl |= DCTL_PWRONPRGDONE;
5371 dwc2_writel(hsotg, dctl, DCTL);
5372 }
5373 /* Wait for interrupts which must be cleared */
5374 mdelay(2);
5375 /* Clear all pending interupts */
5376 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5377
5378 /* Restore global registers */
5379 ret = dwc2_restore_global_registers(hsotg);
5380 if (ret) {
5381 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5382 __func__);
5383 return ret;
5384 }
5385
5386 /* Restore device registers */
5387 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5388 if (ret) {
5389 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5390 __func__);
5391 return ret;
5392 }
5393
5394 if (rem_wakeup) {
5395 mdelay(10);
5396 dctl = dwc2_readl(hsotg, DCTL);
5397 dctl &= ~DCTL_RMTWKUPSIG;
5398 dwc2_writel(hsotg, dctl, DCTL);
5399 }
5400
5401 hsotg->hibernated = 0;
5402 hsotg->lx_state = DWC2_L0;
5403 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5404
5405 return ret;
5406}
5407
5408/**
5409 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5410 * power down.
5411 *
5412 * @hsotg: Programming view of the DWC_otg controller
5413 *
5414 * Return: non-zero if failed to enter device partial power down.
5415 *
5416 * This function is for entering device mode partial power down.
5417 */
5418int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5419{
5420 u32 pcgcctl;
5421 int ret = 0;
5422
5423 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5424
5425 /* Backup all registers */
5426 ret = dwc2_backup_global_registers(hsotg);
5427 if (ret) {
5428 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5429 __func__);
5430 return ret;
5431 }
5432
5433 ret = dwc2_backup_device_registers(hsotg);
5434 if (ret) {
5435 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5436 __func__);
5437 return ret;
5438 }
5439
5440 /*
5441 * Clear any pending interrupts since dwc2 will not be able to
5442 * clear them after entering partial_power_down.
5443 */
5444 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5445
5446 /* Put the controller in low power state */
5447 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5448
5449 pcgcctl |= PCGCTL_PWRCLMP;
5450 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5451 udelay(5);
5452
5453 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5454 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5455 udelay(5);
5456
5457 pcgcctl |= PCGCTL_STOPPCLK;
5458 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5459
5460 /* Set in_ppd flag to 1 as here core enters suspend. */
5461 hsotg->in_ppd = 1;
5462 hsotg->lx_state = DWC2_L2;
5463
5464 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5465
5466 return ret;
5467}
5468
5469/*
5470 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5471 * power down.
5472 *
5473 * @hsotg: Programming view of the DWC_otg controller
5474 * @restore: indicates whether need to restore the registers or not.
5475 *
5476 * Return: non-zero if failed to exit device partial power down.
5477 *
5478 * This function is for exiting from device mode partial power down.
5479 */
5480int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5481 bool restore)
5482{
5483 u32 pcgcctl;
5484 u32 dctl;
5485 struct dwc2_dregs_backup *dr;
5486 int ret = 0;
5487
5488 dr = &hsotg->dr_backup;
5489
5490 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5491
5492 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5493 pcgcctl &= ~PCGCTL_STOPPCLK;
5494 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5495
5496 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5497 pcgcctl &= ~PCGCTL_PWRCLMP;
5498 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5499
5500 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5501 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5502 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5503
5504 udelay(100);
5505 if (restore) {
5506 ret = dwc2_restore_global_registers(hsotg);
5507 if (ret) {
5508 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5509 __func__);
5510 return ret;
5511 }
5512 /* Restore DCFG */
5513 dwc2_writel(hsotg, dr->dcfg, DCFG);
5514
5515 ret = dwc2_restore_device_registers(hsotg, 0);
5516 if (ret) {
5517 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5518 __func__);
5519 return ret;
5520 }
5521 }
5522
5523 /* Set the Power-On Programming done bit */
5524 dctl = dwc2_readl(hsotg, DCTL);
5525 dctl |= DCTL_PWRONPRGDONE;
5526 dwc2_writel(hsotg, dctl, DCTL);
5527
5528 /* Set in_ppd flag to 0 as here core exits from suspend. */
5529 hsotg->in_ppd = 0;
5530 hsotg->lx_state = DWC2_L0;
5531
5532 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5533 return ret;
5534}
5535
5536/**
5537 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5538 *
5539 * @hsotg: Programming view of the DWC_otg controller
5540 *
5541 * Return: non-zero if failed to enter device partial power down.
5542 *
5543 * This function is for entering device mode clock gating.
5544 */
5545void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5546{
5547 u32 pcgctl;
5548
5549 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5550
5551 /* Set the Phy Clock bit as suspend is received. */
5552 pcgctl = dwc2_readl(hsotg, PCGCTL);
5553 pcgctl |= PCGCTL_STOPPCLK;
5554 dwc2_writel(hsotg, pcgctl, PCGCTL);
5555 udelay(5);
5556
5557 /* Set the Gate hclk as suspend is received. */
5558 pcgctl = dwc2_readl(hsotg, PCGCTL);
5559 pcgctl |= PCGCTL_GATEHCLK;
5560 dwc2_writel(hsotg, pcgctl, PCGCTL);
5561 udelay(5);
5562
5563 hsotg->lx_state = DWC2_L2;
5564 hsotg->bus_suspended = true;
5565}
5566
5567/*
5568 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5569 *
5570 * @hsotg: Programming view of the DWC_otg controller
5571 * @rem_wakeup: indicates whether remote wake up is enabled.
5572 *
5573 * This function is for exiting from device mode clock gating.
5574 */
5575void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5576{
5577 u32 pcgctl;
5578 u32 dctl;
5579
5580 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5581
5582 /* Clear the Gate hclk. */
5583 pcgctl = dwc2_readl(hsotg, PCGCTL);
5584 pcgctl &= ~PCGCTL_GATEHCLK;
5585 dwc2_writel(hsotg, pcgctl, PCGCTL);
5586 udelay(5);
5587
5588 /* Phy Clock bit. */
5589 pcgctl = dwc2_readl(hsotg, PCGCTL);
5590 pcgctl &= ~PCGCTL_STOPPCLK;
5591 dwc2_writel(hsotg, pcgctl, PCGCTL);
5592 udelay(5);
5593
5594 if (rem_wakeup) {
5595 /* Set Remote Wakeup Signaling */
5596 dctl = dwc2_readl(hsotg, DCTL);
5597 dctl |= DCTL_RMTWKUPSIG;
5598 dwc2_writel(hsotg, dctl, DCTL);
5599 }
5600
5601 /* Change to L0 state */
5602 call_gadget(hsotg, resume);
5603 hsotg->lx_state = DWC2_L0;
5604 hsotg->bus_suspended = false;
5605}