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1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4/*
5 * iProc SDHCI platform driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/delay.h>
10#include <linux/module.h>
11#include <linux/mmc/host.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include "sdhci-pltfm.h"
15
16struct sdhci_iproc_data {
17 const struct sdhci_pltfm_data *pdata;
18 u32 caps;
19 u32 caps1;
20 u32 mmc_caps;
21};
22
23struct sdhci_iproc_host {
24 const struct sdhci_iproc_data *data;
25 u32 shadow_cmd;
26 u32 shadow_blk;
27 bool is_cmd_shadowed;
28 bool is_blk_shadowed;
29};
30
31#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
32
33static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
34{
35 u32 val = readl(host->ioaddr + reg);
36
37 pr_debug("%s: readl [0x%02x] 0x%08x\n",
38 mmc_hostname(host->mmc), reg, val);
39 return val;
40}
41
42static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
43{
44 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
45 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
46 u32 val;
47 u16 word;
48
49 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
50 /* Get the saved transfer mode */
51 val = iproc_host->shadow_cmd;
52 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
53 iproc_host->is_blk_shadowed) {
54 /* Get the saved block info */
55 val = iproc_host->shadow_blk;
56 } else {
57 val = sdhci_iproc_readl(host, (reg & ~3));
58 }
59 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
60 return word;
61}
62
63static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
64{
65 u32 val = sdhci_iproc_readl(host, (reg & ~3));
66 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
67 return byte;
68}
69
70static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
71{
72 pr_debug("%s: writel [0x%02x] 0x%08x\n",
73 mmc_hostname(host->mmc), reg, val);
74
75 writel(val, host->ioaddr + reg);
76
77 if (host->clock <= 400000) {
78 /* Round up to micro-second four SD clock delay */
79 if (host->clock)
80 udelay((4 * 1000000 + host->clock - 1) / host->clock);
81 else
82 udelay(10);
83 }
84}
85
86/*
87 * The Arasan has a bugette whereby it may lose the content of successive
88 * writes to the same register that are within two SD-card clock cycles of
89 * each other (a clock domain crossing problem). The data
90 * register does not have this problem, which is just as well - otherwise we'd
91 * have to nobble the DMA engine too.
92 *
93 * This wouldn't be a problem with the code except that we can only write the
94 * controller with 32-bit writes. So two different 16-bit registers are
95 * written back to back creates the problem.
96 *
97 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
98 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
99 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
100 * the work around can be further optimized. We can keep shadow values of
101 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
102 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
103 * by the TRANSFER+COMMAND in another 32-bit write.
104 */
105static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
106{
107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
108 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
109 u32 word_shift = REG_OFFSET_IN_BITS(reg);
110 u32 mask = 0xffff << word_shift;
111 u32 oldval, newval;
112
113 if (reg == SDHCI_COMMAND) {
114 /* Write the block now as we are issuing a command */
115 if (iproc_host->is_blk_shadowed) {
116 sdhci_iproc_writel(host, iproc_host->shadow_blk,
117 SDHCI_BLOCK_SIZE);
118 iproc_host->is_blk_shadowed = false;
119 }
120 oldval = iproc_host->shadow_cmd;
121 iproc_host->is_cmd_shadowed = false;
122 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
123 iproc_host->is_blk_shadowed) {
124 /* Block size and count are stored in shadow reg */
125 oldval = iproc_host->shadow_blk;
126 } else {
127 /* Read reg, all other registers are not shadowed */
128 oldval = sdhci_iproc_readl(host, (reg & ~3));
129 }
130 newval = (oldval & ~mask) | (val << word_shift);
131
132 if (reg == SDHCI_TRANSFER_MODE) {
133 /* Save the transfer mode until the command is issued */
134 iproc_host->shadow_cmd = newval;
135 iproc_host->is_cmd_shadowed = true;
136 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
137 /* Save the block info until the command is issued */
138 iproc_host->shadow_blk = newval;
139 iproc_host->is_blk_shadowed = true;
140 } else {
141 /* Command or other regular 32-bit write */
142 sdhci_iproc_writel(host, newval, reg & ~3);
143 }
144}
145
146static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
147{
148 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
149 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
150 u32 mask = 0xff << byte_shift;
151 u32 newval = (oldval & ~mask) | (val << byte_shift);
152
153 sdhci_iproc_writel(host, newval, reg & ~3);
154}
155
156static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
157{
158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
159
160 if (pltfm_host->clk)
161 return sdhci_pltfm_clk_get_max_clock(host);
162 else
163 return pltfm_host->clock;
164}
165
166/*
167 * There is a known bug on BCM2711's SDHCI core integration where the
168 * controller will hang when the difference between the core clock and the bus
169 * clock is too great. Specifically this can be reproduced under the following
170 * conditions:
171 *
172 * - No SD card plugged in, polling thread is running, probing cards at
173 * 100 kHz.
174 * - BCM2711's core clock configured at 500MHz or more
175 *
176 * So we set 200kHz as the minimum clock frequency available for that SoC.
177 */
178static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
179{
180 return 200000;
181}
182
183static const struct sdhci_ops sdhci_iproc_ops = {
184 .set_clock = sdhci_set_clock,
185 .get_max_clock = sdhci_iproc_get_max_clock,
186 .set_bus_width = sdhci_set_bus_width,
187 .reset = sdhci_reset,
188 .set_uhs_signaling = sdhci_set_uhs_signaling,
189};
190
191static const struct sdhci_ops sdhci_iproc_32only_ops = {
192 .read_l = sdhci_iproc_readl,
193 .read_w = sdhci_iproc_readw,
194 .read_b = sdhci_iproc_readb,
195 .write_l = sdhci_iproc_writel,
196 .write_w = sdhci_iproc_writew,
197 .write_b = sdhci_iproc_writeb,
198 .set_clock = sdhci_set_clock,
199 .get_max_clock = sdhci_iproc_get_max_clock,
200 .set_bus_width = sdhci_set_bus_width,
201 .reset = sdhci_reset,
202 .set_uhs_signaling = sdhci_set_uhs_signaling,
203};
204
205static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
206 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
207 SDHCI_QUIRK_NO_HISPD_BIT,
208 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
209 .ops = &sdhci_iproc_32only_ops,
210};
211
212static const struct sdhci_iproc_data iproc_cygnus_data = {
213 .pdata = &sdhci_iproc_cygnus_pltfm_data,
214 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
215 & SDHCI_MAX_BLOCK_MASK) |
216 SDHCI_CAN_VDD_330 |
217 SDHCI_CAN_VDD_180 |
218 SDHCI_CAN_DO_SUSPEND |
219 SDHCI_CAN_DO_HISPD |
220 SDHCI_CAN_DO_ADMA2 |
221 SDHCI_CAN_DO_SDMA,
222 .caps1 = SDHCI_DRIVER_TYPE_C |
223 SDHCI_DRIVER_TYPE_D |
224 SDHCI_SUPPORT_DDR50,
225 .mmc_caps = MMC_CAP_1_8V_DDR,
226};
227
228static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
229 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
230 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
231 SDHCI_QUIRK_NO_HISPD_BIT,
232 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
233 .ops = &sdhci_iproc_ops,
234};
235
236static const struct sdhci_iproc_data iproc_data = {
237 .pdata = &sdhci_iproc_pltfm_data,
238 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
239 & SDHCI_MAX_BLOCK_MASK) |
240 SDHCI_CAN_VDD_330 |
241 SDHCI_CAN_VDD_180 |
242 SDHCI_CAN_DO_SUSPEND |
243 SDHCI_CAN_DO_HISPD |
244 SDHCI_CAN_DO_ADMA2 |
245 SDHCI_CAN_DO_SDMA,
246 .caps1 = SDHCI_DRIVER_TYPE_C |
247 SDHCI_DRIVER_TYPE_D |
248 SDHCI_SUPPORT_DDR50,
249};
250
251static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
252 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
253 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
254 SDHCI_QUIRK_MISSING_CAPS |
255 SDHCI_QUIRK_NO_HISPD_BIT,
256 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
257 .ops = &sdhci_iproc_32only_ops,
258};
259
260static const struct sdhci_iproc_data bcm2835_data = {
261 .pdata = &sdhci_bcm2835_pltfm_data,
262 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
263 & SDHCI_MAX_BLOCK_MASK) |
264 SDHCI_CAN_VDD_330 |
265 SDHCI_CAN_DO_HISPD,
266 .caps1 = SDHCI_DRIVER_TYPE_A |
267 SDHCI_DRIVER_TYPE_C,
268 .mmc_caps = 0x00000000,
269};
270
271static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
272 .read_l = sdhci_iproc_readl,
273 .read_w = sdhci_iproc_readw,
274 .read_b = sdhci_iproc_readb,
275 .write_l = sdhci_iproc_writel,
276 .write_w = sdhci_iproc_writew,
277 .write_b = sdhci_iproc_writeb,
278 .set_clock = sdhci_set_clock,
279 .set_power = sdhci_set_power_and_bus_voltage,
280 .get_max_clock = sdhci_iproc_get_max_clock,
281 .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
282 .set_bus_width = sdhci_set_bus_width,
283 .reset = sdhci_reset,
284 .set_uhs_signaling = sdhci_set_uhs_signaling,
285};
286
287static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
288 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
289 .ops = &sdhci_iproc_bcm2711_ops,
290};
291
292static const struct sdhci_iproc_data bcm2711_data = {
293 .pdata = &sdhci_bcm2711_pltfm_data,
294 .mmc_caps = MMC_CAP_3_3V_DDR,
295};
296
297static const struct sdhci_pltfm_data sdhci_bcm7211a0_pltfm_data = {
298 .quirks = SDHCI_QUIRK_MISSING_CAPS |
299 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
300 SDHCI_QUIRK_BROKEN_DMA |
301 SDHCI_QUIRK_BROKEN_ADMA,
302 .ops = &sdhci_iproc_ops,
303};
304
305#define BCM7211A0_BASE_CLK_MHZ 100
306static const struct sdhci_iproc_data bcm7211a0_data = {
307 .pdata = &sdhci_bcm7211a0_pltfm_data,
308 .caps = ((BCM7211A0_BASE_CLK_MHZ / 2) << SDHCI_TIMEOUT_CLK_SHIFT) |
309 (BCM7211A0_BASE_CLK_MHZ << SDHCI_CLOCK_BASE_SHIFT) |
310 ((0x2 << SDHCI_MAX_BLOCK_SHIFT)
311 & SDHCI_MAX_BLOCK_MASK) |
312 SDHCI_CAN_VDD_330 |
313 SDHCI_CAN_VDD_180 |
314 SDHCI_CAN_DO_SUSPEND |
315 SDHCI_CAN_DO_HISPD,
316 .caps1 = SDHCI_DRIVER_TYPE_C |
317 SDHCI_DRIVER_TYPE_D,
318};
319
320static const struct of_device_id sdhci_iproc_of_match[] = {
321 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
322 { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
323 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
324 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
325 { .compatible = "brcm,bcm7211a0-sdhci", .data = &bcm7211a0_data },
326 { }
327};
328MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
329
330#ifdef CONFIG_ACPI
331/*
332 * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
333 * which are provided by the ACPI table.
334 */
335static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
336 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
337 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
338 SDHCI_QUIRK_NO_HISPD_BIT,
339 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
340 .ops = &sdhci_iproc_32only_ops,
341};
342
343static const struct sdhci_iproc_data bcm_arasan_data = {
344 .pdata = &sdhci_bcm_arasan_data,
345};
346
347static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
348 { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
349 { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
350 { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
351 { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
352 { /* sentinel */ }
353};
354MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
355#endif
356
357static int sdhci_iproc_probe(struct platform_device *pdev)
358{
359 struct device *dev = &pdev->dev;
360 const struct sdhci_iproc_data *iproc_data = NULL;
361 struct sdhci_host *host;
362 struct sdhci_iproc_host *iproc_host;
363 struct sdhci_pltfm_host *pltfm_host;
364 int ret;
365
366 iproc_data = device_get_match_data(dev);
367 if (!iproc_data)
368 return -ENODEV;
369
370 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
371 if (IS_ERR(host))
372 return PTR_ERR(host);
373
374 pltfm_host = sdhci_priv(host);
375 iproc_host = sdhci_pltfm_priv(pltfm_host);
376
377 iproc_host->data = iproc_data;
378
379 ret = mmc_of_parse(host->mmc);
380 if (ret)
381 goto err;
382
383 sdhci_get_property(pdev);
384
385 host->mmc->caps |= iproc_host->data->mmc_caps;
386
387 if (dev->of_node) {
388 pltfm_host->clk = devm_clk_get(dev, NULL);
389 if (IS_ERR(pltfm_host->clk)) {
390 ret = PTR_ERR(pltfm_host->clk);
391 goto err;
392 }
393 ret = clk_prepare_enable(pltfm_host->clk);
394 if (ret) {
395 dev_err(dev, "failed to enable host clk\n");
396 goto err;
397 }
398 }
399
400 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
401 host->caps = iproc_host->data->caps;
402 host->caps1 = iproc_host->data->caps1;
403 }
404
405 ret = sdhci_add_host(host);
406 if (ret)
407 goto err_clk;
408
409 return 0;
410
411err_clk:
412 if (dev->of_node)
413 clk_disable_unprepare(pltfm_host->clk);
414err:
415 sdhci_pltfm_free(pdev);
416 return ret;
417}
418
419static void sdhci_iproc_shutdown(struct platform_device *pdev)
420{
421 sdhci_pltfm_suspend(&pdev->dev);
422}
423
424static struct platform_driver sdhci_iproc_driver = {
425 .driver = {
426 .name = "sdhci-iproc",
427 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
428 .of_match_table = sdhci_iproc_of_match,
429 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
430 .pm = &sdhci_pltfm_pmops,
431 },
432 .probe = sdhci_iproc_probe,
433 .remove = sdhci_pltfm_unregister,
434 .shutdown = sdhci_iproc_shutdown,
435};
436module_platform_driver(sdhci_iproc_driver);
437
438MODULE_AUTHOR("Broadcom");
439MODULE_DESCRIPTION("IPROC SDHCI driver");
440MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/*
15 * iProc SDHCI platform driver
16 */
17
18#include <linux/delay.h>
19#include <linux/module.h>
20#include <linux/mmc/host.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include "sdhci-pltfm.h"
24
25struct sdhci_iproc_data {
26 const struct sdhci_pltfm_data *pdata;
27 u32 caps;
28 u32 caps1;
29 u32 mmc_caps;
30};
31
32struct sdhci_iproc_host {
33 const struct sdhci_iproc_data *data;
34 u32 shadow_cmd;
35 u32 shadow_blk;
36 bool is_cmd_shadowed;
37 bool is_blk_shadowed;
38};
39
40#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
41
42static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
43{
44 u32 val = readl(host->ioaddr + reg);
45
46 pr_debug("%s: readl [0x%02x] 0x%08x\n",
47 mmc_hostname(host->mmc), reg, val);
48 return val;
49}
50
51static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
52{
53 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
54 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
55 u32 val;
56 u16 word;
57
58 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
59 /* Get the saved transfer mode */
60 val = iproc_host->shadow_cmd;
61 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
62 iproc_host->is_blk_shadowed) {
63 /* Get the saved block info */
64 val = iproc_host->shadow_blk;
65 } else {
66 val = sdhci_iproc_readl(host, (reg & ~3));
67 }
68 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
69 return word;
70}
71
72static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
73{
74 u32 val = sdhci_iproc_readl(host, (reg & ~3));
75 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
76 return byte;
77}
78
79static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
80{
81 pr_debug("%s: writel [0x%02x] 0x%08x\n",
82 mmc_hostname(host->mmc), reg, val);
83
84 writel(val, host->ioaddr + reg);
85
86 if (host->clock <= 400000) {
87 /* Round up to micro-second four SD clock delay */
88 if (host->clock)
89 udelay((4 * 1000000 + host->clock - 1) / host->clock);
90 else
91 udelay(10);
92 }
93}
94
95/*
96 * The Arasan has a bugette whereby it may lose the content of successive
97 * writes to the same register that are within two SD-card clock cycles of
98 * each other (a clock domain crossing problem). The data
99 * register does not have this problem, which is just as well - otherwise we'd
100 * have to nobble the DMA engine too.
101 *
102 * This wouldn't be a problem with the code except that we can only write the
103 * controller with 32-bit writes. So two different 16-bit registers are
104 * written back to back creates the problem.
105 *
106 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
107 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
108 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
109 * the work around can be further optimized. We can keep shadow values of
110 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
111 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
112 * by the TRANSFER+COMMAND in another 32-bit write.
113 */
114static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
115{
116 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
117 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
118 u32 word_shift = REG_OFFSET_IN_BITS(reg);
119 u32 mask = 0xffff << word_shift;
120 u32 oldval, newval;
121
122 if (reg == SDHCI_COMMAND) {
123 /* Write the block now as we are issuing a command */
124 if (iproc_host->is_blk_shadowed) {
125 sdhci_iproc_writel(host, iproc_host->shadow_blk,
126 SDHCI_BLOCK_SIZE);
127 iproc_host->is_blk_shadowed = false;
128 }
129 oldval = iproc_host->shadow_cmd;
130 iproc_host->is_cmd_shadowed = false;
131 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
132 iproc_host->is_blk_shadowed) {
133 /* Block size and count are stored in shadow reg */
134 oldval = iproc_host->shadow_blk;
135 } else {
136 /* Read reg, all other registers are not shadowed */
137 oldval = sdhci_iproc_readl(host, (reg & ~3));
138 }
139 newval = (oldval & ~mask) | (val << word_shift);
140
141 if (reg == SDHCI_TRANSFER_MODE) {
142 /* Save the transfer mode until the command is issued */
143 iproc_host->shadow_cmd = newval;
144 iproc_host->is_cmd_shadowed = true;
145 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
146 /* Save the block info until the command is issued */
147 iproc_host->shadow_blk = newval;
148 iproc_host->is_blk_shadowed = true;
149 } else {
150 /* Command or other regular 32-bit write */
151 sdhci_iproc_writel(host, newval, reg & ~3);
152 }
153}
154
155static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
156{
157 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
158 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
159 u32 mask = 0xff << byte_shift;
160 u32 newval = (oldval & ~mask) | (val << byte_shift);
161
162 sdhci_iproc_writel(host, newval, reg & ~3);
163}
164
165static const struct sdhci_ops sdhci_iproc_ops = {
166 .set_clock = sdhci_set_clock,
167 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
168 .set_bus_width = sdhci_set_bus_width,
169 .reset = sdhci_reset,
170 .set_uhs_signaling = sdhci_set_uhs_signaling,
171};
172
173static const struct sdhci_ops sdhci_iproc_32only_ops = {
174 .read_l = sdhci_iproc_readl,
175 .read_w = sdhci_iproc_readw,
176 .read_b = sdhci_iproc_readb,
177 .write_l = sdhci_iproc_writel,
178 .write_w = sdhci_iproc_writew,
179 .write_b = sdhci_iproc_writeb,
180 .set_clock = sdhci_set_clock,
181 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
182 .set_bus_width = sdhci_set_bus_width,
183 .reset = sdhci_reset,
184 .set_uhs_signaling = sdhci_set_uhs_signaling,
185};
186
187static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
188 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
189 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
190 .ops = &sdhci_iproc_32only_ops,
191};
192
193static const struct sdhci_iproc_data iproc_cygnus_data = {
194 .pdata = &sdhci_iproc_cygnus_pltfm_data,
195 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
196 & SDHCI_MAX_BLOCK_MASK) |
197 SDHCI_CAN_VDD_330 |
198 SDHCI_CAN_VDD_180 |
199 SDHCI_CAN_DO_SUSPEND |
200 SDHCI_CAN_DO_HISPD |
201 SDHCI_CAN_DO_ADMA2 |
202 SDHCI_CAN_DO_SDMA,
203 .caps1 = SDHCI_DRIVER_TYPE_C |
204 SDHCI_DRIVER_TYPE_D |
205 SDHCI_SUPPORT_DDR50,
206 .mmc_caps = MMC_CAP_1_8V_DDR,
207};
208
209static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
210 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
211 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
212 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
213 .ops = &sdhci_iproc_ops,
214};
215
216static const struct sdhci_iproc_data iproc_data = {
217 .pdata = &sdhci_iproc_pltfm_data,
218 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
219 & SDHCI_MAX_BLOCK_MASK) |
220 SDHCI_CAN_VDD_330 |
221 SDHCI_CAN_VDD_180 |
222 SDHCI_CAN_DO_SUSPEND |
223 SDHCI_CAN_DO_HISPD |
224 SDHCI_CAN_DO_ADMA2 |
225 SDHCI_CAN_DO_SDMA,
226 .caps1 = SDHCI_DRIVER_TYPE_C |
227 SDHCI_DRIVER_TYPE_D |
228 SDHCI_SUPPORT_DDR50,
229};
230
231static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
232 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
233 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
234 SDHCI_QUIRK_MISSING_CAPS |
235 SDHCI_QUIRK_NO_HISPD_BIT,
236 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
237 .ops = &sdhci_iproc_32only_ops,
238};
239
240static const struct sdhci_iproc_data bcm2835_data = {
241 .pdata = &sdhci_bcm2835_pltfm_data,
242 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
243 & SDHCI_MAX_BLOCK_MASK) |
244 SDHCI_CAN_VDD_330 |
245 SDHCI_CAN_DO_HISPD,
246 .caps1 = SDHCI_DRIVER_TYPE_A |
247 SDHCI_DRIVER_TYPE_C,
248 .mmc_caps = 0x00000000,
249};
250
251static const struct of_device_id sdhci_iproc_of_match[] = {
252 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
253 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
254 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
255 { }
256};
257MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
258
259static int sdhci_iproc_probe(struct platform_device *pdev)
260{
261 const struct of_device_id *match;
262 const struct sdhci_iproc_data *iproc_data;
263 struct sdhci_host *host;
264 struct sdhci_iproc_host *iproc_host;
265 struct sdhci_pltfm_host *pltfm_host;
266 int ret;
267
268 match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
269 if (!match)
270 return -EINVAL;
271 iproc_data = match->data;
272
273 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
274 if (IS_ERR(host))
275 return PTR_ERR(host);
276
277 pltfm_host = sdhci_priv(host);
278 iproc_host = sdhci_pltfm_priv(pltfm_host);
279
280 iproc_host->data = iproc_data;
281
282 mmc_of_parse(host->mmc);
283 sdhci_get_of_property(pdev);
284
285 host->mmc->caps |= iproc_host->data->mmc_caps;
286
287 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
288 if (IS_ERR(pltfm_host->clk)) {
289 ret = PTR_ERR(pltfm_host->clk);
290 goto err;
291 }
292 ret = clk_prepare_enable(pltfm_host->clk);
293 if (ret) {
294 dev_err(&pdev->dev, "failed to enable host clk\n");
295 goto err;
296 }
297
298 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
299 host->caps = iproc_host->data->caps;
300 host->caps1 = iproc_host->data->caps1;
301 }
302
303 ret = sdhci_add_host(host);
304 if (ret)
305 goto err_clk;
306
307 return 0;
308
309err_clk:
310 clk_disable_unprepare(pltfm_host->clk);
311err:
312 sdhci_pltfm_free(pdev);
313 return ret;
314}
315
316static struct platform_driver sdhci_iproc_driver = {
317 .driver = {
318 .name = "sdhci-iproc",
319 .of_match_table = sdhci_iproc_of_match,
320 .pm = &sdhci_pltfm_pmops,
321 },
322 .probe = sdhci_iproc_probe,
323 .remove = sdhci_pltfm_unregister,
324};
325module_platform_driver(sdhci_iproc_driver);
326
327MODULE_AUTHOR("Broadcom");
328MODULE_DESCRIPTION("IPROC SDHCI driver");
329MODULE_LICENSE("GPL v2");