Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4/*
5 * iProc SDHCI platform driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/delay.h>
10#include <linux/module.h>
11#include <linux/mmc/host.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include "sdhci-pltfm.h"
15
16struct sdhci_iproc_data {
17 const struct sdhci_pltfm_data *pdata;
18 u32 caps;
19 u32 caps1;
20 u32 mmc_caps;
21};
22
23struct sdhci_iproc_host {
24 const struct sdhci_iproc_data *data;
25 u32 shadow_cmd;
26 u32 shadow_blk;
27 bool is_cmd_shadowed;
28 bool is_blk_shadowed;
29};
30
31#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
32
33static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
34{
35 u32 val = readl(host->ioaddr + reg);
36
37 pr_debug("%s: readl [0x%02x] 0x%08x\n",
38 mmc_hostname(host->mmc), reg, val);
39 return val;
40}
41
42static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
43{
44 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
45 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
46 u32 val;
47 u16 word;
48
49 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
50 /* Get the saved transfer mode */
51 val = iproc_host->shadow_cmd;
52 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
53 iproc_host->is_blk_shadowed) {
54 /* Get the saved block info */
55 val = iproc_host->shadow_blk;
56 } else {
57 val = sdhci_iproc_readl(host, (reg & ~3));
58 }
59 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
60 return word;
61}
62
63static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
64{
65 u32 val = sdhci_iproc_readl(host, (reg & ~3));
66 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
67 return byte;
68}
69
70static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
71{
72 pr_debug("%s: writel [0x%02x] 0x%08x\n",
73 mmc_hostname(host->mmc), reg, val);
74
75 writel(val, host->ioaddr + reg);
76
77 if (host->clock <= 400000) {
78 /* Round up to micro-second four SD clock delay */
79 if (host->clock)
80 udelay((4 * 1000000 + host->clock - 1) / host->clock);
81 else
82 udelay(10);
83 }
84}
85
86/*
87 * The Arasan has a bugette whereby it may lose the content of successive
88 * writes to the same register that are within two SD-card clock cycles of
89 * each other (a clock domain crossing problem). The data
90 * register does not have this problem, which is just as well - otherwise we'd
91 * have to nobble the DMA engine too.
92 *
93 * This wouldn't be a problem with the code except that we can only write the
94 * controller with 32-bit writes. So two different 16-bit registers are
95 * written back to back creates the problem.
96 *
97 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
98 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
99 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
100 * the work around can be further optimized. We can keep shadow values of
101 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
102 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
103 * by the TRANSFER+COMMAND in another 32-bit write.
104 */
105static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
106{
107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
108 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
109 u32 word_shift = REG_OFFSET_IN_BITS(reg);
110 u32 mask = 0xffff << word_shift;
111 u32 oldval, newval;
112
113 if (reg == SDHCI_COMMAND) {
114 /* Write the block now as we are issuing a command */
115 if (iproc_host->is_blk_shadowed) {
116 sdhci_iproc_writel(host, iproc_host->shadow_blk,
117 SDHCI_BLOCK_SIZE);
118 iproc_host->is_blk_shadowed = false;
119 }
120 oldval = iproc_host->shadow_cmd;
121 iproc_host->is_cmd_shadowed = false;
122 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
123 iproc_host->is_blk_shadowed) {
124 /* Block size and count are stored in shadow reg */
125 oldval = iproc_host->shadow_blk;
126 } else {
127 /* Read reg, all other registers are not shadowed */
128 oldval = sdhci_iproc_readl(host, (reg & ~3));
129 }
130 newval = (oldval & ~mask) | (val << word_shift);
131
132 if (reg == SDHCI_TRANSFER_MODE) {
133 /* Save the transfer mode until the command is issued */
134 iproc_host->shadow_cmd = newval;
135 iproc_host->is_cmd_shadowed = true;
136 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
137 /* Save the block info until the command is issued */
138 iproc_host->shadow_blk = newval;
139 iproc_host->is_blk_shadowed = true;
140 } else {
141 /* Command or other regular 32-bit write */
142 sdhci_iproc_writel(host, newval, reg & ~3);
143 }
144}
145
146static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
147{
148 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
149 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
150 u32 mask = 0xff << byte_shift;
151 u32 newval = (oldval & ~mask) | (val << byte_shift);
152
153 sdhci_iproc_writel(host, newval, reg & ~3);
154}
155
156static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
157{
158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
159
160 if (pltfm_host->clk)
161 return sdhci_pltfm_clk_get_max_clock(host);
162 else
163 return pltfm_host->clock;
164}
165
166/*
167 * There is a known bug on BCM2711's SDHCI core integration where the
168 * controller will hang when the difference between the core clock and the bus
169 * clock is too great. Specifically this can be reproduced under the following
170 * conditions:
171 *
172 * - No SD card plugged in, polling thread is running, probing cards at
173 * 100 kHz.
174 * - BCM2711's core clock configured at 500MHz or more
175 *
176 * So we set 200kHz as the minimum clock frequency available for that SoC.
177 */
178static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
179{
180 return 200000;
181}
182
183static const struct sdhci_ops sdhci_iproc_ops = {
184 .set_clock = sdhci_set_clock,
185 .get_max_clock = sdhci_iproc_get_max_clock,
186 .set_bus_width = sdhci_set_bus_width,
187 .reset = sdhci_reset,
188 .set_uhs_signaling = sdhci_set_uhs_signaling,
189};
190
191static const struct sdhci_ops sdhci_iproc_32only_ops = {
192 .read_l = sdhci_iproc_readl,
193 .read_w = sdhci_iproc_readw,
194 .read_b = sdhci_iproc_readb,
195 .write_l = sdhci_iproc_writel,
196 .write_w = sdhci_iproc_writew,
197 .write_b = sdhci_iproc_writeb,
198 .set_clock = sdhci_set_clock,
199 .get_max_clock = sdhci_iproc_get_max_clock,
200 .set_bus_width = sdhci_set_bus_width,
201 .reset = sdhci_reset,
202 .set_uhs_signaling = sdhci_set_uhs_signaling,
203};
204
205static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
206 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
207 SDHCI_QUIRK_NO_HISPD_BIT,
208 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
209 .ops = &sdhci_iproc_32only_ops,
210};
211
212static const struct sdhci_iproc_data iproc_cygnus_data = {
213 .pdata = &sdhci_iproc_cygnus_pltfm_data,
214 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
215 & SDHCI_MAX_BLOCK_MASK) |
216 SDHCI_CAN_VDD_330 |
217 SDHCI_CAN_VDD_180 |
218 SDHCI_CAN_DO_SUSPEND |
219 SDHCI_CAN_DO_HISPD |
220 SDHCI_CAN_DO_ADMA2 |
221 SDHCI_CAN_DO_SDMA,
222 .caps1 = SDHCI_DRIVER_TYPE_C |
223 SDHCI_DRIVER_TYPE_D |
224 SDHCI_SUPPORT_DDR50,
225 .mmc_caps = MMC_CAP_1_8V_DDR,
226};
227
228static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
229 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
230 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
231 SDHCI_QUIRK_NO_HISPD_BIT,
232 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
233 .ops = &sdhci_iproc_ops,
234};
235
236static const struct sdhci_iproc_data iproc_data = {
237 .pdata = &sdhci_iproc_pltfm_data,
238 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
239 & SDHCI_MAX_BLOCK_MASK) |
240 SDHCI_CAN_VDD_330 |
241 SDHCI_CAN_VDD_180 |
242 SDHCI_CAN_DO_SUSPEND |
243 SDHCI_CAN_DO_HISPD |
244 SDHCI_CAN_DO_ADMA2 |
245 SDHCI_CAN_DO_SDMA,
246 .caps1 = SDHCI_DRIVER_TYPE_C |
247 SDHCI_DRIVER_TYPE_D |
248 SDHCI_SUPPORT_DDR50,
249};
250
251static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
252 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
253 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
254 SDHCI_QUIRK_MISSING_CAPS |
255 SDHCI_QUIRK_NO_HISPD_BIT,
256 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
257 .ops = &sdhci_iproc_32only_ops,
258};
259
260static const struct sdhci_iproc_data bcm2835_data = {
261 .pdata = &sdhci_bcm2835_pltfm_data,
262 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
263 & SDHCI_MAX_BLOCK_MASK) |
264 SDHCI_CAN_VDD_330 |
265 SDHCI_CAN_DO_HISPD,
266 .caps1 = SDHCI_DRIVER_TYPE_A |
267 SDHCI_DRIVER_TYPE_C,
268 .mmc_caps = 0x00000000,
269};
270
271static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
272 .read_l = sdhci_iproc_readl,
273 .read_w = sdhci_iproc_readw,
274 .read_b = sdhci_iproc_readb,
275 .write_l = sdhci_iproc_writel,
276 .write_w = sdhci_iproc_writew,
277 .write_b = sdhci_iproc_writeb,
278 .set_clock = sdhci_set_clock,
279 .set_power = sdhci_set_power_and_bus_voltage,
280 .get_max_clock = sdhci_iproc_get_max_clock,
281 .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
282 .set_bus_width = sdhci_set_bus_width,
283 .reset = sdhci_reset,
284 .set_uhs_signaling = sdhci_set_uhs_signaling,
285};
286
287static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
288 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
289 .ops = &sdhci_iproc_bcm2711_ops,
290};
291
292static const struct sdhci_iproc_data bcm2711_data = {
293 .pdata = &sdhci_bcm2711_pltfm_data,
294 .mmc_caps = MMC_CAP_3_3V_DDR,
295};
296
297static const struct sdhci_pltfm_data sdhci_bcm7211a0_pltfm_data = {
298 .quirks = SDHCI_QUIRK_MISSING_CAPS |
299 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
300 SDHCI_QUIRK_BROKEN_DMA |
301 SDHCI_QUIRK_BROKEN_ADMA,
302 .ops = &sdhci_iproc_ops,
303};
304
305#define BCM7211A0_BASE_CLK_MHZ 100
306static const struct sdhci_iproc_data bcm7211a0_data = {
307 .pdata = &sdhci_bcm7211a0_pltfm_data,
308 .caps = ((BCM7211A0_BASE_CLK_MHZ / 2) << SDHCI_TIMEOUT_CLK_SHIFT) |
309 (BCM7211A0_BASE_CLK_MHZ << SDHCI_CLOCK_BASE_SHIFT) |
310 ((0x2 << SDHCI_MAX_BLOCK_SHIFT)
311 & SDHCI_MAX_BLOCK_MASK) |
312 SDHCI_CAN_VDD_330 |
313 SDHCI_CAN_VDD_180 |
314 SDHCI_CAN_DO_SUSPEND |
315 SDHCI_CAN_DO_HISPD,
316 .caps1 = SDHCI_DRIVER_TYPE_C |
317 SDHCI_DRIVER_TYPE_D,
318};
319
320static const struct of_device_id sdhci_iproc_of_match[] = {
321 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
322 { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
323 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
324 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
325 { .compatible = "brcm,bcm7211a0-sdhci", .data = &bcm7211a0_data },
326 { }
327};
328MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
329
330#ifdef CONFIG_ACPI
331/*
332 * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
333 * which are provided by the ACPI table.
334 */
335static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
336 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
337 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
338 SDHCI_QUIRK_NO_HISPD_BIT,
339 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
340 .ops = &sdhci_iproc_32only_ops,
341};
342
343static const struct sdhci_iproc_data bcm_arasan_data = {
344 .pdata = &sdhci_bcm_arasan_data,
345};
346
347static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
348 { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
349 { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
350 { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
351 { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
352 { /* sentinel */ }
353};
354MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
355#endif
356
357static int sdhci_iproc_probe(struct platform_device *pdev)
358{
359 struct device *dev = &pdev->dev;
360 const struct sdhci_iproc_data *iproc_data = NULL;
361 struct sdhci_host *host;
362 struct sdhci_iproc_host *iproc_host;
363 struct sdhci_pltfm_host *pltfm_host;
364 int ret;
365
366 iproc_data = device_get_match_data(dev);
367 if (!iproc_data)
368 return -ENODEV;
369
370 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
371 if (IS_ERR(host))
372 return PTR_ERR(host);
373
374 pltfm_host = sdhci_priv(host);
375 iproc_host = sdhci_pltfm_priv(pltfm_host);
376
377 iproc_host->data = iproc_data;
378
379 ret = mmc_of_parse(host->mmc);
380 if (ret)
381 goto err;
382
383 sdhci_get_property(pdev);
384
385 host->mmc->caps |= iproc_host->data->mmc_caps;
386
387 if (dev->of_node) {
388 pltfm_host->clk = devm_clk_get(dev, NULL);
389 if (IS_ERR(pltfm_host->clk)) {
390 ret = PTR_ERR(pltfm_host->clk);
391 goto err;
392 }
393 ret = clk_prepare_enable(pltfm_host->clk);
394 if (ret) {
395 dev_err(dev, "failed to enable host clk\n");
396 goto err;
397 }
398 }
399
400 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
401 host->caps = iproc_host->data->caps;
402 host->caps1 = iproc_host->data->caps1;
403 }
404
405 ret = sdhci_add_host(host);
406 if (ret)
407 goto err_clk;
408
409 return 0;
410
411err_clk:
412 if (dev->of_node)
413 clk_disable_unprepare(pltfm_host->clk);
414err:
415 sdhci_pltfm_free(pdev);
416 return ret;
417}
418
419static void sdhci_iproc_shutdown(struct platform_device *pdev)
420{
421 sdhci_pltfm_suspend(&pdev->dev);
422}
423
424static struct platform_driver sdhci_iproc_driver = {
425 .driver = {
426 .name = "sdhci-iproc",
427 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
428 .of_match_table = sdhci_iproc_of_match,
429 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
430 .pm = &sdhci_pltfm_pmops,
431 },
432 .probe = sdhci_iproc_probe,
433 .remove = sdhci_pltfm_unregister,
434 .shutdown = sdhci_iproc_shutdown,
435};
436module_platform_driver(sdhci_iproc_driver);
437
438MODULE_AUTHOR("Broadcom");
439MODULE_DESCRIPTION("IPROC SDHCI driver");
440MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/*
15 * iProc SDHCI platform driver
16 */
17
18#include <linux/acpi.h>
19#include <linux/delay.h>
20#include <linux/module.h>
21#include <linux/mmc/host.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include "sdhci-pltfm.h"
25
26struct sdhci_iproc_data {
27 const struct sdhci_pltfm_data *pdata;
28 u32 caps;
29 u32 caps1;
30 u32 mmc_caps;
31};
32
33struct sdhci_iproc_host {
34 const struct sdhci_iproc_data *data;
35 u32 shadow_cmd;
36 u32 shadow_blk;
37 bool is_cmd_shadowed;
38 bool is_blk_shadowed;
39};
40
41#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
42
43static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
44{
45 u32 val = readl(host->ioaddr + reg);
46
47 pr_debug("%s: readl [0x%02x] 0x%08x\n",
48 mmc_hostname(host->mmc), reg, val);
49 return val;
50}
51
52static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
53{
54 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
55 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
56 u32 val;
57 u16 word;
58
59 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
60 /* Get the saved transfer mode */
61 val = iproc_host->shadow_cmd;
62 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
63 iproc_host->is_blk_shadowed) {
64 /* Get the saved block info */
65 val = iproc_host->shadow_blk;
66 } else {
67 val = sdhci_iproc_readl(host, (reg & ~3));
68 }
69 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
70 return word;
71}
72
73static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
74{
75 u32 val = sdhci_iproc_readl(host, (reg & ~3));
76 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
77 return byte;
78}
79
80static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
81{
82 pr_debug("%s: writel [0x%02x] 0x%08x\n",
83 mmc_hostname(host->mmc), reg, val);
84
85 writel(val, host->ioaddr + reg);
86
87 if (host->clock <= 400000) {
88 /* Round up to micro-second four SD clock delay */
89 if (host->clock)
90 udelay((4 * 1000000 + host->clock - 1) / host->clock);
91 else
92 udelay(10);
93 }
94}
95
96/*
97 * The Arasan has a bugette whereby it may lose the content of successive
98 * writes to the same register that are within two SD-card clock cycles of
99 * each other (a clock domain crossing problem). The data
100 * register does not have this problem, which is just as well - otherwise we'd
101 * have to nobble the DMA engine too.
102 *
103 * This wouldn't be a problem with the code except that we can only write the
104 * controller with 32-bit writes. So two different 16-bit registers are
105 * written back to back creates the problem.
106 *
107 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
108 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
109 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
110 * the work around can be further optimized. We can keep shadow values of
111 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
112 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
113 * by the TRANSFER+COMMAND in another 32-bit write.
114 */
115static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
116{
117 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
118 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
119 u32 word_shift = REG_OFFSET_IN_BITS(reg);
120 u32 mask = 0xffff << word_shift;
121 u32 oldval, newval;
122
123 if (reg == SDHCI_COMMAND) {
124 /* Write the block now as we are issuing a command */
125 if (iproc_host->is_blk_shadowed) {
126 sdhci_iproc_writel(host, iproc_host->shadow_blk,
127 SDHCI_BLOCK_SIZE);
128 iproc_host->is_blk_shadowed = false;
129 }
130 oldval = iproc_host->shadow_cmd;
131 iproc_host->is_cmd_shadowed = false;
132 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
133 iproc_host->is_blk_shadowed) {
134 /* Block size and count are stored in shadow reg */
135 oldval = iproc_host->shadow_blk;
136 } else {
137 /* Read reg, all other registers are not shadowed */
138 oldval = sdhci_iproc_readl(host, (reg & ~3));
139 }
140 newval = (oldval & ~mask) | (val << word_shift);
141
142 if (reg == SDHCI_TRANSFER_MODE) {
143 /* Save the transfer mode until the command is issued */
144 iproc_host->shadow_cmd = newval;
145 iproc_host->is_cmd_shadowed = true;
146 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
147 /* Save the block info until the command is issued */
148 iproc_host->shadow_blk = newval;
149 iproc_host->is_blk_shadowed = true;
150 } else {
151 /* Command or other regular 32-bit write */
152 sdhci_iproc_writel(host, newval, reg & ~3);
153 }
154}
155
156static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
157{
158 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
159 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
160 u32 mask = 0xff << byte_shift;
161 u32 newval = (oldval & ~mask) | (val << byte_shift);
162
163 sdhci_iproc_writel(host, newval, reg & ~3);
164}
165
166static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
167{
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169
170 if (pltfm_host->clk)
171 return sdhci_pltfm_clk_get_max_clock(host);
172 else
173 return pltfm_host->clock;
174}
175
176/*
177 * There is a known bug on BCM2711's SDHCI core integration where the
178 * controller will hang when the difference between the core clock and the bus
179 * clock is too great. Specifically this can be reproduced under the following
180 * conditions:
181 *
182 * - No SD card plugged in, polling thread is running, probing cards at
183 * 100 kHz.
184 * - BCM2711's core clock configured at 500MHz or more
185 *
186 * So we set 200kHz as the minimum clock frequency available for that SoC.
187 */
188static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
189{
190 return 200000;
191}
192
193static const struct sdhci_ops sdhci_iproc_ops = {
194 .set_clock = sdhci_set_clock,
195 .get_max_clock = sdhci_iproc_get_max_clock,
196 .set_bus_width = sdhci_set_bus_width,
197 .reset = sdhci_reset,
198 .set_uhs_signaling = sdhci_set_uhs_signaling,
199};
200
201static const struct sdhci_ops sdhci_iproc_32only_ops = {
202 .read_l = sdhci_iproc_readl,
203 .read_w = sdhci_iproc_readw,
204 .read_b = sdhci_iproc_readb,
205 .write_l = sdhci_iproc_writel,
206 .write_w = sdhci_iproc_writew,
207 .write_b = sdhci_iproc_writeb,
208 .set_clock = sdhci_set_clock,
209 .get_max_clock = sdhci_iproc_get_max_clock,
210 .set_bus_width = sdhci_set_bus_width,
211 .reset = sdhci_reset,
212 .set_uhs_signaling = sdhci_set_uhs_signaling,
213};
214
215static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
216 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
217 SDHCI_QUIRK_NO_HISPD_BIT,
218 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
219 .ops = &sdhci_iproc_32only_ops,
220};
221
222static const struct sdhci_iproc_data iproc_cygnus_data = {
223 .pdata = &sdhci_iproc_cygnus_pltfm_data,
224 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
225 & SDHCI_MAX_BLOCK_MASK) |
226 SDHCI_CAN_VDD_330 |
227 SDHCI_CAN_VDD_180 |
228 SDHCI_CAN_DO_SUSPEND |
229 SDHCI_CAN_DO_HISPD |
230 SDHCI_CAN_DO_ADMA2 |
231 SDHCI_CAN_DO_SDMA,
232 .caps1 = SDHCI_DRIVER_TYPE_C |
233 SDHCI_DRIVER_TYPE_D |
234 SDHCI_SUPPORT_DDR50,
235 .mmc_caps = MMC_CAP_1_8V_DDR,
236};
237
238static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
239 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
240 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
241 SDHCI_QUIRK_NO_HISPD_BIT,
242 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
243 .ops = &sdhci_iproc_ops,
244};
245
246static const struct sdhci_iproc_data iproc_data = {
247 .pdata = &sdhci_iproc_pltfm_data,
248 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
249 & SDHCI_MAX_BLOCK_MASK) |
250 SDHCI_CAN_VDD_330 |
251 SDHCI_CAN_VDD_180 |
252 SDHCI_CAN_DO_SUSPEND |
253 SDHCI_CAN_DO_HISPD |
254 SDHCI_CAN_DO_ADMA2 |
255 SDHCI_CAN_DO_SDMA,
256 .caps1 = SDHCI_DRIVER_TYPE_C |
257 SDHCI_DRIVER_TYPE_D |
258 SDHCI_SUPPORT_DDR50,
259};
260
261static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
262 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
263 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
264 SDHCI_QUIRK_MISSING_CAPS |
265 SDHCI_QUIRK_NO_HISPD_BIT,
266 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
267 .ops = &sdhci_iproc_32only_ops,
268};
269
270static const struct sdhci_iproc_data bcm2835_data = {
271 .pdata = &sdhci_bcm2835_pltfm_data,
272 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
273 & SDHCI_MAX_BLOCK_MASK) |
274 SDHCI_CAN_VDD_330 |
275 SDHCI_CAN_DO_HISPD,
276 .caps1 = SDHCI_DRIVER_TYPE_A |
277 SDHCI_DRIVER_TYPE_C,
278 .mmc_caps = 0x00000000,
279};
280
281static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
282 .read_l = sdhci_iproc_readl,
283 .read_w = sdhci_iproc_readw,
284 .read_b = sdhci_iproc_readb,
285 .write_l = sdhci_iproc_writel,
286 .write_w = sdhci_iproc_writew,
287 .write_b = sdhci_iproc_writeb,
288 .set_clock = sdhci_set_clock,
289 .set_power = sdhci_set_power_and_bus_voltage,
290 .get_max_clock = sdhci_iproc_get_max_clock,
291 .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
292 .set_bus_width = sdhci_set_bus_width,
293 .reset = sdhci_reset,
294 .set_uhs_signaling = sdhci_set_uhs_signaling,
295};
296
297static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
298 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
299 .ops = &sdhci_iproc_bcm2711_ops,
300};
301
302static const struct sdhci_iproc_data bcm2711_data = {
303 .pdata = &sdhci_bcm2711_pltfm_data,
304 .mmc_caps = MMC_CAP_3_3V_DDR,
305};
306
307static const struct sdhci_pltfm_data sdhci_bcm7211a0_pltfm_data = {
308 .quirks = SDHCI_QUIRK_MISSING_CAPS |
309 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
310 SDHCI_QUIRK_BROKEN_DMA |
311 SDHCI_QUIRK_BROKEN_ADMA,
312 .ops = &sdhci_iproc_ops,
313};
314
315#define BCM7211A0_BASE_CLK_MHZ 100
316static const struct sdhci_iproc_data bcm7211a0_data = {
317 .pdata = &sdhci_bcm7211a0_pltfm_data,
318 .caps = ((BCM7211A0_BASE_CLK_MHZ / 2) << SDHCI_TIMEOUT_CLK_SHIFT) |
319 (BCM7211A0_BASE_CLK_MHZ << SDHCI_CLOCK_BASE_SHIFT) |
320 ((0x2 << SDHCI_MAX_BLOCK_SHIFT)
321 & SDHCI_MAX_BLOCK_MASK) |
322 SDHCI_CAN_VDD_330 |
323 SDHCI_CAN_VDD_180 |
324 SDHCI_CAN_DO_SUSPEND |
325 SDHCI_CAN_DO_HISPD,
326 .caps1 = SDHCI_DRIVER_TYPE_C |
327 SDHCI_DRIVER_TYPE_D,
328};
329
330static const struct of_device_id sdhci_iproc_of_match[] = {
331 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
332 { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
333 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
334 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
335 { .compatible = "brcm,bcm7211a0-sdhci", .data = &bcm7211a0_data },
336 { }
337};
338MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
339
340#ifdef CONFIG_ACPI
341/*
342 * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
343 * which are provided by the ACPI table.
344 */
345static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
346 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
347 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
348 SDHCI_QUIRK_NO_HISPD_BIT,
349 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
350 .ops = &sdhci_iproc_32only_ops,
351};
352
353static const struct sdhci_iproc_data bcm_arasan_data = {
354 .pdata = &sdhci_bcm_arasan_data,
355};
356
357static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
358 { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
359 { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
360 { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
361 { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
362 { /* sentinel */ }
363};
364MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
365#endif
366
367static int sdhci_iproc_probe(struct platform_device *pdev)
368{
369 struct device *dev = &pdev->dev;
370 const struct sdhci_iproc_data *iproc_data = NULL;
371 struct sdhci_host *host;
372 struct sdhci_iproc_host *iproc_host;
373 struct sdhci_pltfm_host *pltfm_host;
374 int ret;
375
376 iproc_data = device_get_match_data(dev);
377 if (!iproc_data)
378 return -ENODEV;
379
380 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
381 if (IS_ERR(host))
382 return PTR_ERR(host);
383
384 pltfm_host = sdhci_priv(host);
385 iproc_host = sdhci_pltfm_priv(pltfm_host);
386
387 iproc_host->data = iproc_data;
388
389 ret = mmc_of_parse(host->mmc);
390 if (ret)
391 goto err;
392
393 sdhci_get_property(pdev);
394
395 host->mmc->caps |= iproc_host->data->mmc_caps;
396
397 if (dev->of_node) {
398 pltfm_host->clk = devm_clk_get(dev, NULL);
399 if (IS_ERR(pltfm_host->clk)) {
400 ret = PTR_ERR(pltfm_host->clk);
401 goto err;
402 }
403 ret = clk_prepare_enable(pltfm_host->clk);
404 if (ret) {
405 dev_err(dev, "failed to enable host clk\n");
406 goto err;
407 }
408 }
409
410 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
411 host->caps = iproc_host->data->caps;
412 host->caps1 = iproc_host->data->caps1;
413 }
414
415 ret = sdhci_add_host(host);
416 if (ret)
417 goto err_clk;
418
419 return 0;
420
421err_clk:
422 if (dev->of_node)
423 clk_disable_unprepare(pltfm_host->clk);
424err:
425 sdhci_pltfm_free(pdev);
426 return ret;
427}
428
429static void sdhci_iproc_shutdown(struct platform_device *pdev)
430{
431 sdhci_pltfm_suspend(&pdev->dev);
432}
433
434static struct platform_driver sdhci_iproc_driver = {
435 .driver = {
436 .name = "sdhci-iproc",
437 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
438 .of_match_table = sdhci_iproc_of_match,
439 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
440 .pm = &sdhci_pltfm_pmops,
441 },
442 .probe = sdhci_iproc_probe,
443 .remove = sdhci_pltfm_unregister,
444 .shutdown = sdhci_iproc_shutdown,
445};
446module_platform_driver(sdhci_iproc_driver);
447
448MODULE_AUTHOR("Broadcom");
449MODULE_DESCRIPTION("IPROC SDHCI driver");
450MODULE_LICENSE("GPL v2");