Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - CMT
4 *
5 * Copyright (C) 2008 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/pm_domain.h>
24#include <linux/pm_runtime.h>
25#include <linux/sh_timer.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28
29#ifdef CONFIG_SUPERH
30#include <asm/platform_early.h>
31#endif
32
33struct sh_cmt_device;
34
35/*
36 * The CMT comes in 5 different identified flavours, depending not only on the
37 * SoC but also on the particular instance. The following table lists the main
38 * characteristics of those flavours.
39 *
40 * 16B 32B 32B-F 48B R-Car Gen2
41 * -----------------------------------------------------------------------------
42 * Channels 2 1/4 1 6 2/8
43 * Control Width 16 16 16 16 32
44 * Counter Width 16 32 32 32/48 32/48
45 * Shared Start/Stop Y Y Y Y N
46 *
47 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
48 * located in the channel registers block. All other versions have a shared
49 * start/stop register located in the global space.
50 *
51 * Channels are indexed from 0 to N-1 in the documentation. The channel index
52 * infers the start/stop bit position in the control register and the channel
53 * registers block address. Some CMT instances have a subset of channels
54 * available, in which case the index in the documentation doesn't match the
55 * "real" index as implemented in hardware. This is for instance the case with
56 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
57 * in the documentation but using start/stop bit 5 and having its registers
58 * block at 0x60.
59 *
60 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
61 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
62 */
63
64enum sh_cmt_model {
65 SH_CMT_16BIT,
66 SH_CMT_32BIT,
67 SH_CMT_48BIT,
68 SH_CMT0_RCAR_GEN2,
69 SH_CMT1_RCAR_GEN2,
70};
71
72struct sh_cmt_info {
73 enum sh_cmt_model model;
74
75 unsigned int channels_mask;
76
77 unsigned long width; /* 16 or 32 bit version of hardware block */
78 u32 overflow_bit;
79 u32 clear_bits;
80
81 /* callbacks for CMSTR and CMCSR access */
82 u32 (*read_control)(void __iomem *base, unsigned long offs);
83 void (*write_control)(void __iomem *base, unsigned long offs,
84 u32 value);
85
86 /* callbacks for CMCNT and CMCOR access */
87 u32 (*read_count)(void __iomem *base, unsigned long offs);
88 void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
89};
90
91struct sh_cmt_channel {
92 struct sh_cmt_device *cmt;
93
94 unsigned int index; /* Index in the documentation */
95 unsigned int hwidx; /* Real hardware index */
96
97 void __iomem *iostart;
98 void __iomem *ioctrl;
99
100 unsigned int timer_bit;
101 unsigned long flags;
102 u32 match_value;
103 u32 next_match_value;
104 u32 max_match_value;
105 raw_spinlock_t lock;
106 struct clock_event_device ced;
107 struct clocksource cs;
108 u64 total_cycles;
109 bool cs_enabled;
110};
111
112struct sh_cmt_device {
113 struct platform_device *pdev;
114
115 const struct sh_cmt_info *info;
116
117 void __iomem *mapbase;
118 struct clk *clk;
119 unsigned long rate;
120 unsigned int reg_delay;
121
122 raw_spinlock_t lock; /* Protect the shared start/stop register */
123
124 struct sh_cmt_channel *channels;
125 unsigned int num_channels;
126 unsigned int hw_channels;
127
128 bool has_clockevent;
129 bool has_clocksource;
130};
131
132#define SH_CMT16_CMCSR_CMF (1 << 7)
133#define SH_CMT16_CMCSR_CMIE (1 << 6)
134#define SH_CMT16_CMCSR_CKS8 (0 << 0)
135#define SH_CMT16_CMCSR_CKS32 (1 << 0)
136#define SH_CMT16_CMCSR_CKS128 (2 << 0)
137#define SH_CMT16_CMCSR_CKS512 (3 << 0)
138#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
139
140#define SH_CMT32_CMCSR_CMF (1 << 15)
141#define SH_CMT32_CMCSR_OVF (1 << 14)
142#define SH_CMT32_CMCSR_WRFLG (1 << 13)
143#define SH_CMT32_CMCSR_STTF (1 << 12)
144#define SH_CMT32_CMCSR_STPF (1 << 11)
145#define SH_CMT32_CMCSR_SSIE (1 << 10)
146#define SH_CMT32_CMCSR_CMS (1 << 9)
147#define SH_CMT32_CMCSR_CMM (1 << 8)
148#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
149#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
150#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
151#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
152#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
153#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
154#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
155#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
156#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
157#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
158#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
159
160static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
161{
162 return ioread16(base + (offs << 1));
163}
164
165static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
166{
167 return ioread32(base + (offs << 2));
168}
169
170static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
171{
172 iowrite16(value, base + (offs << 1));
173}
174
175static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
176{
177 iowrite32(value, base + (offs << 2));
178}
179
180static const struct sh_cmt_info sh_cmt_info[] = {
181 [SH_CMT_16BIT] = {
182 .model = SH_CMT_16BIT,
183 .width = 16,
184 .overflow_bit = SH_CMT16_CMCSR_CMF,
185 .clear_bits = ~SH_CMT16_CMCSR_CMF,
186 .read_control = sh_cmt_read16,
187 .write_control = sh_cmt_write16,
188 .read_count = sh_cmt_read16,
189 .write_count = sh_cmt_write16,
190 },
191 [SH_CMT_32BIT] = {
192 .model = SH_CMT_32BIT,
193 .width = 32,
194 .overflow_bit = SH_CMT32_CMCSR_CMF,
195 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
196 .read_control = sh_cmt_read16,
197 .write_control = sh_cmt_write16,
198 .read_count = sh_cmt_read32,
199 .write_count = sh_cmt_write32,
200 },
201 [SH_CMT_48BIT] = {
202 .model = SH_CMT_48BIT,
203 .channels_mask = 0x3f,
204 .width = 32,
205 .overflow_bit = SH_CMT32_CMCSR_CMF,
206 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
207 .read_control = sh_cmt_read32,
208 .write_control = sh_cmt_write32,
209 .read_count = sh_cmt_read32,
210 .write_count = sh_cmt_write32,
211 },
212 [SH_CMT0_RCAR_GEN2] = {
213 .model = SH_CMT0_RCAR_GEN2,
214 .channels_mask = 0x60,
215 .width = 32,
216 .overflow_bit = SH_CMT32_CMCSR_CMF,
217 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
218 .read_control = sh_cmt_read32,
219 .write_control = sh_cmt_write32,
220 .read_count = sh_cmt_read32,
221 .write_count = sh_cmt_write32,
222 },
223 [SH_CMT1_RCAR_GEN2] = {
224 .model = SH_CMT1_RCAR_GEN2,
225 .channels_mask = 0xff,
226 .width = 32,
227 .overflow_bit = SH_CMT32_CMCSR_CMF,
228 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
229 .read_control = sh_cmt_read32,
230 .write_control = sh_cmt_write32,
231 .read_count = sh_cmt_read32,
232 .write_count = sh_cmt_write32,
233 },
234};
235
236#define CMCSR 0 /* channel register */
237#define CMCNT 1 /* channel register */
238#define CMCOR 2 /* channel register */
239
240#define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
241
242static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
243{
244 if (ch->iostart)
245 return ch->cmt->info->read_control(ch->iostart, 0);
246 else
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
248}
249
250static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
251{
252 u32 old_value = sh_cmt_read_cmstr(ch);
253
254 if (value != old_value) {
255 if (ch->iostart) {
256 ch->cmt->info->write_control(ch->iostart, 0, value);
257 udelay(ch->cmt->reg_delay);
258 } else {
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260 udelay(ch->cmt->reg_delay);
261 }
262 }
263}
264
265static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
266{
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
268}
269
270static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
271{
272 u32 old_value = sh_cmt_read_cmcsr(ch);
273
274 if (value != old_value) {
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
276 udelay(ch->cmt->reg_delay);
277 }
278}
279
280static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
281{
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
283}
284
285static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
286{
287 /* Tests showed that we need to wait 3 clocks here */
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
289 u32 reg;
290
291 if (ch->cmt->info->model > SH_CMT_16BIT) {
292 int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg,
293 !(reg & SH_CMT32_CMCSR_WRFLG),
294 1, cmcnt_delay, false, ch);
295 if (ret < 0)
296 return ret;
297 }
298
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
300 udelay(cmcnt_delay);
301 return 0;
302}
303
304static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
305{
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
307
308 if (value != old_value) {
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
310 udelay(ch->cmt->reg_delay);
311 }
312}
313
314static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
315{
316 u32 v1, v2, v3;
317 u32 o1, o2;
318
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
320
321 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
322 do {
323 o2 = o1;
324 v1 = sh_cmt_read_cmcnt(ch);
325 v2 = sh_cmt_read_cmcnt(ch);
326 v3 = sh_cmt_read_cmcnt(ch);
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
328 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
329 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
330
331 *has_wrapped = o1;
332 return v2;
333}
334
335static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
336{
337 unsigned long flags;
338 u32 value;
339
340 /* start stop register shared by multiple timer channels */
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
342 value = sh_cmt_read_cmstr(ch);
343
344 if (start)
345 value |= 1 << ch->timer_bit;
346 else
347 value &= ~(1 << ch->timer_bit);
348
349 sh_cmt_write_cmstr(ch, value);
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
351}
352
353static int sh_cmt_enable(struct sh_cmt_channel *ch)
354{
355 int ret;
356
357 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
358
359 /* enable clock */
360 ret = clk_enable(ch->cmt->clk);
361 if (ret) {
362 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
363 ch->index);
364 goto err0;
365 }
366
367 /* make sure channel is disabled */
368 sh_cmt_start_stop_ch(ch, 0);
369
370 /* configure channel, periodic mode and maximum timeout */
371 if (ch->cmt->info->width == 16) {
372 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
373 SH_CMT16_CMCSR_CKS512);
374 } else {
375 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?
376 SH_CMT32_CMCSR_CMTOUT_IE : 0;
377 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM |
378 SH_CMT32_CMCSR_CMR_IRQ |
379 SH_CMT32_CMCSR_CKS_RCLK8);
380 }
381
382 sh_cmt_write_cmcor(ch, 0xffffffff);
383 ret = sh_cmt_write_cmcnt(ch, 0);
384
385 if (ret || sh_cmt_read_cmcnt(ch)) {
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
387 ch->index);
388 ret = -ETIMEDOUT;
389 goto err1;
390 }
391
392 /* enable channel */
393 sh_cmt_start_stop_ch(ch, 1);
394 return 0;
395 err1:
396 /* stop clock */
397 clk_disable(ch->cmt->clk);
398
399 err0:
400 return ret;
401}
402
403static void sh_cmt_disable(struct sh_cmt_channel *ch)
404{
405 /* disable channel */
406 sh_cmt_start_stop_ch(ch, 0);
407
408 /* disable interrupts in CMT block */
409 sh_cmt_write_cmcsr(ch, 0);
410
411 /* stop clock */
412 clk_disable(ch->cmt->clk);
413
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
415}
416
417/* private flags */
418#define FLAG_CLOCKEVENT (1 << 0)
419#define FLAG_CLOCKSOURCE (1 << 1)
420#define FLAG_REPROGRAM (1 << 2)
421#define FLAG_SKIPEVENT (1 << 3)
422#define FLAG_IRQCONTEXT (1 << 4)
423
424static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
425 int absolute)
426{
427 u32 value = ch->next_match_value;
428 u32 new_match;
429 u32 delay = 0;
430 u32 now = 0;
431 u32 has_wrapped;
432
433 now = sh_cmt_get_counter(ch, &has_wrapped);
434 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
435
436 if (has_wrapped) {
437 /* we're competing with the interrupt handler.
438 * -> let the interrupt handler reprogram the timer.
439 * -> interrupt number two handles the event.
440 */
441 ch->flags |= FLAG_SKIPEVENT;
442 return;
443 }
444
445 if (absolute)
446 now = 0;
447
448 do {
449 /* reprogram the timer hardware,
450 * but don't save the new match value yet.
451 */
452 new_match = now + value + delay;
453 if (new_match > ch->max_match_value)
454 new_match = ch->max_match_value;
455
456 sh_cmt_write_cmcor(ch, new_match);
457
458 now = sh_cmt_get_counter(ch, &has_wrapped);
459 if (has_wrapped && (new_match > ch->match_value)) {
460 /* we are changing to a greater match value,
461 * so this wrap must be caused by the counter
462 * matching the old value.
463 * -> first interrupt reprograms the timer.
464 * -> interrupt number two handles the event.
465 */
466 ch->flags |= FLAG_SKIPEVENT;
467 break;
468 }
469
470 if (has_wrapped) {
471 /* we are changing to a smaller match value,
472 * so the wrap must be caused by the counter
473 * matching the new value.
474 * -> save programmed match value.
475 * -> let isr handle the event.
476 */
477 ch->match_value = new_match;
478 break;
479 }
480
481 /* be safe: verify hardware settings */
482 if (now < new_match) {
483 /* timer value is below match value, all good.
484 * this makes sure we won't miss any match events.
485 * -> save programmed match value.
486 * -> let isr handle the event.
487 */
488 ch->match_value = new_match;
489 break;
490 }
491
492 /* the counter has reached a value greater
493 * than our new match value. and since the
494 * has_wrapped flag isn't set we must have
495 * programmed a too close event.
496 * -> increase delay and retry.
497 */
498 if (delay)
499 delay <<= 1;
500 else
501 delay = 1;
502
503 if (!delay)
504 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
505 ch->index);
506
507 } while (delay);
508}
509
510static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
511{
512 if (delta > ch->max_match_value)
513 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
514 ch->index);
515
516 ch->next_match_value = delta;
517 sh_cmt_clock_event_program_verify(ch, 0);
518}
519
520static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
521{
522 unsigned long flags;
523
524 raw_spin_lock_irqsave(&ch->lock, flags);
525 __sh_cmt_set_next(ch, delta);
526 raw_spin_unlock_irqrestore(&ch->lock, flags);
527}
528
529static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
530{
531 struct sh_cmt_channel *ch = dev_id;
532
533 /* clear flags */
534 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
535 ch->cmt->info->clear_bits);
536
537 /* update clock source counter to begin with if enabled
538 * the wrap flag should be cleared by the timer specific
539 * isr before we end up here.
540 */
541 if (ch->flags & FLAG_CLOCKSOURCE)
542 ch->total_cycles += ch->match_value + 1;
543
544 if (!(ch->flags & FLAG_REPROGRAM))
545 ch->next_match_value = ch->max_match_value;
546
547 ch->flags |= FLAG_IRQCONTEXT;
548
549 if (ch->flags & FLAG_CLOCKEVENT) {
550 if (!(ch->flags & FLAG_SKIPEVENT)) {
551 if (clockevent_state_oneshot(&ch->ced)) {
552 ch->next_match_value = ch->max_match_value;
553 ch->flags |= FLAG_REPROGRAM;
554 }
555
556 ch->ced.event_handler(&ch->ced);
557 }
558 }
559
560 ch->flags &= ~FLAG_SKIPEVENT;
561
562 if (ch->flags & FLAG_REPROGRAM) {
563 ch->flags &= ~FLAG_REPROGRAM;
564 sh_cmt_clock_event_program_verify(ch, 1);
565
566 if (ch->flags & FLAG_CLOCKEVENT)
567 if ((clockevent_state_shutdown(&ch->ced))
568 || (ch->match_value == ch->next_match_value))
569 ch->flags &= ~FLAG_REPROGRAM;
570 }
571
572 ch->flags &= ~FLAG_IRQCONTEXT;
573
574 return IRQ_HANDLED;
575}
576
577static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
578{
579 int ret = 0;
580 unsigned long flags;
581
582 if (flag & FLAG_CLOCKSOURCE)
583 pm_runtime_get_sync(&ch->cmt->pdev->dev);
584
585 raw_spin_lock_irqsave(&ch->lock, flags);
586
587 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
588 if (flag & FLAG_CLOCKEVENT)
589 pm_runtime_get_sync(&ch->cmt->pdev->dev);
590 ret = sh_cmt_enable(ch);
591 }
592
593 if (ret)
594 goto out;
595 ch->flags |= flag;
596
597 /* setup timeout if no clockevent */
598 if (ch->cmt->num_channels == 1 &&
599 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
600 __sh_cmt_set_next(ch, ch->max_match_value);
601 out:
602 raw_spin_unlock_irqrestore(&ch->lock, flags);
603
604 return ret;
605}
606
607static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
608{
609 unsigned long flags;
610 unsigned long f;
611
612 raw_spin_lock_irqsave(&ch->lock, flags);
613
614 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
615 ch->flags &= ~flag;
616
617 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
618 sh_cmt_disable(ch);
619 if (flag & FLAG_CLOCKEVENT)
620 pm_runtime_put(&ch->cmt->pdev->dev);
621 }
622
623 /* adjust the timeout to maximum if only clocksource left */
624 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
625 __sh_cmt_set_next(ch, ch->max_match_value);
626
627 raw_spin_unlock_irqrestore(&ch->lock, flags);
628
629 if (flag & FLAG_CLOCKSOURCE)
630 pm_runtime_put(&ch->cmt->pdev->dev);
631}
632
633static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
634{
635 return container_of(cs, struct sh_cmt_channel, cs);
636}
637
638static u64 sh_cmt_clocksource_read(struct clocksource *cs)
639{
640 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
641 u32 has_wrapped;
642
643 if (ch->cmt->num_channels == 1) {
644 unsigned long flags;
645 u64 value;
646 u32 raw;
647
648 raw_spin_lock_irqsave(&ch->lock, flags);
649 value = ch->total_cycles;
650 raw = sh_cmt_get_counter(ch, &has_wrapped);
651
652 if (unlikely(has_wrapped))
653 raw += ch->match_value + 1;
654 raw_spin_unlock_irqrestore(&ch->lock, flags);
655
656 return value + raw;
657 }
658
659 return sh_cmt_get_counter(ch, &has_wrapped);
660}
661
662static int sh_cmt_clocksource_enable(struct clocksource *cs)
663{
664 int ret;
665 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
666
667 WARN_ON(ch->cs_enabled);
668
669 ch->total_cycles = 0;
670
671 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
672 if (!ret)
673 ch->cs_enabled = true;
674
675 return ret;
676}
677
678static void sh_cmt_clocksource_disable(struct clocksource *cs)
679{
680 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
681
682 WARN_ON(!ch->cs_enabled);
683
684 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
685 ch->cs_enabled = false;
686}
687
688static void sh_cmt_clocksource_suspend(struct clocksource *cs)
689{
690 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
691
692 if (!ch->cs_enabled)
693 return;
694
695 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
696 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
697}
698
699static void sh_cmt_clocksource_resume(struct clocksource *cs)
700{
701 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
702
703 if (!ch->cs_enabled)
704 return;
705
706 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
707 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
708}
709
710static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
711 const char *name)
712{
713 struct clocksource *cs = &ch->cs;
714
715 cs->name = name;
716 cs->rating = 125;
717 cs->read = sh_cmt_clocksource_read;
718 cs->enable = sh_cmt_clocksource_enable;
719 cs->disable = sh_cmt_clocksource_disable;
720 cs->suspend = sh_cmt_clocksource_suspend;
721 cs->resume = sh_cmt_clocksource_resume;
722 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
723 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
724
725 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
726 ch->index);
727
728 clocksource_register_hz(cs, ch->cmt->rate);
729 return 0;
730}
731
732static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
733{
734 return container_of(ced, struct sh_cmt_channel, ced);
735}
736
737static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
738{
739 sh_cmt_start(ch, FLAG_CLOCKEVENT);
740
741 if (periodic)
742 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
743 else
744 sh_cmt_set_next(ch, ch->max_match_value);
745}
746
747static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
748{
749 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
750
751 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
752 return 0;
753}
754
755static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
756 int periodic)
757{
758 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
759
760 /* deal with old setting first */
761 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
762 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
763
764 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
765 ch->index, periodic ? "periodic" : "oneshot");
766 sh_cmt_clock_event_start(ch, periodic);
767 return 0;
768}
769
770static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
771{
772 return sh_cmt_clock_event_set_state(ced, 0);
773}
774
775static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
776{
777 return sh_cmt_clock_event_set_state(ced, 1);
778}
779
780static int sh_cmt_clock_event_next(unsigned long delta,
781 struct clock_event_device *ced)
782{
783 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
784
785 BUG_ON(!clockevent_state_oneshot(ced));
786 if (likely(ch->flags & FLAG_IRQCONTEXT))
787 ch->next_match_value = delta - 1;
788 else
789 sh_cmt_set_next(ch, delta - 1);
790
791 return 0;
792}
793
794static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
795{
796 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
797
798 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
799 clk_unprepare(ch->cmt->clk);
800}
801
802static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
803{
804 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
805
806 clk_prepare(ch->cmt->clk);
807 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
808}
809
810static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
811 const char *name)
812{
813 struct clock_event_device *ced = &ch->ced;
814 int irq;
815 int ret;
816
817 irq = platform_get_irq(ch->cmt->pdev, ch->index);
818 if (irq < 0)
819 return irq;
820
821 ret = request_irq(irq, sh_cmt_interrupt,
822 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
823 dev_name(&ch->cmt->pdev->dev), ch);
824 if (ret) {
825 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
826 ch->index, irq);
827 return ret;
828 }
829
830 ced->name = name;
831 ced->features = CLOCK_EVT_FEAT_PERIODIC;
832 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
833 ced->rating = 125;
834 ced->cpumask = cpu_possible_mask;
835 ced->set_next_event = sh_cmt_clock_event_next;
836 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
837 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
838 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
839 ced->suspend = sh_cmt_clock_event_suspend;
840 ced->resume = sh_cmt_clock_event_resume;
841
842 /* TODO: calculate good shift from rate and counter bit width */
843 ced->shift = 32;
844 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
845 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
846 ced->max_delta_ticks = ch->max_match_value;
847 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
848 ced->min_delta_ticks = 0x1f;
849
850 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
851 ch->index);
852 clockevents_register_device(ced);
853
854 return 0;
855}
856
857static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
858 bool clockevent, bool clocksource)
859{
860 int ret;
861
862 if (clockevent) {
863 ch->cmt->has_clockevent = true;
864 ret = sh_cmt_register_clockevent(ch, name);
865 if (ret < 0)
866 return ret;
867 }
868
869 if (clocksource) {
870 ch->cmt->has_clocksource = true;
871 sh_cmt_register_clocksource(ch, name);
872 }
873
874 return 0;
875}
876
877static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
878 unsigned int hwidx, bool clockevent,
879 bool clocksource, struct sh_cmt_device *cmt)
880{
881 u32 value;
882 int ret;
883
884 /* Skip unused channels. */
885 if (!clockevent && !clocksource)
886 return 0;
887
888 ch->cmt = cmt;
889 ch->index = index;
890 ch->hwidx = hwidx;
891 ch->timer_bit = hwidx;
892
893 /*
894 * Compute the address of the channel control register block. For the
895 * timers with a per-channel start/stop register, compute its address
896 * as well.
897 */
898 switch (cmt->info->model) {
899 case SH_CMT_16BIT:
900 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
901 break;
902 case SH_CMT_32BIT:
903 case SH_CMT_48BIT:
904 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
905 break;
906 case SH_CMT0_RCAR_GEN2:
907 case SH_CMT1_RCAR_GEN2:
908 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
909 ch->ioctrl = ch->iostart + 0x10;
910 ch->timer_bit = 0;
911
912 /* Enable the clock supply to the channel */
913 value = ioread32(cmt->mapbase + CMCLKE);
914 value |= BIT(hwidx);
915 iowrite32(value, cmt->mapbase + CMCLKE);
916 break;
917 }
918
919 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
920 ch->max_match_value = ~0;
921 else
922 ch->max_match_value = (1 << cmt->info->width) - 1;
923
924 ch->match_value = ch->max_match_value;
925 raw_spin_lock_init(&ch->lock);
926
927 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
928 clockevent, clocksource);
929 if (ret) {
930 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
931 ch->index);
932 return ret;
933 }
934 ch->cs_enabled = false;
935
936 return 0;
937}
938
939static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
940{
941 struct resource *mem;
942
943 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
944 if (!mem) {
945 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
946 return -ENXIO;
947 }
948
949 cmt->mapbase = ioremap(mem->start, resource_size(mem));
950 if (cmt->mapbase == NULL) {
951 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
952 return -ENXIO;
953 }
954
955 return 0;
956}
957
958static const struct platform_device_id sh_cmt_id_table[] = {
959 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
960 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
961 { }
962};
963MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
964
965static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
966 {
967 /* deprecated, preserved for backward compatibility */
968 .compatible = "renesas,cmt-48",
969 .data = &sh_cmt_info[SH_CMT_48BIT]
970 },
971 {
972 /* deprecated, preserved for backward compatibility */
973 .compatible = "renesas,cmt-48-gen2",
974 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
975 },
976 {
977 .compatible = "renesas,r8a7740-cmt1",
978 .data = &sh_cmt_info[SH_CMT_48BIT]
979 },
980 {
981 .compatible = "renesas,sh73a0-cmt1",
982 .data = &sh_cmt_info[SH_CMT_48BIT]
983 },
984 {
985 .compatible = "renesas,rcar-gen2-cmt0",
986 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
987 },
988 {
989 .compatible = "renesas,rcar-gen2-cmt1",
990 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
991 },
992 {
993 .compatible = "renesas,rcar-gen3-cmt0",
994 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
995 },
996 {
997 .compatible = "renesas,rcar-gen3-cmt1",
998 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
999 },
1000 {
1001 .compatible = "renesas,rcar-gen4-cmt0",
1002 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
1003 },
1004 {
1005 .compatible = "renesas,rcar-gen4-cmt1",
1006 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
1007 },
1008 { }
1009};
1010MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
1011
1012static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1013{
1014 unsigned int mask, i;
1015 unsigned long rate;
1016 int ret;
1017
1018 cmt->pdev = pdev;
1019 raw_spin_lock_init(&cmt->lock);
1020
1021 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
1022 cmt->info = of_device_get_match_data(&pdev->dev);
1023 cmt->hw_channels = cmt->info->channels_mask;
1024 } else if (pdev->dev.platform_data) {
1025 struct sh_timer_config *cfg = pdev->dev.platform_data;
1026 const struct platform_device_id *id = pdev->id_entry;
1027
1028 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1029 cmt->hw_channels = cfg->channels_mask;
1030 } else {
1031 dev_err(&cmt->pdev->dev, "missing platform data\n");
1032 return -ENXIO;
1033 }
1034
1035 /* Get hold of clock. */
1036 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1037 if (IS_ERR(cmt->clk)) {
1038 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1039 return PTR_ERR(cmt->clk);
1040 }
1041
1042 ret = clk_prepare(cmt->clk);
1043 if (ret < 0)
1044 goto err_clk_put;
1045
1046 /* Determine clock rate. */
1047 ret = clk_enable(cmt->clk);
1048 if (ret < 0)
1049 goto err_clk_unprepare;
1050
1051 rate = clk_get_rate(cmt->clk);
1052 if (!rate) {
1053 ret = -EINVAL;
1054 goto err_clk_disable;
1055 }
1056
1057 /* We shall wait 2 input clks after register writes */
1058 if (cmt->info->model >= SH_CMT_48BIT)
1059 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate);
1060 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
1061
1062 /* Map the memory resource(s). */
1063 ret = sh_cmt_map_memory(cmt);
1064 if (ret < 0)
1065 goto err_clk_disable;
1066
1067 /* Allocate and setup the channels. */
1068 cmt->num_channels = hweight8(cmt->hw_channels);
1069 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1070 GFP_KERNEL);
1071 if (cmt->channels == NULL) {
1072 ret = -ENOMEM;
1073 goto err_unmap;
1074 }
1075
1076 /*
1077 * Use the first channel as a clock event device and the second channel
1078 * as a clock source. If only one channel is available use it for both.
1079 */
1080 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1081 unsigned int hwidx = ffs(mask) - 1;
1082 bool clocksource = i == 1 || cmt->num_channels == 1;
1083 bool clockevent = i == 0;
1084
1085 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1086 clockevent, clocksource, cmt);
1087 if (ret < 0)
1088 goto err_unmap;
1089
1090 mask &= ~(1 << hwidx);
1091 }
1092
1093 clk_disable(cmt->clk);
1094
1095 platform_set_drvdata(pdev, cmt);
1096
1097 return 0;
1098
1099err_unmap:
1100 kfree(cmt->channels);
1101 iounmap(cmt->mapbase);
1102err_clk_disable:
1103 clk_disable(cmt->clk);
1104err_clk_unprepare:
1105 clk_unprepare(cmt->clk);
1106err_clk_put:
1107 clk_put(cmt->clk);
1108 return ret;
1109}
1110
1111static int sh_cmt_probe(struct platform_device *pdev)
1112{
1113 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1114 int ret;
1115
1116 if (!is_sh_early_platform_device(pdev)) {
1117 pm_runtime_set_active(&pdev->dev);
1118 pm_runtime_enable(&pdev->dev);
1119 }
1120
1121 if (cmt) {
1122 dev_info(&pdev->dev, "kept as earlytimer\n");
1123 goto out;
1124 }
1125
1126 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1127 if (cmt == NULL)
1128 return -ENOMEM;
1129
1130 ret = sh_cmt_setup(cmt, pdev);
1131 if (ret) {
1132 kfree(cmt);
1133 pm_runtime_idle(&pdev->dev);
1134 return ret;
1135 }
1136 if (is_sh_early_platform_device(pdev))
1137 return 0;
1138
1139 out:
1140 if (cmt->has_clockevent || cmt->has_clocksource)
1141 pm_runtime_irq_safe(&pdev->dev);
1142 else
1143 pm_runtime_idle(&pdev->dev);
1144
1145 return 0;
1146}
1147
1148static int sh_cmt_remove(struct platform_device *pdev)
1149{
1150 return -EBUSY; /* cannot unregister clockevent and clocksource */
1151}
1152
1153static struct platform_driver sh_cmt_device_driver = {
1154 .probe = sh_cmt_probe,
1155 .remove = sh_cmt_remove,
1156 .driver = {
1157 .name = "sh_cmt",
1158 .of_match_table = of_match_ptr(sh_cmt_of_table),
1159 },
1160 .id_table = sh_cmt_id_table,
1161};
1162
1163static int __init sh_cmt_init(void)
1164{
1165 return platform_driver_register(&sh_cmt_device_driver);
1166}
1167
1168static void __exit sh_cmt_exit(void)
1169{
1170 platform_driver_unregister(&sh_cmt_device_driver);
1171}
1172
1173#ifdef CONFIG_SUPERH
1174sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1175#endif
1176
1177subsys_initcall(sh_cmt_init);
1178module_exit(sh_cmt_exit);
1179
1180MODULE_AUTHOR("Magnus Damm");
1181MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1182MODULE_LICENSE("GPL v2");
1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/platform_device.h>
30#include <linux/pm_domain.h>
31#include <linux/pm_runtime.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34#include <linux/spinlock.h>
35
36struct sh_cmt_device;
37
38/*
39 * The CMT comes in 5 different identified flavours, depending not only on the
40 * SoC but also on the particular instance. The following table lists the main
41 * characteristics of those flavours.
42 *
43 * 16B 32B 32B-F 48B R-Car Gen2
44 * -----------------------------------------------------------------------------
45 * Channels 2 1/4 1 6 2/8
46 * Control Width 16 16 16 16 32
47 * Counter Width 16 32 32 32/48 32/48
48 * Shared Start/Stop Y Y Y Y N
49 *
50 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
51 * located in the channel registers block. All other versions have a shared
52 * start/stop register located in the global space.
53 *
54 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * infers the start/stop bit position in the control register and the channel
56 * registers block address. Some CMT instances have a subset of channels
57 * available, in which case the index in the documentation doesn't match the
58 * "real" index as implemented in hardware. This is for instance the case with
59 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
60 * in the documentation but using start/stop bit 5 and having its registers
61 * block at 0x60.
62 *
63 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
64 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
65 */
66
67enum sh_cmt_model {
68 SH_CMT_16BIT,
69 SH_CMT_32BIT,
70 SH_CMT_48BIT,
71 SH_CMT0_RCAR_GEN2,
72 SH_CMT1_RCAR_GEN2,
73};
74
75struct sh_cmt_info {
76 enum sh_cmt_model model;
77
78 unsigned int channels_mask;
79
80 unsigned long width; /* 16 or 32 bit version of hardware block */
81 unsigned long overflow_bit;
82 unsigned long clear_bits;
83
84 /* callbacks for CMSTR and CMCSR access */
85 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
86 void (*write_control)(void __iomem *base, unsigned long offs,
87 unsigned long value);
88
89 /* callbacks for CMCNT and CMCOR access */
90 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
91 void (*write_count)(void __iomem *base, unsigned long offs,
92 unsigned long value);
93};
94
95struct sh_cmt_channel {
96 struct sh_cmt_device *cmt;
97
98 unsigned int index; /* Index in the documentation */
99 unsigned int hwidx; /* Real hardware index */
100
101 void __iomem *iostart;
102 void __iomem *ioctrl;
103
104 unsigned int timer_bit;
105 unsigned long flags;
106 unsigned long match_value;
107 unsigned long next_match_value;
108 unsigned long max_match_value;
109 raw_spinlock_t lock;
110 struct clock_event_device ced;
111 struct clocksource cs;
112 unsigned long total_cycles;
113 bool cs_enabled;
114};
115
116struct sh_cmt_device {
117 struct platform_device *pdev;
118
119 const struct sh_cmt_info *info;
120
121 void __iomem *mapbase;
122 struct clk *clk;
123 unsigned long rate;
124
125 raw_spinlock_t lock; /* Protect the shared start/stop register */
126
127 struct sh_cmt_channel *channels;
128 unsigned int num_channels;
129 unsigned int hw_channels;
130
131 bool has_clockevent;
132 bool has_clocksource;
133};
134
135#define SH_CMT16_CMCSR_CMF (1 << 7)
136#define SH_CMT16_CMCSR_CMIE (1 << 6)
137#define SH_CMT16_CMCSR_CKS8 (0 << 0)
138#define SH_CMT16_CMCSR_CKS32 (1 << 0)
139#define SH_CMT16_CMCSR_CKS128 (2 << 0)
140#define SH_CMT16_CMCSR_CKS512 (3 << 0)
141#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
142
143#define SH_CMT32_CMCSR_CMF (1 << 15)
144#define SH_CMT32_CMCSR_OVF (1 << 14)
145#define SH_CMT32_CMCSR_WRFLG (1 << 13)
146#define SH_CMT32_CMCSR_STTF (1 << 12)
147#define SH_CMT32_CMCSR_STPF (1 << 11)
148#define SH_CMT32_CMCSR_SSIE (1 << 10)
149#define SH_CMT32_CMCSR_CMS (1 << 9)
150#define SH_CMT32_CMCSR_CMM (1 << 8)
151#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
152#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
153#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
154#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
155#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
156#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
157#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
158#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
159#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
160#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
161#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
162
163static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
164{
165 return ioread16(base + (offs << 1));
166}
167
168static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
169{
170 return ioread32(base + (offs << 2));
171}
172
173static void sh_cmt_write16(void __iomem *base, unsigned long offs,
174 unsigned long value)
175{
176 iowrite16(value, base + (offs << 1));
177}
178
179static void sh_cmt_write32(void __iomem *base, unsigned long offs,
180 unsigned long value)
181{
182 iowrite32(value, base + (offs << 2));
183}
184
185static const struct sh_cmt_info sh_cmt_info[] = {
186 [SH_CMT_16BIT] = {
187 .model = SH_CMT_16BIT,
188 .width = 16,
189 .overflow_bit = SH_CMT16_CMCSR_CMF,
190 .clear_bits = ~SH_CMT16_CMCSR_CMF,
191 .read_control = sh_cmt_read16,
192 .write_control = sh_cmt_write16,
193 .read_count = sh_cmt_read16,
194 .write_count = sh_cmt_write16,
195 },
196 [SH_CMT_32BIT] = {
197 .model = SH_CMT_32BIT,
198 .width = 32,
199 .overflow_bit = SH_CMT32_CMCSR_CMF,
200 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
201 .read_control = sh_cmt_read16,
202 .write_control = sh_cmt_write16,
203 .read_count = sh_cmt_read32,
204 .write_count = sh_cmt_write32,
205 },
206 [SH_CMT_48BIT] = {
207 .model = SH_CMT_48BIT,
208 .channels_mask = 0x3f,
209 .width = 32,
210 .overflow_bit = SH_CMT32_CMCSR_CMF,
211 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
212 .read_control = sh_cmt_read32,
213 .write_control = sh_cmt_write32,
214 .read_count = sh_cmt_read32,
215 .write_count = sh_cmt_write32,
216 },
217 [SH_CMT0_RCAR_GEN2] = {
218 .model = SH_CMT0_RCAR_GEN2,
219 .channels_mask = 0x60,
220 .width = 32,
221 .overflow_bit = SH_CMT32_CMCSR_CMF,
222 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
223 .read_control = sh_cmt_read32,
224 .write_control = sh_cmt_write32,
225 .read_count = sh_cmt_read32,
226 .write_count = sh_cmt_write32,
227 },
228 [SH_CMT1_RCAR_GEN2] = {
229 .model = SH_CMT1_RCAR_GEN2,
230 .channels_mask = 0xff,
231 .width = 32,
232 .overflow_bit = SH_CMT32_CMCSR_CMF,
233 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
234 .read_control = sh_cmt_read32,
235 .write_control = sh_cmt_write32,
236 .read_count = sh_cmt_read32,
237 .write_count = sh_cmt_write32,
238 },
239};
240
241#define CMCSR 0 /* channel register */
242#define CMCNT 1 /* channel register */
243#define CMCOR 2 /* channel register */
244
245static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
246{
247 if (ch->iostart)
248 return ch->cmt->info->read_control(ch->iostart, 0);
249 else
250 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
251}
252
253static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
254 unsigned long value)
255{
256 if (ch->iostart)
257 ch->cmt->info->write_control(ch->iostart, 0, value);
258 else
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260}
261
262static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
263{
264 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
265}
266
267static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
268 unsigned long value)
269{
270 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
271}
272
273static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
274{
275 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
276}
277
278static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
279 unsigned long value)
280{
281 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
282}
283
284static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
285 unsigned long value)
286{
287 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
288}
289
290static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
291 int *has_wrapped)
292{
293 unsigned long v1, v2, v3;
294 int o1, o2;
295
296 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
297
298 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
299 do {
300 o2 = o1;
301 v1 = sh_cmt_read_cmcnt(ch);
302 v2 = sh_cmt_read_cmcnt(ch);
303 v3 = sh_cmt_read_cmcnt(ch);
304 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
305 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
306 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
307
308 *has_wrapped = o1;
309 return v2;
310}
311
312static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
313{
314 unsigned long flags, value;
315
316 /* start stop register shared by multiple timer channels */
317 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
318 value = sh_cmt_read_cmstr(ch);
319
320 if (start)
321 value |= 1 << ch->timer_bit;
322 else
323 value &= ~(1 << ch->timer_bit);
324
325 sh_cmt_write_cmstr(ch, value);
326 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
327}
328
329static int sh_cmt_enable(struct sh_cmt_channel *ch)
330{
331 int k, ret;
332
333 pm_runtime_get_sync(&ch->cmt->pdev->dev);
334 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
335
336 /* enable clock */
337 ret = clk_enable(ch->cmt->clk);
338 if (ret) {
339 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
340 ch->index);
341 goto err0;
342 }
343
344 /* make sure channel is disabled */
345 sh_cmt_start_stop_ch(ch, 0);
346
347 /* configure channel, periodic mode and maximum timeout */
348 if (ch->cmt->info->width == 16) {
349 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
350 SH_CMT16_CMCSR_CKS512);
351 } else {
352 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
353 SH_CMT32_CMCSR_CMTOUT_IE |
354 SH_CMT32_CMCSR_CMR_IRQ |
355 SH_CMT32_CMCSR_CKS_RCLK8);
356 }
357
358 sh_cmt_write_cmcor(ch, 0xffffffff);
359 sh_cmt_write_cmcnt(ch, 0);
360
361 /*
362 * According to the sh73a0 user's manual, as CMCNT can be operated
363 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
364 * modifying CMCNT register; two RCLK cycles are necessary before
365 * this register is either read or any modification of the value
366 * it holds is reflected in the LSI's actual operation.
367 *
368 * While at it, we're supposed to clear out the CMCNT as of this
369 * moment, so make sure it's processed properly here. This will
370 * take RCLKx2 at maximum.
371 */
372 for (k = 0; k < 100; k++) {
373 if (!sh_cmt_read_cmcnt(ch))
374 break;
375 udelay(1);
376 }
377
378 if (sh_cmt_read_cmcnt(ch)) {
379 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
380 ch->index);
381 ret = -ETIMEDOUT;
382 goto err1;
383 }
384
385 /* enable channel */
386 sh_cmt_start_stop_ch(ch, 1);
387 return 0;
388 err1:
389 /* stop clock */
390 clk_disable(ch->cmt->clk);
391
392 err0:
393 return ret;
394}
395
396static void sh_cmt_disable(struct sh_cmt_channel *ch)
397{
398 /* disable channel */
399 sh_cmt_start_stop_ch(ch, 0);
400
401 /* disable interrupts in CMT block */
402 sh_cmt_write_cmcsr(ch, 0);
403
404 /* stop clock */
405 clk_disable(ch->cmt->clk);
406
407 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
408 pm_runtime_put(&ch->cmt->pdev->dev);
409}
410
411/* private flags */
412#define FLAG_CLOCKEVENT (1 << 0)
413#define FLAG_CLOCKSOURCE (1 << 1)
414#define FLAG_REPROGRAM (1 << 2)
415#define FLAG_SKIPEVENT (1 << 3)
416#define FLAG_IRQCONTEXT (1 << 4)
417
418static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
419 int absolute)
420{
421 unsigned long new_match;
422 unsigned long value = ch->next_match_value;
423 unsigned long delay = 0;
424 unsigned long now = 0;
425 int has_wrapped;
426
427 now = sh_cmt_get_counter(ch, &has_wrapped);
428 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
429
430 if (has_wrapped) {
431 /* we're competing with the interrupt handler.
432 * -> let the interrupt handler reprogram the timer.
433 * -> interrupt number two handles the event.
434 */
435 ch->flags |= FLAG_SKIPEVENT;
436 return;
437 }
438
439 if (absolute)
440 now = 0;
441
442 do {
443 /* reprogram the timer hardware,
444 * but don't save the new match value yet.
445 */
446 new_match = now + value + delay;
447 if (new_match > ch->max_match_value)
448 new_match = ch->max_match_value;
449
450 sh_cmt_write_cmcor(ch, new_match);
451
452 now = sh_cmt_get_counter(ch, &has_wrapped);
453 if (has_wrapped && (new_match > ch->match_value)) {
454 /* we are changing to a greater match value,
455 * so this wrap must be caused by the counter
456 * matching the old value.
457 * -> first interrupt reprograms the timer.
458 * -> interrupt number two handles the event.
459 */
460 ch->flags |= FLAG_SKIPEVENT;
461 break;
462 }
463
464 if (has_wrapped) {
465 /* we are changing to a smaller match value,
466 * so the wrap must be caused by the counter
467 * matching the new value.
468 * -> save programmed match value.
469 * -> let isr handle the event.
470 */
471 ch->match_value = new_match;
472 break;
473 }
474
475 /* be safe: verify hardware settings */
476 if (now < new_match) {
477 /* timer value is below match value, all good.
478 * this makes sure we won't miss any match events.
479 * -> save programmed match value.
480 * -> let isr handle the event.
481 */
482 ch->match_value = new_match;
483 break;
484 }
485
486 /* the counter has reached a value greater
487 * than our new match value. and since the
488 * has_wrapped flag isn't set we must have
489 * programmed a too close event.
490 * -> increase delay and retry.
491 */
492 if (delay)
493 delay <<= 1;
494 else
495 delay = 1;
496
497 if (!delay)
498 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
499 ch->index);
500
501 } while (delay);
502}
503
504static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
505{
506 if (delta > ch->max_match_value)
507 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
508 ch->index);
509
510 ch->next_match_value = delta;
511 sh_cmt_clock_event_program_verify(ch, 0);
512}
513
514static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
515{
516 unsigned long flags;
517
518 raw_spin_lock_irqsave(&ch->lock, flags);
519 __sh_cmt_set_next(ch, delta);
520 raw_spin_unlock_irqrestore(&ch->lock, flags);
521}
522
523static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
524{
525 struct sh_cmt_channel *ch = dev_id;
526
527 /* clear flags */
528 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
529 ch->cmt->info->clear_bits);
530
531 /* update clock source counter to begin with if enabled
532 * the wrap flag should be cleared by the timer specific
533 * isr before we end up here.
534 */
535 if (ch->flags & FLAG_CLOCKSOURCE)
536 ch->total_cycles += ch->match_value + 1;
537
538 if (!(ch->flags & FLAG_REPROGRAM))
539 ch->next_match_value = ch->max_match_value;
540
541 ch->flags |= FLAG_IRQCONTEXT;
542
543 if (ch->flags & FLAG_CLOCKEVENT) {
544 if (!(ch->flags & FLAG_SKIPEVENT)) {
545 if (clockevent_state_oneshot(&ch->ced)) {
546 ch->next_match_value = ch->max_match_value;
547 ch->flags |= FLAG_REPROGRAM;
548 }
549
550 ch->ced.event_handler(&ch->ced);
551 }
552 }
553
554 ch->flags &= ~FLAG_SKIPEVENT;
555
556 if (ch->flags & FLAG_REPROGRAM) {
557 ch->flags &= ~FLAG_REPROGRAM;
558 sh_cmt_clock_event_program_verify(ch, 1);
559
560 if (ch->flags & FLAG_CLOCKEVENT)
561 if ((clockevent_state_shutdown(&ch->ced))
562 || (ch->match_value == ch->next_match_value))
563 ch->flags &= ~FLAG_REPROGRAM;
564 }
565
566 ch->flags &= ~FLAG_IRQCONTEXT;
567
568 return IRQ_HANDLED;
569}
570
571static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
572{
573 int ret = 0;
574 unsigned long flags;
575
576 raw_spin_lock_irqsave(&ch->lock, flags);
577
578 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
579 ret = sh_cmt_enable(ch);
580
581 if (ret)
582 goto out;
583 ch->flags |= flag;
584
585 /* setup timeout if no clockevent */
586 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
587 __sh_cmt_set_next(ch, ch->max_match_value);
588 out:
589 raw_spin_unlock_irqrestore(&ch->lock, flags);
590
591 return ret;
592}
593
594static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
595{
596 unsigned long flags;
597 unsigned long f;
598
599 raw_spin_lock_irqsave(&ch->lock, flags);
600
601 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
602 ch->flags &= ~flag;
603
604 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
605 sh_cmt_disable(ch);
606
607 /* adjust the timeout to maximum if only clocksource left */
608 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
609 __sh_cmt_set_next(ch, ch->max_match_value);
610
611 raw_spin_unlock_irqrestore(&ch->lock, flags);
612}
613
614static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
615{
616 return container_of(cs, struct sh_cmt_channel, cs);
617}
618
619static u64 sh_cmt_clocksource_read(struct clocksource *cs)
620{
621 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
622 unsigned long flags, raw;
623 unsigned long value;
624 int has_wrapped;
625
626 raw_spin_lock_irqsave(&ch->lock, flags);
627 value = ch->total_cycles;
628 raw = sh_cmt_get_counter(ch, &has_wrapped);
629
630 if (unlikely(has_wrapped))
631 raw += ch->match_value + 1;
632 raw_spin_unlock_irqrestore(&ch->lock, flags);
633
634 return value + raw;
635}
636
637static int sh_cmt_clocksource_enable(struct clocksource *cs)
638{
639 int ret;
640 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
641
642 WARN_ON(ch->cs_enabled);
643
644 ch->total_cycles = 0;
645
646 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
647 if (!ret)
648 ch->cs_enabled = true;
649
650 return ret;
651}
652
653static void sh_cmt_clocksource_disable(struct clocksource *cs)
654{
655 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
656
657 WARN_ON(!ch->cs_enabled);
658
659 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
660 ch->cs_enabled = false;
661}
662
663static void sh_cmt_clocksource_suspend(struct clocksource *cs)
664{
665 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
666
667 if (!ch->cs_enabled)
668 return;
669
670 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
671 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
672}
673
674static void sh_cmt_clocksource_resume(struct clocksource *cs)
675{
676 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
677
678 if (!ch->cs_enabled)
679 return;
680
681 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
682 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
683}
684
685static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
686 const char *name)
687{
688 struct clocksource *cs = &ch->cs;
689
690 cs->name = name;
691 cs->rating = 125;
692 cs->read = sh_cmt_clocksource_read;
693 cs->enable = sh_cmt_clocksource_enable;
694 cs->disable = sh_cmt_clocksource_disable;
695 cs->suspend = sh_cmt_clocksource_suspend;
696 cs->resume = sh_cmt_clocksource_resume;
697 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
698 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
699
700 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
701 ch->index);
702
703 clocksource_register_hz(cs, ch->cmt->rate);
704 return 0;
705}
706
707static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
708{
709 return container_of(ced, struct sh_cmt_channel, ced);
710}
711
712static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
713{
714 sh_cmt_start(ch, FLAG_CLOCKEVENT);
715
716 if (periodic)
717 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
718 else
719 sh_cmt_set_next(ch, ch->max_match_value);
720}
721
722static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
723{
724 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
725
726 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
727 return 0;
728}
729
730static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
731 int periodic)
732{
733 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
734
735 /* deal with old setting first */
736 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
737 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
738
739 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
740 ch->index, periodic ? "periodic" : "oneshot");
741 sh_cmt_clock_event_start(ch, periodic);
742 return 0;
743}
744
745static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
746{
747 return sh_cmt_clock_event_set_state(ced, 0);
748}
749
750static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
751{
752 return sh_cmt_clock_event_set_state(ced, 1);
753}
754
755static int sh_cmt_clock_event_next(unsigned long delta,
756 struct clock_event_device *ced)
757{
758 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
759
760 BUG_ON(!clockevent_state_oneshot(ced));
761 if (likely(ch->flags & FLAG_IRQCONTEXT))
762 ch->next_match_value = delta - 1;
763 else
764 sh_cmt_set_next(ch, delta - 1);
765
766 return 0;
767}
768
769static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
770{
771 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
772
773 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
774 clk_unprepare(ch->cmt->clk);
775}
776
777static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
778{
779 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
780
781 clk_prepare(ch->cmt->clk);
782 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
783}
784
785static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
786 const char *name)
787{
788 struct clock_event_device *ced = &ch->ced;
789 int irq;
790 int ret;
791
792 irq = platform_get_irq(ch->cmt->pdev, ch->index);
793 if (irq < 0) {
794 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
795 ch->index);
796 return irq;
797 }
798
799 ret = request_irq(irq, sh_cmt_interrupt,
800 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
801 dev_name(&ch->cmt->pdev->dev), ch);
802 if (ret) {
803 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
804 ch->index, irq);
805 return ret;
806 }
807
808 ced->name = name;
809 ced->features = CLOCK_EVT_FEAT_PERIODIC;
810 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
811 ced->rating = 125;
812 ced->cpumask = cpu_possible_mask;
813 ced->set_next_event = sh_cmt_clock_event_next;
814 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
815 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
816 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
817 ced->suspend = sh_cmt_clock_event_suspend;
818 ced->resume = sh_cmt_clock_event_resume;
819
820 /* TODO: calculate good shift from rate and counter bit width */
821 ced->shift = 32;
822 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
823 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
824 ced->max_delta_ticks = ch->max_match_value;
825 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
826 ced->min_delta_ticks = 0x1f;
827
828 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
829 ch->index);
830 clockevents_register_device(ced);
831
832 return 0;
833}
834
835static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
836 bool clockevent, bool clocksource)
837{
838 int ret;
839
840 if (clockevent) {
841 ch->cmt->has_clockevent = true;
842 ret = sh_cmt_register_clockevent(ch, name);
843 if (ret < 0)
844 return ret;
845 }
846
847 if (clocksource) {
848 ch->cmt->has_clocksource = true;
849 sh_cmt_register_clocksource(ch, name);
850 }
851
852 return 0;
853}
854
855static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
856 unsigned int hwidx, bool clockevent,
857 bool clocksource, struct sh_cmt_device *cmt)
858{
859 int ret;
860
861 /* Skip unused channels. */
862 if (!clockevent && !clocksource)
863 return 0;
864
865 ch->cmt = cmt;
866 ch->index = index;
867 ch->hwidx = hwidx;
868 ch->timer_bit = hwidx;
869
870 /*
871 * Compute the address of the channel control register block. For the
872 * timers with a per-channel start/stop register, compute its address
873 * as well.
874 */
875 switch (cmt->info->model) {
876 case SH_CMT_16BIT:
877 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
878 break;
879 case SH_CMT_32BIT:
880 case SH_CMT_48BIT:
881 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
882 break;
883 case SH_CMT0_RCAR_GEN2:
884 case SH_CMT1_RCAR_GEN2:
885 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
886 ch->ioctrl = ch->iostart + 0x10;
887 ch->timer_bit = 0;
888 break;
889 }
890
891 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
892 ch->max_match_value = ~0;
893 else
894 ch->max_match_value = (1 << cmt->info->width) - 1;
895
896 ch->match_value = ch->max_match_value;
897 raw_spin_lock_init(&ch->lock);
898
899 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
900 clockevent, clocksource);
901 if (ret) {
902 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
903 ch->index);
904 return ret;
905 }
906 ch->cs_enabled = false;
907
908 return 0;
909}
910
911static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
912{
913 struct resource *mem;
914
915 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
916 if (!mem) {
917 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
918 return -ENXIO;
919 }
920
921 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
922 if (cmt->mapbase == NULL) {
923 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
924 return -ENXIO;
925 }
926
927 return 0;
928}
929
930static const struct platform_device_id sh_cmt_id_table[] = {
931 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
932 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
933 { }
934};
935MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
936
937static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
938 { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
939 {
940 /* deprecated, preserved for backward compatibility */
941 .compatible = "renesas,cmt-48-gen2",
942 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
943 },
944 { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
945 { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
946 { }
947};
948MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
949
950static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
951{
952 unsigned int mask;
953 unsigned int i;
954 int ret;
955
956 cmt->pdev = pdev;
957 raw_spin_lock_init(&cmt->lock);
958
959 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
960 cmt->info = of_device_get_match_data(&pdev->dev);
961 cmt->hw_channels = cmt->info->channels_mask;
962 } else if (pdev->dev.platform_data) {
963 struct sh_timer_config *cfg = pdev->dev.platform_data;
964 const struct platform_device_id *id = pdev->id_entry;
965
966 cmt->info = (const struct sh_cmt_info *)id->driver_data;
967 cmt->hw_channels = cfg->channels_mask;
968 } else {
969 dev_err(&cmt->pdev->dev, "missing platform data\n");
970 return -ENXIO;
971 }
972
973 /* Get hold of clock. */
974 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
975 if (IS_ERR(cmt->clk)) {
976 dev_err(&cmt->pdev->dev, "cannot get clock\n");
977 return PTR_ERR(cmt->clk);
978 }
979
980 ret = clk_prepare(cmt->clk);
981 if (ret < 0)
982 goto err_clk_put;
983
984 /* Determine clock rate. */
985 ret = clk_enable(cmt->clk);
986 if (ret < 0)
987 goto err_clk_unprepare;
988
989 if (cmt->info->width == 16)
990 cmt->rate = clk_get_rate(cmt->clk) / 512;
991 else
992 cmt->rate = clk_get_rate(cmt->clk) / 8;
993
994 clk_disable(cmt->clk);
995
996 /* Map the memory resource(s). */
997 ret = sh_cmt_map_memory(cmt);
998 if (ret < 0)
999 goto err_clk_unprepare;
1000
1001 /* Allocate and setup the channels. */
1002 cmt->num_channels = hweight8(cmt->hw_channels);
1003 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1004 GFP_KERNEL);
1005 if (cmt->channels == NULL) {
1006 ret = -ENOMEM;
1007 goto err_unmap;
1008 }
1009
1010 /*
1011 * Use the first channel as a clock event device and the second channel
1012 * as a clock source. If only one channel is available use it for both.
1013 */
1014 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1015 unsigned int hwidx = ffs(mask) - 1;
1016 bool clocksource = i == 1 || cmt->num_channels == 1;
1017 bool clockevent = i == 0;
1018
1019 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1020 clockevent, clocksource, cmt);
1021 if (ret < 0)
1022 goto err_unmap;
1023
1024 mask &= ~(1 << hwidx);
1025 }
1026
1027 platform_set_drvdata(pdev, cmt);
1028
1029 return 0;
1030
1031err_unmap:
1032 kfree(cmt->channels);
1033 iounmap(cmt->mapbase);
1034err_clk_unprepare:
1035 clk_unprepare(cmt->clk);
1036err_clk_put:
1037 clk_put(cmt->clk);
1038 return ret;
1039}
1040
1041static int sh_cmt_probe(struct platform_device *pdev)
1042{
1043 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1044 int ret;
1045
1046 if (!is_early_platform_device(pdev)) {
1047 pm_runtime_set_active(&pdev->dev);
1048 pm_runtime_enable(&pdev->dev);
1049 }
1050
1051 if (cmt) {
1052 dev_info(&pdev->dev, "kept as earlytimer\n");
1053 goto out;
1054 }
1055
1056 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1057 if (cmt == NULL)
1058 return -ENOMEM;
1059
1060 ret = sh_cmt_setup(cmt, pdev);
1061 if (ret) {
1062 kfree(cmt);
1063 pm_runtime_idle(&pdev->dev);
1064 return ret;
1065 }
1066 if (is_early_platform_device(pdev))
1067 return 0;
1068
1069 out:
1070 if (cmt->has_clockevent || cmt->has_clocksource)
1071 pm_runtime_irq_safe(&pdev->dev);
1072 else
1073 pm_runtime_idle(&pdev->dev);
1074
1075 return 0;
1076}
1077
1078static int sh_cmt_remove(struct platform_device *pdev)
1079{
1080 return -EBUSY; /* cannot unregister clockevent and clocksource */
1081}
1082
1083static struct platform_driver sh_cmt_device_driver = {
1084 .probe = sh_cmt_probe,
1085 .remove = sh_cmt_remove,
1086 .driver = {
1087 .name = "sh_cmt",
1088 .of_match_table = of_match_ptr(sh_cmt_of_table),
1089 },
1090 .id_table = sh_cmt_id_table,
1091};
1092
1093static int __init sh_cmt_init(void)
1094{
1095 return platform_driver_register(&sh_cmt_device_driver);
1096}
1097
1098static void __exit sh_cmt_exit(void)
1099{
1100 platform_driver_unregister(&sh_cmt_device_driver);
1101}
1102
1103early_platform_init("earlytimer", &sh_cmt_device_driver);
1104subsys_initcall(sh_cmt_init);
1105module_exit(sh_cmt_exit);
1106
1107MODULE_AUTHOR("Magnus Damm");
1108MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1109MODULE_LICENSE("GPL v2");