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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas Timer Support - OSTM
4 *
5 * Copyright (C) 2017 Renesas Electronics America, Inc.
6 * Copyright (C) 2017 Chris Brandt
7 */
8
9#include <linux/clk.h>
10#include <linux/clockchips.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/reset.h>
14#include <linux/sched_clock.h>
15#include <linux/slab.h>
16
17#include "timer-of.h"
18
19/*
20 * The OSTM contains independent channels.
21 * The first OSTM channel probed will be set up as a free running
22 * clocksource. Additionally we will use this clocksource for the system
23 * schedule timer sched_clock().
24 *
25 * The second (or more) channel probed will be set up as an interrupt
26 * driven clock event.
27 */
28
29static void __iomem *system_clock; /* For sched_clock() */
30
31/* OSTM REGISTERS */
32#define OSTM_CMP 0x000 /* RW,32 */
33#define OSTM_CNT 0x004 /* R,32 */
34#define OSTM_TE 0x010 /* R,8 */
35#define OSTM_TS 0x014 /* W,8 */
36#define OSTM_TT 0x018 /* W,8 */
37#define OSTM_CTL 0x020 /* RW,8 */
38
39#define TE 0x01
40#define TS 0x01
41#define TT 0x01
42#define CTL_PERIODIC 0x00
43#define CTL_ONESHOT 0x02
44#define CTL_FREERUN 0x02
45
46static void ostm_timer_stop(struct timer_of *to)
47{
48 if (readb(timer_of_base(to) + OSTM_TE) & TE) {
49 writeb(TT, timer_of_base(to) + OSTM_TT);
50
51 /*
52 * Read back the register simply to confirm the write operation
53 * has completed since I/O writes can sometimes get queued by
54 * the bus architecture.
55 */
56 while (readb(timer_of_base(to) + OSTM_TE) & TE)
57 ;
58 }
59}
60
61static int __init ostm_init_clksrc(struct timer_of *to)
62{
63 ostm_timer_stop(to);
64
65 writel(0, timer_of_base(to) + OSTM_CMP);
66 writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL);
67 writeb(TS, timer_of_base(to) + OSTM_TS);
68
69 return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT,
70 to->np->full_name, timer_of_rate(to), 300,
71 32, clocksource_mmio_readl_up);
72}
73
74static u64 notrace ostm_read_sched_clock(void)
75{
76 return readl(system_clock);
77}
78
79static void __init ostm_init_sched_clock(struct timer_of *to)
80{
81 system_clock = timer_of_base(to) + OSTM_CNT;
82 sched_clock_register(ostm_read_sched_clock, 32, timer_of_rate(to));
83}
84
85static int ostm_clock_event_next(unsigned long delta,
86 struct clock_event_device *ced)
87{
88 struct timer_of *to = to_timer_of(ced);
89
90 ostm_timer_stop(to);
91
92 writel(delta, timer_of_base(to) + OSTM_CMP);
93 writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL);
94 writeb(TS, timer_of_base(to) + OSTM_TS);
95
96 return 0;
97}
98
99static int ostm_shutdown(struct clock_event_device *ced)
100{
101 struct timer_of *to = to_timer_of(ced);
102
103 ostm_timer_stop(to);
104
105 return 0;
106}
107static int ostm_set_periodic(struct clock_event_device *ced)
108{
109 struct timer_of *to = to_timer_of(ced);
110
111 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
112 ostm_timer_stop(to);
113
114 writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP);
115 writeb(CTL_PERIODIC, timer_of_base(to) + OSTM_CTL);
116 writeb(TS, timer_of_base(to) + OSTM_TS);
117
118 return 0;
119}
120
121static int ostm_set_oneshot(struct clock_event_device *ced)
122{
123 struct timer_of *to = to_timer_of(ced);
124
125 ostm_timer_stop(to);
126
127 return 0;
128}
129
130static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
131{
132 struct clock_event_device *ced = dev_id;
133
134 if (clockevent_state_oneshot(ced))
135 ostm_timer_stop(to_timer_of(ced));
136
137 /* notify clockevent layer */
138 if (ced->event_handler)
139 ced->event_handler(ced);
140
141 return IRQ_HANDLED;
142}
143
144static int __init ostm_init_clkevt(struct timer_of *to)
145{
146 struct clock_event_device *ced = &to->clkevt;
147
148 ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
149 ced->set_state_shutdown = ostm_shutdown;
150 ced->set_state_periodic = ostm_set_periodic;
151 ced->set_state_oneshot = ostm_set_oneshot;
152 ced->set_next_event = ostm_clock_event_next;
153 ced->shift = 32;
154 ced->rating = 300;
155 ced->cpumask = cpumask_of(0);
156 clockevents_config_and_register(ced, timer_of_rate(to), 0xf,
157 0xffffffff);
158
159 return 0;
160}
161
162static int __init ostm_init(struct device_node *np)
163{
164 struct reset_control *rstc;
165 struct timer_of *to;
166 int ret;
167
168 to = kzalloc(sizeof(*to), GFP_KERNEL);
169 if (!to)
170 return -ENOMEM;
171
172 rstc = of_reset_control_get_optional_exclusive(np, NULL);
173 if (IS_ERR(rstc)) {
174 ret = PTR_ERR(rstc);
175 goto err_free;
176 }
177
178 reset_control_deassert(rstc);
179
180 to->flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
181 if (system_clock) {
182 /*
183 * clock sources don't use interrupts, clock events do
184 */
185 to->flags |= TIMER_OF_IRQ;
186 to->of_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
187 to->of_irq.handler = ostm_timer_interrupt;
188 }
189
190 ret = timer_of_init(np, to);
191 if (ret)
192 goto err_reset;
193
194 /*
195 * First probed device will be used as system clocksource. Any
196 * additional devices will be used as clock events.
197 */
198 if (!system_clock) {
199 ret = ostm_init_clksrc(to);
200 if (ret)
201 goto err_cleanup;
202
203 ostm_init_sched_clock(to);
204 pr_info("%pOF: used for clocksource\n", np);
205 } else {
206 ret = ostm_init_clkevt(to);
207 if (ret)
208 goto err_cleanup;
209
210 pr_info("%pOF: used for clock events\n", np);
211 }
212
213 return 0;
214
215err_cleanup:
216 timer_of_cleanup(to);
217err_reset:
218 reset_control_assert(rstc);
219 reset_control_put(rstc);
220err_free:
221 kfree(to);
222 return ret;
223}
224
225TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
226
227#ifdef CONFIG_ARCH_RZG2L
228static int __init ostm_probe(struct platform_device *pdev)
229{
230 struct device *dev = &pdev->dev;
231
232 return ostm_init(dev->of_node);
233}
234
235static const struct of_device_id ostm_of_table[] = {
236 { .compatible = "renesas,ostm", },
237 { /* sentinel */ }
238};
239
240static struct platform_driver ostm_device_driver = {
241 .driver = {
242 .name = "renesas_ostm",
243 .of_match_table = of_match_ptr(ostm_of_table),
244 .suppress_bind_attrs = true,
245 },
246};
247builtin_platform_driver_probe(ostm_device_driver, ostm_probe);
248#endif
1/*
2 * Renesas Timer Support - OSTM
3 *
4 * Copyright (C) 2017 Renesas Electronics America, Inc.
5 * Copyright (C) 2017 Chris Brandt
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/clk.h>
21#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/sched_clock.h>
24#include <linux/slab.h>
25
26/*
27 * The OSTM contains independent channels.
28 * The first OSTM channel probed will be set up as a free running
29 * clocksource. Additionally we will use this clocksource for the system
30 * schedule timer sched_clock().
31 *
32 * The second (or more) channel probed will be set up as an interrupt
33 * driven clock event.
34 */
35
36struct ostm_device {
37 void __iomem *base;
38 unsigned long ticks_per_jiffy;
39 struct clock_event_device ced;
40};
41
42static void __iomem *system_clock; /* For sched_clock() */
43
44/* OSTM REGISTERS */
45#define OSTM_CMP 0x000 /* RW,32 */
46#define OSTM_CNT 0x004 /* R,32 */
47#define OSTM_TE 0x010 /* R,8 */
48#define OSTM_TS 0x014 /* W,8 */
49#define OSTM_TT 0x018 /* W,8 */
50#define OSTM_CTL 0x020 /* RW,8 */
51
52#define TE 0x01
53#define TS 0x01
54#define TT 0x01
55#define CTL_PERIODIC 0x00
56#define CTL_ONESHOT 0x02
57#define CTL_FREERUN 0x02
58
59static struct ostm_device *ced_to_ostm(struct clock_event_device *ced)
60{
61 return container_of(ced, struct ostm_device, ced);
62}
63
64static void ostm_timer_stop(struct ostm_device *ostm)
65{
66 if (readb(ostm->base + OSTM_TE) & TE) {
67 writeb(TT, ostm->base + OSTM_TT);
68
69 /*
70 * Read back the register simply to confirm the write operation
71 * has completed since I/O writes can sometimes get queued by
72 * the bus architecture.
73 */
74 while (readb(ostm->base + OSTM_TE) & TE)
75 ;
76 }
77}
78
79static int __init ostm_init_clksrc(struct ostm_device *ostm, unsigned long rate)
80{
81 /*
82 * irq not used (clock sources don't use interrupts)
83 */
84
85 ostm_timer_stop(ostm);
86
87 writel(0, ostm->base + OSTM_CMP);
88 writeb(CTL_FREERUN, ostm->base + OSTM_CTL);
89 writeb(TS, ostm->base + OSTM_TS);
90
91 return clocksource_mmio_init(ostm->base + OSTM_CNT,
92 "ostm", rate,
93 300, 32, clocksource_mmio_readl_up);
94}
95
96static u64 notrace ostm_read_sched_clock(void)
97{
98 return readl(system_clock);
99}
100
101static void __init ostm_init_sched_clock(struct ostm_device *ostm,
102 unsigned long rate)
103{
104 system_clock = ostm->base + OSTM_CNT;
105 sched_clock_register(ostm_read_sched_clock, 32, rate);
106}
107
108static int ostm_clock_event_next(unsigned long delta,
109 struct clock_event_device *ced)
110{
111 struct ostm_device *ostm = ced_to_ostm(ced);
112
113 ostm_timer_stop(ostm);
114
115 writel(delta, ostm->base + OSTM_CMP);
116 writeb(CTL_ONESHOT, ostm->base + OSTM_CTL);
117 writeb(TS, ostm->base + OSTM_TS);
118
119 return 0;
120}
121
122static int ostm_shutdown(struct clock_event_device *ced)
123{
124 struct ostm_device *ostm = ced_to_ostm(ced);
125
126 ostm_timer_stop(ostm);
127
128 return 0;
129}
130static int ostm_set_periodic(struct clock_event_device *ced)
131{
132 struct ostm_device *ostm = ced_to_ostm(ced);
133
134 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
135 ostm_timer_stop(ostm);
136
137 writel(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP);
138 writeb(CTL_PERIODIC, ostm->base + OSTM_CTL);
139 writeb(TS, ostm->base + OSTM_TS);
140
141 return 0;
142}
143
144static int ostm_set_oneshot(struct clock_event_device *ced)
145{
146 struct ostm_device *ostm = ced_to_ostm(ced);
147
148 ostm_timer_stop(ostm);
149
150 return 0;
151}
152
153static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
154{
155 struct ostm_device *ostm = dev_id;
156
157 if (clockevent_state_oneshot(&ostm->ced))
158 ostm_timer_stop(ostm);
159
160 /* notify clockevent layer */
161 if (ostm->ced.event_handler)
162 ostm->ced.event_handler(&ostm->ced);
163
164 return IRQ_HANDLED;
165}
166
167static int __init ostm_init_clkevt(struct ostm_device *ostm, int irq,
168 unsigned long rate)
169{
170 struct clock_event_device *ced = &ostm->ced;
171 int ret = -ENXIO;
172
173 ret = request_irq(irq, ostm_timer_interrupt,
174 IRQF_TIMER | IRQF_IRQPOLL,
175 "ostm", ostm);
176 if (ret) {
177 pr_err("ostm: failed to request irq\n");
178 return ret;
179 }
180
181 ced->name = "ostm";
182 ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
183 ced->set_state_shutdown = ostm_shutdown;
184 ced->set_state_periodic = ostm_set_periodic;
185 ced->set_state_oneshot = ostm_set_oneshot;
186 ced->set_next_event = ostm_clock_event_next;
187 ced->shift = 32;
188 ced->rating = 300;
189 ced->cpumask = cpumask_of(0);
190 clockevents_config_and_register(ced, rate, 0xf, 0xffffffff);
191
192 return 0;
193}
194
195static int __init ostm_init(struct device_node *np)
196{
197 struct ostm_device *ostm;
198 int ret = -EFAULT;
199 struct clk *ostm_clk = NULL;
200 int irq;
201 unsigned long rate;
202
203 ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
204 if (!ostm)
205 return -ENOMEM;
206
207 ostm->base = of_iomap(np, 0);
208 if (!ostm->base) {
209 pr_err("ostm: failed to remap I/O memory\n");
210 goto err;
211 }
212
213 irq = irq_of_parse_and_map(np, 0);
214 if (irq < 0) {
215 pr_err("ostm: Failed to get irq\n");
216 goto err;
217 }
218
219 ostm_clk = of_clk_get(np, 0);
220 if (IS_ERR(ostm_clk)) {
221 pr_err("ostm: Failed to get clock\n");
222 ostm_clk = NULL;
223 goto err;
224 }
225
226 ret = clk_prepare_enable(ostm_clk);
227 if (ret) {
228 pr_err("ostm: Failed to enable clock\n");
229 goto err;
230 }
231
232 rate = clk_get_rate(ostm_clk);
233 ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
234
235 /*
236 * First probed device will be used as system clocksource. Any
237 * additional devices will be used as clock events.
238 */
239 if (!system_clock) {
240 ret = ostm_init_clksrc(ostm, rate);
241
242 if (!ret) {
243 ostm_init_sched_clock(ostm, rate);
244 pr_info("ostm: used for clocksource\n");
245 }
246
247 } else {
248 ret = ostm_init_clkevt(ostm, irq, rate);
249
250 if (!ret)
251 pr_info("ostm: used for clock events\n");
252 }
253
254err:
255 if (ret) {
256 clk_disable_unprepare(ostm_clk);
257 iounmap(ostm->base);
258 kfree(ostm);
259 return ret;
260 }
261
262 return 0;
263}
264
265TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);