1# SPDX-License-Identifier: GPL-2.0-only
  2config CSKY
  3	def_bool y
  4	select ARCH_32BIT_OFF_T
  5	select ARCH_HAS_DMA_PREP_COHERENT
  6	select ARCH_HAS_GCOV_PROFILE_ALL
  7	select ARCH_HAS_SYNC_DMA_FOR_CPU
  8	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  9	select ARCH_USE_BUILTIN_BSWAP
 10	select ARCH_USE_QUEUED_RWLOCKS
 11	select ARCH_USE_QUEUED_SPINLOCKS
 12	select ARCH_HAS_CURRENT_STACK_POINTER
 13	select ARCH_INLINE_READ_LOCK if !PREEMPTION
 14	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
 15	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
 16	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
 17	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
 18	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
 19	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
 20	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
 21	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
 22	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
 23	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
 24	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
 25	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
 26	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
 27	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
 28	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
 29	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
 30	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
 31	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
 32	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
 33	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
 34	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
 35	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
 36	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
 37	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
 38	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
 39	select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
 40	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
 41	select COMMON_CLK
 42	select CLKSRC_MMIO
 43	select CSKY_MPINTC if CPU_CK860
 44	select CSKY_MP_TIMER if CPU_CK860
 45	select CSKY_APB_INTC
 46	select DMA_DIRECT_REMAP
 47	select IRQ_DOMAIN
 48	select DW_APB_TIMER_OF
 49	select GENERIC_IOREMAP
 50	select GENERIC_LIB_ASHLDI3
 51	select GENERIC_LIB_ASHRDI3
 52	select GENERIC_LIB_LSHRDI3
 53	select GENERIC_LIB_MULDI3
 54	select GENERIC_LIB_CMPDI2
 55	select GENERIC_LIB_UCMPDI2
 56	select GENERIC_ALLOCATOR
 57	select GENERIC_ATOMIC64
 58	select GENERIC_CPU_DEVICES
 59	select GENERIC_IRQ_CHIP
 60	select GENERIC_IRQ_PROBE
 61	select GENERIC_IRQ_SHOW
 62	select GENERIC_IRQ_MULTI_HANDLER
 63	select GENERIC_SCHED_CLOCK
 64	select GENERIC_SMP_IDLE_THREAD
 65	select GENERIC_TIME_VSYSCALL
 66	select GENERIC_VDSO_32
 67	select GENERIC_GETTIMEOFDAY
 68	select GX6605S_TIMER if CPU_CK610
 69	select HAVE_ARCH_TRACEHOOK
 70	select HAVE_ARCH_AUDITSYSCALL
 71	select HAVE_ARCH_JUMP_LABEL if !CPU_CK610
 72	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 73	select HAVE_ARCH_MMAP_RND_BITS
 74	select HAVE_ARCH_SECCOMP_FILTER
 75	select HAVE_CONTEXT_TRACKING_USER
 76	select HAVE_VIRT_CPU_ACCOUNTING_GEN
 77	select HAVE_DEBUG_BUGVERBOSE
 78	select HAVE_DEBUG_KMEMLEAK
 79	select HAVE_DYNAMIC_FTRACE
 80	select HAVE_DYNAMIC_FTRACE_WITH_REGS
 81	select HAVE_GENERIC_VDSO
 82	select HAVE_FUNCTION_TRACER
 83	select HAVE_FUNCTION_GRAPH_TRACER
 84	select HAVE_FUNCTION_ERROR_INJECTION
 85	select HAVE_FTRACE_MCOUNT_RECORD
 86	select HAVE_KERNEL_GZIP
 87	select HAVE_KERNEL_LZO
 88	select HAVE_KERNEL_LZMA
 89	select HAVE_KPROBES if !CPU_CK610
 90	select HAVE_KPROBES_ON_FTRACE if !CPU_CK610
 91	select HAVE_KRETPROBES if !CPU_CK610
 92	select HAVE_PERF_EVENTS
 93	select HAVE_PERF_REGS
 94	select HAVE_PERF_USER_STACK_DUMP
 95	select HAVE_DMA_CONTIGUOUS
 96	select HAVE_REGS_AND_STACK_ACCESS_API
 97	select HAVE_STACKPROTECTOR
 98	select HAVE_SYSCALL_TRACEPOINTS
 99	select MAY_HAVE_SPARSE_IRQ
100	select MODULES_USE_ELF_RELA if MODULES
101	select OF
102	select OF_EARLY_FLATTREE
103	select PERF_USE_VMALLOC if CPU_CK610
104	select RTC_LIB
105	select TIMER_OF
106	select GENERIC_PCI_IOMAP
107	select HAVE_PCI
108	select PCI_DOMAINS_GENERIC if PCI
109	select PCI_SYSCALL if PCI
110	select PCI_MSI if PCI
111	select TRACE_IRQFLAGS_SUPPORT
112
113config LOCKDEP_SUPPORT
114	def_bool y
115
116config ARCH_SUPPORTS_UPROBES
117	def_bool y if !CPU_CK610
118
119config CPU_HAS_CACHEV2
120	bool
121
122config CPU_HAS_FPUV2
123	bool
124
125config CPU_HAS_HILO
126	bool
127
128config CPU_HAS_TLBI
129	bool
130
131config CPU_HAS_LDSTEX
132	bool
133	help
134	  For SMP, CPU needs "ldex&stex" instructions for atomic operations.
135
136config CPU_NEED_TLBSYNC
137	bool
138
139config CPU_NEED_SOFTALIGN
140	bool
141
142config CPU_NO_USER_BKPT
143	bool
144	help
145	  For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
146	  abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
147	  So we need a 16bit instruction as user space bkpt, and it will cause an illegal
148	  instruction exception.
149	  In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
150
151config GENERIC_CALIBRATE_DELAY
152	def_bool y
153
154config GENERIC_CSUM
155	def_bool y
156
157config GENERIC_HWEIGHT
158	def_bool y
159
160config MMU
161	def_bool y
162
163config STACKTRACE_SUPPORT
164	def_bool y
165
166config TIME_LOW_RES
167	def_bool y
168
169config CPU_TLB_SIZE
170	int
171	default "128"	if (CPU_CK610 || CPU_CK807 || CPU_CK810)
172	default "1024"	if (CPU_CK860)
173
174config CPU_ASID_BITS
175	int
176	default "8"	if (CPU_CK610 || CPU_CK807 || CPU_CK810)
177	default "12"	if (CPU_CK860)
178
179config L1_CACHE_SHIFT
180	int
181	default "4"	if (CPU_CK610)
182	default "5"	if (CPU_CK807 || CPU_CK810)
183	default "6"	if (CPU_CK860)
184
185config ARCH_MMAP_RND_BITS_MIN
186	default 8
187
188# max bits determined by the following formula:
189#  VA_BITS - PAGE_SHIFT - 3
190config ARCH_MMAP_RND_BITS_MAX
191	default 17
192
193menu "Processor type and features"
194
195choice
196	prompt "CPU MODEL"
197	default CPU_CK807
198
199config CPU_CK610
200	bool "CSKY CPU ck610"
201	select CPU_NEED_TLBSYNC
202	select CPU_NEED_SOFTALIGN
203	select CPU_NO_USER_BKPT
204
205config CPU_CK810
206	bool "CSKY CPU ck810"
207	select CPU_HAS_HILO
208	select CPU_NEED_TLBSYNC
209
210config CPU_CK807
211	bool "CSKY CPU ck807"
212	select CPU_HAS_HILO
213
214config CPU_CK860
215	bool "CSKY CPU ck860"
216	select CPU_HAS_TLBI
217	select CPU_HAS_CACHEV2
218	select CPU_HAS_LDSTEX
219	select CPU_HAS_FPUV2
220endchoice
221
222choice
223	prompt "PAGE OFFSET"
224	default PAGE_OFFSET_80000000
225
226config PAGE_OFFSET_80000000
227	bool "PAGE OFFSET 2G (user:kernel = 2:2)"
228
229config PAGE_OFFSET_A0000000
230	bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"
231endchoice
232
233config PAGE_OFFSET
234	hex
235	default 0x80000000 if PAGE_OFFSET_80000000
236	default 0xa0000000 if PAGE_OFFSET_A0000000
237choice
238
239	prompt "C-SKY PMU type"
240	depends on PERF_EVENTS
241	depends on CPU_CK807 || CPU_CK810 || CPU_CK860
242
243config CPU_PMU_NONE
244	bool "None"
245
246config CSKY_PMU_V1
247	bool "Performance Monitoring Unit Ver.1"
248
249endchoice
250
251choice
252	prompt "Power Manager Instruction (wait/doze/stop)"
253	default CPU_PM_NONE
254
255config CPU_PM_NONE
256	bool "None"
257
258config CPU_PM_WAIT
259	bool "wait"
260
261config CPU_PM_DOZE
262	bool "doze"
263
264config CPU_PM_STOP
265	bool "stop"
266endchoice
267
268menuconfig HAVE_TCM
269	bool "Tightly-Coupled/Sram Memory"
270	depends on !COMPILE_TEST
271	help
272	  The implementation are not only used by TCM (Tightly-Coupled Memory)
273	  but also used by sram on SOC bus. It follow existed linux tcm
274	  software interface, so that old tcm application codes could be
275	  re-used directly.
276
277if HAVE_TCM
278config ITCM_RAM_BASE
279	hex "ITCM ram base"
280	default 0xffffffff
281
282config ITCM_NR_PAGES
283	int "Page count of ITCM size: NR*4KB"
284	range 1 256
285	default 32
286
287config HAVE_DTCM
288	bool "DTCM Support"
289
290config DTCM_RAM_BASE
291	hex "DTCM ram base"
292	depends on HAVE_DTCM
293	default 0xffffffff
294
295config DTCM_NR_PAGES
296	int "Page count of DTCM size: NR*4KB"
297	depends on HAVE_DTCM
298	range 1 256
299	default 32
300endif
301
302config CPU_HAS_VDSP
303	bool "CPU has VDSP coprocessor"
304	depends on CPU_HAS_FPU && CPU_HAS_FPUV2
305
306config CPU_HAS_FPU
307	bool "CPU has FPU coprocessor"
308	depends on CPU_CK807 || CPU_CK810 || CPU_CK860
309
310config CPU_HAS_ICACHE_INS
311	bool "CPU has Icache invalidate instructions"
312	depends on CPU_HAS_CACHEV2
313
314config CPU_HAS_TEE
315	bool "CPU has Trusted Execution Environment"
316	depends on CPU_CK810
317
318config SMP
319	bool "Symmetric Multi-Processing (SMP) support for C-SKY"
320	depends on CPU_CK860
321	default n
322
323config NR_CPUS
324	int "Maximum number of CPUs (2-32)"
325	range 2 32
326	depends on SMP
327	default "4"
328
329config HIGHMEM
330	bool "High Memory Support"
331	depends on !CPU_CK610
332	select KMAP_LOCAL
333	default y
334
335config ARCH_FORCE_MAX_ORDER
336	int "Maximum zone order"
337	default "11"
338
339config DRAM_BASE
340	hex "DRAM start addr (the same with memory-section in dts)"
341	default 0x0
342
343config HOTPLUG_CPU
344	bool "Support for hot-pluggable CPUs"
345	select GENERIC_IRQ_MIGRATION
346	depends on SMP
347	help
348	  Say Y here to allow turning CPUs off and on. CPUs can be
349	  controlled through /sys/devices/system/cpu/cpu1/hotplug/target.
350
351	  Say N if you want to disable CPU hotplug.
352
353config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
354	bool "Enable EFFICIENT_UNALIGNED_STRING_OPS for abiv2"
355	depends on CPU_CK807 || CPU_CK810 || CPU_CK860
356	help
357	  Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
358	  deal with unaligned access by hardware.
359
360endmenu
361
362source "arch/csky/Kconfig.platforms"
363
364source "kernel/Kconfig.hz"