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1# SPDX-License-Identifier: GPL-2.0-only
2config CSKY
3 def_bool y
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_DMA_PREP_COHERENT
6 select ARCH_HAS_GCOV_PROFILE_ALL
7 select ARCH_HAS_SYNC_DMA_FOR_CPU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_QUEUED_RWLOCKS
11 select ARCH_USE_QUEUED_SPINLOCKS
12 select ARCH_HAS_CURRENT_STACK_POINTER
13 select ARCH_INLINE_READ_LOCK if !PREEMPTION
14 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
15 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
16 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
17 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
18 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
19 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
20 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
21 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
22 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
23 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
24 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
25 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
26 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
27 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
28 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
29 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
30 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
31 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
32 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
33 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
34 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
35 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
36 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
37 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
38 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
39 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
41 select COMMON_CLK
42 select CLKSRC_MMIO
43 select CSKY_MPINTC if CPU_CK860
44 select CSKY_MP_TIMER if CPU_CK860
45 select CSKY_APB_INTC
46 select DMA_DIRECT_REMAP
47 select IRQ_DOMAIN
48 select DW_APB_TIMER_OF
49 select GENERIC_IOREMAP
50 select GENERIC_LIB_ASHLDI3
51 select GENERIC_LIB_ASHRDI3
52 select GENERIC_LIB_LSHRDI3
53 select GENERIC_LIB_MULDI3
54 select GENERIC_LIB_CMPDI2
55 select GENERIC_LIB_UCMPDI2
56 select GENERIC_ALLOCATOR
57 select GENERIC_ATOMIC64
58 select GENERIC_CPU_DEVICES
59 select GENERIC_IRQ_CHIP
60 select GENERIC_IRQ_PROBE
61 select GENERIC_IRQ_SHOW
62 select GENERIC_IRQ_MULTI_HANDLER
63 select GENERIC_SCHED_CLOCK
64 select GENERIC_SMP_IDLE_THREAD
65 select GENERIC_TIME_VSYSCALL
66 select GENERIC_VDSO_32
67 select GENERIC_GETTIMEOFDAY
68 select GX6605S_TIMER if CPU_CK610
69 select HAVE_ARCH_TRACEHOOK
70 select HAVE_ARCH_AUDITSYSCALL
71 select HAVE_ARCH_JUMP_LABEL if !CPU_CK610
72 select HAVE_ARCH_JUMP_LABEL_RELATIVE
73 select HAVE_ARCH_MMAP_RND_BITS
74 select HAVE_ARCH_SECCOMP_FILTER
75 select HAVE_CONTEXT_TRACKING_USER
76 select HAVE_VIRT_CPU_ACCOUNTING_GEN
77 select HAVE_DEBUG_BUGVERBOSE
78 select HAVE_DEBUG_KMEMLEAK
79 select HAVE_DYNAMIC_FTRACE
80 select HAVE_DYNAMIC_FTRACE_WITH_REGS
81 select HAVE_GENERIC_VDSO
82 select HAVE_FUNCTION_TRACER
83 select HAVE_FUNCTION_GRAPH_TRACER
84 select HAVE_FUNCTION_ERROR_INJECTION
85 select HAVE_FTRACE_MCOUNT_RECORD
86 select HAVE_KERNEL_GZIP
87 select HAVE_KERNEL_LZO
88 select HAVE_KERNEL_LZMA
89 select HAVE_KPROBES if !CPU_CK610
90 select HAVE_KPROBES_ON_FTRACE if !CPU_CK610
91 select HAVE_KRETPROBES if !CPU_CK610
92 select HAVE_PERF_EVENTS
93 select HAVE_PERF_REGS
94 select HAVE_PERF_USER_STACK_DUMP
95 select HAVE_DMA_CONTIGUOUS
96 select HAVE_REGS_AND_STACK_ACCESS_API
97 select HAVE_STACKPROTECTOR
98 select HAVE_SYSCALL_TRACEPOINTS
99 select MAY_HAVE_SPARSE_IRQ
100 select MODULES_USE_ELF_RELA if MODULES
101 select OF
102 select OF_EARLY_FLATTREE
103 select PERF_USE_VMALLOC if CPU_CK610
104 select RTC_LIB
105 select TIMER_OF
106 select GENERIC_PCI_IOMAP
107 select HAVE_PCI
108 select PCI_DOMAINS_GENERIC if PCI
109 select PCI_SYSCALL if PCI
110 select PCI_MSI if PCI
111 select TRACE_IRQFLAGS_SUPPORT
112
113config LOCKDEP_SUPPORT
114 def_bool y
115
116config ARCH_SUPPORTS_UPROBES
117 def_bool y if !CPU_CK610
118
119config CPU_HAS_CACHEV2
120 bool
121
122config CPU_HAS_FPUV2
123 bool
124
125config CPU_HAS_HILO
126 bool
127
128config CPU_HAS_TLBI
129 bool
130
131config CPU_HAS_LDSTEX
132 bool
133 help
134 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
135
136config CPU_NEED_TLBSYNC
137 bool
138
139config CPU_NEED_SOFTALIGN
140 bool
141
142config CPU_NO_USER_BKPT
143 bool
144 help
145 For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
146 abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
147 So we need a 16bit instruction as user space bkpt, and it will cause an illegal
148 instruction exception.
149 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
150
151config GENERIC_CALIBRATE_DELAY
152 def_bool y
153
154config GENERIC_CSUM
155 def_bool y
156
157config GENERIC_HWEIGHT
158 def_bool y
159
160config MMU
161 def_bool y
162
163config STACKTRACE_SUPPORT
164 def_bool y
165
166config TIME_LOW_RES
167 def_bool y
168
169config CPU_TLB_SIZE
170 int
171 default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
172 default "1024" if (CPU_CK860)
173
174config CPU_ASID_BITS
175 int
176 default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
177 default "12" if (CPU_CK860)
178
179config L1_CACHE_SHIFT
180 int
181 default "4" if (CPU_CK610)
182 default "5" if (CPU_CK807 || CPU_CK810)
183 default "6" if (CPU_CK860)
184
185config ARCH_MMAP_RND_BITS_MIN
186 default 8
187
188# max bits determined by the following formula:
189# VA_BITS - PAGE_SHIFT - 3
190config ARCH_MMAP_RND_BITS_MAX
191 default 17
192
193menu "Processor type and features"
194
195choice
196 prompt "CPU MODEL"
197 default CPU_CK807
198
199config CPU_CK610
200 bool "CSKY CPU ck610"
201 select CPU_NEED_TLBSYNC
202 select CPU_NEED_SOFTALIGN
203 select CPU_NO_USER_BKPT
204
205config CPU_CK810
206 bool "CSKY CPU ck810"
207 select CPU_HAS_HILO
208 select CPU_NEED_TLBSYNC
209
210config CPU_CK807
211 bool "CSKY CPU ck807"
212 select CPU_HAS_HILO
213
214config CPU_CK860
215 bool "CSKY CPU ck860"
216 select CPU_HAS_TLBI
217 select CPU_HAS_CACHEV2
218 select CPU_HAS_LDSTEX
219 select CPU_HAS_FPUV2
220endchoice
221
222choice
223 prompt "PAGE OFFSET"
224 default PAGE_OFFSET_80000000
225
226config PAGE_OFFSET_80000000
227 bool "PAGE OFFSET 2G (user:kernel = 2:2)"
228
229config PAGE_OFFSET_A0000000
230 bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"
231endchoice
232
233config PAGE_OFFSET
234 hex
235 default 0x80000000 if PAGE_OFFSET_80000000
236 default 0xa0000000 if PAGE_OFFSET_A0000000
237choice
238
239 prompt "C-SKY PMU type"
240 depends on PERF_EVENTS
241 depends on CPU_CK807 || CPU_CK810 || CPU_CK860
242
243config CPU_PMU_NONE
244 bool "None"
245
246config CSKY_PMU_V1
247 bool "Performance Monitoring Unit Ver.1"
248
249endchoice
250
251choice
252 prompt "Power Manager Instruction (wait/doze/stop)"
253 default CPU_PM_NONE
254
255config CPU_PM_NONE
256 bool "None"
257
258config CPU_PM_WAIT
259 bool "wait"
260
261config CPU_PM_DOZE
262 bool "doze"
263
264config CPU_PM_STOP
265 bool "stop"
266endchoice
267
268menuconfig HAVE_TCM
269 bool "Tightly-Coupled/Sram Memory"
270 depends on !COMPILE_TEST
271 help
272 The implementation are not only used by TCM (Tightly-Coupled Memory)
273 but also used by sram on SOC bus. It follow existed linux tcm
274 software interface, so that old tcm application codes could be
275 re-used directly.
276
277if HAVE_TCM
278config ITCM_RAM_BASE
279 hex "ITCM ram base"
280 default 0xffffffff
281
282config ITCM_NR_PAGES
283 int "Page count of ITCM size: NR*4KB"
284 range 1 256
285 default 32
286
287config HAVE_DTCM
288 bool "DTCM Support"
289
290config DTCM_RAM_BASE
291 hex "DTCM ram base"
292 depends on HAVE_DTCM
293 default 0xffffffff
294
295config DTCM_NR_PAGES
296 int "Page count of DTCM size: NR*4KB"
297 depends on HAVE_DTCM
298 range 1 256
299 default 32
300endif
301
302config CPU_HAS_VDSP
303 bool "CPU has VDSP coprocessor"
304 depends on CPU_HAS_FPU && CPU_HAS_FPUV2
305
306config CPU_HAS_FPU
307 bool "CPU has FPU coprocessor"
308 depends on CPU_CK807 || CPU_CK810 || CPU_CK860
309
310config CPU_HAS_ICACHE_INS
311 bool "CPU has Icache invalidate instructions"
312 depends on CPU_HAS_CACHEV2
313
314config CPU_HAS_TEE
315 bool "CPU has Trusted Execution Environment"
316 depends on CPU_CK810
317
318config SMP
319 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
320 depends on CPU_CK860
321 default n
322
323config NR_CPUS
324 int "Maximum number of CPUs (2-32)"
325 range 2 32
326 depends on SMP
327 default "4"
328
329config HIGHMEM
330 bool "High Memory Support"
331 depends on !CPU_CK610
332 select KMAP_LOCAL
333 default y
334
335config ARCH_FORCE_MAX_ORDER
336 int "Maximum zone order"
337 default "11"
338
339config DRAM_BASE
340 hex "DRAM start addr (the same with memory-section in dts)"
341 default 0x0
342
343config HOTPLUG_CPU
344 bool "Support for hot-pluggable CPUs"
345 select GENERIC_IRQ_MIGRATION
346 depends on SMP
347 help
348 Say Y here to allow turning CPUs off and on. CPUs can be
349 controlled through /sys/devices/system/cpu/cpu1/hotplug/target.
350
351 Say N if you want to disable CPU hotplug.
352
353config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
354 bool "Enable EFFICIENT_UNALIGNED_STRING_OPS for abiv2"
355 depends on CPU_CK807 || CPU_CK810 || CPU_CK860
356 help
357 Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
358 deal with unaligned access by hardware.
359
360endmenu
361
362source "arch/csky/Kconfig.platforms"
363
364source "kernel/Kconfig.hz"
1# SPDX-License-Identifier: GPL-2.0-only
2config CSKY
3 def_bool y
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_DMA_PREP_COHERENT
6 select ARCH_HAS_GCOV_PROFILE_ALL
7 select ARCH_HAS_SYNC_DMA_FOR_CPU
8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2
11 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610
12 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
13 select COMMON_CLK
14 select CLKSRC_MMIO
15 select CSKY_MPINTC if CPU_CK860
16 select CSKY_MP_TIMER if CPU_CK860
17 select CSKY_APB_INTC
18 select DMA_DIRECT_REMAP
19 select IRQ_DOMAIN
20 select HANDLE_DOMAIN_IRQ
21 select DW_APB_TIMER_OF
22 select GENERIC_IOREMAP
23 select GENERIC_LIB_ASHLDI3
24 select GENERIC_LIB_ASHRDI3
25 select GENERIC_LIB_LSHRDI3
26 select GENERIC_LIB_MULDI3
27 select GENERIC_LIB_CMPDI2
28 select GENERIC_LIB_UCMPDI2
29 select GENERIC_ALLOCATOR
30 select GENERIC_ATOMIC64
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CPU_DEVICES
33 select GENERIC_IRQ_CHIP
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
36 select GENERIC_IRQ_MULTI_HANDLER
37 select GENERIC_SCHED_CLOCK
38 select GENERIC_SMP_IDLE_THREAD
39 select GX6605S_TIMER if CPU_CK610
40 select HAVE_ARCH_TRACEHOOK
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_MMAP_RND_BITS
43 select HAVE_ARCH_SECCOMP_FILTER
44 select HAVE_CONTEXT_TRACKING
45 select HAVE_VIRT_CPU_ACCOUNTING_GEN
46 select HAVE_DEBUG_BUGVERBOSE
47 select HAVE_DYNAMIC_FTRACE
48 select HAVE_DYNAMIC_FTRACE_WITH_REGS
49 select HAVE_FUNCTION_TRACER
50 select HAVE_FUNCTION_GRAPH_TRACER
51 select HAVE_FUNCTION_ERROR_INJECTION
52 select HAVE_FTRACE_MCOUNT_RECORD
53 select HAVE_KERNEL_GZIP
54 select HAVE_KERNEL_LZO
55 select HAVE_KERNEL_LZMA
56 select HAVE_KPROBES if !CPU_CK610
57 select HAVE_KPROBES_ON_FTRACE if !CPU_CK610
58 select HAVE_KRETPROBES if !CPU_CK610
59 select HAVE_PERF_EVENTS
60 select HAVE_PERF_REGS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_DMA_CONTIGUOUS
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_RSEQ
65 select HAVE_STACKPROTECTOR
66 select HAVE_SYSCALL_TRACEPOINTS
67 select MAY_HAVE_SPARSE_IRQ
68 select MODULES_USE_ELF_RELA if MODULES
69 select OF
70 select OF_EARLY_FLATTREE
71 select PERF_USE_VMALLOC if CPU_CK610
72 select RTC_LIB
73 select TIMER_OF
74 select USB_ARCH_HAS_EHCI
75 select USB_ARCH_HAS_OHCI
76 select GENERIC_PCI_IOMAP
77 select HAVE_PCI
78 select PCI_DOMAINS_GENERIC if PCI
79 select PCI_SYSCALL if PCI
80 select PCI_MSI if PCI
81
82config LOCKDEP_SUPPORT
83 def_bool y
84
85config ARCH_SUPPORTS_UPROBES
86 def_bool y if !CPU_CK610
87
88config CPU_HAS_CACHEV2
89 bool
90
91config CPU_HAS_FPUV2
92 bool
93
94config CPU_HAS_HILO
95 bool
96
97config CPU_HAS_TLBI
98 bool
99
100config CPU_HAS_LDSTEX
101 bool
102 help
103 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
104
105config CPU_NEED_TLBSYNC
106 bool
107
108config CPU_NEED_SOFTALIGN
109 bool
110
111config CPU_NO_USER_BKPT
112 bool
113 help
114 For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
115 abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
116 So we need a 16bit instruction as user space bkpt, and it will cause an illegal
117 instruction exception.
118 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
119
120config GENERIC_CALIBRATE_DELAY
121 def_bool y
122
123config GENERIC_CSUM
124 def_bool y
125
126config GENERIC_HWEIGHT
127 def_bool y
128
129config MMU
130 def_bool y
131
132config STACKTRACE_SUPPORT
133 def_bool y
134
135config TIME_LOW_RES
136 def_bool y
137
138config TRACE_IRQFLAGS_SUPPORT
139 def_bool y
140
141config CPU_TLB_SIZE
142 int
143 default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
144 default "1024" if (CPU_CK860)
145
146config CPU_ASID_BITS
147 int
148 default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
149 default "12" if (CPU_CK860)
150
151config L1_CACHE_SHIFT
152 int
153 default "4" if (CPU_CK610)
154 default "5" if (CPU_CK807 || CPU_CK810)
155 default "6" if (CPU_CK860)
156
157config ARCH_MMAP_RND_BITS_MIN
158 default 8
159
160# max bits determined by the following formula:
161# VA_BITS - PAGE_SHIFT - 3
162config ARCH_MMAP_RND_BITS_MAX
163 default 17
164
165menu "Processor type and features"
166
167choice
168 prompt "CPU MODEL"
169 default CPU_CK807
170
171config CPU_CK610
172 bool "CSKY CPU ck610"
173 select CPU_NEED_TLBSYNC
174 select CPU_NEED_SOFTALIGN
175 select CPU_NO_USER_BKPT
176
177config CPU_CK810
178 bool "CSKY CPU ck810"
179 select CPU_HAS_HILO
180 select CPU_NEED_TLBSYNC
181
182config CPU_CK807
183 bool "CSKY CPU ck807"
184 select CPU_HAS_HILO
185
186config CPU_CK860
187 bool "CSKY CPU ck860"
188 select CPU_HAS_TLBI
189 select CPU_HAS_CACHEV2
190 select CPU_HAS_LDSTEX
191 select CPU_HAS_FPUV2
192endchoice
193
194choice
195 prompt "C-SKY PMU type"
196 depends on PERF_EVENTS
197 depends on CPU_CK807 || CPU_CK810 || CPU_CK860
198
199config CPU_PMU_NONE
200 bool "None"
201
202config CSKY_PMU_V1
203 bool "Performance Monitoring Unit Ver.1"
204
205endchoice
206
207choice
208 prompt "Power Manager Instruction (wait/doze/stop)"
209 default CPU_PM_NONE
210
211config CPU_PM_NONE
212 bool "None"
213
214config CPU_PM_WAIT
215 bool "wait"
216
217config CPU_PM_DOZE
218 bool "doze"
219
220config CPU_PM_STOP
221 bool "stop"
222endchoice
223
224menuconfig HAVE_TCM
225 bool "Tightly-Coupled/Sram Memory"
226 select GENERIC_ALLOCATOR
227 help
228 The implementation are not only used by TCM (Tightly-Coupled Meory)
229 but also used by sram on SOC bus. It follow existed linux tcm
230 software interface, so that old tcm application codes could be
231 re-used directly.
232
233if HAVE_TCM
234config ITCM_RAM_BASE
235 hex "ITCM ram base"
236 default 0xffffffff
237
238config ITCM_NR_PAGES
239 int "Page count of ITCM size: NR*4KB"
240 range 1 256
241 default 32
242
243config HAVE_DTCM
244 bool "DTCM Support"
245
246config DTCM_RAM_BASE
247 hex "DTCM ram base"
248 depends on HAVE_DTCM
249 default 0xffffffff
250
251config DTCM_NR_PAGES
252 int "Page count of DTCM size: NR*4KB"
253 depends on HAVE_DTCM
254 range 1 256
255 default 32
256endif
257
258config CPU_HAS_VDSP
259 bool "CPU has VDSP coprocessor"
260 depends on CPU_HAS_FPU && CPU_HAS_FPUV2
261
262config CPU_HAS_FPU
263 bool "CPU has FPU coprocessor"
264 depends on CPU_CK807 || CPU_CK810 || CPU_CK860
265
266config CPU_HAS_ICACHE_INS
267 bool "CPU has Icache invalidate instructions"
268 depends on CPU_HAS_CACHEV2
269
270config CPU_HAS_TEE
271 bool "CPU has Trusted Execution Environment"
272 depends on CPU_CK810
273
274config SMP
275 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
276 depends on CPU_CK860
277 default n
278
279config NR_CPUS
280 int "Maximum number of CPUs (2-32)"
281 range 2 32
282 depends on SMP
283 default "4"
284
285config HIGHMEM
286 bool "High Memory Support"
287 depends on !CPU_CK610
288 default y
289
290config FORCE_MAX_ZONEORDER
291 int "Maximum zone order"
292 default "11"
293
294config RAM_BASE
295 hex "DRAM start addr (the same with memory-section in dts)"
296 default 0x0
297
298config HOTPLUG_CPU
299 bool "Support for hot-pluggable CPUs"
300 select GENERIC_IRQ_MIGRATION
301 depends on SMP
302 help
303 Say Y here to allow turning CPUs off and on. CPUs can be
304 controlled through /sys/devices/system/cpu/cpu1/hotplug/target.
305
306 Say N if you want to disable CPU hotplug.
307endmenu
308
309source "arch/csky/Kconfig.platforms"
310
311source "kernel/Kconfig.hz"
312
313config SECCOMP
314 bool "Enable seccomp to safely compute untrusted bytecode"
315 help
316 This kernel feature is useful for number crunching applications
317 that may need to compute untrusted bytecode during their
318 execution. By using pipes or other transports made available to
319 the process as file descriptors supporting the read/write
320 syscalls, it's possible to isolate those applications in
321 their own address space using seccomp. Once seccomp is
322 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
323 and the task is only allowed to execute a few safe syscalls
324 defined by each seccomp mode.