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1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/pm_runtime.h>
26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
29#include <linux/platform_data/davinci_asp.h>
30#include <linux/math64.h>
31
32#include <sound/asoundef.h>
33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
38#include <sound/dmaengine_pcm.h>
39#include <sound/omap-pcm.h>
40
41#include "edma-pcm.h"
42#include "davinci-mcasp.h"
43
44#define MCASP_MAX_AFIFO_DEPTH 64
45
46static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
60};
61
62struct davinci_mcasp_context {
63 u32 config_regs[ARRAY_SIZE(context_regs)];
64 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
66 bool pm_state;
67};
68
69struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
74struct davinci_mcasp {
75 struct snd_dmaengine_dai_dma_data dma_data[2];
76 void __iomem *base;
77 u32 fifo_base;
78 struct device *dev;
79 struct snd_pcm_substream *substreams[2];
80 unsigned int dai_fmt;
81
82 /* McASP specific data */
83 int tdm_slots;
84 u32 tdm_mask[2];
85 int slot_width;
86 u8 op_mode;
87 u8 num_serializer;
88 u8 *serial_dir;
89 u8 version;
90 u8 bclk_div;
91 int streams;
92 u32 irq_request[2];
93 int dma_request[2];
94
95 int sysclk_freq;
96 bool bclk_master;
97
98 /* McASP FIFO related */
99 u8 txnumevt;
100 u8 rxnumevt;
101
102 bool dat_port;
103
104 /* Used for comstraint setting on the second stream */
105 u32 channels;
106
107#ifdef CONFIG_PM_SLEEP
108 struct davinci_mcasp_context context;
109#endif
110
111 struct davinci_mcasp_ruledata ruledata[2];
112 struct snd_pcm_hw_constraint_list chconstr[2];
113};
114
115static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
116 u32 val)
117{
118 void __iomem *reg = mcasp->base + offset;
119 __raw_writel(__raw_readl(reg) | val, reg);
120}
121
122static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
123 u32 val)
124{
125 void __iomem *reg = mcasp->base + offset;
126 __raw_writel((__raw_readl(reg) & ~(val)), reg);
127}
128
129static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
130 u32 val, u32 mask)
131{
132 void __iomem *reg = mcasp->base + offset;
133 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
134}
135
136static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
137 u32 val)
138{
139 __raw_writel(val, mcasp->base + offset);
140}
141
142static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
143{
144 return (u32)__raw_readl(mcasp->base + offset);
145}
146
147static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
148{
149 int i = 0;
150
151 mcasp_set_bits(mcasp, ctl_reg, val);
152
153 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
154 /* loop count is to avoid the lock-up */
155 for (i = 0; i < 1000; i++) {
156 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
157 break;
158 }
159
160 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
161 printk(KERN_ERR "GBLCTL write error\n");
162}
163
164static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
165{
166 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
167 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
168
169 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
170}
171
172static void mcasp_start_rx(struct davinci_mcasp *mcasp)
173{
174 if (mcasp->rxnumevt) { /* enable FIFO */
175 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
176
177 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
178 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
179 }
180
181 /* Start clocks */
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
184 /*
185 * When ASYNC == 0 the transmit and receive sections operate
186 * synchronously from the transmit clock and frame sync. We need to make
187 * sure that the TX signlas are enabled when starting reception.
188 */
189 if (mcasp_is_synchronous(mcasp)) {
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
192 }
193
194 /* Activate serializer(s) */
195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
196 /* Release RX state machine */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
198 /* Release Frame Sync generator */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
200 if (mcasp_is_synchronous(mcasp))
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
202
203 /* enable receive IRQs */
204 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
205 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
206}
207
208static void mcasp_start_tx(struct davinci_mcasp *mcasp)
209{
210 u32 cnt;
211
212 if (mcasp->txnumevt) { /* enable FIFO */
213 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
214
215 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
216 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
217 }
218
219 /* Start clocks */
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
222 /* Activate serializer(s) */
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
224
225 /* wait for XDATA to be cleared */
226 cnt = 0;
227 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
228 (cnt < 100000))
229 cnt++;
230
231 /* Release TX state machine */
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
233 /* Release Frame Sync generator */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
235
236 /* enable transmit IRQs */
237 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
238 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
239}
240
241static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
242{
243 mcasp->streams++;
244
245 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
246 mcasp_start_tx(mcasp);
247 else
248 mcasp_start_rx(mcasp);
249}
250
251static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
252{
253 /* disable IRQ sources */
254 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
255 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
256
257 /*
258 * In synchronous mode stop the TX clocks if no other stream is
259 * running
260 */
261 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
263
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
265 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
266
267 if (mcasp->rxnumevt) { /* disable FIFO */
268 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
269
270 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
271 }
272}
273
274static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
275{
276 u32 val = 0;
277
278 /* disable IRQ sources */
279 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
280 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
281
282 /*
283 * In synchronous mode keep TX clocks running if the capture stream is
284 * still running.
285 */
286 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
287 val = TXHCLKRST | TXCLKRST | TXFSRST;
288
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
290 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
291
292 if (mcasp->txnumevt) { /* disable FIFO */
293 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
294
295 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
296 }
297}
298
299static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
300{
301 mcasp->streams--;
302
303 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
304 mcasp_stop_tx(mcasp);
305 else
306 mcasp_stop_rx(mcasp);
307}
308
309static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
310{
311 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
312 struct snd_pcm_substream *substream;
313 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
314 u32 handled_mask = 0;
315 u32 stat;
316
317 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
318 if (stat & XUNDRN & irq_mask) {
319 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
320 handled_mask |= XUNDRN;
321
322 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
323 if (substream) {
324 snd_pcm_stream_lock_irq(substream);
325 if (snd_pcm_running(substream))
326 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
327 snd_pcm_stream_unlock_irq(substream);
328 }
329 }
330
331 if (!handled_mask)
332 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
333 stat);
334
335 if (stat & XRERR)
336 handled_mask |= XRERR;
337
338 /* Ack the handled event only */
339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
340
341 return IRQ_RETVAL(handled_mask);
342}
343
344static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
345{
346 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
347 struct snd_pcm_substream *substream;
348 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
349 u32 handled_mask = 0;
350 u32 stat;
351
352 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
353 if (stat & ROVRN & irq_mask) {
354 dev_warn(mcasp->dev, "Receive buffer overflow\n");
355 handled_mask |= ROVRN;
356
357 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
358 if (substream) {
359 snd_pcm_stream_lock_irq(substream);
360 if (snd_pcm_running(substream))
361 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
362 snd_pcm_stream_unlock_irq(substream);
363 }
364 }
365
366 if (!handled_mask)
367 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
368 stat);
369
370 if (stat & XRERR)
371 handled_mask |= XRERR;
372
373 /* Ack the handled event only */
374 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
375
376 return IRQ_RETVAL(handled_mask);
377}
378
379static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
380{
381 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
382 irqreturn_t ret = IRQ_NONE;
383
384 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
385 ret = davinci_mcasp_tx_irq_handler(irq, data);
386
387 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
388 ret |= davinci_mcasp_rx_irq_handler(irq, data);
389
390 return ret;
391}
392
393static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
394 unsigned int fmt)
395{
396 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
397 int ret = 0;
398 u32 data_delay;
399 bool fs_pol_rising;
400 bool inv_fs = false;
401
402 if (!fmt)
403 return 0;
404
405 pm_runtime_get_sync(mcasp->dev);
406 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
407 case SND_SOC_DAIFMT_DSP_A:
408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
410 /* 1st data bit occur one ACLK cycle after the frame sync */
411 data_delay = 1;
412 break;
413 case SND_SOC_DAIFMT_DSP_B:
414 case SND_SOC_DAIFMT_AC97:
415 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
416 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
417 /* No delay after FS */
418 data_delay = 0;
419 break;
420 case SND_SOC_DAIFMT_I2S:
421 /* configure a full-word SYNC pulse (LRCLK) */
422 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
423 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
424 /* 1st data bit occur one ACLK cycle after the frame sync */
425 data_delay = 1;
426 /* FS need to be inverted */
427 inv_fs = true;
428 break;
429 case SND_SOC_DAIFMT_LEFT_J:
430 /* configure a full-word SYNC pulse (LRCLK) */
431 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
432 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
433 /* No delay after FS */
434 data_delay = 0;
435 break;
436 default:
437 ret = -EINVAL;
438 goto out;
439 }
440
441 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
442 FSXDLY(3));
443 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
444 FSRDLY(3));
445
446 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
447 case SND_SOC_DAIFMT_CBS_CFS:
448 /* codec is clock and frame slave */
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
451
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
453 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
454
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
457 mcasp->bclk_master = 1;
458 break;
459 case SND_SOC_DAIFMT_CBS_CFM:
460 /* codec is clock slave and frame master */
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
463
464 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
465 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
466
467 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
469 mcasp->bclk_master = 1;
470 break;
471 case SND_SOC_DAIFMT_CBM_CFS:
472 /* codec is clock master and frame slave */
473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
475
476 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
477 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
478
479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
480 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
481 mcasp->bclk_master = 0;
482 break;
483 case SND_SOC_DAIFMT_CBM_CFM:
484 /* codec is clock and frame master */
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
487
488 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
489 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
490
491 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
492 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
493 mcasp->bclk_master = 0;
494 break;
495 default:
496 ret = -EINVAL;
497 goto out;
498 }
499
500 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
501 case SND_SOC_DAIFMT_IB_NF:
502 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
503 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
504 fs_pol_rising = true;
505 break;
506 case SND_SOC_DAIFMT_NB_IF:
507 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
508 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
509 fs_pol_rising = false;
510 break;
511 case SND_SOC_DAIFMT_IB_IF:
512 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
513 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
514 fs_pol_rising = false;
515 break;
516 case SND_SOC_DAIFMT_NB_NF:
517 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
518 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
519 fs_pol_rising = true;
520 break;
521 default:
522 ret = -EINVAL;
523 goto out;
524 }
525
526 if (inv_fs)
527 fs_pol_rising = !fs_pol_rising;
528
529 if (fs_pol_rising) {
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
531 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
532 } else {
533 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
535 }
536
537 mcasp->dai_fmt = fmt;
538out:
539 pm_runtime_put(mcasp->dev);
540 return ret;
541}
542
543static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
544 int div, bool explicit)
545{
546 pm_runtime_get_sync(mcasp->dev);
547 switch (div_id) {
548 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
550 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
552 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
553 break;
554
555 case MCASP_CLKDIV_BCLK: /* BCLK divider */
556 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
557 ACLKXDIV(div - 1), ACLKXDIV_MASK);
558 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
559 ACLKRDIV(div - 1), ACLKRDIV_MASK);
560 if (explicit)
561 mcasp->bclk_div = div;
562 break;
563
564 case MCASP_CLKDIV_BCLK_FS_RATIO:
565 /*
566 * BCLK/LRCLK ratio descries how many bit-clock cycles
567 * fit into one frame. The clock ratio is given for a
568 * full period of data (for I2S format both left and
569 * right channels), so it has to be divided by number
570 * of tdm-slots (for I2S - divided by 2).
571 * Instead of storing this ratio, we calculate a new
572 * tdm_slot width by dividing the the ratio by the
573 * number of configured tdm slots.
574 */
575 mcasp->slot_width = div / mcasp->tdm_slots;
576 if (div % mcasp->tdm_slots)
577 dev_warn(mcasp->dev,
578 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
579 __func__, div, mcasp->tdm_slots);
580 break;
581
582 default:
583 return -EINVAL;
584 }
585
586 pm_runtime_put(mcasp->dev);
587 return 0;
588}
589
590static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
591 int div)
592{
593 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
594
595 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
596}
597
598static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
599 unsigned int freq, int dir)
600{
601 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
602
603 pm_runtime_get_sync(mcasp->dev);
604 if (dir == SND_SOC_CLOCK_OUT) {
605 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
606 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
607 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
608 } else {
609 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
610 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
611 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
612 }
613
614 mcasp->sysclk_freq = freq;
615
616 pm_runtime_put(mcasp->dev);
617 return 0;
618}
619
620/* All serializers must have equal number of channels */
621static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
622 int serializers)
623{
624 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
625 unsigned int *list = (unsigned int *) cl->list;
626 int slots = mcasp->tdm_slots;
627 int i, count = 0;
628
629 if (mcasp->tdm_mask[stream])
630 slots = hweight32(mcasp->tdm_mask[stream]);
631
632 for (i = 1; i <= slots; i++)
633 list[count++] = i;
634
635 for (i = 2; i <= serializers; i++)
636 list[count++] = i*slots;
637
638 cl->count = count;
639
640 return 0;
641}
642
643static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
644{
645 int rx_serializers = 0, tx_serializers = 0, ret, i;
646
647 for (i = 0; i < mcasp->num_serializer; i++)
648 if (mcasp->serial_dir[i] == TX_MODE)
649 tx_serializers++;
650 else if (mcasp->serial_dir[i] == RX_MODE)
651 rx_serializers++;
652
653 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
654 tx_serializers);
655 if (ret)
656 return ret;
657
658 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
659 rx_serializers);
660
661 return ret;
662}
663
664
665static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
666 unsigned int tx_mask,
667 unsigned int rx_mask,
668 int slots, int slot_width)
669{
670 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
671
672 dev_dbg(mcasp->dev,
673 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
674 __func__, tx_mask, rx_mask, slots, slot_width);
675
676 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
677 dev_err(mcasp->dev,
678 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
679 tx_mask, rx_mask, slots);
680 return -EINVAL;
681 }
682
683 if (slot_width &&
684 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
685 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
686 __func__, slot_width);
687 return -EINVAL;
688 }
689
690 mcasp->tdm_slots = slots;
691 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
692 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
693 mcasp->slot_width = slot_width;
694
695 return davinci_mcasp_set_ch_constraints(mcasp);
696}
697
698static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
699 int sample_width)
700{
701 u32 fmt;
702 u32 tx_rotate = (sample_width / 4) & 0x7;
703 u32 mask = (1ULL << sample_width) - 1;
704 u32 slot_width = sample_width;
705
706 /*
707 * For captured data we should not rotate, inversion and masking is
708 * enoguh to get the data to the right position:
709 * Format data from bus after reverse (XRBUF)
710 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
711 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
712 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
713 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
714 */
715 u32 rx_rotate = 0;
716
717 /*
718 * Setting the tdm slot width either with set_clkdiv() or
719 * set_tdm_slot() allows us to for example send 32 bits per
720 * channel to the codec, while only 16 of them carry audio
721 * payload.
722 */
723 if (mcasp->slot_width) {
724 /*
725 * When we have more bclk then it is needed for the
726 * data, we need to use the rotation to move the
727 * received samples to have correct alignment.
728 */
729 slot_width = mcasp->slot_width;
730 rx_rotate = (slot_width - sample_width) / 4;
731 }
732
733 /* mapping of the XSSZ bit-field as described in the datasheet */
734 fmt = (slot_width >> 1) - 1;
735
736 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
737 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
738 RXSSZ(0x0F));
739 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
740 TXSSZ(0x0F));
741 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
742 TXROT(7));
743 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
744 RXROT(7));
745 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
746 }
747
748 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
749
750 return 0;
751}
752
753static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
754 int period_words, int channels)
755{
756 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
757 int i;
758 u8 tx_ser = 0;
759 u8 rx_ser = 0;
760 u8 slots = mcasp->tdm_slots;
761 u8 max_active_serializers = (channels + slots - 1) / slots;
762 int active_serializers, numevt;
763 u32 reg;
764 /* Default configuration */
765 if (mcasp->version < MCASP_VERSION_3)
766 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
767
768 /* All PINS as McASP */
769 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
770
771 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
772 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
773 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
774 } else {
775 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
776 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
777 }
778
779 for (i = 0; i < mcasp->num_serializer; i++) {
780 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
781 mcasp->serial_dir[i]);
782 if (mcasp->serial_dir[i] == TX_MODE &&
783 tx_ser < max_active_serializers) {
784 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
785 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
786 DISMOD_LOW, DISMOD_MASK);
787 tx_ser++;
788 } else if (mcasp->serial_dir[i] == RX_MODE &&
789 rx_ser < max_active_serializers) {
790 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
791 rx_ser++;
792 } else {
793 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
794 SRMOD_INACTIVE, SRMOD_MASK);
795 }
796 }
797
798 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
799 active_serializers = tx_ser;
800 numevt = mcasp->txnumevt;
801 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
802 } else {
803 active_serializers = rx_ser;
804 numevt = mcasp->rxnumevt;
805 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
806 }
807
808 if (active_serializers < max_active_serializers) {
809 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
810 "enabled in mcasp (%d)\n", channels,
811 active_serializers * slots);
812 return -EINVAL;
813 }
814
815 /* AFIFO is not in use */
816 if (!numevt) {
817 /* Configure the burst size for platform drivers */
818 if (active_serializers > 1) {
819 /*
820 * If more than one serializers are in use we have one
821 * DMA request to provide data for all serializers.
822 * For example if three serializers are enabled the DMA
823 * need to transfer three words per DMA request.
824 */
825 dma_data->maxburst = active_serializers;
826 } else {
827 dma_data->maxburst = 0;
828 }
829 return 0;
830 }
831
832 if (period_words % active_serializers) {
833 dev_err(mcasp->dev, "Invalid combination of period words and "
834 "active serializers: %d, %d\n", period_words,
835 active_serializers);
836 return -EINVAL;
837 }
838
839 /*
840 * Calculate the optimal AFIFO depth for platform side:
841 * The number of words for numevt need to be in steps of active
842 * serializers.
843 */
844 numevt = (numevt / active_serializers) * active_serializers;
845
846 while (period_words % numevt && numevt > 0)
847 numevt -= active_serializers;
848 if (numevt <= 0)
849 numevt = active_serializers;
850
851 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
852 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
853
854 /* Configure the burst size for platform drivers */
855 if (numevt == 1)
856 numevt = 0;
857 dma_data->maxburst = numevt;
858
859 return 0;
860}
861
862static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
863 int channels)
864{
865 int i, active_slots;
866 int total_slots;
867 int active_serializers;
868 u32 mask = 0;
869 u32 busel = 0;
870
871 total_slots = mcasp->tdm_slots;
872
873 /*
874 * If more than one serializer is needed, then use them with
875 * all the specified tdm_slots. Otherwise, one serializer can
876 * cope with the transaction using just as many slots as there
877 * are channels in the stream.
878 */
879 if (mcasp->tdm_mask[stream]) {
880 active_slots = hweight32(mcasp->tdm_mask[stream]);
881 active_serializers = (channels + active_slots - 1) /
882 active_slots;
883 if (active_serializers == 1) {
884 active_slots = channels;
885 for (i = 0; i < total_slots; i++) {
886 if ((1 << i) & mcasp->tdm_mask[stream]) {
887 mask |= (1 << i);
888 if (--active_slots <= 0)
889 break;
890 }
891 }
892 }
893 } else {
894 active_serializers = (channels + total_slots - 1) / total_slots;
895 if (active_serializers == 1)
896 active_slots = channels;
897 else
898 active_slots = total_slots;
899
900 for (i = 0; i < active_slots; i++)
901 mask |= (1 << i);
902 }
903 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
904
905 if (!mcasp->dat_port)
906 busel = TXSEL;
907
908 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
909 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
910 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
911 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
912 FSXMOD(total_slots), FSXMOD(0x1FF));
913 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
914 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
915 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
916 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
917 FSRMOD(total_slots), FSRMOD(0x1FF));
918 /*
919 * If McASP is set to be TX/RX synchronous and the playback is
920 * not running already we need to configure the TX slots in
921 * order to have correct FSX on the bus
922 */
923 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
924 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
925 FSXMOD(total_slots), FSXMOD(0x1FF));
926 }
927
928 return 0;
929}
930
931/* S/PDIF */
932static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
933 unsigned int rate)
934{
935 u32 cs_value = 0;
936 u8 *cs_bytes = (u8*) &cs_value;
937
938 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
939 and LSB first */
940 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
941
942 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
943 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
944
945 /* Set the TX tdm : for all the slots */
946 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
947
948 /* Set the TX clock controls : div = 1 and internal */
949 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
950
951 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
952
953 /* Only 44100 and 48000 are valid, both have the same setting */
954 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
955
956 /* Enable the DIT */
957 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
958
959 /* Set S/PDIF channel status bits */
960 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
961 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
962
963 switch (rate) {
964 case 22050:
965 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
966 break;
967 case 24000:
968 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
969 break;
970 case 32000:
971 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
972 break;
973 case 44100:
974 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
975 break;
976 case 48000:
977 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
978 break;
979 case 88200:
980 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
981 break;
982 case 96000:
983 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
984 break;
985 case 176400:
986 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
987 break;
988 case 192000:
989 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
990 break;
991 default:
992 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
993 return -EINVAL;
994 }
995
996 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
997 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
998
999 return 0;
1000}
1001
1002static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1003 unsigned int bclk_freq, bool set)
1004{
1005 int error_ppm;
1006 unsigned int sysclk_freq = mcasp->sysclk_freq;
1007 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1008 int div = sysclk_freq / bclk_freq;
1009 int rem = sysclk_freq % bclk_freq;
1010 int aux_div = 1;
1011
1012 if (div > (ACLKXDIV_MASK + 1)) {
1013 if (reg & AHCLKXE) {
1014 aux_div = div / (ACLKXDIV_MASK + 1);
1015 if (div % (ACLKXDIV_MASK + 1))
1016 aux_div++;
1017
1018 sysclk_freq /= aux_div;
1019 div = sysclk_freq / bclk_freq;
1020 rem = sysclk_freq % bclk_freq;
1021 } else if (set) {
1022 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1023 sysclk_freq);
1024 }
1025 }
1026
1027 if (rem != 0) {
1028 if (div == 0 ||
1029 ((sysclk_freq / div) - bclk_freq) >
1030 (bclk_freq - (sysclk_freq / (div+1)))) {
1031 div++;
1032 rem = rem - bclk_freq;
1033 }
1034 }
1035 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1036 (int)bclk_freq)) / div - 1000000;
1037
1038 if (set) {
1039 if (error_ppm)
1040 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1041 error_ppm);
1042
1043 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1044 if (reg & AHCLKXE)
1045 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1046 aux_div, 0);
1047 }
1048
1049 return error_ppm;
1050}
1051
1052static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1053 struct snd_pcm_hw_params *params,
1054 struct snd_soc_dai *cpu_dai)
1055{
1056 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1057 int word_length;
1058 int channels = params_channels(params);
1059 int period_size = params_period_size(params);
1060 int ret;
1061
1062 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1063 if (ret)
1064 return ret;
1065
1066 /*
1067 * If mcasp is BCLK master, and a BCLK divider was not provided by
1068 * the machine driver, we need to calculate the ratio.
1069 */
1070 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1071 int slots = mcasp->tdm_slots;
1072 int rate = params_rate(params);
1073 int sbits = params_width(params);
1074
1075 if (mcasp->slot_width)
1076 sbits = mcasp->slot_width;
1077
1078 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1079 }
1080
1081 ret = mcasp_common_hw_param(mcasp, substream->stream,
1082 period_size * channels, channels);
1083 if (ret)
1084 return ret;
1085
1086 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1087 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1088 else
1089 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1090 channels);
1091
1092 if (ret)
1093 return ret;
1094
1095 switch (params_format(params)) {
1096 case SNDRV_PCM_FORMAT_U8:
1097 case SNDRV_PCM_FORMAT_S8:
1098 word_length = 8;
1099 break;
1100
1101 case SNDRV_PCM_FORMAT_U16_LE:
1102 case SNDRV_PCM_FORMAT_S16_LE:
1103 word_length = 16;
1104 break;
1105
1106 case SNDRV_PCM_FORMAT_U24_3LE:
1107 case SNDRV_PCM_FORMAT_S24_3LE:
1108 word_length = 24;
1109 break;
1110
1111 case SNDRV_PCM_FORMAT_U24_LE:
1112 case SNDRV_PCM_FORMAT_S24_LE:
1113 word_length = 24;
1114 break;
1115
1116 case SNDRV_PCM_FORMAT_U32_LE:
1117 case SNDRV_PCM_FORMAT_S32_LE:
1118 word_length = 32;
1119 break;
1120
1121 default:
1122 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1123 return -EINVAL;
1124 }
1125
1126 davinci_config_channel_size(mcasp, word_length);
1127
1128 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1129 mcasp->channels = channels;
1130
1131 return 0;
1132}
1133
1134static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1135 int cmd, struct snd_soc_dai *cpu_dai)
1136{
1137 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1138 int ret = 0;
1139
1140 switch (cmd) {
1141 case SNDRV_PCM_TRIGGER_RESUME:
1142 case SNDRV_PCM_TRIGGER_START:
1143 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1144 davinci_mcasp_start(mcasp, substream->stream);
1145 break;
1146 case SNDRV_PCM_TRIGGER_SUSPEND:
1147 case SNDRV_PCM_TRIGGER_STOP:
1148 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1149 davinci_mcasp_stop(mcasp, substream->stream);
1150 break;
1151
1152 default:
1153 ret = -EINVAL;
1154 }
1155
1156 return ret;
1157}
1158
1159static const unsigned int davinci_mcasp_dai_rates[] = {
1160 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1161 88200, 96000, 176400, 192000,
1162};
1163
1164#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1165
1166static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1167 struct snd_pcm_hw_rule *rule)
1168{
1169 struct davinci_mcasp_ruledata *rd = rule->private;
1170 struct snd_interval *ri =
1171 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1172 int sbits = params_width(params);
1173 int slots = rd->mcasp->tdm_slots;
1174 struct snd_interval range;
1175 int i;
1176
1177 if (rd->mcasp->slot_width)
1178 sbits = rd->mcasp->slot_width;
1179
1180 snd_interval_any(&range);
1181 range.empty = 1;
1182
1183 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1184 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1185 uint bclk_freq = sbits*slots*
1186 davinci_mcasp_dai_rates[i];
1187 int ppm;
1188
1189 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1190 false);
1191 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1192 if (range.empty) {
1193 range.min = davinci_mcasp_dai_rates[i];
1194 range.empty = 0;
1195 }
1196 range.max = davinci_mcasp_dai_rates[i];
1197 }
1198 }
1199 }
1200
1201 dev_dbg(rd->mcasp->dev,
1202 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1203 ri->min, ri->max, range.min, range.max, sbits, slots);
1204
1205 return snd_interval_refine(hw_param_interval(params, rule->var),
1206 &range);
1207}
1208
1209static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1210 struct snd_pcm_hw_rule *rule)
1211{
1212 struct davinci_mcasp_ruledata *rd = rule->private;
1213 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1214 struct snd_mask nfmt;
1215 int rate = params_rate(params);
1216 int slots = rd->mcasp->tdm_slots;
1217 int i, count = 0;
1218
1219 snd_mask_none(&nfmt);
1220
1221 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1222 if (snd_mask_test(fmt, i)) {
1223 uint sbits = snd_pcm_format_width(i);
1224 int ppm;
1225
1226 if (rd->mcasp->slot_width)
1227 sbits = rd->mcasp->slot_width;
1228
1229 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1230 sbits * slots * rate,
1231 false);
1232 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1233 snd_mask_set(&nfmt, i);
1234 count++;
1235 }
1236 }
1237 }
1238 dev_dbg(rd->mcasp->dev,
1239 "%d possible sample format for %d Hz and %d tdm slots\n",
1240 count, rate, slots);
1241
1242 return snd_mask_refine(fmt, &nfmt);
1243}
1244
1245static int davinci_mcasp_hw_rule_min_periodsize(
1246 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1247{
1248 struct snd_interval *period_size = hw_param_interval(params,
1249 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1250 struct snd_interval frames;
1251
1252 snd_interval_any(&frames);
1253 frames.min = 64;
1254 frames.integer = 1;
1255
1256 return snd_interval_refine(period_size, &frames);
1257}
1258
1259static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1260 struct snd_soc_dai *cpu_dai)
1261{
1262 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1263 struct davinci_mcasp_ruledata *ruledata =
1264 &mcasp->ruledata[substream->stream];
1265 u32 max_channels = 0;
1266 int i, dir;
1267 int tdm_slots = mcasp->tdm_slots;
1268
1269 /* Do not allow more then one stream per direction */
1270 if (mcasp->substreams[substream->stream])
1271 return -EBUSY;
1272
1273 mcasp->substreams[substream->stream] = substream;
1274
1275 if (mcasp->tdm_mask[substream->stream])
1276 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1277
1278 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1279 return 0;
1280
1281 /*
1282 * Limit the maximum allowed channels for the first stream:
1283 * number of serializers for the direction * tdm slots per serializer
1284 */
1285 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1286 dir = TX_MODE;
1287 else
1288 dir = RX_MODE;
1289
1290 for (i = 0; i < mcasp->num_serializer; i++) {
1291 if (mcasp->serial_dir[i] == dir)
1292 max_channels++;
1293 }
1294 ruledata->serializers = max_channels;
1295 max_channels *= tdm_slots;
1296 /*
1297 * If the already active stream has less channels than the calculated
1298 * limnit based on the seirializers * tdm_slots, we need to use that as
1299 * a constraint for the second stream.
1300 * Otherwise (first stream or less allowed channels) we use the
1301 * calculated constraint.
1302 */
1303 if (mcasp->channels && mcasp->channels < max_channels)
1304 max_channels = mcasp->channels;
1305 /*
1306 * But we can always allow channels upto the amount of
1307 * the available tdm_slots.
1308 */
1309 if (max_channels < tdm_slots)
1310 max_channels = tdm_slots;
1311
1312 snd_pcm_hw_constraint_minmax(substream->runtime,
1313 SNDRV_PCM_HW_PARAM_CHANNELS,
1314 0, max_channels);
1315
1316 snd_pcm_hw_constraint_list(substream->runtime,
1317 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1318 &mcasp->chconstr[substream->stream]);
1319
1320 if (mcasp->slot_width)
1321 snd_pcm_hw_constraint_minmax(substream->runtime,
1322 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1323 8, mcasp->slot_width);
1324
1325 /*
1326 * If we rely on implicit BCLK divider setting we should
1327 * set constraints based on what we can provide.
1328 */
1329 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1330 int ret;
1331
1332 ruledata->mcasp = mcasp;
1333
1334 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1335 SNDRV_PCM_HW_PARAM_RATE,
1336 davinci_mcasp_hw_rule_rate,
1337 ruledata,
1338 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1339 if (ret)
1340 return ret;
1341 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1342 SNDRV_PCM_HW_PARAM_FORMAT,
1343 davinci_mcasp_hw_rule_format,
1344 ruledata,
1345 SNDRV_PCM_HW_PARAM_RATE, -1);
1346 if (ret)
1347 return ret;
1348 }
1349
1350 snd_pcm_hw_rule_add(substream->runtime, 0,
1351 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1352 davinci_mcasp_hw_rule_min_periodsize, NULL,
1353 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1354
1355 return 0;
1356}
1357
1358static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1359 struct snd_soc_dai *cpu_dai)
1360{
1361 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1362
1363 mcasp->substreams[substream->stream] = NULL;
1364
1365 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1366 return;
1367
1368 if (!cpu_dai->active)
1369 mcasp->channels = 0;
1370}
1371
1372static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1373 .startup = davinci_mcasp_startup,
1374 .shutdown = davinci_mcasp_shutdown,
1375 .trigger = davinci_mcasp_trigger,
1376 .hw_params = davinci_mcasp_hw_params,
1377 .set_fmt = davinci_mcasp_set_dai_fmt,
1378 .set_clkdiv = davinci_mcasp_set_clkdiv,
1379 .set_sysclk = davinci_mcasp_set_sysclk,
1380 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1381};
1382
1383static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1384{
1385 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1386
1387 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1388 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1389
1390 return 0;
1391}
1392
1393#ifdef CONFIG_PM_SLEEP
1394static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1395{
1396 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1397 struct davinci_mcasp_context *context = &mcasp->context;
1398 u32 reg;
1399 int i;
1400
1401 context->pm_state = pm_runtime_active(mcasp->dev);
1402 if (!context->pm_state)
1403 pm_runtime_get_sync(mcasp->dev);
1404
1405 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1406 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1407
1408 if (mcasp->txnumevt) {
1409 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1410 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1411 }
1412 if (mcasp->rxnumevt) {
1413 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1414 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1415 }
1416
1417 for (i = 0; i < mcasp->num_serializer; i++)
1418 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1419 DAVINCI_MCASP_XRSRCTL_REG(i));
1420
1421 pm_runtime_put_sync(mcasp->dev);
1422
1423 return 0;
1424}
1425
1426static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1427{
1428 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1429 struct davinci_mcasp_context *context = &mcasp->context;
1430 u32 reg;
1431 int i;
1432
1433 pm_runtime_get_sync(mcasp->dev);
1434
1435 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1436 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1437
1438 if (mcasp->txnumevt) {
1439 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1440 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1441 }
1442 if (mcasp->rxnumevt) {
1443 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1444 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1445 }
1446
1447 for (i = 0; i < mcasp->num_serializer; i++)
1448 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1449 context->xrsr_regs[i]);
1450
1451 if (!context->pm_state)
1452 pm_runtime_put_sync(mcasp->dev);
1453
1454 return 0;
1455}
1456#else
1457#define davinci_mcasp_suspend NULL
1458#define davinci_mcasp_resume NULL
1459#endif
1460
1461#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1462
1463#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1464 SNDRV_PCM_FMTBIT_U8 | \
1465 SNDRV_PCM_FMTBIT_S16_LE | \
1466 SNDRV_PCM_FMTBIT_U16_LE | \
1467 SNDRV_PCM_FMTBIT_S24_LE | \
1468 SNDRV_PCM_FMTBIT_U24_LE | \
1469 SNDRV_PCM_FMTBIT_S24_3LE | \
1470 SNDRV_PCM_FMTBIT_U24_3LE | \
1471 SNDRV_PCM_FMTBIT_S32_LE | \
1472 SNDRV_PCM_FMTBIT_U32_LE)
1473
1474static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1475 {
1476 .name = "davinci-mcasp.0",
1477 .probe = davinci_mcasp_dai_probe,
1478 .suspend = davinci_mcasp_suspend,
1479 .resume = davinci_mcasp_resume,
1480 .playback = {
1481 .channels_min = 1,
1482 .channels_max = 32 * 16,
1483 .rates = DAVINCI_MCASP_RATES,
1484 .formats = DAVINCI_MCASP_PCM_FMTS,
1485 },
1486 .capture = {
1487 .channels_min = 1,
1488 .channels_max = 32 * 16,
1489 .rates = DAVINCI_MCASP_RATES,
1490 .formats = DAVINCI_MCASP_PCM_FMTS,
1491 },
1492 .ops = &davinci_mcasp_dai_ops,
1493
1494 .symmetric_samplebits = 1,
1495 .symmetric_rates = 1,
1496 },
1497 {
1498 .name = "davinci-mcasp.1",
1499 .probe = davinci_mcasp_dai_probe,
1500 .playback = {
1501 .channels_min = 1,
1502 .channels_max = 384,
1503 .rates = DAVINCI_MCASP_RATES,
1504 .formats = DAVINCI_MCASP_PCM_FMTS,
1505 },
1506 .ops = &davinci_mcasp_dai_ops,
1507 },
1508
1509};
1510
1511static const struct snd_soc_component_driver davinci_mcasp_component = {
1512 .name = "davinci-mcasp",
1513};
1514
1515/* Some HW specific values and defaults. The rest is filled in from DT. */
1516static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1517 .tx_dma_offset = 0x400,
1518 .rx_dma_offset = 0x400,
1519 .version = MCASP_VERSION_1,
1520};
1521
1522static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1523 .tx_dma_offset = 0x2000,
1524 .rx_dma_offset = 0x2000,
1525 .version = MCASP_VERSION_2,
1526};
1527
1528static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1529 .tx_dma_offset = 0,
1530 .rx_dma_offset = 0,
1531 .version = MCASP_VERSION_3,
1532};
1533
1534static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1535 /* The CFG port offset will be calculated if it is needed */
1536 .tx_dma_offset = 0,
1537 .rx_dma_offset = 0,
1538 .version = MCASP_VERSION_4,
1539};
1540
1541static const struct of_device_id mcasp_dt_ids[] = {
1542 {
1543 .compatible = "ti,dm646x-mcasp-audio",
1544 .data = &dm646x_mcasp_pdata,
1545 },
1546 {
1547 .compatible = "ti,da830-mcasp-audio",
1548 .data = &da830_mcasp_pdata,
1549 },
1550 {
1551 .compatible = "ti,am33xx-mcasp-audio",
1552 .data = &am33xx_mcasp_pdata,
1553 },
1554 {
1555 .compatible = "ti,dra7-mcasp-audio",
1556 .data = &dra7_mcasp_pdata,
1557 },
1558 { /* sentinel */ }
1559};
1560MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1561
1562static int mcasp_reparent_fck(struct platform_device *pdev)
1563{
1564 struct device_node *node = pdev->dev.of_node;
1565 struct clk *gfclk, *parent_clk;
1566 const char *parent_name;
1567 int ret;
1568
1569 if (!node)
1570 return 0;
1571
1572 parent_name = of_get_property(node, "fck_parent", NULL);
1573 if (!parent_name)
1574 return 0;
1575
1576 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1577
1578 gfclk = clk_get(&pdev->dev, "fck");
1579 if (IS_ERR(gfclk)) {
1580 dev_err(&pdev->dev, "failed to get fck\n");
1581 return PTR_ERR(gfclk);
1582 }
1583
1584 parent_clk = clk_get(NULL, parent_name);
1585 if (IS_ERR(parent_clk)) {
1586 dev_err(&pdev->dev, "failed to get parent clock\n");
1587 ret = PTR_ERR(parent_clk);
1588 goto err1;
1589 }
1590
1591 ret = clk_set_parent(gfclk, parent_clk);
1592 if (ret) {
1593 dev_err(&pdev->dev, "failed to reparent fck\n");
1594 goto err2;
1595 }
1596
1597err2:
1598 clk_put(parent_clk);
1599err1:
1600 clk_put(gfclk);
1601 return ret;
1602}
1603
1604static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1605 struct platform_device *pdev)
1606{
1607 struct device_node *np = pdev->dev.of_node;
1608 struct davinci_mcasp_pdata *pdata = NULL;
1609 const struct of_device_id *match =
1610 of_match_device(mcasp_dt_ids, &pdev->dev);
1611 struct of_phandle_args dma_spec;
1612
1613 const u32 *of_serial_dir32;
1614 u32 val;
1615 int i, ret = 0;
1616
1617 if (pdev->dev.platform_data) {
1618 pdata = pdev->dev.platform_data;
1619 return pdata;
1620 } else if (match) {
1621 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1622 GFP_KERNEL);
1623 if (!pdata) {
1624 ret = -ENOMEM;
1625 return pdata;
1626 }
1627 } else {
1628 /* control shouldn't reach here. something is wrong */
1629 ret = -EINVAL;
1630 goto nodata;
1631 }
1632
1633 ret = of_property_read_u32(np, "op-mode", &val);
1634 if (ret >= 0)
1635 pdata->op_mode = val;
1636
1637 ret = of_property_read_u32(np, "tdm-slots", &val);
1638 if (ret >= 0) {
1639 if (val < 2 || val > 32) {
1640 dev_err(&pdev->dev,
1641 "tdm-slots must be in rage [2-32]\n");
1642 ret = -EINVAL;
1643 goto nodata;
1644 }
1645
1646 pdata->tdm_slots = val;
1647 }
1648
1649 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1650 val /= sizeof(u32);
1651 if (of_serial_dir32) {
1652 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1653 (sizeof(*of_serial_dir) * val),
1654 GFP_KERNEL);
1655 if (!of_serial_dir) {
1656 ret = -ENOMEM;
1657 goto nodata;
1658 }
1659
1660 for (i = 0; i < val; i++)
1661 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1662
1663 pdata->num_serializer = val;
1664 pdata->serial_dir = of_serial_dir;
1665 }
1666
1667 ret = of_property_match_string(np, "dma-names", "tx");
1668 if (ret < 0)
1669 goto nodata;
1670
1671 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1672 &dma_spec);
1673 if (ret < 0)
1674 goto nodata;
1675
1676 pdata->tx_dma_channel = dma_spec.args[0];
1677
1678 /* RX is not valid in DIT mode */
1679 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1680 ret = of_property_match_string(np, "dma-names", "rx");
1681 if (ret < 0)
1682 goto nodata;
1683
1684 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1685 &dma_spec);
1686 if (ret < 0)
1687 goto nodata;
1688
1689 pdata->rx_dma_channel = dma_spec.args[0];
1690 }
1691
1692 ret = of_property_read_u32(np, "tx-num-evt", &val);
1693 if (ret >= 0)
1694 pdata->txnumevt = val;
1695
1696 ret = of_property_read_u32(np, "rx-num-evt", &val);
1697 if (ret >= 0)
1698 pdata->rxnumevt = val;
1699
1700 ret = of_property_read_u32(np, "sram-size-playback", &val);
1701 if (ret >= 0)
1702 pdata->sram_size_playback = val;
1703
1704 ret = of_property_read_u32(np, "sram-size-capture", &val);
1705 if (ret >= 0)
1706 pdata->sram_size_capture = val;
1707
1708 return pdata;
1709
1710nodata:
1711 if (ret < 0) {
1712 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1713 ret);
1714 pdata = NULL;
1715 }
1716 return pdata;
1717}
1718
1719enum {
1720 PCM_EDMA,
1721 PCM_SDMA,
1722};
1723static const char *sdma_prefix = "ti,omap";
1724
1725static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1726{
1727 struct dma_chan *chan;
1728 const char *tmp;
1729 int ret = PCM_EDMA;
1730
1731 if (!mcasp->dev->of_node)
1732 return PCM_EDMA;
1733
1734 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1735 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1736 if (IS_ERR(chan)) {
1737 if (PTR_ERR(chan) != -EPROBE_DEFER)
1738 dev_err(mcasp->dev,
1739 "Can't verify DMA configuration (%ld)\n",
1740 PTR_ERR(chan));
1741 return PTR_ERR(chan);
1742 }
1743 if (WARN_ON(!chan->device || !chan->device->dev))
1744 return -EINVAL;
1745
1746 if (chan->device->dev->of_node)
1747 ret = of_property_read_string(chan->device->dev->of_node,
1748 "compatible", &tmp);
1749 else
1750 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1751
1752 dma_release_channel(chan);
1753 if (ret)
1754 return ret;
1755
1756 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1757 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1758 return PCM_SDMA;
1759
1760 return PCM_EDMA;
1761}
1762
1763static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1764{
1765 int i;
1766 u32 offset = 0;
1767
1768 if (pdata->version != MCASP_VERSION_4)
1769 return pdata->tx_dma_offset;
1770
1771 for (i = 0; i < pdata->num_serializer; i++) {
1772 if (pdata->serial_dir[i] == TX_MODE) {
1773 if (!offset) {
1774 offset = DAVINCI_MCASP_TXBUF_REG(i);
1775 } else {
1776 pr_err("%s: Only one serializer allowed!\n",
1777 __func__);
1778 break;
1779 }
1780 }
1781 }
1782
1783 return offset;
1784}
1785
1786static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1787{
1788 int i;
1789 u32 offset = 0;
1790
1791 if (pdata->version != MCASP_VERSION_4)
1792 return pdata->rx_dma_offset;
1793
1794 for (i = 0; i < pdata->num_serializer; i++) {
1795 if (pdata->serial_dir[i] == RX_MODE) {
1796 if (!offset) {
1797 offset = DAVINCI_MCASP_RXBUF_REG(i);
1798 } else {
1799 pr_err("%s: Only one serializer allowed!\n",
1800 __func__);
1801 break;
1802 }
1803 }
1804 }
1805
1806 return offset;
1807}
1808
1809static int davinci_mcasp_probe(struct platform_device *pdev)
1810{
1811 struct snd_dmaengine_dai_dma_data *dma_data;
1812 struct resource *mem, *res, *dat;
1813 struct davinci_mcasp_pdata *pdata;
1814 struct davinci_mcasp *mcasp;
1815 char *irq_name;
1816 int *dma;
1817 int irq;
1818 int ret;
1819
1820 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1821 dev_err(&pdev->dev, "No platform data supplied\n");
1822 return -EINVAL;
1823 }
1824
1825 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1826 GFP_KERNEL);
1827 if (!mcasp)
1828 return -ENOMEM;
1829
1830 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1831 if (!pdata) {
1832 dev_err(&pdev->dev, "no platform data\n");
1833 return -EINVAL;
1834 }
1835
1836 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1837 if (!mem) {
1838 dev_warn(mcasp->dev,
1839 "\"mpu\" mem resource not found, using index 0\n");
1840 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1841 if (!mem) {
1842 dev_err(&pdev->dev, "no mem resource?\n");
1843 return -ENODEV;
1844 }
1845 }
1846
1847 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1848 if (IS_ERR(mcasp->base))
1849 return PTR_ERR(mcasp->base);
1850
1851 pm_runtime_enable(&pdev->dev);
1852
1853 mcasp->op_mode = pdata->op_mode;
1854 /* sanity check for tdm slots parameter */
1855 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1856 if (pdata->tdm_slots < 2) {
1857 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1858 pdata->tdm_slots);
1859 mcasp->tdm_slots = 2;
1860 } else if (pdata->tdm_slots > 32) {
1861 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1862 pdata->tdm_slots);
1863 mcasp->tdm_slots = 32;
1864 } else {
1865 mcasp->tdm_slots = pdata->tdm_slots;
1866 }
1867 }
1868
1869 mcasp->num_serializer = pdata->num_serializer;
1870#ifdef CONFIG_PM_SLEEP
1871 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1872 sizeof(u32) * mcasp->num_serializer,
1873 GFP_KERNEL);
1874 if (!mcasp->context.xrsr_regs) {
1875 ret = -ENOMEM;
1876 goto err;
1877 }
1878#endif
1879 mcasp->serial_dir = pdata->serial_dir;
1880 mcasp->version = pdata->version;
1881 mcasp->txnumevt = pdata->txnumevt;
1882 mcasp->rxnumevt = pdata->rxnumevt;
1883
1884 mcasp->dev = &pdev->dev;
1885
1886 irq = platform_get_irq_byname(pdev, "common");
1887 if (irq >= 0) {
1888 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1889 dev_name(&pdev->dev));
1890 if (!irq_name) {
1891 ret = -ENOMEM;
1892 goto err;
1893 }
1894 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1895 davinci_mcasp_common_irq_handler,
1896 IRQF_ONESHOT | IRQF_SHARED,
1897 irq_name, mcasp);
1898 if (ret) {
1899 dev_err(&pdev->dev, "common IRQ request failed\n");
1900 goto err;
1901 }
1902
1903 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1904 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1905 }
1906
1907 irq = platform_get_irq_byname(pdev, "rx");
1908 if (irq >= 0) {
1909 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1910 dev_name(&pdev->dev));
1911 if (!irq_name) {
1912 ret = -ENOMEM;
1913 goto err;
1914 }
1915 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1916 davinci_mcasp_rx_irq_handler,
1917 IRQF_ONESHOT, irq_name, mcasp);
1918 if (ret) {
1919 dev_err(&pdev->dev, "RX IRQ request failed\n");
1920 goto err;
1921 }
1922
1923 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1924 }
1925
1926 irq = platform_get_irq_byname(pdev, "tx");
1927 if (irq >= 0) {
1928 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1929 dev_name(&pdev->dev));
1930 if (!irq_name) {
1931 ret = -ENOMEM;
1932 goto err;
1933 }
1934 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1935 davinci_mcasp_tx_irq_handler,
1936 IRQF_ONESHOT, irq_name, mcasp);
1937 if (ret) {
1938 dev_err(&pdev->dev, "TX IRQ request failed\n");
1939 goto err;
1940 }
1941
1942 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1943 }
1944
1945 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1946 if (dat)
1947 mcasp->dat_port = true;
1948
1949 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1950 if (dat)
1951 dma_data->addr = dat->start;
1952 else
1953 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1954
1955 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1956 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1957 if (res)
1958 *dma = res->start;
1959 else
1960 *dma = pdata->tx_dma_channel;
1961
1962 /* dmaengine filter data for DT and non-DT boot */
1963 if (pdev->dev.of_node)
1964 dma_data->filter_data = "tx";
1965 else
1966 dma_data->filter_data = dma;
1967
1968 /* RX is not valid in DIT mode */
1969 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1970 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1971 if (dat)
1972 dma_data->addr = dat->start;
1973 else
1974 dma_data->addr =
1975 mem->start + davinci_mcasp_rxdma_offset(pdata);
1976
1977 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1978 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1979 if (res)
1980 *dma = res->start;
1981 else
1982 *dma = pdata->rx_dma_channel;
1983
1984 /* dmaengine filter data for DT and non-DT boot */
1985 if (pdev->dev.of_node)
1986 dma_data->filter_data = "rx";
1987 else
1988 dma_data->filter_data = dma;
1989 }
1990
1991 if (mcasp->version < MCASP_VERSION_3) {
1992 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1993 /* dma_params->dma_addr is pointing to the data port address */
1994 mcasp->dat_port = true;
1995 } else {
1996 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1997 }
1998
1999 /* Allocate memory for long enough list for all possible
2000 * scenarios. Maximum number tdm slots is 32 and there cannot
2001 * be more serializers than given in the configuration. The
2002 * serializer directions could be taken into account, but it
2003 * would make code much more complex and save only couple of
2004 * bytes.
2005 */
2006 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2007 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2008 (32 + mcasp->num_serializer - 1),
2009 GFP_KERNEL);
2010
2011 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2012 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2013 (32 + mcasp->num_serializer - 1),
2014 GFP_KERNEL);
2015
2016 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2017 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2018 ret = -ENOMEM;
2019 goto err;
2020 }
2021
2022 ret = davinci_mcasp_set_ch_constraints(mcasp);
2023 if (ret)
2024 goto err;
2025
2026 dev_set_drvdata(&pdev->dev, mcasp);
2027
2028 mcasp_reparent_fck(pdev);
2029
2030 ret = devm_snd_soc_register_component(&pdev->dev,
2031 &davinci_mcasp_component,
2032 &davinci_mcasp_dai[pdata->op_mode], 1);
2033
2034 if (ret != 0)
2035 goto err;
2036
2037 ret = davinci_mcasp_get_dma_type(mcasp);
2038 switch (ret) {
2039 case PCM_EDMA:
2040#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2041 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2042 IS_MODULE(CONFIG_SND_EDMA_SOC))
2043 ret = edma_pcm_platform_register(&pdev->dev);
2044#else
2045 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2046 ret = -EINVAL;
2047 goto err;
2048#endif
2049 break;
2050 case PCM_SDMA:
2051#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
2052 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2053 IS_MODULE(CONFIG_SND_OMAP_SOC))
2054 ret = omap_pcm_platform_register(&pdev->dev);
2055#else
2056 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2057 ret = -EINVAL;
2058 goto err;
2059#endif
2060 break;
2061 default:
2062 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2063 case -EPROBE_DEFER:
2064 goto err;
2065 break;
2066 }
2067
2068 if (ret) {
2069 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2070 goto err;
2071 }
2072
2073 return 0;
2074
2075err:
2076 pm_runtime_disable(&pdev->dev);
2077 return ret;
2078}
2079
2080static int davinci_mcasp_remove(struct platform_device *pdev)
2081{
2082 pm_runtime_disable(&pdev->dev);
2083
2084 return 0;
2085}
2086
2087static struct platform_driver davinci_mcasp_driver = {
2088 .probe = davinci_mcasp_probe,
2089 .remove = davinci_mcasp_remove,
2090 .driver = {
2091 .name = "davinci-mcasp",
2092 .of_match_table = mcasp_dt_ids,
2093 },
2094};
2095
2096module_platform_driver(davinci_mcasp_driver);
2097
2098MODULE_AUTHOR("Steve Chen");
2099MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2100MODULE_LICENSE("GPL");