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1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/initval.h>
30#include <sound/soc.h>
31
32#include "davinci-pcm.h"
33#include "davinci-mcasp.h"
34
35/*
36 * McASP register definitions
37 */
38#define DAVINCI_MCASP_PID_REG 0x00
39#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
40
41#define DAVINCI_MCASP_PFUNC_REG 0x10
42#define DAVINCI_MCASP_PDIR_REG 0x14
43#define DAVINCI_MCASP_PDOUT_REG 0x18
44#define DAVINCI_MCASP_PDSET_REG 0x1c
45
46#define DAVINCI_MCASP_PDCLR_REG 0x20
47
48#define DAVINCI_MCASP_TLGC_REG 0x30
49#define DAVINCI_MCASP_TLMR_REG 0x34
50
51#define DAVINCI_MCASP_GBLCTL_REG 0x44
52#define DAVINCI_MCASP_AMUTE_REG 0x48
53#define DAVINCI_MCASP_LBCTL_REG 0x4c
54
55#define DAVINCI_MCASP_TXDITCTL_REG 0x50
56
57#define DAVINCI_MCASP_GBLCTLR_REG 0x60
58#define DAVINCI_MCASP_RXMASK_REG 0x64
59#define DAVINCI_MCASP_RXFMT_REG 0x68
60#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
61
62#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
63#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
64#define DAVINCI_MCASP_RXTDM_REG 0x78
65#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
66
67#define DAVINCI_MCASP_RXSTAT_REG 0x80
68#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
69#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
70#define DAVINCI_MCASP_REVTCTL_REG 0x8c
71
72#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
73#define DAVINCI_MCASP_TXMASK_REG 0xa4
74#define DAVINCI_MCASP_TXFMT_REG 0xa8
75#define DAVINCI_MCASP_TXFMCTL_REG 0xac
76
77#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
78#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
79#define DAVINCI_MCASP_TXTDM_REG 0xb8
80#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
81
82#define DAVINCI_MCASP_TXSTAT_REG 0xc0
83#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
84#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
85#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
86
87/* Left(even TDM Slot) Channel Status Register File */
88#define DAVINCI_MCASP_DITCSRA_REG 0x100
89/* Right(odd TDM slot) Channel Status Register File */
90#define DAVINCI_MCASP_DITCSRB_REG 0x118
91/* Left(even TDM slot) User Data Register File */
92#define DAVINCI_MCASP_DITUDRA_REG 0x130
93/* Right(odd TDM Slot) User Data Register File */
94#define DAVINCI_MCASP_DITUDRB_REG 0x148
95
96/* Serializer n Control Register */
97#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
98#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
99 (n << 2))
100
101/* Transmit Buffer for Serializer n */
102#define DAVINCI_MCASP_TXBUF_REG 0x200
103/* Receive Buffer for Serializer n */
104#define DAVINCI_MCASP_RXBUF_REG 0x280
105
106/* McASP FIFO Registers */
107#define DAVINCI_MCASP_WFIFOCTL (0x1010)
108#define DAVINCI_MCASP_WFIFOSTS (0x1014)
109#define DAVINCI_MCASP_RFIFOCTL (0x1018)
110#define DAVINCI_MCASP_RFIFOSTS (0x101C)
111
112/*
113 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
114 * Register Bits
115 */
116#define MCASP_FREE BIT(0)
117#define MCASP_SOFT BIT(1)
118
119/*
120 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
121 */
122#define AXR(n) (1<<n)
123#define PFUNC_AMUTE BIT(25)
124#define ACLKX BIT(26)
125#define AHCLKX BIT(27)
126#define AFSX BIT(28)
127#define ACLKR BIT(29)
128#define AHCLKR BIT(30)
129#define AFSR BIT(31)
130
131/*
132 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
133 */
134#define AXR(n) (1<<n)
135#define PDIR_AMUTE BIT(25)
136#define ACLKX BIT(26)
137#define AHCLKX BIT(27)
138#define AFSX BIT(28)
139#define ACLKR BIT(29)
140#define AHCLKR BIT(30)
141#define AFSR BIT(31)
142
143/*
144 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
145 */
146#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
147#define VA BIT(2)
148#define VB BIT(3)
149
150/*
151 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
152 */
153#define TXROT(val) (val)
154#define TXSEL BIT(3)
155#define TXSSZ(val) (val<<4)
156#define TXPBIT(val) (val<<8)
157#define TXPAD(val) (val<<13)
158#define TXORD BIT(15)
159#define FSXDLY(val) (val<<16)
160
161/*
162 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
163 */
164#define RXROT(val) (val)
165#define RXSEL BIT(3)
166#define RXSSZ(val) (val<<4)
167#define RXPBIT(val) (val<<8)
168#define RXPAD(val) (val<<13)
169#define RXORD BIT(15)
170#define FSRDLY(val) (val<<16)
171
172/*
173 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
174 */
175#define FSXPOL BIT(0)
176#define AFSXE BIT(1)
177#define FSXDUR BIT(4)
178#define FSXMOD(val) (val<<7)
179
180/*
181 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
182 */
183#define FSRPOL BIT(0)
184#define AFSRE BIT(1)
185#define FSRDUR BIT(4)
186#define FSRMOD(val) (val<<7)
187
188/*
189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
190 */
191#define ACLKXDIV(val) (val)
192#define ACLKXE BIT(5)
193#define TX_ASYNC BIT(6)
194#define ACLKXPOL BIT(7)
195
196/*
197 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
198 */
199#define ACLKRDIV(val) (val)
200#define ACLKRE BIT(5)
201#define RX_ASYNC BIT(6)
202#define ACLKRPOL BIT(7)
203
204/*
205 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
206 * Register Bits
207 */
208#define AHCLKXDIV(val) (val)
209#define AHCLKXPOL BIT(14)
210#define AHCLKXE BIT(15)
211
212/*
213 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
214 * Register Bits
215 */
216#define AHCLKRDIV(val) (val)
217#define AHCLKRPOL BIT(14)
218#define AHCLKRE BIT(15)
219
220/*
221 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
222 */
223#define MODE(val) (val)
224#define DISMOD (val)(val<<2)
225#define TXSTATE BIT(4)
226#define RXSTATE BIT(5)
227
228/*
229 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
230 */
231#define LBEN BIT(0)
232#define LBORD BIT(1)
233#define LBGENMODE(val) (val<<2)
234
235/*
236 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
237 */
238#define TXTDMS(n) (1<<n)
239
240/*
241 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
242 */
243#define RXTDMS(n) (1<<n)
244
245/*
246 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
247 */
248#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
249#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
250#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
251#define RXSMRST BIT(3) /* Receiver State Machine Reset */
252#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
253#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
254#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
255#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
256#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
257#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
258
259/*
260 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
261 */
262#define MUTENA(val) (val)
263#define MUTEINPOL BIT(2)
264#define MUTEINENA BIT(3)
265#define MUTEIN BIT(4)
266#define MUTER BIT(5)
267#define MUTEX BIT(6)
268#define MUTEFSR BIT(7)
269#define MUTEFSX BIT(8)
270#define MUTEBADCLKR BIT(9)
271#define MUTEBADCLKX BIT(10)
272#define MUTERXDMAERR BIT(11)
273#define MUTETXDMAERR BIT(12)
274
275/*
276 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
277 */
278#define RXDATADMADIS BIT(0)
279
280/*
281 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
282 */
283#define TXDATADMADIS BIT(0)
284
285/*
286 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
287 */
288#define FIFO_ENABLE BIT(16)
289#define NUMEVT_MASK (0xFF << 8)
290#define NUMDMA_MASK (0xFF)
291
292#define DAVINCI_MCASP_NUM_SERIALIZER 16
293
294static inline void mcasp_set_bits(void __iomem *reg, u32 val)
295{
296 __raw_writel(__raw_readl(reg) | val, reg);
297}
298
299static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
300{
301 __raw_writel((__raw_readl(reg) & ~(val)), reg);
302}
303
304static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
305{
306 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
307}
308
309static inline void mcasp_set_reg(void __iomem *reg, u32 val)
310{
311 __raw_writel(val, reg);
312}
313
314static inline u32 mcasp_get_reg(void __iomem *reg)
315{
316 return (unsigned int)__raw_readl(reg);
317}
318
319static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
320{
321 int i = 0;
322
323 mcasp_set_bits(regs, val);
324
325 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
326 /* loop count is to avoid the lock-up */
327 for (i = 0; i < 1000; i++) {
328 if ((mcasp_get_reg(regs) & val) == val)
329 break;
330 }
331
332 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
333 printk(KERN_ERR "GBLCTL write error\n");
334}
335
336static void mcasp_start_rx(struct davinci_audio_dev *dev)
337{
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
340 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
341 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
342
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
344 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
345 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
346
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
349}
350
351static void mcasp_start_tx(struct davinci_audio_dev *dev)
352{
353 u8 offset = 0, i;
354 u32 cnt;
355
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
359 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
360
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
362 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
363 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
364 for (i = 0; i < dev->num_serializer; i++) {
365 if (dev->serial_dir[i] == TX_MODE) {
366 offset = i;
367 break;
368 }
369 }
370
371 /* wait for TX ready */
372 cnt = 0;
373 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
374 TXSTATE) && (cnt < 100000))
375 cnt++;
376
377 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
378}
379
380static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
381{
382 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
383 if (dev->txnumevt) /* enable FIFO */
384 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
385 FIFO_ENABLE);
386 mcasp_start_tx(dev);
387 } else {
388 if (dev->rxnumevt) /* enable FIFO */
389 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
390 FIFO_ENABLE);
391 mcasp_start_rx(dev);
392 }
393}
394
395static void mcasp_stop_rx(struct davinci_audio_dev *dev)
396{
397 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
398 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
399}
400
401static void mcasp_stop_tx(struct davinci_audio_dev *dev)
402{
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
405}
406
407static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
408{
409 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
410 if (dev->txnumevt) /* disable FIFO */
411 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
412 FIFO_ENABLE);
413 mcasp_stop_tx(dev);
414 } else {
415 if (dev->rxnumevt) /* disable FIFO */
416 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
417 FIFO_ENABLE);
418 mcasp_stop_rx(dev);
419 }
420}
421
422static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
423 unsigned int fmt)
424{
425 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
426 void __iomem *base = dev->base;
427
428 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
429 case SND_SOC_DAIFMT_CBS_CFS:
430 /* codec is clock and frame slave */
431 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
432 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
433
434 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
435 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
436
437 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
438 ACLKX | AHCLKX | AFSX);
439 break;
440 case SND_SOC_DAIFMT_CBM_CFS:
441 /* codec is clock master and frame slave */
442 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
443 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
444
445 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
446 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
447
448 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
449 ACLKX | ACLKR);
450 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
451 AFSX | AFSR);
452 break;
453 case SND_SOC_DAIFMT_CBM_CFM:
454 /* codec is clock and frame master */
455 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
457
458 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
460
461 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
462 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
463 break;
464
465 default:
466 return -EINVAL;
467 }
468
469 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
470 case SND_SOC_DAIFMT_IB_NF:
471 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
472 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
473
474 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
475 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
476 break;
477
478 case SND_SOC_DAIFMT_NB_IF:
479 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
480 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
481
482 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
483 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
484 break;
485
486 case SND_SOC_DAIFMT_IB_IF:
487 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
488 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
489
490 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
491 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
492 break;
493
494 case SND_SOC_DAIFMT_NB_NF:
495 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
496 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
497
498 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
499 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 return 0;
507}
508
509static int davinci_config_channel_size(struct davinci_audio_dev *dev,
510 int channel_size)
511{
512 u32 fmt = 0;
513 u32 mask, rotate;
514
515 switch (channel_size) {
516 case DAVINCI_AUDIO_WORD_8:
517 fmt = 0x03;
518 rotate = 6;
519 mask = 0x000000ff;
520 break;
521
522 case DAVINCI_AUDIO_WORD_12:
523 fmt = 0x05;
524 rotate = 5;
525 mask = 0x00000fff;
526 break;
527
528 case DAVINCI_AUDIO_WORD_16:
529 fmt = 0x07;
530 rotate = 4;
531 mask = 0x0000ffff;
532 break;
533
534 case DAVINCI_AUDIO_WORD_20:
535 fmt = 0x09;
536 rotate = 3;
537 mask = 0x000fffff;
538 break;
539
540 case DAVINCI_AUDIO_WORD_24:
541 fmt = 0x0B;
542 rotate = 2;
543 mask = 0x00ffffff;
544 break;
545
546 case DAVINCI_AUDIO_WORD_28:
547 fmt = 0x0D;
548 rotate = 1;
549 mask = 0x0fffffff;
550 break;
551
552 case DAVINCI_AUDIO_WORD_32:
553 fmt = 0x0F;
554 rotate = 0;
555 mask = 0xffffffff;
556 break;
557
558 default:
559 return -EINVAL;
560 }
561
562 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
563 RXSSZ(fmt), RXSSZ(0x0F));
564 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
565 TXSSZ(fmt), TXSSZ(0x0F));
566 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
567 TXROT(7));
568 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
569 RXROT(7));
570 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
571 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
572
573 return 0;
574}
575
576static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
577{
578 int i;
579 u8 tx_ser = 0;
580 u8 rx_ser = 0;
581
582 /* Default configuration */
583 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
584
585 /* All PINS as McASP */
586 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
587
588 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
589 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
590 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
591 TXDATADMADIS);
592 } else {
593 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
594 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
595 RXDATADMADIS);
596 }
597
598 for (i = 0; i < dev->num_serializer; i++) {
599 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
600 dev->serial_dir[i]);
601 if (dev->serial_dir[i] == TX_MODE) {
602 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
603 AXR(i));
604 tx_ser++;
605 } else if (dev->serial_dir[i] == RX_MODE) {
606 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
607 AXR(i));
608 rx_ser++;
609 }
610 }
611
612 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
613 if (dev->txnumevt * tx_ser > 64)
614 dev->txnumevt = 1;
615
616 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
617 NUMDMA_MASK);
618 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
619 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
620 }
621
622 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
623 if (dev->rxnumevt * rx_ser > 64)
624 dev->rxnumevt = 1;
625
626 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
627 NUMDMA_MASK);
628 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
629 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
630 }
631}
632
633static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
634{
635 int i, active_slots;
636 u32 mask = 0;
637
638 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
639 for (i = 0; i < active_slots; i++)
640 mask |= (1 << i);
641
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
643
644 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
645 /* bit stream is MSB first with no delay */
646 /* DSP_B mode */
647 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
648 AHCLKXE);
649 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
650 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
651
652 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
653 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
654 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
655 else
656 printk(KERN_ERR "playback tdm slot %d not supported\n",
657 dev->tdm_slots);
658
659 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
660 } else {
661 /* bit stream is MSB first with no delay */
662 /* DSP_B mode */
663 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
664 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
665 AHCLKRE);
666 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
667
668 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
669 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
670 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
671 else
672 printk(KERN_ERR "capture tdm slot %d not supported\n",
673 dev->tdm_slots);
674
675 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
676 }
677}
678
679/* S/PDIF */
680static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
681{
682 /* Set the PDIR for Serialiser as output */
683 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
684
685 /* TXMASK for 24 bits */
686 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
687
688 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
689 and LSB first */
690 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
691 TXROT(6) | TXSSZ(15));
692
693 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
694 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
695 AFSXE | FSXMOD(0x180));
696
697 /* Set the TX tdm : for all the slots */
698 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
699
700 /* Set the TX clock controls : div = 1 and internal */
701 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
702 ACLKXE | TX_ASYNC);
703
704 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
705
706 /* Only 44100 and 48000 are valid, both have the same setting */
707 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
708
709 /* Enable the DIT */
710 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
711}
712
713static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
714 struct snd_pcm_hw_params *params,
715 struct snd_soc_dai *cpu_dai)
716{
717 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
718 struct davinci_pcm_dma_params *dma_params =
719 &dev->dma_params[substream->stream];
720 int word_length;
721 u8 fifo_level;
722
723 davinci_hw_common_param(dev, substream->stream);
724 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
725 fifo_level = dev->txnumevt;
726 else
727 fifo_level = dev->rxnumevt;
728
729 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
730 davinci_hw_dit_param(dev);
731 else
732 davinci_hw_param(dev, substream->stream);
733
734 switch (params_format(params)) {
735 case SNDRV_PCM_FORMAT_U8:
736 case SNDRV_PCM_FORMAT_S8:
737 dma_params->data_type = 1;
738 word_length = DAVINCI_AUDIO_WORD_8;
739 break;
740
741 case SNDRV_PCM_FORMAT_U16_LE:
742 case SNDRV_PCM_FORMAT_S16_LE:
743 dma_params->data_type = 2;
744 word_length = DAVINCI_AUDIO_WORD_16;
745 break;
746
747 case SNDRV_PCM_FORMAT_U32_LE:
748 case SNDRV_PCM_FORMAT_S32_LE:
749 dma_params->data_type = 4;
750 word_length = DAVINCI_AUDIO_WORD_32;
751 break;
752
753 default:
754 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
755 return -EINVAL;
756 }
757
758 if (dev->version == MCASP_VERSION_2 && !fifo_level)
759 dma_params->acnt = 4;
760 else
761 dma_params->acnt = dma_params->data_type;
762
763 dma_params->fifo_level = fifo_level;
764 davinci_config_channel_size(dev, word_length);
765
766 return 0;
767}
768
769static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
770 int cmd, struct snd_soc_dai *cpu_dai)
771{
772 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
773 int ret = 0;
774
775 switch (cmd) {
776 case SNDRV_PCM_TRIGGER_RESUME:
777 case SNDRV_PCM_TRIGGER_START:
778 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
779 if (!dev->clk_active) {
780 clk_enable(dev->clk);
781 dev->clk_active = 1;
782 }
783 davinci_mcasp_start(dev, substream->stream);
784 break;
785
786 case SNDRV_PCM_TRIGGER_SUSPEND:
787 davinci_mcasp_stop(dev, substream->stream);
788 if (dev->clk_active) {
789 clk_disable(dev->clk);
790 dev->clk_active = 0;
791 }
792
793 break;
794
795 case SNDRV_PCM_TRIGGER_STOP:
796 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
797 davinci_mcasp_stop(dev, substream->stream);
798 break;
799
800 default:
801 ret = -EINVAL;
802 }
803
804 return ret;
805}
806
807static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
808 struct snd_soc_dai *dai)
809{
810 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
811
812 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
813 return 0;
814}
815
816static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
817 .startup = davinci_mcasp_startup,
818 .trigger = davinci_mcasp_trigger,
819 .hw_params = davinci_mcasp_hw_params,
820 .set_fmt = davinci_mcasp_set_dai_fmt,
821
822};
823
824#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
825 SNDRV_PCM_FMTBIT_U8 | \
826 SNDRV_PCM_FMTBIT_S16_LE | \
827 SNDRV_PCM_FMTBIT_U16_LE | \
828 SNDRV_PCM_FMTBIT_S32_LE | \
829 SNDRV_PCM_FMTBIT_U32_LE)
830
831static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
832 {
833 .name = "davinci-mcasp.0",
834 .playback = {
835 .channels_min = 2,
836 .channels_max = 2,
837 .rates = DAVINCI_MCASP_RATES,
838 .formats = DAVINCI_MCASP_PCM_FMTS,
839 },
840 .capture = {
841 .channels_min = 2,
842 .channels_max = 2,
843 .rates = DAVINCI_MCASP_RATES,
844 .formats = DAVINCI_MCASP_PCM_FMTS,
845 },
846 .ops = &davinci_mcasp_dai_ops,
847
848 },
849 {
850 "davinci-mcasp.1",
851 .playback = {
852 .channels_min = 1,
853 .channels_max = 384,
854 .rates = DAVINCI_MCASP_RATES,
855 .formats = DAVINCI_MCASP_PCM_FMTS,
856 },
857 .ops = &davinci_mcasp_dai_ops,
858 },
859
860};
861
862static int davinci_mcasp_probe(struct platform_device *pdev)
863{
864 struct davinci_pcm_dma_params *dma_data;
865 struct resource *mem, *ioarea, *res;
866 struct snd_platform_data *pdata;
867 struct davinci_audio_dev *dev;
868 int ret;
869
870 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
871 GFP_KERNEL);
872 if (!dev)
873 return -ENOMEM;
874
875 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
876 if (!mem) {
877 dev_err(&pdev->dev, "no mem resource?\n");
878 return -ENODEV;
879 }
880
881 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
882 resource_size(mem), pdev->name);
883 if (!ioarea) {
884 dev_err(&pdev->dev, "Audio region already claimed\n");
885 return -EBUSY;
886 }
887
888 pdata = pdev->dev.platform_data;
889 dev->clk = clk_get(&pdev->dev, NULL);
890 if (IS_ERR(dev->clk))
891 return -ENODEV;
892
893 clk_enable(dev->clk);
894 dev->clk_active = 1;
895
896 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
897 if (!dev->base) {
898 dev_err(&pdev->dev, "ioremap failed\n");
899 ret = -ENOMEM;
900 goto err_release_clk;
901 }
902
903 dev->op_mode = pdata->op_mode;
904 dev->tdm_slots = pdata->tdm_slots;
905 dev->num_serializer = pdata->num_serializer;
906 dev->serial_dir = pdata->serial_dir;
907 dev->codec_fmt = pdata->codec_fmt;
908 dev->version = pdata->version;
909 dev->txnumevt = pdata->txnumevt;
910 dev->rxnumevt = pdata->rxnumevt;
911
912 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
913 dma_data->asp_chan_q = pdata->asp_chan_q;
914 dma_data->ram_chan_q = pdata->ram_chan_q;
915 dma_data->sram_size = pdata->sram_size_playback;
916 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
917 mem->start);
918
919 /* first TX, then RX */
920 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
921 if (!res) {
922 dev_err(&pdev->dev, "no DMA resource\n");
923 ret = -ENODEV;
924 goto err_release_clk;
925 }
926
927 dma_data->channel = res->start;
928
929 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
930 dma_data->asp_chan_q = pdata->asp_chan_q;
931 dma_data->ram_chan_q = pdata->ram_chan_q;
932 dma_data->sram_size = pdata->sram_size_capture;
933 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
934 mem->start);
935
936 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
937 if (!res) {
938 dev_err(&pdev->dev, "no DMA resource\n");
939 ret = -ENODEV;
940 goto err_release_clk;
941 }
942
943 dma_data->channel = res->start;
944 dev_set_drvdata(&pdev->dev, dev);
945 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
946
947 if (ret != 0)
948 goto err_release_clk;
949 return 0;
950
951err_release_clk:
952 clk_disable(dev->clk);
953 clk_put(dev->clk);
954 return ret;
955}
956
957static int davinci_mcasp_remove(struct platform_device *pdev)
958{
959 struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
960
961 snd_soc_unregister_dai(&pdev->dev);
962 clk_disable(dev->clk);
963 clk_put(dev->clk);
964 dev->clk = NULL;
965
966 return 0;
967}
968
969static struct platform_driver davinci_mcasp_driver = {
970 .probe = davinci_mcasp_probe,
971 .remove = davinci_mcasp_remove,
972 .driver = {
973 .name = "davinci-mcasp",
974 .owner = THIS_MODULE,
975 },
976};
977
978module_platform_driver(davinci_mcasp_driver);
979
980MODULE_AUTHOR("Steve Chen");
981MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
982MODULE_LICENSE("GPL");
983