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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/dmaengine.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/pinctrl/consumer.h>
13#include <linux/platform_device.h>
14#include <linux/spi/spi.h>
15#include <linux/pm_runtime.h>
16#include <linux/scatterlist.h>
17
18#define DRIVER_NAME "rockchip-spi"
19
20#define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
22#define ROCKCHIP_SPI_SET_BITS(reg, bits) \
23 writel_relaxed(readl_relaxed(reg) | (bits), reg)
24
25/* SPI register offsets */
26#define ROCKCHIP_SPI_CTRLR0 0x0000
27#define ROCKCHIP_SPI_CTRLR1 0x0004
28#define ROCKCHIP_SPI_SSIENR 0x0008
29#define ROCKCHIP_SPI_SER 0x000c
30#define ROCKCHIP_SPI_BAUDR 0x0010
31#define ROCKCHIP_SPI_TXFTLR 0x0014
32#define ROCKCHIP_SPI_RXFTLR 0x0018
33#define ROCKCHIP_SPI_TXFLR 0x001c
34#define ROCKCHIP_SPI_RXFLR 0x0020
35#define ROCKCHIP_SPI_SR 0x0024
36#define ROCKCHIP_SPI_IPR 0x0028
37#define ROCKCHIP_SPI_IMR 0x002c
38#define ROCKCHIP_SPI_ISR 0x0030
39#define ROCKCHIP_SPI_RISR 0x0034
40#define ROCKCHIP_SPI_ICR 0x0038
41#define ROCKCHIP_SPI_DMACR 0x003c
42#define ROCKCHIP_SPI_DMATDLR 0x0040
43#define ROCKCHIP_SPI_DMARDLR 0x0044
44#define ROCKCHIP_SPI_VERSION 0x0048
45#define ROCKCHIP_SPI_TXDR 0x0400
46#define ROCKCHIP_SPI_RXDR 0x0800
47
48/* Bit fields in CTRLR0 */
49#define CR0_DFS_OFFSET 0
50#define CR0_DFS_4BIT 0x0
51#define CR0_DFS_8BIT 0x1
52#define CR0_DFS_16BIT 0x2
53
54#define CR0_CFS_OFFSET 2
55
56#define CR0_SCPH_OFFSET 6
57
58#define CR0_SCPOL_OFFSET 7
59
60#define CR0_CSM_OFFSET 8
61#define CR0_CSM_KEEP 0x0
62/* ss_n be high for half sclk_out cycles */
63#define CR0_CSM_HALF 0X1
64/* ss_n be high for one sclk_out cycle */
65#define CR0_CSM_ONE 0x2
66
67/* ss_n to sclk_out delay */
68#define CR0_SSD_OFFSET 10
69/*
70 * The period between ss_n active and
71 * sclk_out active is half sclk_out cycles
72 */
73#define CR0_SSD_HALF 0x0
74/*
75 * The period between ss_n active and
76 * sclk_out active is one sclk_out cycle
77 */
78#define CR0_SSD_ONE 0x1
79
80#define CR0_EM_OFFSET 11
81#define CR0_EM_LITTLE 0x0
82#define CR0_EM_BIG 0x1
83
84#define CR0_FBM_OFFSET 12
85#define CR0_FBM_MSB 0x0
86#define CR0_FBM_LSB 0x1
87
88#define CR0_BHT_OFFSET 13
89#define CR0_BHT_16BIT 0x0
90#define CR0_BHT_8BIT 0x1
91
92#define CR0_RSD_OFFSET 14
93#define CR0_RSD_MAX 0x3
94
95#define CR0_FRF_OFFSET 16
96#define CR0_FRF_SPI 0x0
97#define CR0_FRF_SSP 0x1
98#define CR0_FRF_MICROWIRE 0x2
99
100#define CR0_XFM_OFFSET 18
101#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
102#define CR0_XFM_TR 0x0
103#define CR0_XFM_TO 0x1
104#define CR0_XFM_RO 0x2
105
106#define CR0_OPM_OFFSET 20
107#define CR0_OPM_MASTER 0x0
108#define CR0_OPM_SLAVE 0x1
109
110#define CR0_SOI_OFFSET 23
111
112#define CR0_MTM_OFFSET 0x21
113
114/* Bit fields in SER, 2bit */
115#define SER_MASK 0x3
116
117/* Bit fields in BAUDR */
118#define BAUDR_SCKDV_MIN 2
119#define BAUDR_SCKDV_MAX 65534
120
121/* Bit fields in SR, 6bit */
122#define SR_MASK 0x3f
123#define SR_BUSY (1 << 0)
124#define SR_TF_FULL (1 << 1)
125#define SR_TF_EMPTY (1 << 2)
126#define SR_RF_EMPTY (1 << 3)
127#define SR_RF_FULL (1 << 4)
128#define SR_SLAVE_TX_BUSY (1 << 5)
129
130/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
131#define INT_MASK 0x1f
132#define INT_TF_EMPTY (1 << 0)
133#define INT_TF_OVERFLOW (1 << 1)
134#define INT_RF_UNDERFLOW (1 << 2)
135#define INT_RF_OVERFLOW (1 << 3)
136#define INT_RF_FULL (1 << 4)
137#define INT_CS_INACTIVE (1 << 6)
138
139/* Bit fields in ICR, 4bit */
140#define ICR_MASK 0x0f
141#define ICR_ALL (1 << 0)
142#define ICR_RF_UNDERFLOW (1 << 1)
143#define ICR_RF_OVERFLOW (1 << 2)
144#define ICR_TF_OVERFLOW (1 << 3)
145
146/* Bit fields in DMACR */
147#define RF_DMA_EN (1 << 0)
148#define TF_DMA_EN (1 << 1)
149
150/* Driver state flags */
151#define RXDMA (1 << 0)
152#define TXDMA (1 << 1)
153
154/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
155#define MAX_SCLK_OUT 50000000U
156
157/*
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
159 * the controller seems to hang when given 0x10000, so stick with this for now.
160 */
161#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
162
163/* 2 for native cs, 2 for cs-gpio */
164#define ROCKCHIP_SPI_MAX_CS_NUM 4
165#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
166#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
167
168#define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000
169
170struct rockchip_spi {
171 struct device *dev;
172
173 struct clk *spiclk;
174 struct clk *apb_pclk;
175
176 void __iomem *regs;
177 dma_addr_t dma_addr_rx;
178 dma_addr_t dma_addr_tx;
179
180 const void *tx;
181 void *rx;
182 unsigned int tx_left;
183 unsigned int rx_left;
184
185 atomic_t state;
186
187 /*depth of the FIFO buffer */
188 u32 fifo_len;
189 /* frequency of spiclk */
190 u32 freq;
191
192 u8 n_bytes;
193 u8 rsd;
194
195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
196
197 bool slave_abort;
198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */
199 bool cs_high_supported; /* native CS supports active-high polarity */
200
201 struct spi_transfer *xfer; /* Store xfer temporarily */
202};
203
204static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
205{
206 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
207}
208
209static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
210{
211 unsigned long timeout = jiffies + msecs_to_jiffies(5);
212
213 do {
214 if (slave_mode) {
215 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
216 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
217 return;
218 } else {
219 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
220 return;
221 }
222 } while (!time_after(jiffies, timeout));
223
224 dev_warn(rs->dev, "spi controller is in busy state!\n");
225}
226
227static u32 get_fifo_len(struct rockchip_spi *rs)
228{
229 u32 ver;
230
231 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
232
233 switch (ver) {
234 case ROCKCHIP_SPI_VER2_TYPE1:
235 case ROCKCHIP_SPI_VER2_TYPE2:
236 return 64;
237 default:
238 return 32;
239 }
240}
241
242static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
243{
244 struct spi_controller *ctlr = spi->controller;
245 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
246 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
247
248 /* Return immediately for no-op */
249 if (cs_asserted == rs->cs_asserted[spi->chip_select])
250 return;
251
252 if (cs_asserted) {
253 /* Keep things powered as long as CS is asserted */
254 pm_runtime_get_sync(rs->dev);
255
256 if (spi->cs_gpiod)
257 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
258 else
259 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
260 } else {
261 if (spi->cs_gpiod)
262 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
263 else
264 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
265
266 /* Drop reference from when we first asserted CS */
267 pm_runtime_put(rs->dev);
268 }
269
270 rs->cs_asserted[spi->chip_select] = cs_asserted;
271}
272
273static void rockchip_spi_handle_err(struct spi_controller *ctlr,
274 struct spi_message *msg)
275{
276 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
277
278 /* stop running spi transfer
279 * this also flushes both rx and tx fifos
280 */
281 spi_enable_chip(rs, false);
282
283 /* make sure all interrupts are masked and status cleared */
284 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
285 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
286
287 if (atomic_read(&rs->state) & TXDMA)
288 dmaengine_terminate_async(ctlr->dma_tx);
289
290 if (atomic_read(&rs->state) & RXDMA)
291 dmaengine_terminate_async(ctlr->dma_rx);
292}
293
294static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
295{
296 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
297 u32 words = min(rs->tx_left, tx_free);
298
299 rs->tx_left -= words;
300 for (; words; words--) {
301 u32 txw;
302
303 if (rs->n_bytes == 1)
304 txw = *(u8 *)rs->tx;
305 else
306 txw = *(u16 *)rs->tx;
307
308 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
309 rs->tx += rs->n_bytes;
310 }
311}
312
313static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
314{
315 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
316 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
317
318 /* the hardware doesn't allow us to change fifo threshold
319 * level while spi is enabled, so instead make sure to leave
320 * enough words in the rx fifo to get the last interrupt
321 * exactly when all words have been received
322 */
323 if (rx_left) {
324 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
325
326 if (rx_left < ftl) {
327 rx_left = ftl;
328 words = rs->rx_left - rx_left;
329 }
330 }
331
332 rs->rx_left = rx_left;
333 for (; words; words--) {
334 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
335
336 if (!rs->rx)
337 continue;
338
339 if (rs->n_bytes == 1)
340 *(u8 *)rs->rx = (u8)rxw;
341 else
342 *(u16 *)rs->rx = (u16)rxw;
343 rs->rx += rs->n_bytes;
344 }
345}
346
347static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
348{
349 struct spi_controller *ctlr = dev_id;
350 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
351
352 /* When int_cs_inactive comes, spi slave abort */
353 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
354 ctlr->slave_abort(ctlr);
355 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
356 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
357
358 return IRQ_HANDLED;
359 }
360
361 if (rs->tx_left)
362 rockchip_spi_pio_writer(rs);
363
364 rockchip_spi_pio_reader(rs);
365 if (!rs->rx_left) {
366 spi_enable_chip(rs, false);
367 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
368 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
369 spi_finalize_current_transfer(ctlr);
370 }
371
372 return IRQ_HANDLED;
373}
374
375static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
376 struct spi_controller *ctlr,
377 struct spi_transfer *xfer)
378{
379 rs->tx = xfer->tx_buf;
380 rs->rx = xfer->rx_buf;
381 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
382 rs->rx_left = xfer->len / rs->n_bytes;
383
384 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
385
386 spi_enable_chip(rs, true);
387
388 if (rs->tx_left)
389 rockchip_spi_pio_writer(rs);
390
391 if (rs->cs_inactive)
392 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
393 else
394 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
395
396 /* 1 means the transfer is in progress */
397 return 1;
398}
399
400static void rockchip_spi_dma_rxcb(void *data)
401{
402 struct spi_controller *ctlr = data;
403 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
404 int state = atomic_fetch_andnot(RXDMA, &rs->state);
405
406 if (state & TXDMA && !rs->slave_abort)
407 return;
408
409 if (rs->cs_inactive)
410 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
411
412 spi_enable_chip(rs, false);
413 spi_finalize_current_transfer(ctlr);
414}
415
416static void rockchip_spi_dma_txcb(void *data)
417{
418 struct spi_controller *ctlr = data;
419 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
420 int state = atomic_fetch_andnot(TXDMA, &rs->state);
421
422 if (state & RXDMA && !rs->slave_abort)
423 return;
424
425 /* Wait until the FIFO data completely. */
426 wait_for_tx_idle(rs, ctlr->slave);
427
428 spi_enable_chip(rs, false);
429 spi_finalize_current_transfer(ctlr);
430}
431
432static u32 rockchip_spi_calc_burst_size(u32 data_len)
433{
434 u32 i;
435
436 /* burst size: 1, 2, 4, 8 */
437 for (i = 1; i < 8; i <<= 1) {
438 if (data_len & i)
439 break;
440 }
441
442 return i;
443}
444
445static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
446 struct spi_controller *ctlr, struct spi_transfer *xfer)
447{
448 struct dma_async_tx_descriptor *rxdesc, *txdesc;
449
450 atomic_set(&rs->state, 0);
451
452 rs->tx = xfer->tx_buf;
453 rs->rx = xfer->rx_buf;
454
455 rxdesc = NULL;
456 if (xfer->rx_buf) {
457 struct dma_slave_config rxconf = {
458 .direction = DMA_DEV_TO_MEM,
459 .src_addr = rs->dma_addr_rx,
460 .src_addr_width = rs->n_bytes,
461 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
462 };
463
464 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
465
466 rxdesc = dmaengine_prep_slave_sg(
467 ctlr->dma_rx,
468 xfer->rx_sg.sgl, xfer->rx_sg.nents,
469 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
470 if (!rxdesc)
471 return -EINVAL;
472
473 rxdesc->callback = rockchip_spi_dma_rxcb;
474 rxdesc->callback_param = ctlr;
475 }
476
477 txdesc = NULL;
478 if (xfer->tx_buf) {
479 struct dma_slave_config txconf = {
480 .direction = DMA_MEM_TO_DEV,
481 .dst_addr = rs->dma_addr_tx,
482 .dst_addr_width = rs->n_bytes,
483 .dst_maxburst = rs->fifo_len / 4,
484 };
485
486 dmaengine_slave_config(ctlr->dma_tx, &txconf);
487
488 txdesc = dmaengine_prep_slave_sg(
489 ctlr->dma_tx,
490 xfer->tx_sg.sgl, xfer->tx_sg.nents,
491 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
492 if (!txdesc) {
493 if (rxdesc)
494 dmaengine_terminate_sync(ctlr->dma_rx);
495 return -EINVAL;
496 }
497
498 txdesc->callback = rockchip_spi_dma_txcb;
499 txdesc->callback_param = ctlr;
500 }
501
502 /* rx must be started before tx due to spi instinct */
503 if (rxdesc) {
504 atomic_or(RXDMA, &rs->state);
505 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
506 dma_async_issue_pending(ctlr->dma_rx);
507 }
508
509 if (rs->cs_inactive)
510 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
511
512 spi_enable_chip(rs, true);
513
514 if (txdesc) {
515 atomic_or(TXDMA, &rs->state);
516 dmaengine_submit(txdesc);
517 dma_async_issue_pending(ctlr->dma_tx);
518 }
519
520 /* 1 means the transfer is in progress */
521 return 1;
522}
523
524static int rockchip_spi_config(struct rockchip_spi *rs,
525 struct spi_device *spi, struct spi_transfer *xfer,
526 bool use_dma, bool slave_mode)
527{
528 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
529 | CR0_BHT_8BIT << CR0_BHT_OFFSET
530 | CR0_SSD_ONE << CR0_SSD_OFFSET
531 | CR0_EM_BIG << CR0_EM_OFFSET;
532 u32 cr1;
533 u32 dmacr = 0;
534
535 if (slave_mode)
536 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
537 rs->slave_abort = false;
538
539 cr0 |= rs->rsd << CR0_RSD_OFFSET;
540 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
541 if (spi->mode & SPI_LSB_FIRST)
542 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
543 if (spi->mode & SPI_CS_HIGH)
544 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
545
546 if (xfer->rx_buf && xfer->tx_buf)
547 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
548 else if (xfer->rx_buf)
549 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
550 else if (use_dma)
551 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
552
553 switch (xfer->bits_per_word) {
554 case 4:
555 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
556 cr1 = xfer->len - 1;
557 break;
558 case 8:
559 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
560 cr1 = xfer->len - 1;
561 break;
562 case 16:
563 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
564 cr1 = xfer->len / 2 - 1;
565 break;
566 default:
567 /* we only whitelist 4, 8 and 16 bit words in
568 * ctlr->bits_per_word_mask, so this shouldn't
569 * happen
570 */
571 dev_err(rs->dev, "unknown bits per word: %d\n",
572 xfer->bits_per_word);
573 return -EINVAL;
574 }
575
576 if (use_dma) {
577 if (xfer->tx_buf)
578 dmacr |= TF_DMA_EN;
579 if (xfer->rx_buf)
580 dmacr |= RF_DMA_EN;
581 }
582
583 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
584 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
585
586 /* unfortunately setting the fifo threshold level to generate an
587 * interrupt exactly when the fifo is full doesn't seem to work,
588 * so we need the strict inequality here
589 */
590 if ((xfer->len / rs->n_bytes) < rs->fifo_len)
591 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
592 else
593 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
594
595 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
596 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
597 rs->regs + ROCKCHIP_SPI_DMARDLR);
598 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
599
600 /* the hardware only supports an even clock divisor, so
601 * round divisor = spiclk / speed up to nearest even number
602 * so that the resulting speed is <= the requested speed
603 */
604 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
605 rs->regs + ROCKCHIP_SPI_BAUDR);
606
607 return 0;
608}
609
610static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
611{
612 return ROCKCHIP_SPI_MAX_TRANLEN;
613}
614
615static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
616{
617 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
618 u32 rx_fifo_left;
619 struct dma_tx_state state;
620 enum dma_status status;
621
622 /* Get current dma rx point */
623 if (atomic_read(&rs->state) & RXDMA) {
624 dmaengine_pause(ctlr->dma_rx);
625 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
626 if (status == DMA_ERROR) {
627 rs->rx = rs->xfer->rx_buf;
628 rs->xfer->len = 0;
629 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
630 for (; rx_fifo_left; rx_fifo_left--)
631 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
632 goto out;
633 } else {
634 rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
635 }
636 }
637
638 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
639 if (rs->rx) {
640 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
641 for (; rx_fifo_left; rx_fifo_left--) {
642 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
643
644 if (rs->n_bytes == 1)
645 *(u8 *)rs->rx = (u8)rxw;
646 else
647 *(u16 *)rs->rx = (u16)rxw;
648 rs->rx += rs->n_bytes;
649 }
650 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
651 }
652
653out:
654 if (atomic_read(&rs->state) & RXDMA)
655 dmaengine_terminate_sync(ctlr->dma_rx);
656 if (atomic_read(&rs->state) & TXDMA)
657 dmaengine_terminate_sync(ctlr->dma_tx);
658 atomic_set(&rs->state, 0);
659 spi_enable_chip(rs, false);
660 rs->slave_abort = true;
661 spi_finalize_current_transfer(ctlr);
662
663 return 0;
664}
665
666static int rockchip_spi_transfer_one(
667 struct spi_controller *ctlr,
668 struct spi_device *spi,
669 struct spi_transfer *xfer)
670{
671 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
672 int ret;
673 bool use_dma;
674
675 /* Zero length transfers won't trigger an interrupt on completion */
676 if (!xfer->len) {
677 spi_finalize_current_transfer(ctlr);
678 return 1;
679 }
680
681 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
682 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
683
684 if (!xfer->tx_buf && !xfer->rx_buf) {
685 dev_err(rs->dev, "No buffer for transfer\n");
686 return -EINVAL;
687 }
688
689 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
690 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
691 return -EINVAL;
692 }
693
694 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
695 rs->xfer = xfer;
696 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
697
698 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
699 if (ret)
700 return ret;
701
702 if (use_dma)
703 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
704
705 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
706}
707
708static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
709 struct spi_device *spi,
710 struct spi_transfer *xfer)
711{
712 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
713 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
714
715 /* if the numbor of spi words to transfer is less than the fifo
716 * length we can just fill the fifo and wait for a single irq,
717 * so don't bother setting up dma
718 */
719 return xfer->len / bytes_per_word >= rs->fifo_len;
720}
721
722static int rockchip_spi_setup(struct spi_device *spi)
723{
724 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
725 u32 cr0;
726
727 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
728 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
729 return -EINVAL;
730 }
731
732 pm_runtime_get_sync(rs->dev);
733
734 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
735
736 cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
737 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
738 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
739 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
740 else if (spi->chip_select <= 1)
741 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
742
743 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
744
745 pm_runtime_put(rs->dev);
746
747 return 0;
748}
749
750static int rockchip_spi_probe(struct platform_device *pdev)
751{
752 int ret;
753 struct rockchip_spi *rs;
754 struct spi_controller *ctlr;
755 struct resource *mem;
756 struct device_node *np = pdev->dev.of_node;
757 u32 rsd_nsecs, num_cs;
758 bool slave_mode;
759
760 slave_mode = of_property_read_bool(np, "spi-slave");
761
762 if (slave_mode)
763 ctlr = spi_alloc_slave(&pdev->dev,
764 sizeof(struct rockchip_spi));
765 else
766 ctlr = spi_alloc_master(&pdev->dev,
767 sizeof(struct rockchip_spi));
768
769 if (!ctlr)
770 return -ENOMEM;
771
772 platform_set_drvdata(pdev, ctlr);
773
774 rs = spi_controller_get_devdata(ctlr);
775 ctlr->slave = slave_mode;
776
777 /* Get basic io resource and map it */
778 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
779 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
780 if (IS_ERR(rs->regs)) {
781 ret = PTR_ERR(rs->regs);
782 goto err_put_ctlr;
783 }
784
785 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
786 if (IS_ERR(rs->apb_pclk)) {
787 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
788 ret = PTR_ERR(rs->apb_pclk);
789 goto err_put_ctlr;
790 }
791
792 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
793 if (IS_ERR(rs->spiclk)) {
794 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
795 ret = PTR_ERR(rs->spiclk);
796 goto err_put_ctlr;
797 }
798
799 ret = clk_prepare_enable(rs->apb_pclk);
800 if (ret < 0) {
801 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
802 goto err_put_ctlr;
803 }
804
805 ret = clk_prepare_enable(rs->spiclk);
806 if (ret < 0) {
807 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
808 goto err_disable_apbclk;
809 }
810
811 spi_enable_chip(rs, false);
812
813 ret = platform_get_irq(pdev, 0);
814 if (ret < 0)
815 goto err_disable_spiclk;
816
817 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
818 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
819 if (ret)
820 goto err_disable_spiclk;
821
822 rs->dev = &pdev->dev;
823 rs->freq = clk_get_rate(rs->spiclk);
824
825 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
826 &rsd_nsecs)) {
827 /* rx sample delay is expressed in parent clock cycles (max 3) */
828 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
829 1000000000 >> 8);
830 if (!rsd) {
831 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
832 rs->freq, rsd_nsecs);
833 } else if (rsd > CR0_RSD_MAX) {
834 rsd = CR0_RSD_MAX;
835 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
836 rs->freq, rsd_nsecs,
837 CR0_RSD_MAX * 1000000000U / rs->freq);
838 }
839 rs->rsd = rsd;
840 }
841
842 rs->fifo_len = get_fifo_len(rs);
843 if (!rs->fifo_len) {
844 dev_err(&pdev->dev, "Failed to get fifo length\n");
845 ret = -EINVAL;
846 goto err_disable_spiclk;
847 }
848
849 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
850 pm_runtime_use_autosuspend(&pdev->dev);
851 pm_runtime_set_active(&pdev->dev);
852 pm_runtime_enable(&pdev->dev);
853
854 ctlr->auto_runtime_pm = true;
855 ctlr->bus_num = pdev->id;
856 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
857 if (slave_mode) {
858 ctlr->mode_bits |= SPI_NO_CS;
859 ctlr->slave_abort = rockchip_spi_slave_abort;
860 } else {
861 ctlr->flags = SPI_MASTER_GPIO_SS;
862 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
863 /*
864 * rk spi0 has two native cs, spi1..5 one cs only
865 * if num-cs is missing in the dts, default to 1
866 */
867 if (of_property_read_u32(np, "num-cs", &num_cs))
868 num_cs = 1;
869 ctlr->num_chipselect = num_cs;
870 ctlr->use_gpio_descriptors = true;
871 }
872 ctlr->dev.of_node = pdev->dev.of_node;
873 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
874 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
875 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
876
877 ctlr->setup = rockchip_spi_setup;
878 ctlr->set_cs = rockchip_spi_set_cs;
879 ctlr->transfer_one = rockchip_spi_transfer_one;
880 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
881 ctlr->handle_err = rockchip_spi_handle_err;
882
883 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
884 if (IS_ERR(ctlr->dma_tx)) {
885 /* Check tx to see if we need defer probing driver */
886 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
887 ret = -EPROBE_DEFER;
888 goto err_disable_pm_runtime;
889 }
890 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
891 ctlr->dma_tx = NULL;
892 }
893
894 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
895 if (IS_ERR(ctlr->dma_rx)) {
896 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
897 ret = -EPROBE_DEFER;
898 goto err_free_dma_tx;
899 }
900 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
901 ctlr->dma_rx = NULL;
902 }
903
904 if (ctlr->dma_tx && ctlr->dma_rx) {
905 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
906 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
907 ctlr->can_dma = rockchip_spi_can_dma;
908 }
909
910 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
911 case ROCKCHIP_SPI_VER2_TYPE2:
912 rs->cs_high_supported = true;
913 ctlr->mode_bits |= SPI_CS_HIGH;
914 if (ctlr->can_dma && slave_mode)
915 rs->cs_inactive = true;
916 else
917 rs->cs_inactive = false;
918 break;
919 default:
920 rs->cs_inactive = false;
921 break;
922 }
923
924 ret = devm_spi_register_controller(&pdev->dev, ctlr);
925 if (ret < 0) {
926 dev_err(&pdev->dev, "Failed to register controller\n");
927 goto err_free_dma_rx;
928 }
929
930 return 0;
931
932err_free_dma_rx:
933 if (ctlr->dma_rx)
934 dma_release_channel(ctlr->dma_rx);
935err_free_dma_tx:
936 if (ctlr->dma_tx)
937 dma_release_channel(ctlr->dma_tx);
938err_disable_pm_runtime:
939 pm_runtime_disable(&pdev->dev);
940err_disable_spiclk:
941 clk_disable_unprepare(rs->spiclk);
942err_disable_apbclk:
943 clk_disable_unprepare(rs->apb_pclk);
944err_put_ctlr:
945 spi_controller_put(ctlr);
946
947 return ret;
948}
949
950static int rockchip_spi_remove(struct platform_device *pdev)
951{
952 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
953 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
954
955 pm_runtime_get_sync(&pdev->dev);
956
957 clk_disable_unprepare(rs->spiclk);
958 clk_disable_unprepare(rs->apb_pclk);
959
960 pm_runtime_put_noidle(&pdev->dev);
961 pm_runtime_disable(&pdev->dev);
962 pm_runtime_set_suspended(&pdev->dev);
963
964 if (ctlr->dma_tx)
965 dma_release_channel(ctlr->dma_tx);
966 if (ctlr->dma_rx)
967 dma_release_channel(ctlr->dma_rx);
968
969 spi_controller_put(ctlr);
970
971 return 0;
972}
973
974#ifdef CONFIG_PM_SLEEP
975static int rockchip_spi_suspend(struct device *dev)
976{
977 int ret;
978 struct spi_controller *ctlr = dev_get_drvdata(dev);
979 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
980
981 ret = spi_controller_suspend(ctlr);
982 if (ret < 0)
983 return ret;
984
985 clk_disable_unprepare(rs->spiclk);
986 clk_disable_unprepare(rs->apb_pclk);
987
988 pinctrl_pm_select_sleep_state(dev);
989
990 return 0;
991}
992
993static int rockchip_spi_resume(struct device *dev)
994{
995 int ret;
996 struct spi_controller *ctlr = dev_get_drvdata(dev);
997 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
998
999 pinctrl_pm_select_default_state(dev);
1000
1001 ret = clk_prepare_enable(rs->apb_pclk);
1002 if (ret < 0)
1003 return ret;
1004
1005 ret = clk_prepare_enable(rs->spiclk);
1006 if (ret < 0)
1007 clk_disable_unprepare(rs->apb_pclk);
1008
1009 ret = spi_controller_resume(ctlr);
1010 if (ret < 0) {
1011 clk_disable_unprepare(rs->spiclk);
1012 clk_disable_unprepare(rs->apb_pclk);
1013 }
1014
1015 return 0;
1016}
1017#endif /* CONFIG_PM_SLEEP */
1018
1019#ifdef CONFIG_PM
1020static int rockchip_spi_runtime_suspend(struct device *dev)
1021{
1022 struct spi_controller *ctlr = dev_get_drvdata(dev);
1023 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1024
1025 clk_disable_unprepare(rs->spiclk);
1026 clk_disable_unprepare(rs->apb_pclk);
1027
1028 return 0;
1029}
1030
1031static int rockchip_spi_runtime_resume(struct device *dev)
1032{
1033 int ret;
1034 struct spi_controller *ctlr = dev_get_drvdata(dev);
1035 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1036
1037 ret = clk_prepare_enable(rs->apb_pclk);
1038 if (ret < 0)
1039 return ret;
1040
1041 ret = clk_prepare_enable(rs->spiclk);
1042 if (ret < 0)
1043 clk_disable_unprepare(rs->apb_pclk);
1044
1045 return 0;
1046}
1047#endif /* CONFIG_PM */
1048
1049static const struct dev_pm_ops rockchip_spi_pm = {
1050 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1051 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1052 rockchip_spi_runtime_resume, NULL)
1053};
1054
1055static const struct of_device_id rockchip_spi_dt_match[] = {
1056 { .compatible = "rockchip,px30-spi", },
1057 { .compatible = "rockchip,rk3036-spi", },
1058 { .compatible = "rockchip,rk3066-spi", },
1059 { .compatible = "rockchip,rk3188-spi", },
1060 { .compatible = "rockchip,rk3228-spi", },
1061 { .compatible = "rockchip,rk3288-spi", },
1062 { .compatible = "rockchip,rk3308-spi", },
1063 { .compatible = "rockchip,rk3328-spi", },
1064 { .compatible = "rockchip,rk3368-spi", },
1065 { .compatible = "rockchip,rk3399-spi", },
1066 { .compatible = "rockchip,rv1108-spi", },
1067 { .compatible = "rockchip,rv1126-spi", },
1068 { },
1069};
1070MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1071
1072static struct platform_driver rockchip_spi_driver = {
1073 .driver = {
1074 .name = DRIVER_NAME,
1075 .pm = &rockchip_spi_pm,
1076 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1077 },
1078 .probe = rockchip_spi_probe,
1079 .remove = rockchip_spi_remove,
1080};
1081
1082module_platform_driver(rockchip_spi_driver);
1083
1084MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1085MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1086MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/dmaengine.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/pm_runtime.h>
24#include <linux/scatterlist.h>
25
26#define DRIVER_NAME "rockchip-spi"
27
28#define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
29 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
30#define ROCKCHIP_SPI_SET_BITS(reg, bits) \
31 writel_relaxed(readl_relaxed(reg) | (bits), reg)
32
33/* SPI register offsets */
34#define ROCKCHIP_SPI_CTRLR0 0x0000
35#define ROCKCHIP_SPI_CTRLR1 0x0004
36#define ROCKCHIP_SPI_SSIENR 0x0008
37#define ROCKCHIP_SPI_SER 0x000c
38#define ROCKCHIP_SPI_BAUDR 0x0010
39#define ROCKCHIP_SPI_TXFTLR 0x0014
40#define ROCKCHIP_SPI_RXFTLR 0x0018
41#define ROCKCHIP_SPI_TXFLR 0x001c
42#define ROCKCHIP_SPI_RXFLR 0x0020
43#define ROCKCHIP_SPI_SR 0x0024
44#define ROCKCHIP_SPI_IPR 0x0028
45#define ROCKCHIP_SPI_IMR 0x002c
46#define ROCKCHIP_SPI_ISR 0x0030
47#define ROCKCHIP_SPI_RISR 0x0034
48#define ROCKCHIP_SPI_ICR 0x0038
49#define ROCKCHIP_SPI_DMACR 0x003c
50#define ROCKCHIP_SPI_DMATDLR 0x0040
51#define ROCKCHIP_SPI_DMARDLR 0x0044
52#define ROCKCHIP_SPI_TXDR 0x0400
53#define ROCKCHIP_SPI_RXDR 0x0800
54
55/* Bit fields in CTRLR0 */
56#define CR0_DFS_OFFSET 0
57
58#define CR0_CFS_OFFSET 2
59
60#define CR0_SCPH_OFFSET 6
61
62#define CR0_SCPOL_OFFSET 7
63
64#define CR0_CSM_OFFSET 8
65#define CR0_CSM_KEEP 0x0
66/* ss_n be high for half sclk_out cycles */
67#define CR0_CSM_HALF 0X1
68/* ss_n be high for one sclk_out cycle */
69#define CR0_CSM_ONE 0x2
70
71/* ss_n to sclk_out delay */
72#define CR0_SSD_OFFSET 10
73/*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77#define CR0_SSD_HALF 0x0
78/*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82#define CR0_SSD_ONE 0x1
83
84#define CR0_EM_OFFSET 11
85#define CR0_EM_LITTLE 0x0
86#define CR0_EM_BIG 0x1
87
88#define CR0_FBM_OFFSET 12
89#define CR0_FBM_MSB 0x0
90#define CR0_FBM_LSB 0x1
91
92#define CR0_BHT_OFFSET 13
93#define CR0_BHT_16BIT 0x0
94#define CR0_BHT_8BIT 0x1
95
96#define CR0_RSD_OFFSET 14
97
98#define CR0_FRF_OFFSET 16
99#define CR0_FRF_SPI 0x0
100#define CR0_FRF_SSP 0x1
101#define CR0_FRF_MICROWIRE 0x2
102
103#define CR0_XFM_OFFSET 18
104#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105#define CR0_XFM_TR 0x0
106#define CR0_XFM_TO 0x1
107#define CR0_XFM_RO 0x2
108
109#define CR0_OPM_OFFSET 20
110#define CR0_OPM_MASTER 0x0
111#define CR0_OPM_SLAVE 0x1
112
113#define CR0_MTM_OFFSET 0x21
114
115/* Bit fields in SER, 2bit */
116#define SER_MASK 0x3
117
118/* Bit fields in SR, 5bit */
119#define SR_MASK 0x1f
120#define SR_BUSY (1 << 0)
121#define SR_TF_FULL (1 << 1)
122#define SR_TF_EMPTY (1 << 2)
123#define SR_RF_EMPTY (1 << 3)
124#define SR_RF_FULL (1 << 4)
125
126/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127#define INT_MASK 0x1f
128#define INT_TF_EMPTY (1 << 0)
129#define INT_TF_OVERFLOW (1 << 1)
130#define INT_RF_UNDERFLOW (1 << 2)
131#define INT_RF_OVERFLOW (1 << 3)
132#define INT_RF_FULL (1 << 4)
133
134/* Bit fields in ICR, 4bit */
135#define ICR_MASK 0x0f
136#define ICR_ALL (1 << 0)
137#define ICR_RF_UNDERFLOW (1 << 1)
138#define ICR_RF_OVERFLOW (1 << 2)
139#define ICR_TF_OVERFLOW (1 << 3)
140
141/* Bit fields in DMACR */
142#define RF_DMA_EN (1 << 0)
143#define TF_DMA_EN (1 << 1)
144
145#define RXBUSY (1 << 0)
146#define TXBUSY (1 << 1)
147
148/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149#define MAX_SCLK_OUT 50000000
150
151/*
152 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
153 * the controller seems to hang when given 0x10000, so stick with this for now.
154 */
155#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
156
157#define ROCKCHIP_SPI_MAX_CS_NUM 2
158
159enum rockchip_ssi_type {
160 SSI_MOTO_SPI = 0,
161 SSI_TI_SSP,
162 SSI_NS_MICROWIRE,
163};
164
165struct rockchip_spi_dma_data {
166 struct dma_chan *ch;
167 enum dma_transfer_direction direction;
168 dma_addr_t addr;
169};
170
171struct rockchip_spi {
172 struct device *dev;
173 struct spi_master *master;
174
175 struct clk *spiclk;
176 struct clk *apb_pclk;
177
178 void __iomem *regs;
179 /*depth of the FIFO buffer */
180 u32 fifo_len;
181 /* max bus freq supported */
182 u32 max_freq;
183 /* supported slave numbers */
184 enum rockchip_ssi_type type;
185
186 u16 mode;
187 u8 tmode;
188 u8 bpw;
189 u8 n_bytes;
190 u32 rsd_nsecs;
191 unsigned len;
192 u32 speed;
193
194 const void *tx;
195 const void *tx_end;
196 void *rx;
197 void *rx_end;
198
199 u32 state;
200 /* protect state */
201 spinlock_t lock;
202
203 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
204
205 u32 use_dma;
206 struct sg_table tx_sg;
207 struct sg_table rx_sg;
208 struct rockchip_spi_dma_data dma_rx;
209 struct rockchip_spi_dma_data dma_tx;
210 struct dma_slave_caps dma_caps;
211};
212
213static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
214{
215 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
216}
217
218static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
219{
220 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
221}
222
223static inline void flush_fifo(struct rockchip_spi *rs)
224{
225 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
226 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
227}
228
229static inline void wait_for_idle(struct rockchip_spi *rs)
230{
231 unsigned long timeout = jiffies + msecs_to_jiffies(5);
232
233 do {
234 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
235 return;
236 } while (!time_after(jiffies, timeout));
237
238 dev_warn(rs->dev, "spi controller is in busy state!\n");
239}
240
241static u32 get_fifo_len(struct rockchip_spi *rs)
242{
243 u32 fifo;
244
245 for (fifo = 2; fifo < 32; fifo++) {
246 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
247 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
248 break;
249 }
250
251 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
252
253 return (fifo == 31) ? 0 : fifo;
254}
255
256static inline u32 tx_max(struct rockchip_spi *rs)
257{
258 u32 tx_left, tx_room;
259
260 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
261 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
262
263 return min(tx_left, tx_room);
264}
265
266static inline u32 rx_max(struct rockchip_spi *rs)
267{
268 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
269 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
270
271 return min(rx_left, rx_room);
272}
273
274static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
275{
276 struct spi_master *master = spi->master;
277 struct rockchip_spi *rs = spi_master_get_devdata(master);
278 bool cs_asserted = !enable;
279
280 /* Return immediately for no-op */
281 if (cs_asserted == rs->cs_asserted[spi->chip_select])
282 return;
283
284 if (cs_asserted) {
285 /* Keep things powered as long as CS is asserted */
286 pm_runtime_get_sync(rs->dev);
287
288 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
289 BIT(spi->chip_select));
290 } else {
291 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
292 BIT(spi->chip_select));
293
294 /* Drop reference from when we first asserted CS */
295 pm_runtime_put(rs->dev);
296 }
297
298 rs->cs_asserted[spi->chip_select] = cs_asserted;
299}
300
301static int rockchip_spi_prepare_message(struct spi_master *master,
302 struct spi_message *msg)
303{
304 struct rockchip_spi *rs = spi_master_get_devdata(master);
305 struct spi_device *spi = msg->spi;
306
307 rs->mode = spi->mode;
308
309 return 0;
310}
311
312static void rockchip_spi_handle_err(struct spi_master *master,
313 struct spi_message *msg)
314{
315 unsigned long flags;
316 struct rockchip_spi *rs = spi_master_get_devdata(master);
317
318 spin_lock_irqsave(&rs->lock, flags);
319
320 /*
321 * For DMA mode, we need terminate DMA channel and flush
322 * fifo for the next transfer if DMA thansfer timeout.
323 * handle_err() was called by core if transfer failed.
324 * Maybe it is reasonable for error handling here.
325 */
326 if (rs->use_dma) {
327 if (rs->state & RXBUSY) {
328 dmaengine_terminate_async(rs->dma_rx.ch);
329 flush_fifo(rs);
330 }
331
332 if (rs->state & TXBUSY)
333 dmaengine_terminate_async(rs->dma_tx.ch);
334 }
335
336 spin_unlock_irqrestore(&rs->lock, flags);
337}
338
339static int rockchip_spi_unprepare_message(struct spi_master *master,
340 struct spi_message *msg)
341{
342 struct rockchip_spi *rs = spi_master_get_devdata(master);
343
344 spi_enable_chip(rs, 0);
345
346 return 0;
347}
348
349static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
350{
351 u32 max = tx_max(rs);
352 u32 txw = 0;
353
354 while (max--) {
355 if (rs->n_bytes == 1)
356 txw = *(u8 *)(rs->tx);
357 else
358 txw = *(u16 *)(rs->tx);
359
360 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
361 rs->tx += rs->n_bytes;
362 }
363}
364
365static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
366{
367 u32 max = rx_max(rs);
368 u32 rxw;
369
370 while (max--) {
371 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
372 if (rs->n_bytes == 1)
373 *(u8 *)(rs->rx) = (u8)rxw;
374 else
375 *(u16 *)(rs->rx) = (u16)rxw;
376 rs->rx += rs->n_bytes;
377 }
378}
379
380static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
381{
382 int remain = 0;
383
384 do {
385 if (rs->tx) {
386 remain = rs->tx_end - rs->tx;
387 rockchip_spi_pio_writer(rs);
388 }
389
390 if (rs->rx) {
391 remain = rs->rx_end - rs->rx;
392 rockchip_spi_pio_reader(rs);
393 }
394
395 cpu_relax();
396 } while (remain);
397
398 /* If tx, wait until the FIFO data completely. */
399 if (rs->tx)
400 wait_for_idle(rs);
401
402 spi_enable_chip(rs, 0);
403
404 return 0;
405}
406
407static void rockchip_spi_dma_rxcb(void *data)
408{
409 unsigned long flags;
410 struct rockchip_spi *rs = data;
411
412 spin_lock_irqsave(&rs->lock, flags);
413
414 rs->state &= ~RXBUSY;
415 if (!(rs->state & TXBUSY)) {
416 spi_enable_chip(rs, 0);
417 spi_finalize_current_transfer(rs->master);
418 }
419
420 spin_unlock_irqrestore(&rs->lock, flags);
421}
422
423static void rockchip_spi_dma_txcb(void *data)
424{
425 unsigned long flags;
426 struct rockchip_spi *rs = data;
427
428 /* Wait until the FIFO data completely. */
429 wait_for_idle(rs);
430
431 spin_lock_irqsave(&rs->lock, flags);
432
433 rs->state &= ~TXBUSY;
434 if (!(rs->state & RXBUSY)) {
435 spi_enable_chip(rs, 0);
436 spi_finalize_current_transfer(rs->master);
437 }
438
439 spin_unlock_irqrestore(&rs->lock, flags);
440}
441
442static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
443{
444 unsigned long flags;
445 struct dma_slave_config rxconf, txconf;
446 struct dma_async_tx_descriptor *rxdesc, *txdesc;
447
448 spin_lock_irqsave(&rs->lock, flags);
449 rs->state &= ~RXBUSY;
450 rs->state &= ~TXBUSY;
451 spin_unlock_irqrestore(&rs->lock, flags);
452
453 rxdesc = NULL;
454 if (rs->rx) {
455 rxconf.direction = rs->dma_rx.direction;
456 rxconf.src_addr = rs->dma_rx.addr;
457 rxconf.src_addr_width = rs->n_bytes;
458 if (rs->dma_caps.max_burst > 4)
459 rxconf.src_maxburst = 4;
460 else
461 rxconf.src_maxburst = 1;
462 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
463
464 rxdesc = dmaengine_prep_slave_sg(
465 rs->dma_rx.ch,
466 rs->rx_sg.sgl, rs->rx_sg.nents,
467 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
468 if (!rxdesc)
469 return -EINVAL;
470
471 rxdesc->callback = rockchip_spi_dma_rxcb;
472 rxdesc->callback_param = rs;
473 }
474
475 txdesc = NULL;
476 if (rs->tx) {
477 txconf.direction = rs->dma_tx.direction;
478 txconf.dst_addr = rs->dma_tx.addr;
479 txconf.dst_addr_width = rs->n_bytes;
480 if (rs->dma_caps.max_burst > 4)
481 txconf.dst_maxburst = 4;
482 else
483 txconf.dst_maxburst = 1;
484 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
485
486 txdesc = dmaengine_prep_slave_sg(
487 rs->dma_tx.ch,
488 rs->tx_sg.sgl, rs->tx_sg.nents,
489 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
490 if (!txdesc) {
491 if (rxdesc)
492 dmaengine_terminate_sync(rs->dma_rx.ch);
493 return -EINVAL;
494 }
495
496 txdesc->callback = rockchip_spi_dma_txcb;
497 txdesc->callback_param = rs;
498 }
499
500 /* rx must be started before tx due to spi instinct */
501 if (rxdesc) {
502 spin_lock_irqsave(&rs->lock, flags);
503 rs->state |= RXBUSY;
504 spin_unlock_irqrestore(&rs->lock, flags);
505 dmaengine_submit(rxdesc);
506 dma_async_issue_pending(rs->dma_rx.ch);
507 }
508
509 if (txdesc) {
510 spin_lock_irqsave(&rs->lock, flags);
511 rs->state |= TXBUSY;
512 spin_unlock_irqrestore(&rs->lock, flags);
513 dmaengine_submit(txdesc);
514 dma_async_issue_pending(rs->dma_tx.ch);
515 }
516
517 return 0;
518}
519
520static void rockchip_spi_config(struct rockchip_spi *rs)
521{
522 u32 div = 0;
523 u32 dmacr = 0;
524 int rsd = 0;
525
526 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
527 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
528 | (CR0_EM_BIG << CR0_EM_OFFSET);
529
530 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
531 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
532 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
533 cr0 |= (rs->type << CR0_FRF_OFFSET);
534
535 if (rs->use_dma) {
536 if (rs->tx)
537 dmacr |= TF_DMA_EN;
538 if (rs->rx)
539 dmacr |= RF_DMA_EN;
540 }
541
542 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
543 rs->speed = MAX_SCLK_OUT;
544
545 /* the minimum divisor is 2 */
546 if (rs->max_freq < 2 * rs->speed) {
547 clk_set_rate(rs->spiclk, 2 * rs->speed);
548 rs->max_freq = clk_get_rate(rs->spiclk);
549 }
550
551 /* div doesn't support odd number */
552 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
553 div = (div + 1) & 0xfffe;
554
555 /* Rx sample delay is expressed in parent clock cycles (max 3) */
556 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
557 1000000000 >> 8);
558 if (!rsd && rs->rsd_nsecs) {
559 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
560 rs->max_freq, rs->rsd_nsecs);
561 } else if (rsd > 3) {
562 rsd = 3;
563 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
564 rs->max_freq, rs->rsd_nsecs,
565 rsd * 1000000000U / rs->max_freq);
566 }
567 cr0 |= rsd << CR0_RSD_OFFSET;
568
569 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
570
571 if (rs->n_bytes == 1)
572 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
573 else if (rs->n_bytes == 2)
574 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
575 else
576 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
577
578 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
579 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
580
581 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
582 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
583 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
584
585 spi_set_clk(rs, div);
586
587 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
588}
589
590static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
591{
592 return ROCKCHIP_SPI_MAX_TRANLEN;
593}
594
595static int rockchip_spi_transfer_one(
596 struct spi_master *master,
597 struct spi_device *spi,
598 struct spi_transfer *xfer)
599{
600 int ret = 0;
601 struct rockchip_spi *rs = spi_master_get_devdata(master);
602
603 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
604 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
605
606 if (!xfer->tx_buf && !xfer->rx_buf) {
607 dev_err(rs->dev, "No buffer for transfer\n");
608 return -EINVAL;
609 }
610
611 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
612 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
613 return -EINVAL;
614 }
615
616 rs->speed = xfer->speed_hz;
617 rs->bpw = xfer->bits_per_word;
618 rs->n_bytes = rs->bpw >> 3;
619
620 rs->tx = xfer->tx_buf;
621 rs->tx_end = rs->tx + xfer->len;
622 rs->rx = xfer->rx_buf;
623 rs->rx_end = rs->rx + xfer->len;
624 rs->len = xfer->len;
625
626 rs->tx_sg = xfer->tx_sg;
627 rs->rx_sg = xfer->rx_sg;
628
629 if (rs->tx && rs->rx)
630 rs->tmode = CR0_XFM_TR;
631 else if (rs->tx)
632 rs->tmode = CR0_XFM_TO;
633 else if (rs->rx)
634 rs->tmode = CR0_XFM_RO;
635
636 /* we need prepare dma before spi was enabled */
637 if (master->can_dma && master->can_dma(master, spi, xfer))
638 rs->use_dma = 1;
639 else
640 rs->use_dma = 0;
641
642 rockchip_spi_config(rs);
643
644 if (rs->use_dma) {
645 if (rs->tmode == CR0_XFM_RO) {
646 /* rx: dma must be prepared first */
647 ret = rockchip_spi_prepare_dma(rs);
648 spi_enable_chip(rs, 1);
649 } else {
650 /* tx or tr: spi must be enabled first */
651 spi_enable_chip(rs, 1);
652 ret = rockchip_spi_prepare_dma(rs);
653 }
654 /* successful DMA prepare means the transfer is in progress */
655 ret = ret ? ret : 1;
656 } else {
657 spi_enable_chip(rs, 1);
658 ret = rockchip_spi_pio_transfer(rs);
659 }
660
661 return ret;
662}
663
664static bool rockchip_spi_can_dma(struct spi_master *master,
665 struct spi_device *spi,
666 struct spi_transfer *xfer)
667{
668 struct rockchip_spi *rs = spi_master_get_devdata(master);
669
670 return (xfer->len > rs->fifo_len);
671}
672
673static int rockchip_spi_probe(struct platform_device *pdev)
674{
675 int ret;
676 struct rockchip_spi *rs;
677 struct spi_master *master;
678 struct resource *mem;
679 u32 rsd_nsecs;
680
681 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
682 if (!master)
683 return -ENOMEM;
684
685 platform_set_drvdata(pdev, master);
686
687 rs = spi_master_get_devdata(master);
688
689 /* Get basic io resource and map it */
690 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
692 if (IS_ERR(rs->regs)) {
693 ret = PTR_ERR(rs->regs);
694 goto err_put_master;
695 }
696
697 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
698 if (IS_ERR(rs->apb_pclk)) {
699 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
700 ret = PTR_ERR(rs->apb_pclk);
701 goto err_put_master;
702 }
703
704 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
705 if (IS_ERR(rs->spiclk)) {
706 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
707 ret = PTR_ERR(rs->spiclk);
708 goto err_put_master;
709 }
710
711 ret = clk_prepare_enable(rs->apb_pclk);
712 if (ret < 0) {
713 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
714 goto err_put_master;
715 }
716
717 ret = clk_prepare_enable(rs->spiclk);
718 if (ret < 0) {
719 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
720 goto err_disable_apbclk;
721 }
722
723 spi_enable_chip(rs, 0);
724
725 rs->type = SSI_MOTO_SPI;
726 rs->master = master;
727 rs->dev = &pdev->dev;
728 rs->max_freq = clk_get_rate(rs->spiclk);
729
730 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
731 &rsd_nsecs))
732 rs->rsd_nsecs = rsd_nsecs;
733
734 rs->fifo_len = get_fifo_len(rs);
735 if (!rs->fifo_len) {
736 dev_err(&pdev->dev, "Failed to get fifo length\n");
737 ret = -EINVAL;
738 goto err_disable_spiclk;
739 }
740
741 spin_lock_init(&rs->lock);
742
743 pm_runtime_set_active(&pdev->dev);
744 pm_runtime_enable(&pdev->dev);
745
746 master->auto_runtime_pm = true;
747 master->bus_num = pdev->id;
748 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
749 master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
750 master->dev.of_node = pdev->dev.of_node;
751 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
752
753 master->set_cs = rockchip_spi_set_cs;
754 master->prepare_message = rockchip_spi_prepare_message;
755 master->unprepare_message = rockchip_spi_unprepare_message;
756 master->transfer_one = rockchip_spi_transfer_one;
757 master->max_transfer_size = rockchip_spi_max_transfer_size;
758 master->handle_err = rockchip_spi_handle_err;
759 master->flags = SPI_MASTER_GPIO_SS;
760
761 rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
762 if (IS_ERR(rs->dma_tx.ch)) {
763 /* Check tx to see if we need defer probing driver */
764 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
765 ret = -EPROBE_DEFER;
766 goto err_disable_pm_runtime;
767 }
768 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
769 rs->dma_tx.ch = NULL;
770 }
771
772 rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
773 if (IS_ERR(rs->dma_rx.ch)) {
774 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
775 ret = -EPROBE_DEFER;
776 goto err_free_dma_tx;
777 }
778 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
779 rs->dma_rx.ch = NULL;
780 }
781
782 if (rs->dma_tx.ch && rs->dma_rx.ch) {
783 dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps));
784 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
785 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
786 rs->dma_tx.direction = DMA_MEM_TO_DEV;
787 rs->dma_rx.direction = DMA_DEV_TO_MEM;
788
789 master->can_dma = rockchip_spi_can_dma;
790 master->dma_tx = rs->dma_tx.ch;
791 master->dma_rx = rs->dma_rx.ch;
792 }
793
794 ret = devm_spi_register_master(&pdev->dev, master);
795 if (ret < 0) {
796 dev_err(&pdev->dev, "Failed to register master\n");
797 goto err_free_dma_rx;
798 }
799
800 return 0;
801
802err_free_dma_rx:
803 if (rs->dma_rx.ch)
804 dma_release_channel(rs->dma_rx.ch);
805err_free_dma_tx:
806 if (rs->dma_tx.ch)
807 dma_release_channel(rs->dma_tx.ch);
808err_disable_pm_runtime:
809 pm_runtime_disable(&pdev->dev);
810err_disable_spiclk:
811 clk_disable_unprepare(rs->spiclk);
812err_disable_apbclk:
813 clk_disable_unprepare(rs->apb_pclk);
814err_put_master:
815 spi_master_put(master);
816
817 return ret;
818}
819
820static int rockchip_spi_remove(struct platform_device *pdev)
821{
822 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
823 struct rockchip_spi *rs = spi_master_get_devdata(master);
824
825 pm_runtime_get_sync(&pdev->dev);
826
827 clk_disable_unprepare(rs->spiclk);
828 clk_disable_unprepare(rs->apb_pclk);
829
830 pm_runtime_put_noidle(&pdev->dev);
831 pm_runtime_disable(&pdev->dev);
832 pm_runtime_set_suspended(&pdev->dev);
833
834 if (rs->dma_tx.ch)
835 dma_release_channel(rs->dma_tx.ch);
836 if (rs->dma_rx.ch)
837 dma_release_channel(rs->dma_rx.ch);
838
839 spi_master_put(master);
840
841 return 0;
842}
843
844#ifdef CONFIG_PM_SLEEP
845static int rockchip_spi_suspend(struct device *dev)
846{
847 int ret;
848 struct spi_master *master = dev_get_drvdata(dev);
849 struct rockchip_spi *rs = spi_master_get_devdata(master);
850
851 ret = spi_master_suspend(rs->master);
852 if (ret < 0)
853 return ret;
854
855 ret = pm_runtime_force_suspend(dev);
856 if (ret < 0)
857 return ret;
858
859 pinctrl_pm_select_sleep_state(dev);
860
861 return 0;
862}
863
864static int rockchip_spi_resume(struct device *dev)
865{
866 int ret;
867 struct spi_master *master = dev_get_drvdata(dev);
868 struct rockchip_spi *rs = spi_master_get_devdata(master);
869
870 pinctrl_pm_select_default_state(dev);
871
872 ret = pm_runtime_force_resume(dev);
873 if (ret < 0)
874 return ret;
875
876 ret = spi_master_resume(rs->master);
877 if (ret < 0) {
878 clk_disable_unprepare(rs->spiclk);
879 clk_disable_unprepare(rs->apb_pclk);
880 }
881
882 return 0;
883}
884#endif /* CONFIG_PM_SLEEP */
885
886#ifdef CONFIG_PM
887static int rockchip_spi_runtime_suspend(struct device *dev)
888{
889 struct spi_master *master = dev_get_drvdata(dev);
890 struct rockchip_spi *rs = spi_master_get_devdata(master);
891
892 clk_disable_unprepare(rs->spiclk);
893 clk_disable_unprepare(rs->apb_pclk);
894
895 return 0;
896}
897
898static int rockchip_spi_runtime_resume(struct device *dev)
899{
900 int ret;
901 struct spi_master *master = dev_get_drvdata(dev);
902 struct rockchip_spi *rs = spi_master_get_devdata(master);
903
904 ret = clk_prepare_enable(rs->apb_pclk);
905 if (ret < 0)
906 return ret;
907
908 ret = clk_prepare_enable(rs->spiclk);
909 if (ret < 0)
910 clk_disable_unprepare(rs->apb_pclk);
911
912 return 0;
913}
914#endif /* CONFIG_PM */
915
916static const struct dev_pm_ops rockchip_spi_pm = {
917 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
918 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
919 rockchip_spi_runtime_resume, NULL)
920};
921
922static const struct of_device_id rockchip_spi_dt_match[] = {
923 { .compatible = "rockchip,rv1108-spi", },
924 { .compatible = "rockchip,rk3036-spi", },
925 { .compatible = "rockchip,rk3066-spi", },
926 { .compatible = "rockchip,rk3188-spi", },
927 { .compatible = "rockchip,rk3228-spi", },
928 { .compatible = "rockchip,rk3288-spi", },
929 { .compatible = "rockchip,rk3368-spi", },
930 { .compatible = "rockchip,rk3399-spi", },
931 { },
932};
933MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
934
935static struct platform_driver rockchip_spi_driver = {
936 .driver = {
937 .name = DRIVER_NAME,
938 .pm = &rockchip_spi_pm,
939 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
940 },
941 .probe = rockchip_spi_probe,
942 .remove = rockchip_spi_remove,
943};
944
945module_platform_driver(rockchip_spi_driver);
946
947MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
948MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
949MODULE_LICENSE("GPL v2");