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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
4 *
5 * Copyright 2016 Broadcom
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi-mem.h>
23#include <linux/sysfs.h>
24#include <linux/types.h>
25#include "spi-bcm-qspi.h"
26
27#define DRIVER_NAME "bcm_qspi"
28
29
30/* BSPI register offsets */
31#define BSPI_REVISION_ID 0x000
32#define BSPI_SCRATCH 0x004
33#define BSPI_MAST_N_BOOT_CTRL 0x008
34#define BSPI_BUSY_STATUS 0x00c
35#define BSPI_INTR_STATUS 0x010
36#define BSPI_B0_STATUS 0x014
37#define BSPI_B0_CTRL 0x018
38#define BSPI_B1_STATUS 0x01c
39#define BSPI_B1_CTRL 0x020
40#define BSPI_STRAP_OVERRIDE_CTRL 0x024
41#define BSPI_FLEX_MODE_ENABLE 0x028
42#define BSPI_BITS_PER_CYCLE 0x02c
43#define BSPI_BITS_PER_PHASE 0x030
44#define BSPI_CMD_AND_MODE_BYTE 0x034
45#define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
46#define BSPI_BSPI_XOR_VALUE 0x03c
47#define BSPI_BSPI_XOR_ENABLE 0x040
48#define BSPI_BSPI_PIO_MODE_ENABLE 0x044
49#define BSPI_BSPI_PIO_IODIR 0x048
50#define BSPI_BSPI_PIO_DATA 0x04c
51
52/* RAF register offsets */
53#define BSPI_RAF_START_ADDR 0x100
54#define BSPI_RAF_NUM_WORDS 0x104
55#define BSPI_RAF_CTRL 0x108
56#define BSPI_RAF_FULLNESS 0x10c
57#define BSPI_RAF_WATERMARK 0x110
58#define BSPI_RAF_STATUS 0x114
59#define BSPI_RAF_READ_DATA 0x118
60#define BSPI_RAF_WORD_CNT 0x11c
61#define BSPI_RAF_CURR_ADDR 0x120
62
63/* Override mode masks */
64#define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
65#define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
66#define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
67#define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
68#define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
69
70#define BSPI_ADDRLEN_3BYTES 3
71#define BSPI_ADDRLEN_4BYTES 4
72
73#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
74
75#define BSPI_RAF_CTRL_START_MASK BIT(0)
76#define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
77
78#define BSPI_BPP_MODE_SELECT_MASK BIT(8)
79#define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
80
81#define BSPI_READ_LENGTH 256
82
83/* MSPI register offsets */
84#define MSPI_SPCR0_LSB 0x000
85#define MSPI_SPCR0_MSB 0x004
86#define MSPI_SPCR0_MSB_CPHA BIT(0)
87#define MSPI_SPCR0_MSB_CPOL BIT(1)
88#define MSPI_SPCR0_MSB_BITS_SHIFT 0x2
89#define MSPI_SPCR1_LSB 0x008
90#define MSPI_SPCR1_MSB 0x00c
91#define MSPI_NEWQP 0x010
92#define MSPI_ENDQP 0x014
93#define MSPI_SPCR2 0x018
94#define MSPI_MSPI_STATUS 0x020
95#define MSPI_CPTQP 0x024
96#define MSPI_SPCR3 0x028
97#define MSPI_REV 0x02c
98#define MSPI_TXRAM 0x040
99#define MSPI_RXRAM 0x0c0
100#define MSPI_CDRAM 0x140
101#define MSPI_WRITE_LOCK 0x180
102
103#define MSPI_MASTER_BIT BIT(7)
104
105#define MSPI_NUM_CDRAM 16
106#define MSPI_CDRAM_OUTP BIT(8)
107#define MSPI_CDRAM_CONT_BIT BIT(7)
108#define MSPI_CDRAM_BITSE_BIT BIT(6)
109#define MSPI_CDRAM_DT_BIT BIT(5)
110#define MSPI_CDRAM_PCS 0xf
111
112#define MSPI_SPCR2_SPE BIT(6)
113#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
114
115#define MSPI_SPCR3_FASTBR BIT(0)
116#define MSPI_SPCR3_FASTDT BIT(1)
117#define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10)
118#define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \
119 ~(BIT(10) | BIT(11)))
120#define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \
121 BIT(11))
122#define MSPI_SPCR3_TXRXDAM_MASK GENMASK(4, 2)
123#define MSPI_SPCR3_DAM_8BYTE 0
124#define MSPI_SPCR3_DAM_16BYTE (BIT(2) | BIT(4))
125#define MSPI_SPCR3_DAM_32BYTE (BIT(3) | BIT(5))
126#define MSPI_SPCR3_HALFDUPLEX BIT(6)
127#define MSPI_SPCR3_HDOUTTYPE BIT(7)
128#define MSPI_SPCR3_DATA_REG_SZ BIT(8)
129#define MSPI_SPCR3_CPHARX BIT(9)
130
131#define MSPI_MSPI_STATUS_SPIF BIT(0)
132
133#define INTR_BASE_BIT_SHIFT 0x02
134#define INTR_COUNT 0x07
135
136#define NUM_CHIPSELECT 4
137#define QSPI_SPBR_MAX 255U
138#define MSPI_BASE_FREQ 27000000UL
139
140#define OPCODE_DIOR 0xBB
141#define OPCODE_QIOR 0xEB
142#define OPCODE_DIOR_4B 0xBC
143#define OPCODE_QIOR_4B 0xEC
144
145#define MAX_CMD_SIZE 6
146
147#define ADDR_4MB_MASK GENMASK(22, 0)
148
149/* stop at end of transfer, no other reason */
150#define TRANS_STATUS_BREAK_NONE 0
151/* stop at end of spi_message */
152#define TRANS_STATUS_BREAK_EOM 1
153/* stop at end of spi_transfer if delay */
154#define TRANS_STATUS_BREAK_DELAY 2
155/* stop at end of spi_transfer if cs_change */
156#define TRANS_STATUS_BREAK_CS_CHANGE 4
157/* stop if we run out of bytes */
158#define TRANS_STATUS_BREAK_NO_BYTES 8
159
160/* events that make us stop filling TX slots */
161#define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
162 TRANS_STATUS_BREAK_DELAY | \
163 TRANS_STATUS_BREAK_CS_CHANGE)
164
165/* events that make us deassert CS */
166#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
167 TRANS_STATUS_BREAK_CS_CHANGE)
168
169/*
170 * Used for writing and reading data in the right order
171 * to TXRAM and RXRAM when used as 32-bit registers respectively
172 */
173#define swap4bytes(__val) \
174 ((((__val) >> 24) & 0x000000FF) | (((__val) >> 8) & 0x0000FF00) | \
175 (((__val) << 8) & 0x00FF0000) | (((__val) << 24) & 0xFF000000))
176
177struct bcm_qspi_parms {
178 u32 speed_hz;
179 u8 mode;
180 u8 bits_per_word;
181};
182
183struct bcm_xfer_mode {
184 bool flex_mode;
185 unsigned int width;
186 unsigned int addrlen;
187 unsigned int hp;
188};
189
190enum base_type {
191 MSPI,
192 BSPI,
193 CHIP_SELECT,
194 BASEMAX,
195};
196
197enum irq_source {
198 SINGLE_L2,
199 MUXED_L1,
200};
201
202struct bcm_qspi_irq {
203 const char *irq_name;
204 const irq_handler_t irq_handler;
205 int irq_source;
206 u32 mask;
207};
208
209struct bcm_qspi_dev_id {
210 const struct bcm_qspi_irq *irqp;
211 void *dev;
212};
213
214
215struct qspi_trans {
216 struct spi_transfer *trans;
217 int byte;
218 bool mspi_last_trans;
219};
220
221struct bcm_qspi {
222 struct platform_device *pdev;
223 struct spi_master *master;
224 struct clk *clk;
225 u32 base_clk;
226 u32 max_speed_hz;
227 void __iomem *base[BASEMAX];
228
229 /* Some SoCs provide custom interrupt status register(s) */
230 struct bcm_qspi_soc_intc *soc_intc;
231
232 struct bcm_qspi_parms last_parms;
233 struct qspi_trans trans_pos;
234 int curr_cs;
235 int bspi_maj_rev;
236 int bspi_min_rev;
237 int bspi_enabled;
238 const struct spi_mem_op *bspi_rf_op;
239 u32 bspi_rf_op_idx;
240 u32 bspi_rf_op_len;
241 u32 bspi_rf_op_status;
242 struct bcm_xfer_mode xfer_mode;
243 u32 s3_strap_override_ctrl;
244 bool bspi_mode;
245 bool big_endian;
246 int num_irqs;
247 struct bcm_qspi_dev_id *dev_ids;
248 struct completion mspi_done;
249 struct completion bspi_done;
250 u8 mspi_maj_rev;
251 u8 mspi_min_rev;
252 bool mspi_spcr3_sysclk;
253};
254
255static inline bool has_bspi(struct bcm_qspi *qspi)
256{
257 return qspi->bspi_mode;
258}
259
260/* hardware supports spcr3 and fast baud-rate */
261static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
262{
263 if (!has_bspi(qspi) &&
264 ((qspi->mspi_maj_rev >= 1) &&
265 (qspi->mspi_min_rev >= 5)))
266 return true;
267
268 return false;
269}
270
271/* hardware supports sys clk 108Mhz */
272static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
273{
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
275 ((qspi->mspi_maj_rev >= 1) &&
276 (qspi->mspi_min_rev >= 6))))
277 return true;
278
279 return false;
280}
281
282static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
283{
284 if (bcm_qspi_has_fastbr(qspi))
285 return (bcm_qspi_has_sysclk_108(qspi) ? 4 : 1);
286 else
287 return 8;
288}
289
290static u32 bcm_qspi_calc_spbr(u32 clk_speed_hz,
291 const struct bcm_qspi_parms *xp)
292{
293 u32 spbr = 0;
294
295 /* SPBR = System Clock/(2 * SCK Baud Rate) */
296 if (xp->speed_hz)
297 spbr = clk_speed_hz / (xp->speed_hz * 2);
298
299 return spbr;
300}
301
302/* Read qspi controller register*/
303static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
304 unsigned int offset)
305{
306 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
307}
308
309/* Write qspi controller register*/
310static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
311 unsigned int offset, unsigned int data)
312{
313 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
314}
315
316/* BSPI helpers */
317static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
318{
319 int i;
320
321 /* this should normally finish within 10us */
322 for (i = 0; i < 1000; i++) {
323 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
324 return 0;
325 udelay(1);
326 }
327 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
328 return -EIO;
329}
330
331static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
332{
333 if (qspi->bspi_maj_rev < 4)
334 return true;
335 return false;
336}
337
338static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
339{
340 bcm_qspi_bspi_busy_poll(qspi);
341 /* Force rising edge for the b0/b1 'flush' field */
342 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
343 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
344 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
345 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
346}
347
348static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
349{
350 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
351 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
352}
353
354static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
355{
356 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
357
358 /* BSPI v3 LR is LE only, convert data to host endianness */
359 if (bcm_qspi_bspi_ver_three(qspi))
360 data = le32_to_cpu(data);
361
362 return data;
363}
364
365static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
366{
367 bcm_qspi_bspi_busy_poll(qspi);
368 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
369 BSPI_RAF_CTRL_START_MASK);
370}
371
372static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
373{
374 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
375 BSPI_RAF_CTRL_CLEAR_MASK);
376 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
377}
378
379static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
380{
381 u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
382 u32 data = 0;
383
384 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
385 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
386 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
387 data = bcm_qspi_bspi_lr_read_fifo(qspi);
388 if (likely(qspi->bspi_rf_op_len >= 4) &&
389 IS_ALIGNED((uintptr_t)buf, 4)) {
390 buf[qspi->bspi_rf_op_idx++] = data;
391 qspi->bspi_rf_op_len -= 4;
392 } else {
393 /* Read out remaining bytes, make sure*/
394 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
395
396 data = cpu_to_le32(data);
397 while (qspi->bspi_rf_op_len) {
398 *cbuf++ = (u8)data;
399 data >>= 8;
400 qspi->bspi_rf_op_len--;
401 }
402 }
403 }
404}
405
406static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
407 int bpp, int bpc, int flex_mode)
408{
409 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
410 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
411 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
412 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
413 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
414}
415
416static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
417 const struct spi_mem_op *op, int hp)
418{
419 int bpc = 0, bpp = 0;
420 u8 command = op->cmd.opcode;
421 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
422 int addrlen = op->addr.nbytes;
423 int flex_mode = 1;
424
425 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
426 width, addrlen, hp);
427
428 if (addrlen == BSPI_ADDRLEN_4BYTES)
429 bpp = BSPI_BPP_ADDR_SELECT_MASK;
430
431 if (op->dummy.nbytes)
432 bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
433
434 switch (width) {
435 case SPI_NBITS_SINGLE:
436 if (addrlen == BSPI_ADDRLEN_3BYTES)
437 /* default mode, does not need flex_cmd */
438 flex_mode = 0;
439 break;
440 case SPI_NBITS_DUAL:
441 bpc = 0x00000001;
442 if (hp) {
443 bpc |= 0x00010100; /* address and mode are 2-bit */
444 bpp = BSPI_BPP_MODE_SELECT_MASK;
445 }
446 break;
447 case SPI_NBITS_QUAD:
448 bpc = 0x00000002;
449 if (hp) {
450 bpc |= 0x00020200; /* address and mode are 4-bit */
451 bpp |= BSPI_BPP_MODE_SELECT_MASK;
452 }
453 break;
454 default:
455 return -EINVAL;
456 }
457
458 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
459
460 return 0;
461}
462
463static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
464 const struct spi_mem_op *op, int hp)
465{
466 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
467 int addrlen = op->addr.nbytes;
468 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
469
470 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
471 width, addrlen, hp);
472
473 switch (width) {
474 case SPI_NBITS_SINGLE:
475 /* clear quad/dual mode */
476 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
477 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
478 break;
479 case SPI_NBITS_QUAD:
480 /* clear dual mode and set quad mode */
481 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
482 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
483 break;
484 case SPI_NBITS_DUAL:
485 /* clear quad mode set dual mode */
486 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
487 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 if (addrlen == BSPI_ADDRLEN_4BYTES)
494 /* set 4byte mode*/
495 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
496 else
497 /* clear 4 byte mode */
498 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
499
500 /* set the override mode */
501 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
502 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
503 bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
504
505 return 0;
506}
507
508static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
509 const struct spi_mem_op *op, int hp)
510{
511 int error = 0;
512 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
513 int addrlen = op->addr.nbytes;
514
515 /* default mode */
516 qspi->xfer_mode.flex_mode = true;
517
518 if (!bcm_qspi_bspi_ver_three(qspi)) {
519 u32 val, mask;
520
521 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
522 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
523 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
524 qspi->xfer_mode.flex_mode = false;
525 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
526 error = bcm_qspi_bspi_set_override(qspi, op, hp);
527 }
528 }
529
530 if (qspi->xfer_mode.flex_mode)
531 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
532
533 if (error) {
534 dev_warn(&qspi->pdev->dev,
535 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
536 width, addrlen, hp);
537 } else if (qspi->xfer_mode.width != width ||
538 qspi->xfer_mode.addrlen != addrlen ||
539 qspi->xfer_mode.hp != hp) {
540 qspi->xfer_mode.width = width;
541 qspi->xfer_mode.addrlen = addrlen;
542 qspi->xfer_mode.hp = hp;
543 dev_dbg(&qspi->pdev->dev,
544 "cs:%d %d-lane output, %d-byte address%s\n",
545 qspi->curr_cs,
546 qspi->xfer_mode.width,
547 qspi->xfer_mode.addrlen,
548 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
549 }
550
551 return error;
552}
553
554static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
555{
556 if (!has_bspi(qspi))
557 return;
558
559 qspi->bspi_enabled = 1;
560 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
561 return;
562
563 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
564 udelay(1);
565 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
566 udelay(1);
567}
568
569static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
570{
571 if (!has_bspi(qspi))
572 return;
573
574 qspi->bspi_enabled = 0;
575 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
576 return;
577
578 bcm_qspi_bspi_busy_poll(qspi);
579 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
580 udelay(1);
581}
582
583static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
584{
585 u32 rd = 0;
586 u32 wr = 0;
587
588 if (cs >= 0 && qspi->base[CHIP_SELECT]) {
589 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
590 wr = (rd & ~0xff) | (1 << cs);
591 if (rd == wr)
592 return;
593 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
594 usleep_range(10, 20);
595 }
596
597 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
598 qspi->curr_cs = cs;
599}
600
601static bool bcmspi_parms_did_change(const struct bcm_qspi_parms * const cur,
602 const struct bcm_qspi_parms * const prev)
603{
604 return (cur->speed_hz != prev->speed_hz) ||
605 (cur->mode != prev->mode) ||
606 (cur->bits_per_word != prev->bits_per_word);
607}
608
609
610/* MSPI helpers */
611static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
612 const struct bcm_qspi_parms *xp)
613{
614 u32 spcr, spbr = 0;
615
616 if (!bcmspi_parms_did_change(xp, &qspi->last_parms))
617 return;
618
619 if (!qspi->mspi_maj_rev)
620 /* legacy controller */
621 spcr = MSPI_MASTER_BIT;
622 else
623 spcr = 0;
624
625 /*
626 * Bits per transfer. BITS determines the number of data bits
627 * transferred if the command control bit (BITSE of a
628 * CDRAM Register) is equal to 1.
629 * If CDRAM BITSE is equal to 0, 8 data bits are transferred
630 * regardless
631 */
632 if (xp->bits_per_word != 16 && xp->bits_per_word != 64)
633 spcr |= xp->bits_per_word << MSPI_SPCR0_MSB_BITS_SHIFT;
634
635 spcr |= xp->mode & (MSPI_SPCR0_MSB_CPHA | MSPI_SPCR0_MSB_CPOL);
636 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
637
638 if (bcm_qspi_has_fastbr(qspi)) {
639 spcr = 0;
640
641 /* enable fastbr */
642 spcr |= MSPI_SPCR3_FASTBR;
643
644 if (xp->mode & SPI_3WIRE)
645 spcr |= MSPI_SPCR3_HALFDUPLEX | MSPI_SPCR3_HDOUTTYPE;
646
647 if (bcm_qspi_has_sysclk_108(qspi)) {
648 /* check requested baud rate before moving to 108Mhz */
649 spbr = bcm_qspi_calc_spbr(MSPI_BASE_FREQ * 4, xp);
650 if (spbr > QSPI_SPBR_MAX) {
651 /* use SYSCLK_27Mhz for slower baud rates */
652 spcr &= ~MSPI_SPCR3_SYSCLKSEL_MASK;
653 qspi->base_clk = MSPI_BASE_FREQ;
654 } else {
655 /* SYSCLK_108Mhz */
656 spcr |= MSPI_SPCR3_SYSCLKSEL_108;
657 qspi->base_clk = MSPI_BASE_FREQ * 4;
658 }
659 }
660
661 if (xp->bits_per_word > 16) {
662 /* data_reg_size 1 (64bit) */
663 spcr |= MSPI_SPCR3_DATA_REG_SZ;
664 /* TxRx RAM data access mode 2 for 32B and set fastdt */
665 spcr |= MSPI_SPCR3_DAM_32BYTE | MSPI_SPCR3_FASTDT;
666 /*
667 * Set length of delay after transfer
668 * DTL from 0(256) to 1
669 */
670 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
671 } else {
672 /* data_reg_size[8] = 0 */
673 spcr &= ~(MSPI_SPCR3_DATA_REG_SZ);
674
675 /*
676 * TxRx RAM access mode 8B
677 * and disable fastdt
678 */
679 spcr &= ~(MSPI_SPCR3_DAM_32BYTE);
680 }
681 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
682 }
683
684 /* SCK Baud Rate = System Clock/(2 * SPBR) */
685 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
686 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp);
687 spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
688 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
689
690 qspi->last_parms = *xp;
691}
692
693static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
694 struct spi_device *spi,
695 struct spi_transfer *trans)
696{
697 struct bcm_qspi_parms xp;
698
699 xp.speed_hz = trans->speed_hz;
700 xp.bits_per_word = trans->bits_per_word;
701 xp.mode = spi->mode;
702
703 bcm_qspi_hw_set_parms(qspi, &xp);
704}
705
706static int bcm_qspi_setup(struct spi_device *spi)
707{
708 struct bcm_qspi_parms *xp;
709
710 if (spi->bits_per_word > 64)
711 return -EINVAL;
712
713 xp = spi_get_ctldata(spi);
714 if (!xp) {
715 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
716 if (!xp)
717 return -ENOMEM;
718 spi_set_ctldata(spi, xp);
719 }
720 xp->speed_hz = spi->max_speed_hz;
721 xp->mode = spi->mode;
722
723 if (spi->bits_per_word)
724 xp->bits_per_word = spi->bits_per_word;
725 else
726 xp->bits_per_word = 8;
727
728 return 0;
729}
730
731static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
732 struct qspi_trans *qt)
733{
734 if (qt->mspi_last_trans &&
735 spi_transfer_is_last(qspi->master, qt->trans))
736 return true;
737 else
738 return false;
739}
740
741static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
742 struct qspi_trans *qt, int flags)
743{
744 int ret = TRANS_STATUS_BREAK_NONE;
745
746 /* count the last transferred bytes */
747 if (qt->trans->bits_per_word <= 8)
748 qt->byte++;
749 else if (qt->trans->bits_per_word <= 16)
750 qt->byte += 2;
751 else if (qt->trans->bits_per_word <= 32)
752 qt->byte += 4;
753 else if (qt->trans->bits_per_word <= 64)
754 qt->byte += 8;
755
756 if (qt->byte >= qt->trans->len) {
757 /* we're at the end of the spi_transfer */
758 /* in TX mode, need to pause for a delay or CS change */
759 if (qt->trans->delay.value &&
760 (flags & TRANS_STATUS_BREAK_DELAY))
761 ret |= TRANS_STATUS_BREAK_DELAY;
762 if (qt->trans->cs_change &&
763 (flags & TRANS_STATUS_BREAK_CS_CHANGE))
764 ret |= TRANS_STATUS_BREAK_CS_CHANGE;
765
766 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
767 ret |= TRANS_STATUS_BREAK_EOM;
768 else
769 ret |= TRANS_STATUS_BREAK_NO_BYTES;
770
771 qt->trans = NULL;
772 }
773
774 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
775 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
776 return ret;
777}
778
779static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
780{
781 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
782
783 /* mask out reserved bits */
784 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
785}
786
787static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
788{
789 u32 reg_offset = MSPI_RXRAM;
790 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
791 u32 msb_offset = reg_offset + (slot << 3);
792
793 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
794 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
795}
796
797static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot)
798{
799 u32 reg_offset = MSPI_RXRAM;
800 u32 offset = reg_offset + (slot << 3);
801 u32 val;
802
803 val = bcm_qspi_read(qspi, MSPI, offset);
804 val = swap4bytes(val);
805
806 return val;
807}
808
809static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot)
810{
811 u32 reg_offset = MSPI_RXRAM;
812 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
813 u32 msb_offset = reg_offset + (slot << 3);
814 u32 msb, lsb;
815
816 msb = bcm_qspi_read(qspi, MSPI, msb_offset);
817 msb = swap4bytes(msb);
818 lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
819 lsb = swap4bytes(lsb);
820
821 return ((u64)msb << 32 | lsb);
822}
823
824static void read_from_hw(struct bcm_qspi *qspi, int slots)
825{
826 struct qspi_trans tp;
827 int slot;
828
829 bcm_qspi_disable_bspi(qspi);
830
831 if (slots > MSPI_NUM_CDRAM) {
832 /* should never happen */
833 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
834 return;
835 }
836
837 tp = qspi->trans_pos;
838
839 for (slot = 0; slot < slots; slot++) {
840 if (tp.trans->bits_per_word <= 8) {
841 u8 *buf = tp.trans->rx_buf;
842
843 if (buf)
844 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
845 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
846 buf ? buf[tp.byte] : 0x0);
847 } else if (tp.trans->bits_per_word <= 16) {
848 u16 *buf = tp.trans->rx_buf;
849
850 if (buf)
851 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
852 slot);
853 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
854 buf ? buf[tp.byte / 2] : 0x0);
855 } else if (tp.trans->bits_per_word <= 32) {
856 u32 *buf = tp.trans->rx_buf;
857
858 if (buf)
859 buf[tp.byte / 4] = read_rxram_slot_u32(qspi,
860 slot);
861 dev_dbg(&qspi->pdev->dev, "RD %08x\n",
862 buf ? buf[tp.byte / 4] : 0x0);
863
864 } else if (tp.trans->bits_per_word <= 64) {
865 u64 *buf = tp.trans->rx_buf;
866
867 if (buf)
868 buf[tp.byte / 8] = read_rxram_slot_u64(qspi,
869 slot);
870 dev_dbg(&qspi->pdev->dev, "RD %llx\n",
871 buf ? buf[tp.byte / 8] : 0x0);
872
873
874 }
875
876 update_qspi_trans_byte_count(qspi, &tp,
877 TRANS_STATUS_BREAK_NONE);
878 }
879
880 qspi->trans_pos = tp;
881}
882
883static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
884 u8 val)
885{
886 u32 reg_offset = MSPI_TXRAM + (slot << 3);
887
888 /* mask out reserved bits */
889 bcm_qspi_write(qspi, MSPI, reg_offset, val);
890}
891
892static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
893 u16 val)
894{
895 u32 reg_offset = MSPI_TXRAM;
896 u32 msb_offset = reg_offset + (slot << 3);
897 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
898
899 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
900 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
901}
902
903static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot,
904 u32 val)
905{
906 u32 reg_offset = MSPI_TXRAM;
907 u32 msb_offset = reg_offset + (slot << 3);
908
909 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
910}
911
912static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot,
913 u64 val)
914{
915 u32 reg_offset = MSPI_TXRAM;
916 u32 msb_offset = reg_offset + (slot << 3);
917 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
918 u32 msb = upper_32_bits(val);
919 u32 lsb = lower_32_bits(val);
920
921 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
922 bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
923}
924
925static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
926{
927 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
928}
929
930static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
931{
932 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
933}
934
935/* Return number of slots written */
936static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
937{
938 struct qspi_trans tp;
939 int slot = 0, tstatus = 0;
940 u32 mspi_cdram = 0;
941
942 bcm_qspi_disable_bspi(qspi);
943 tp = qspi->trans_pos;
944 bcm_qspi_update_parms(qspi, spi, tp.trans);
945
946 /* Run until end of transfer or reached the max data */
947 while (!tstatus && slot < MSPI_NUM_CDRAM) {
948 mspi_cdram = MSPI_CDRAM_CONT_BIT;
949 if (tp.trans->bits_per_word <= 8) {
950 const u8 *buf = tp.trans->tx_buf;
951 u8 val = buf ? buf[tp.byte] : 0x00;
952
953 write_txram_slot_u8(qspi, slot, val);
954 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
955 } else if (tp.trans->bits_per_word <= 16) {
956 const u16 *buf = tp.trans->tx_buf;
957 u16 val = buf ? buf[tp.byte / 2] : 0x0000;
958
959 write_txram_slot_u16(qspi, slot, val);
960 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
961 } else if (tp.trans->bits_per_word <= 32) {
962 const u32 *buf = tp.trans->tx_buf;
963 u32 val = buf ? buf[tp.byte/4] : 0x0;
964
965 write_txram_slot_u32(qspi, slot, val);
966 dev_dbg(&qspi->pdev->dev, "WR %08x\n", val);
967 } else if (tp.trans->bits_per_word <= 64) {
968 const u64 *buf = tp.trans->tx_buf;
969 u64 val = (buf ? buf[tp.byte/8] : 0x0);
970
971 /* use the length of delay from SPCR1_LSB */
972 if (bcm_qspi_has_fastbr(qspi))
973 mspi_cdram |= MSPI_CDRAM_DT_BIT;
974
975 write_txram_slot_u64(qspi, slot, val);
976 dev_dbg(&qspi->pdev->dev, "WR %llx\n", val);
977 }
978
979 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
980 MSPI_CDRAM_BITSE_BIT);
981
982 /* set 3wrire halfduplex mode data from master to slave */
983 if ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf)
984 mspi_cdram |= MSPI_CDRAM_OUTP;
985
986 if (has_bspi(qspi))
987 mspi_cdram &= ~1;
988 else
989 mspi_cdram |= (~(1 << spi->chip_select) &
990 MSPI_CDRAM_PCS);
991
992 write_cdram_slot(qspi, slot, mspi_cdram);
993
994 tstatus = update_qspi_trans_byte_count(qspi, &tp,
995 TRANS_STATUS_BREAK_TX);
996 slot++;
997 }
998
999 if (!slot) {
1000 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
1001 goto done;
1002 }
1003
1004 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
1005 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1006 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
1007
1008 /*
1009 * case 1) EOM =1, cs_change =0: SSb inactive
1010 * case 2) EOM =1, cs_change =1: SSb stay active
1011 * case 3) EOM =0, cs_change =0: SSb stay active
1012 * case 4) EOM =0, cs_change =1: SSb inactive
1013 */
1014 if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
1015 == TRANS_STATUS_BREAK_CS_CHANGE) ||
1016 ((tstatus & TRANS_STATUS_BREAK_DESELECT)
1017 == TRANS_STATUS_BREAK_EOM)) {
1018 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
1019 ~MSPI_CDRAM_CONT_BIT;
1020 write_cdram_slot(qspi, slot - 1, mspi_cdram);
1021 }
1022
1023 if (has_bspi(qspi))
1024 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
1025
1026 /* Must flush previous writes before starting MSPI operation */
1027 mb();
1028 /* Set cont | spe | spifie */
1029 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
1030
1031done:
1032 return slot;
1033}
1034
1035static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
1036 const struct spi_mem_op *op)
1037{
1038 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1039 u32 addr = 0, len, rdlen, len_words, from = 0;
1040 int ret = 0;
1041 unsigned long timeo = msecs_to_jiffies(100);
1042 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1043
1044 if (bcm_qspi_bspi_ver_three(qspi))
1045 if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
1046 return -EIO;
1047
1048 from = op->addr.val;
1049 if (!spi->cs_gpiod)
1050 bcm_qspi_chip_select(qspi, spi->chip_select);
1051 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1052
1053 /*
1054 * when using flex mode we need to send
1055 * the upper address byte to bspi
1056 */
1057 if (!bcm_qspi_bspi_ver_three(qspi)) {
1058 addr = from & 0xff000000;
1059 bcm_qspi_write(qspi, BSPI,
1060 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
1061 }
1062
1063 if (!qspi->xfer_mode.flex_mode)
1064 addr = from;
1065 else
1066 addr = from & 0x00ffffff;
1067
1068 if (bcm_qspi_bspi_ver_three(qspi) == true)
1069 addr = (addr + 0xc00000) & 0xffffff;
1070
1071 /*
1072 * read into the entire buffer by breaking the reads
1073 * into RAF buffer read lengths
1074 */
1075 len = op->data.nbytes;
1076 qspi->bspi_rf_op_idx = 0;
1077
1078 do {
1079 if (len > BSPI_READ_LENGTH)
1080 rdlen = BSPI_READ_LENGTH;
1081 else
1082 rdlen = len;
1083
1084 reinit_completion(&qspi->bspi_done);
1085 bcm_qspi_enable_bspi(qspi);
1086 len_words = (rdlen + 3) >> 2;
1087 qspi->bspi_rf_op = op;
1088 qspi->bspi_rf_op_status = 0;
1089 qspi->bspi_rf_op_len = rdlen;
1090 dev_dbg(&qspi->pdev->dev,
1091 "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
1092 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
1093 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
1094 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
1095 if (qspi->soc_intc) {
1096 /*
1097 * clear soc MSPI and BSPI interrupts and enable
1098 * BSPI interrupts.
1099 */
1100 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
1101 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
1102 }
1103
1104 /* Must flush previous writes before starting BSPI operation */
1105 mb();
1106 bcm_qspi_bspi_lr_start(qspi);
1107 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
1108 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
1109 ret = -ETIMEDOUT;
1110 break;
1111 }
1112
1113 /* set msg return length */
1114 addr += rdlen;
1115 len -= rdlen;
1116 } while (len);
1117
1118 return ret;
1119}
1120
1121static int bcm_qspi_transfer_one(struct spi_master *master,
1122 struct spi_device *spi,
1123 struct spi_transfer *trans)
1124{
1125 struct bcm_qspi *qspi = spi_master_get_devdata(master);
1126 int slots;
1127 unsigned long timeo = msecs_to_jiffies(100);
1128
1129 if (!spi->cs_gpiod)
1130 bcm_qspi_chip_select(qspi, spi->chip_select);
1131 qspi->trans_pos.trans = trans;
1132 qspi->trans_pos.byte = 0;
1133
1134 while (qspi->trans_pos.byte < trans->len) {
1135 reinit_completion(&qspi->mspi_done);
1136
1137 slots = write_to_hw(qspi, spi);
1138 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
1139 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
1140 return -ETIMEDOUT;
1141 }
1142
1143 read_from_hw(qspi, slots);
1144 }
1145 bcm_qspi_enable_bspi(qspi);
1146
1147 return 0;
1148}
1149
1150static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
1151 const struct spi_mem_op *op)
1152{
1153 struct spi_master *master = spi->master;
1154 struct bcm_qspi *qspi = spi_master_get_devdata(master);
1155 struct spi_transfer t[2];
1156 u8 cmd[6] = { };
1157 int ret, i;
1158
1159 memset(cmd, 0, sizeof(cmd));
1160 memset(t, 0, sizeof(t));
1161
1162 /* tx */
1163 /* opcode is in cmd[0] */
1164 cmd[0] = op->cmd.opcode;
1165 for (i = 0; i < op->addr.nbytes; i++)
1166 cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
1167
1168 t[0].tx_buf = cmd;
1169 t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
1170 t[0].bits_per_word = spi->bits_per_word;
1171 t[0].tx_nbits = op->cmd.buswidth;
1172 /* lets mspi know that this is not last transfer */
1173 qspi->trans_pos.mspi_last_trans = false;
1174 ret = bcm_qspi_transfer_one(master, spi, &t[0]);
1175
1176 /* rx */
1177 qspi->trans_pos.mspi_last_trans = true;
1178 if (!ret) {
1179 /* rx */
1180 t[1].rx_buf = op->data.buf.in;
1181 t[1].len = op->data.nbytes;
1182 t[1].rx_nbits = op->data.buswidth;
1183 t[1].bits_per_word = spi->bits_per_word;
1184 ret = bcm_qspi_transfer_one(master, spi, &t[1]);
1185 }
1186
1187 return ret;
1188}
1189
1190static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
1191 const struct spi_mem_op *op)
1192{
1193 struct spi_device *spi = mem->spi;
1194 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1195 int ret = 0;
1196 bool mspi_read = false;
1197 u32 addr = 0, len;
1198 u_char *buf;
1199
1200 if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
1201 op->data.dir != SPI_MEM_DATA_IN)
1202 return -ENOTSUPP;
1203
1204 buf = op->data.buf.in;
1205 addr = op->addr.val;
1206 len = op->data.nbytes;
1207
1208 if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
1209 /*
1210 * The address coming into this function is a raw flash offset.
1211 * But for BSPI <= V3, we need to convert it to a remapped BSPI
1212 * address. If it crosses a 4MB boundary, just revert back to
1213 * using MSPI.
1214 */
1215 addr = (addr + 0xc00000) & 0xffffff;
1216
1217 if ((~ADDR_4MB_MASK & addr) ^
1218 (~ADDR_4MB_MASK & (addr + len - 1)))
1219 mspi_read = true;
1220 }
1221
1222 /* non-aligned and very short transfers are handled by MSPI */
1223 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
1224 len < 4)
1225 mspi_read = true;
1226
1227 if (!has_bspi(qspi) || mspi_read)
1228 return bcm_qspi_mspi_exec_mem_op(spi, op);
1229
1230 ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
1231
1232 if (!ret)
1233 ret = bcm_qspi_bspi_exec_mem_op(spi, op);
1234
1235 return ret;
1236}
1237
1238static void bcm_qspi_cleanup(struct spi_device *spi)
1239{
1240 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1241
1242 kfree(xp);
1243}
1244
1245static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1246{
1247 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1248 struct bcm_qspi *qspi = qspi_dev_id->dev;
1249 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1250
1251 if (status & MSPI_MSPI_STATUS_SPIF) {
1252 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1253 /* clear interrupt */
1254 status &= ~MSPI_MSPI_STATUS_SPIF;
1255 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1256 if (qspi->soc_intc)
1257 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1258 complete(&qspi->mspi_done);
1259 return IRQ_HANDLED;
1260 }
1261
1262 return IRQ_NONE;
1263}
1264
1265static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1266{
1267 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1268 struct bcm_qspi *qspi = qspi_dev_id->dev;
1269 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1270 u32 status = qspi_dev_id->irqp->mask;
1271
1272 if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1273 bcm_qspi_bspi_lr_data_read(qspi);
1274 if (qspi->bspi_rf_op_len == 0) {
1275 qspi->bspi_rf_op = NULL;
1276 if (qspi->soc_intc) {
1277 /* disable soc BSPI interrupt */
1278 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1279 false);
1280 /* indicate done */
1281 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1282 }
1283
1284 if (qspi->bspi_rf_op_status)
1285 bcm_qspi_bspi_lr_clear(qspi);
1286 else
1287 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1288 }
1289
1290 if (qspi->soc_intc)
1291 /* clear soc BSPI interrupt */
1292 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1293 }
1294
1295 status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1296 if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1297 complete(&qspi->bspi_done);
1298
1299 return IRQ_HANDLED;
1300}
1301
1302static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1303{
1304 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1305 struct bcm_qspi *qspi = qspi_dev_id->dev;
1306 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1307
1308 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1309 qspi->bspi_rf_op_status = -EIO;
1310 if (qspi->soc_intc)
1311 /* clear soc interrupt */
1312 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1313
1314 complete(&qspi->bspi_done);
1315 return IRQ_HANDLED;
1316}
1317
1318static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1319{
1320 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1321 struct bcm_qspi *qspi = qspi_dev_id->dev;
1322 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1323 irqreturn_t ret = IRQ_NONE;
1324
1325 if (soc_intc) {
1326 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1327
1328 if (status & MSPI_DONE)
1329 ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1330 else if (status & BSPI_DONE)
1331 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1332 else if (status & BSPI_ERR)
1333 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1334 }
1335
1336 return ret;
1337}
1338
1339static const struct bcm_qspi_irq qspi_irq_tab[] = {
1340 {
1341 .irq_name = "spi_lr_fullness_reached",
1342 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1343 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1344 },
1345 {
1346 .irq_name = "spi_lr_session_aborted",
1347 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1348 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1349 },
1350 {
1351 .irq_name = "spi_lr_impatient",
1352 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1353 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1354 },
1355 {
1356 .irq_name = "spi_lr_session_done",
1357 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1358 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1359 },
1360#ifdef QSPI_INT_DEBUG
1361 /* this interrupt is for debug purposes only, dont request irq */
1362 {
1363 .irq_name = "spi_lr_overread",
1364 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1365 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1366 },
1367#endif
1368 {
1369 .irq_name = "mspi_done",
1370 .irq_handler = bcm_qspi_mspi_l2_isr,
1371 .mask = INTR_MSPI_DONE_MASK,
1372 },
1373 {
1374 .irq_name = "mspi_halted",
1375 .irq_handler = bcm_qspi_mspi_l2_isr,
1376 .mask = INTR_MSPI_HALTED_MASK,
1377 },
1378 {
1379 /* single muxed L1 interrupt source */
1380 .irq_name = "spi_l1_intr",
1381 .irq_handler = bcm_qspi_l1_isr,
1382 .irq_source = MUXED_L1,
1383 .mask = QSPI_INTERRUPTS_ALL,
1384 },
1385};
1386
1387static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1388{
1389 u32 val = 0;
1390
1391 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1392 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1393 qspi->bspi_min_rev = val & 0xff;
1394 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1395 /* Force mapping of BSPI address -> flash offset */
1396 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1397 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1398 }
1399 qspi->bspi_enabled = 1;
1400 bcm_qspi_disable_bspi(qspi);
1401 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1402 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1403}
1404
1405static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1406{
1407 struct bcm_qspi_parms parms;
1408
1409 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1410 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1411 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1412 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1413 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1414
1415 parms.mode = SPI_MODE_3;
1416 parms.bits_per_word = 8;
1417 parms.speed_hz = qspi->max_speed_hz;
1418 bcm_qspi_hw_set_parms(qspi, &parms);
1419
1420 if (has_bspi(qspi))
1421 bcm_qspi_bspi_init(qspi);
1422}
1423
1424static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1425{
1426 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1427
1428 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1429 if (has_bspi(qspi))
1430 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1431
1432 /* clear interrupt */
1433 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1434}
1435
1436static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
1437 .exec_op = bcm_qspi_exec_mem_op,
1438};
1439
1440struct bcm_qspi_data {
1441 bool has_mspi_rev;
1442 bool has_spcr3_sysclk;
1443};
1444
1445static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
1446 .has_mspi_rev = false,
1447 .has_spcr3_sysclk = false,
1448};
1449
1450static const struct bcm_qspi_data bcm_qspi_rev_data = {
1451 .has_mspi_rev = true,
1452 .has_spcr3_sysclk = false,
1453};
1454
1455static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
1456 .has_mspi_rev = true,
1457 .has_spcr3_sysclk = true,
1458};
1459
1460static const struct of_device_id bcm_qspi_of_match[] = {
1461 {
1462 .compatible = "brcm,spi-bcm7445-qspi",
1463 .data = &bcm_qspi_rev_data,
1464
1465 },
1466 {
1467 .compatible = "brcm,spi-bcm-qspi",
1468 .data = &bcm_qspi_no_rev_data,
1469 },
1470 {
1471 .compatible = "brcm,spi-bcm7216-qspi",
1472 .data = &bcm_qspi_spcr3_data,
1473 },
1474 {
1475 .compatible = "brcm,spi-bcm7278-qspi",
1476 .data = &bcm_qspi_spcr3_data,
1477 },
1478 {},
1479};
1480MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1481
1482int bcm_qspi_probe(struct platform_device *pdev,
1483 struct bcm_qspi_soc_intc *soc_intc)
1484{
1485 const struct of_device_id *of_id = NULL;
1486 const struct bcm_qspi_data *data;
1487 struct device *dev = &pdev->dev;
1488 struct bcm_qspi *qspi;
1489 struct spi_master *master;
1490 struct resource *res;
1491 int irq, ret = 0, num_ints = 0;
1492 u32 val;
1493 u32 rev = 0;
1494 const char *name = NULL;
1495 int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1496
1497 /* We only support device-tree instantiation */
1498 if (!dev->of_node)
1499 return -ENODEV;
1500
1501 of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
1502 if (!of_id)
1503 return -ENODEV;
1504
1505 data = of_id->data;
1506
1507 master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
1508 if (!master) {
1509 dev_err(dev, "error allocating spi_master\n");
1510 return -ENOMEM;
1511 }
1512
1513 qspi = spi_master_get_devdata(master);
1514
1515 qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1516 if (IS_ERR(qspi->clk))
1517 return PTR_ERR(qspi->clk);
1518
1519 qspi->pdev = pdev;
1520 qspi->trans_pos.trans = NULL;
1521 qspi->trans_pos.byte = 0;
1522 qspi->trans_pos.mspi_last_trans = true;
1523 qspi->master = master;
1524
1525 master->bus_num = -1;
1526 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD |
1527 SPI_3WIRE;
1528 master->setup = bcm_qspi_setup;
1529 master->transfer_one = bcm_qspi_transfer_one;
1530 master->mem_ops = &bcm_qspi_mem_ops;
1531 master->cleanup = bcm_qspi_cleanup;
1532 master->dev.of_node = dev->of_node;
1533 master->num_chipselect = NUM_CHIPSELECT;
1534 master->use_gpio_descriptors = true;
1535
1536 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1537
1538 if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1539 master->num_chipselect = val;
1540
1541 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1542 if (!res)
1543 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1544 "mspi");
1545
1546 if (res) {
1547 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1548 if (IS_ERR(qspi->base[MSPI]))
1549 return PTR_ERR(qspi->base[MSPI]);
1550 } else {
1551 return 0;
1552 }
1553
1554 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1555 if (res) {
1556 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1557 if (IS_ERR(qspi->base[BSPI]))
1558 return PTR_ERR(qspi->base[BSPI]);
1559 qspi->bspi_mode = true;
1560 } else {
1561 qspi->bspi_mode = false;
1562 }
1563
1564 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1565
1566 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1567 if (res) {
1568 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1569 if (IS_ERR(qspi->base[CHIP_SELECT]))
1570 return PTR_ERR(qspi->base[CHIP_SELECT]);
1571 }
1572
1573 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1574 GFP_KERNEL);
1575 if (!qspi->dev_ids)
1576 return -ENOMEM;
1577
1578 /*
1579 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1580 * in specific ways
1581 */
1582 if (soc_intc) {
1583 qspi->soc_intc = soc_intc;
1584 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1585 } else {
1586 qspi->soc_intc = NULL;
1587 }
1588
1589 if (qspi->clk) {
1590 ret = clk_prepare_enable(qspi->clk);
1591 if (ret) {
1592 dev_err(dev, "failed to prepare clock\n");
1593 goto qspi_probe_err;
1594 }
1595 qspi->base_clk = clk_get_rate(qspi->clk);
1596 } else {
1597 qspi->base_clk = MSPI_BASE_FREQ;
1598 }
1599
1600 if (data->has_mspi_rev) {
1601 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1602 /* some older revs do not have a MSPI_REV register */
1603 if ((rev & 0xff) == 0xff)
1604 rev = 0;
1605 }
1606
1607 qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1608 qspi->mspi_min_rev = rev & 0xf;
1609 qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1610
1611 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1612
1613 /*
1614 * On SW resets it is possible to have the mask still enabled
1615 * Need to disable the mask and clear the status while we init
1616 */
1617 bcm_qspi_hw_uninit(qspi);
1618
1619 for (val = 0; val < num_irqs; val++) {
1620 irq = -1;
1621 name = qspi_irq_tab[val].irq_name;
1622 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1623 /* get the l2 interrupts */
1624 irq = platform_get_irq_byname_optional(pdev, name);
1625 } else if (!num_ints && soc_intc) {
1626 /* all mspi, bspi intrs muxed to one L1 intr */
1627 irq = platform_get_irq(pdev, 0);
1628 }
1629
1630 if (irq >= 0) {
1631 ret = devm_request_irq(&pdev->dev, irq,
1632 qspi_irq_tab[val].irq_handler, 0,
1633 name,
1634 &qspi->dev_ids[val]);
1635 if (ret < 0) {
1636 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1637 goto qspi_unprepare_err;
1638 }
1639
1640 qspi->dev_ids[val].dev = qspi;
1641 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1642 num_ints++;
1643 dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1644 qspi_irq_tab[val].irq_name,
1645 irq);
1646 }
1647 }
1648
1649 if (!num_ints) {
1650 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1651 ret = -EINVAL;
1652 goto qspi_unprepare_err;
1653 }
1654
1655 bcm_qspi_hw_init(qspi);
1656 init_completion(&qspi->mspi_done);
1657 init_completion(&qspi->bspi_done);
1658 qspi->curr_cs = -1;
1659
1660 platform_set_drvdata(pdev, qspi);
1661
1662 qspi->xfer_mode.width = -1;
1663 qspi->xfer_mode.addrlen = -1;
1664 qspi->xfer_mode.hp = -1;
1665
1666 ret = spi_register_master(master);
1667 if (ret < 0) {
1668 dev_err(dev, "can't register master\n");
1669 goto qspi_reg_err;
1670 }
1671
1672 return 0;
1673
1674qspi_reg_err:
1675 bcm_qspi_hw_uninit(qspi);
1676qspi_unprepare_err:
1677 clk_disable_unprepare(qspi->clk);
1678qspi_probe_err:
1679 kfree(qspi->dev_ids);
1680 return ret;
1681}
1682/* probe function to be called by SoC specific platform driver probe */
1683EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1684
1685void bcm_qspi_remove(struct platform_device *pdev)
1686{
1687 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1688
1689 spi_unregister_master(qspi->master);
1690 bcm_qspi_hw_uninit(qspi);
1691 clk_disable_unprepare(qspi->clk);
1692 kfree(qspi->dev_ids);
1693}
1694
1695/* function to be called by SoC specific platform driver remove() */
1696EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1697
1698static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1699{
1700 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1701
1702 /* store the override strap value */
1703 if (!bcm_qspi_bspi_ver_three(qspi))
1704 qspi->s3_strap_override_ctrl =
1705 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1706
1707 spi_master_suspend(qspi->master);
1708 clk_disable_unprepare(qspi->clk);
1709 bcm_qspi_hw_uninit(qspi);
1710
1711 return 0;
1712};
1713
1714static int __maybe_unused bcm_qspi_resume(struct device *dev)
1715{
1716 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1717 int ret = 0;
1718
1719 bcm_qspi_hw_init(qspi);
1720 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1721 if (qspi->soc_intc)
1722 /* enable MSPI interrupt */
1723 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1724 true);
1725
1726 ret = clk_prepare_enable(qspi->clk);
1727 if (!ret)
1728 spi_master_resume(qspi->master);
1729
1730 return ret;
1731}
1732
1733SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1734
1735/* pm_ops to be called by SoC specific platform driver */
1736EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1737
1738MODULE_AUTHOR("Kamal Dasu");
1739MODULE_DESCRIPTION("Broadcom QSPI driver");
1740MODULE_LICENSE("GPL v2");
1741MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
3 *
4 * Copyright 2016 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation (the "GPL").
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License version 2 (GPLv2) for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * version 2 (GPLv2) along with this source code.
17 */
18
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/device.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/ioport.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/mtd/spi-nor.h>
29#include <linux/of.h>
30#include <linux/of_irq.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/spi/spi.h>
34#include <linux/sysfs.h>
35#include <linux/types.h>
36#include "spi-bcm-qspi.h"
37
38#define DRIVER_NAME "bcm_qspi"
39
40
41/* BSPI register offsets */
42#define BSPI_REVISION_ID 0x000
43#define BSPI_SCRATCH 0x004
44#define BSPI_MAST_N_BOOT_CTRL 0x008
45#define BSPI_BUSY_STATUS 0x00c
46#define BSPI_INTR_STATUS 0x010
47#define BSPI_B0_STATUS 0x014
48#define BSPI_B0_CTRL 0x018
49#define BSPI_B1_STATUS 0x01c
50#define BSPI_B1_CTRL 0x020
51#define BSPI_STRAP_OVERRIDE_CTRL 0x024
52#define BSPI_FLEX_MODE_ENABLE 0x028
53#define BSPI_BITS_PER_CYCLE 0x02c
54#define BSPI_BITS_PER_PHASE 0x030
55#define BSPI_CMD_AND_MODE_BYTE 0x034
56#define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
57#define BSPI_BSPI_XOR_VALUE 0x03c
58#define BSPI_BSPI_XOR_ENABLE 0x040
59#define BSPI_BSPI_PIO_MODE_ENABLE 0x044
60#define BSPI_BSPI_PIO_IODIR 0x048
61#define BSPI_BSPI_PIO_DATA 0x04c
62
63/* RAF register offsets */
64#define BSPI_RAF_START_ADDR 0x100
65#define BSPI_RAF_NUM_WORDS 0x104
66#define BSPI_RAF_CTRL 0x108
67#define BSPI_RAF_FULLNESS 0x10c
68#define BSPI_RAF_WATERMARK 0x110
69#define BSPI_RAF_STATUS 0x114
70#define BSPI_RAF_READ_DATA 0x118
71#define BSPI_RAF_WORD_CNT 0x11c
72#define BSPI_RAF_CURR_ADDR 0x120
73
74/* Override mode masks */
75#define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
76#define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
77#define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
78#define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
79#define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
80
81#define BSPI_ADDRLEN_3BYTES 3
82#define BSPI_ADDRLEN_4BYTES 4
83
84#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
85
86#define BSPI_RAF_CTRL_START_MASK BIT(0)
87#define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
88
89#define BSPI_BPP_MODE_SELECT_MASK BIT(8)
90#define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
91
92#define BSPI_READ_LENGTH 256
93
94/* MSPI register offsets */
95#define MSPI_SPCR0_LSB 0x000
96#define MSPI_SPCR0_MSB 0x004
97#define MSPI_SPCR1_LSB 0x008
98#define MSPI_SPCR1_MSB 0x00c
99#define MSPI_NEWQP 0x010
100#define MSPI_ENDQP 0x014
101#define MSPI_SPCR2 0x018
102#define MSPI_MSPI_STATUS 0x020
103#define MSPI_CPTQP 0x024
104#define MSPI_SPCR3 0x028
105#define MSPI_TXRAM 0x040
106#define MSPI_RXRAM 0x0c0
107#define MSPI_CDRAM 0x140
108#define MSPI_WRITE_LOCK 0x180
109
110#define MSPI_MASTER_BIT BIT(7)
111
112#define MSPI_NUM_CDRAM 16
113#define MSPI_CDRAM_CONT_BIT BIT(7)
114#define MSPI_CDRAM_BITSE_BIT BIT(6)
115#define MSPI_CDRAM_PCS 0xf
116
117#define MSPI_SPCR2_SPE BIT(6)
118#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
119
120#define MSPI_MSPI_STATUS_SPIF BIT(0)
121
122#define INTR_BASE_BIT_SHIFT 0x02
123#define INTR_COUNT 0x07
124
125#define NUM_CHIPSELECT 4
126#define QSPI_SPBR_MIN 8U
127#define QSPI_SPBR_MAX 255U
128
129#define OPCODE_DIOR 0xBB
130#define OPCODE_QIOR 0xEB
131#define OPCODE_DIOR_4B 0xBC
132#define OPCODE_QIOR_4B 0xEC
133
134#define MAX_CMD_SIZE 6
135
136#define ADDR_4MB_MASK GENMASK(22, 0)
137
138/* stop at end of transfer, no other reason */
139#define TRANS_STATUS_BREAK_NONE 0
140/* stop at end of spi_message */
141#define TRANS_STATUS_BREAK_EOM 1
142/* stop at end of spi_transfer if delay */
143#define TRANS_STATUS_BREAK_DELAY 2
144/* stop at end of spi_transfer if cs_change */
145#define TRANS_STATUS_BREAK_CS_CHANGE 4
146/* stop if we run out of bytes */
147#define TRANS_STATUS_BREAK_NO_BYTES 8
148
149/* events that make us stop filling TX slots */
150#define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
151 TRANS_STATUS_BREAK_DELAY | \
152 TRANS_STATUS_BREAK_CS_CHANGE)
153
154/* events that make us deassert CS */
155#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
156 TRANS_STATUS_BREAK_CS_CHANGE)
157
158struct bcm_qspi_parms {
159 u32 speed_hz;
160 u8 mode;
161 u8 bits_per_word;
162};
163
164struct bcm_xfer_mode {
165 bool flex_mode;
166 unsigned int width;
167 unsigned int addrlen;
168 unsigned int hp;
169};
170
171enum base_type {
172 MSPI,
173 BSPI,
174 CHIP_SELECT,
175 BASEMAX,
176};
177
178enum irq_source {
179 SINGLE_L2,
180 MUXED_L1,
181};
182
183struct bcm_qspi_irq {
184 const char *irq_name;
185 const irq_handler_t irq_handler;
186 int irq_source;
187 u32 mask;
188};
189
190struct bcm_qspi_dev_id {
191 const struct bcm_qspi_irq *irqp;
192 void *dev;
193};
194
195struct qspi_trans {
196 struct spi_transfer *trans;
197 int byte;
198};
199
200struct bcm_qspi {
201 struct platform_device *pdev;
202 struct spi_master *master;
203 struct clk *clk;
204 u32 base_clk;
205 u32 max_speed_hz;
206 void __iomem *base[BASEMAX];
207
208 /* Some SoCs provide custom interrupt status register(s) */
209 struct bcm_qspi_soc_intc *soc_intc;
210
211 struct bcm_qspi_parms last_parms;
212 struct qspi_trans trans_pos;
213 int curr_cs;
214 int bspi_maj_rev;
215 int bspi_min_rev;
216 int bspi_enabled;
217 struct spi_flash_read_message *bspi_rf_msg;
218 u32 bspi_rf_msg_idx;
219 u32 bspi_rf_msg_len;
220 u32 bspi_rf_msg_status;
221 struct bcm_xfer_mode xfer_mode;
222 u32 s3_strap_override_ctrl;
223 bool bspi_mode;
224 bool big_endian;
225 int num_irqs;
226 struct bcm_qspi_dev_id *dev_ids;
227 struct completion mspi_done;
228 struct completion bspi_done;
229};
230
231static inline bool has_bspi(struct bcm_qspi *qspi)
232{
233 return qspi->bspi_mode;
234}
235
236/* Read qspi controller register*/
237static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
238 unsigned int offset)
239{
240 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
241}
242
243/* Write qspi controller register*/
244static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
245 unsigned int offset, unsigned int data)
246{
247 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
248}
249
250/* BSPI helpers */
251static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
252{
253 int i;
254
255 /* this should normally finish within 10us */
256 for (i = 0; i < 1000; i++) {
257 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
258 return 0;
259 udelay(1);
260 }
261 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
262 return -EIO;
263}
264
265static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
266{
267 if (qspi->bspi_maj_rev < 4)
268 return true;
269 return false;
270}
271
272static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
273{
274 bcm_qspi_bspi_busy_poll(qspi);
275 /* Force rising edge for the b0/b1 'flush' field */
276 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
277 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
278 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
279 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
280}
281
282static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
283{
284 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
285 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
286}
287
288static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
289{
290 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
291
292 /* BSPI v3 LR is LE only, convert data to host endianness */
293 if (bcm_qspi_bspi_ver_three(qspi))
294 data = le32_to_cpu(data);
295
296 return data;
297}
298
299static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
300{
301 bcm_qspi_bspi_busy_poll(qspi);
302 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
303 BSPI_RAF_CTRL_START_MASK);
304}
305
306static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
307{
308 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
309 BSPI_RAF_CTRL_CLEAR_MASK);
310 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
311}
312
313static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
314{
315 u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
316 u32 data = 0;
317
318 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
319 qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
320 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
321 data = bcm_qspi_bspi_lr_read_fifo(qspi);
322 if (likely(qspi->bspi_rf_msg_len >= 4) &&
323 IS_ALIGNED((uintptr_t)buf, 4)) {
324 buf[qspi->bspi_rf_msg_idx++] = data;
325 qspi->bspi_rf_msg_len -= 4;
326 } else {
327 /* Read out remaining bytes, make sure*/
328 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
329
330 data = cpu_to_le32(data);
331 while (qspi->bspi_rf_msg_len) {
332 *cbuf++ = (u8)data;
333 data >>= 8;
334 qspi->bspi_rf_msg_len--;
335 }
336 }
337 }
338}
339
340static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
341 int bpp, int bpc, int flex_mode)
342{
343 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
344 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
345 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
346 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
347 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
348}
349
350static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width,
351 int addrlen, int hp)
352{
353 int bpc = 0, bpp = 0;
354 u8 command = SPINOR_OP_READ_FAST;
355 int flex_mode = 1, rv = 0;
356 bool spans_4byte = false;
357
358 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
359 width, addrlen, hp);
360
361 if (addrlen == BSPI_ADDRLEN_4BYTES) {
362 bpp = BSPI_BPP_ADDR_SELECT_MASK;
363 spans_4byte = true;
364 }
365
366 bpp |= 8;
367
368 switch (width) {
369 case SPI_NBITS_SINGLE:
370 if (addrlen == BSPI_ADDRLEN_3BYTES)
371 /* default mode, does not need flex_cmd */
372 flex_mode = 0;
373 else
374 command = SPINOR_OP_READ4_FAST;
375 break;
376 case SPI_NBITS_DUAL:
377 bpc = 0x00000001;
378 if (hp) {
379 bpc |= 0x00010100; /* address and mode are 2-bit */
380 bpp = BSPI_BPP_MODE_SELECT_MASK;
381 command = OPCODE_DIOR;
382 if (spans_4byte)
383 command = OPCODE_DIOR_4B;
384 } else {
385 command = SPINOR_OP_READ_1_1_2;
386 if (spans_4byte)
387 command = SPINOR_OP_READ4_1_1_2;
388 }
389 break;
390 case SPI_NBITS_QUAD:
391 bpc = 0x00000002;
392 if (hp) {
393 bpc |= 0x00020200; /* address and mode are 4-bit */
394 bpp = 4; /* dummy cycles */
395 bpp |= BSPI_BPP_ADDR_SELECT_MASK;
396 command = OPCODE_QIOR;
397 if (spans_4byte)
398 command = OPCODE_QIOR_4B;
399 } else {
400 command = SPINOR_OP_READ_1_1_4;
401 if (spans_4byte)
402 command = SPINOR_OP_READ4_1_1_4;
403 }
404 break;
405 default:
406 rv = -EINVAL;
407 break;
408 }
409
410 if (rv == 0)
411 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc,
412 flex_mode);
413
414 return rv;
415}
416
417static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
418 int addrlen, int hp)
419{
420 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
421
422 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
423 width, addrlen, hp);
424
425 switch (width) {
426 case SPI_NBITS_SINGLE:
427 /* clear quad/dual mode */
428 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
429 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
430 break;
431
432 case SPI_NBITS_QUAD:
433 /* clear dual mode and set quad mode */
434 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
435 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
436 break;
437 case SPI_NBITS_DUAL:
438 /* clear quad mode set dual mode */
439 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
440 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 if (addrlen == BSPI_ADDRLEN_4BYTES)
447 /* set 4byte mode*/
448 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
449 else
450 /* clear 4 byte mode */
451 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
452
453 /* set the override mode */
454 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
455 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
456 bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0);
457
458 return 0;
459}
460
461static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
462 int width, int addrlen, int hp)
463{
464 int error = 0;
465
466 /* default mode */
467 qspi->xfer_mode.flex_mode = true;
468
469 if (!bcm_qspi_bspi_ver_three(qspi)) {
470 u32 val, mask;
471
472 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
473 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
474 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
475 qspi->xfer_mode.flex_mode = false;
476 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE,
477 0);
478
479 if ((val | qspi->s3_strap_override_ctrl) &
480 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL)
481 width = SPI_NBITS_DUAL;
482 else if ((val | qspi->s3_strap_override_ctrl) &
483 BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD)
484 width = SPI_NBITS_QUAD;
485
486 error = bcm_qspi_bspi_set_override(qspi, width, addrlen,
487 hp);
488 }
489 }
490
491 if (qspi->xfer_mode.flex_mode)
492 error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp);
493
494 if (error) {
495 dev_warn(&qspi->pdev->dev,
496 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
497 width, addrlen, hp);
498 } else if (qspi->xfer_mode.width != width ||
499 qspi->xfer_mode.addrlen != addrlen ||
500 qspi->xfer_mode.hp != hp) {
501 qspi->xfer_mode.width = width;
502 qspi->xfer_mode.addrlen = addrlen;
503 qspi->xfer_mode.hp = hp;
504 dev_dbg(&qspi->pdev->dev,
505 "cs:%d %d-lane output, %d-byte address%s\n",
506 qspi->curr_cs,
507 qspi->xfer_mode.width,
508 qspi->xfer_mode.addrlen,
509 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
510 }
511
512 return error;
513}
514
515static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
516{
517 if (!has_bspi(qspi) || (qspi->bspi_enabled))
518 return;
519
520 qspi->bspi_enabled = 1;
521 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
522 return;
523
524 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
525 udelay(1);
526 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
527 udelay(1);
528}
529
530static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
531{
532 if (!has_bspi(qspi) || (!qspi->bspi_enabled))
533 return;
534
535 qspi->bspi_enabled = 0;
536 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
537 return;
538
539 bcm_qspi_bspi_busy_poll(qspi);
540 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
541 udelay(1);
542}
543
544static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
545{
546 u32 data = 0;
547
548 if (qspi->curr_cs == cs)
549 return;
550 if (qspi->base[CHIP_SELECT]) {
551 data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
552 data = (data & ~0xff) | (1 << cs);
553 bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
554 usleep_range(10, 20);
555 }
556 qspi->curr_cs = cs;
557}
558
559/* MSPI helpers */
560static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
561 const struct bcm_qspi_parms *xp)
562{
563 u32 spcr, spbr = 0;
564
565 if (xp->speed_hz)
566 spbr = qspi->base_clk / (2 * xp->speed_hz);
567
568 spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
569 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
570
571 spcr = MSPI_MASTER_BIT;
572 /* for 16 bit the data should be zero */
573 if (xp->bits_per_word != 16)
574 spcr |= xp->bits_per_word << 2;
575 spcr |= xp->mode & 3;
576 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
577
578 qspi->last_parms = *xp;
579}
580
581static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
582 struct spi_device *spi,
583 struct spi_transfer *trans)
584{
585 struct bcm_qspi_parms xp;
586
587 xp.speed_hz = trans->speed_hz;
588 xp.bits_per_word = trans->bits_per_word;
589 xp.mode = spi->mode;
590
591 bcm_qspi_hw_set_parms(qspi, &xp);
592}
593
594static int bcm_qspi_setup(struct spi_device *spi)
595{
596 struct bcm_qspi_parms *xp;
597
598 if (spi->bits_per_word > 16)
599 return -EINVAL;
600
601 xp = spi_get_ctldata(spi);
602 if (!xp) {
603 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
604 if (!xp)
605 return -ENOMEM;
606 spi_set_ctldata(spi, xp);
607 }
608 xp->speed_hz = spi->max_speed_hz;
609 xp->mode = spi->mode;
610
611 if (spi->bits_per_word)
612 xp->bits_per_word = spi->bits_per_word;
613 else
614 xp->bits_per_word = 8;
615
616 return 0;
617}
618
619static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
620 struct qspi_trans *qt, int flags)
621{
622 int ret = TRANS_STATUS_BREAK_NONE;
623
624 /* count the last transferred bytes */
625 if (qt->trans->bits_per_word <= 8)
626 qt->byte++;
627 else
628 qt->byte += 2;
629
630 if (qt->byte >= qt->trans->len) {
631 /* we're at the end of the spi_transfer */
632
633 /* in TX mode, need to pause for a delay or CS change */
634 if (qt->trans->delay_usecs &&
635 (flags & TRANS_STATUS_BREAK_DELAY))
636 ret |= TRANS_STATUS_BREAK_DELAY;
637 if (qt->trans->cs_change &&
638 (flags & TRANS_STATUS_BREAK_CS_CHANGE))
639 ret |= TRANS_STATUS_BREAK_CS_CHANGE;
640 if (ret)
641 goto done;
642
643 dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
644 if (spi_transfer_is_last(qspi->master, qt->trans))
645 ret = TRANS_STATUS_BREAK_EOM;
646 else
647 ret = TRANS_STATUS_BREAK_NO_BYTES;
648
649 qt->trans = NULL;
650 }
651
652done:
653 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
654 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
655 return ret;
656}
657
658static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
659{
660 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
661
662 /* mask out reserved bits */
663 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
664}
665
666static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
667{
668 u32 reg_offset = MSPI_RXRAM;
669 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
670 u32 msb_offset = reg_offset + (slot << 3);
671
672 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
673 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
674}
675
676static void read_from_hw(struct bcm_qspi *qspi, int slots)
677{
678 struct qspi_trans tp;
679 int slot;
680
681 bcm_qspi_disable_bspi(qspi);
682
683 if (slots > MSPI_NUM_CDRAM) {
684 /* should never happen */
685 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
686 return;
687 }
688
689 tp = qspi->trans_pos;
690
691 for (slot = 0; slot < slots; slot++) {
692 if (tp.trans->bits_per_word <= 8) {
693 u8 *buf = tp.trans->rx_buf;
694
695 if (buf)
696 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
697 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
698 buf ? buf[tp.byte] : 0xff);
699 } else {
700 u16 *buf = tp.trans->rx_buf;
701
702 if (buf)
703 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
704 slot);
705 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
706 buf ? buf[tp.byte] : 0xffff);
707 }
708
709 update_qspi_trans_byte_count(qspi, &tp,
710 TRANS_STATUS_BREAK_NONE);
711 }
712
713 qspi->trans_pos = tp;
714}
715
716static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
717 u8 val)
718{
719 u32 reg_offset = MSPI_TXRAM + (slot << 3);
720
721 /* mask out reserved bits */
722 bcm_qspi_write(qspi, MSPI, reg_offset, val);
723}
724
725static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
726 u16 val)
727{
728 u32 reg_offset = MSPI_TXRAM;
729 u32 msb_offset = reg_offset + (slot << 3);
730 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
731
732 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
733 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
734}
735
736static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
737{
738 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
739}
740
741static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
742{
743 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
744}
745
746/* Return number of slots written */
747static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
748{
749 struct qspi_trans tp;
750 int slot = 0, tstatus = 0;
751 u32 mspi_cdram = 0;
752
753 bcm_qspi_disable_bspi(qspi);
754 tp = qspi->trans_pos;
755 bcm_qspi_update_parms(qspi, spi, tp.trans);
756
757 /* Run until end of transfer or reached the max data */
758 while (!tstatus && slot < MSPI_NUM_CDRAM) {
759 if (tp.trans->bits_per_word <= 8) {
760 const u8 *buf = tp.trans->tx_buf;
761 u8 val = buf ? buf[tp.byte] : 0xff;
762
763 write_txram_slot_u8(qspi, slot, val);
764 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
765 } else {
766 const u16 *buf = tp.trans->tx_buf;
767 u16 val = buf ? buf[tp.byte / 2] : 0xffff;
768
769 write_txram_slot_u16(qspi, slot, val);
770 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
771 }
772 mspi_cdram = MSPI_CDRAM_CONT_BIT;
773 mspi_cdram |= (~(1 << spi->chip_select) &
774 MSPI_CDRAM_PCS);
775 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
776 MSPI_CDRAM_BITSE_BIT);
777
778 write_cdram_slot(qspi, slot, mspi_cdram);
779
780 tstatus = update_qspi_trans_byte_count(qspi, &tp,
781 TRANS_STATUS_BREAK_TX);
782 slot++;
783 }
784
785 if (!slot) {
786 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
787 goto done;
788 }
789
790 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
791 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
792 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
793
794 if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
795 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
796 ~MSPI_CDRAM_CONT_BIT;
797 write_cdram_slot(qspi, slot - 1, mspi_cdram);
798 }
799
800 if (has_bspi(qspi))
801 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
802
803 /* Must flush previous writes before starting MSPI operation */
804 mb();
805 /* Set cont | spe | spifie */
806 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
807
808done:
809 return slot;
810}
811
812static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
813 struct spi_flash_read_message *msg)
814{
815 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
816 u32 addr = 0, len, len_words;
817 int ret = 0;
818 unsigned long timeo = msecs_to_jiffies(100);
819 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
820
821 if (bcm_qspi_bspi_ver_three(qspi))
822 if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
823 return -EIO;
824
825 bcm_qspi_chip_select(qspi, spi->chip_select);
826 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
827
828 /*
829 * when using flex mode mode we need to send
830 * the upper address byte to bspi
831 */
832 if (bcm_qspi_bspi_ver_three(qspi) == false) {
833 addr = msg->from & 0xff000000;
834 bcm_qspi_write(qspi, BSPI,
835 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
836 }
837
838 if (!qspi->xfer_mode.flex_mode)
839 addr = msg->from;
840 else
841 addr = msg->from & 0x00ffffff;
842
843 /* set BSPI RAF buffer max read length */
844 len = msg->len;
845 if (len > BSPI_READ_LENGTH)
846 len = BSPI_READ_LENGTH;
847
848 if (bcm_qspi_bspi_ver_three(qspi) == true)
849 addr = (addr + 0xc00000) & 0xffffff;
850
851 reinit_completion(&qspi->bspi_done);
852 bcm_qspi_enable_bspi(qspi);
853 len_words = (len + 3) >> 2;
854 qspi->bspi_rf_msg = msg;
855 qspi->bspi_rf_msg_status = 0;
856 qspi->bspi_rf_msg_idx = 0;
857 qspi->bspi_rf_msg_len = len;
858 dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
859
860 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
861 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
862 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
863
864 if (qspi->soc_intc) {
865 /*
866 * clear soc MSPI and BSPI interrupts and enable
867 * BSPI interrupts.
868 */
869 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
870 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
871 }
872
873 /* Must flush previous writes before starting BSPI operation */
874 mb();
875
876 bcm_qspi_bspi_lr_start(qspi);
877 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
878 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
879 ret = -ETIMEDOUT;
880 } else {
881 /* set the return length for the caller */
882 msg->retlen = len;
883 }
884
885 return ret;
886}
887
888static int bcm_qspi_flash_read(struct spi_device *spi,
889 struct spi_flash_read_message *msg)
890{
891 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
892 int ret = 0;
893 bool mspi_read = false;
894 u32 io_width, addrlen, addr, len;
895 u_char *buf;
896
897 buf = msg->buf;
898 addr = msg->from;
899 len = msg->len;
900
901 if (bcm_qspi_bspi_ver_three(qspi) == true) {
902 /*
903 * The address coming into this function is a raw flash offset.
904 * But for BSPI <= V3, we need to convert it to a remapped BSPI
905 * address. If it crosses a 4MB boundary, just revert back to
906 * using MSPI.
907 */
908 addr = (addr + 0xc00000) & 0xffffff;
909
910 if ((~ADDR_4MB_MASK & addr) ^
911 (~ADDR_4MB_MASK & (addr + len - 1)))
912 mspi_read = true;
913 }
914
915 /* non-aligned and very short transfers are handled by MSPI */
916 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
917 len < 4)
918 mspi_read = true;
919
920 if (mspi_read)
921 /* this will make the m25p80 read to fallback to mspi read */
922 return -EAGAIN;
923
924 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
925 addrlen = msg->addr_width;
926 ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1);
927
928 if (!ret)
929 ret = bcm_qspi_bspi_flash_read(spi, msg);
930
931 return ret;
932}
933
934static int bcm_qspi_transfer_one(struct spi_master *master,
935 struct spi_device *spi,
936 struct spi_transfer *trans)
937{
938 struct bcm_qspi *qspi = spi_master_get_devdata(master);
939 int slots;
940 unsigned long timeo = msecs_to_jiffies(100);
941
942 bcm_qspi_chip_select(qspi, spi->chip_select);
943 qspi->trans_pos.trans = trans;
944 qspi->trans_pos.byte = 0;
945
946 while (qspi->trans_pos.byte < trans->len) {
947 reinit_completion(&qspi->mspi_done);
948
949 slots = write_to_hw(qspi, spi);
950 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
951 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
952 return -ETIMEDOUT;
953 }
954
955 read_from_hw(qspi, slots);
956 }
957
958 return 0;
959}
960
961static void bcm_qspi_cleanup(struct spi_device *spi)
962{
963 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
964
965 kfree(xp);
966}
967
968static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
969{
970 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
971 struct bcm_qspi *qspi = qspi_dev_id->dev;
972 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
973
974 if (status & MSPI_MSPI_STATUS_SPIF) {
975 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
976 /* clear interrupt */
977 status &= ~MSPI_MSPI_STATUS_SPIF;
978 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
979 if (qspi->soc_intc)
980 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
981 complete(&qspi->mspi_done);
982 return IRQ_HANDLED;
983 }
984
985 return IRQ_NONE;
986}
987
988static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
989{
990 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
991 struct bcm_qspi *qspi = qspi_dev_id->dev;
992 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
993 u32 status = qspi_dev_id->irqp->mask;
994
995 if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
996 bcm_qspi_bspi_lr_data_read(qspi);
997 if (qspi->bspi_rf_msg_len == 0) {
998 qspi->bspi_rf_msg = NULL;
999 if (qspi->soc_intc) {
1000 /* disable soc BSPI interrupt */
1001 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1002 false);
1003 /* indicate done */
1004 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1005 }
1006
1007 if (qspi->bspi_rf_msg_status)
1008 bcm_qspi_bspi_lr_clear(qspi);
1009 else
1010 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1011 }
1012
1013 if (qspi->soc_intc)
1014 /* clear soc BSPI interrupt */
1015 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1016 }
1017
1018 status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1019 if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
1020 complete(&qspi->bspi_done);
1021
1022 return IRQ_HANDLED;
1023}
1024
1025static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1026{
1027 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1028 struct bcm_qspi *qspi = qspi_dev_id->dev;
1029 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1030
1031 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1032 qspi->bspi_rf_msg_status = -EIO;
1033 if (qspi->soc_intc)
1034 /* clear soc interrupt */
1035 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1036
1037 complete(&qspi->bspi_done);
1038 return IRQ_HANDLED;
1039}
1040
1041static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1042{
1043 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1044 struct bcm_qspi *qspi = qspi_dev_id->dev;
1045 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1046 irqreturn_t ret = IRQ_NONE;
1047
1048 if (soc_intc) {
1049 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1050
1051 if (status & MSPI_DONE)
1052 ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1053 else if (status & BSPI_DONE)
1054 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1055 else if (status & BSPI_ERR)
1056 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1057 }
1058
1059 return ret;
1060}
1061
1062static const struct bcm_qspi_irq qspi_irq_tab[] = {
1063 {
1064 .irq_name = "spi_lr_fullness_reached",
1065 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1066 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1067 },
1068 {
1069 .irq_name = "spi_lr_session_aborted",
1070 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1071 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1072 },
1073 {
1074 .irq_name = "spi_lr_impatient",
1075 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1076 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1077 },
1078 {
1079 .irq_name = "spi_lr_session_done",
1080 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1081 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1082 },
1083#ifdef QSPI_INT_DEBUG
1084 /* this interrupt is for debug purposes only, dont request irq */
1085 {
1086 .irq_name = "spi_lr_overread",
1087 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1088 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1089 },
1090#endif
1091 {
1092 .irq_name = "mspi_done",
1093 .irq_handler = bcm_qspi_mspi_l2_isr,
1094 .mask = INTR_MSPI_DONE_MASK,
1095 },
1096 {
1097 .irq_name = "mspi_halted",
1098 .irq_handler = bcm_qspi_mspi_l2_isr,
1099 .mask = INTR_MSPI_HALTED_MASK,
1100 },
1101 {
1102 /* single muxed L1 interrupt source */
1103 .irq_name = "spi_l1_intr",
1104 .irq_handler = bcm_qspi_l1_isr,
1105 .irq_source = MUXED_L1,
1106 .mask = QSPI_INTERRUPTS_ALL,
1107 },
1108};
1109
1110static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1111{
1112 u32 val = 0;
1113
1114 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1115 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1116 qspi->bspi_min_rev = val & 0xff;
1117 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1118 /* Force mapping of BSPI address -> flash offset */
1119 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1120 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1121 }
1122 qspi->bspi_enabled = 1;
1123 bcm_qspi_disable_bspi(qspi);
1124 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1125 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1126}
1127
1128static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1129{
1130 struct bcm_qspi_parms parms;
1131
1132 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1133 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1134 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1135 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1136 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1137
1138 parms.mode = SPI_MODE_3;
1139 parms.bits_per_word = 8;
1140 parms.speed_hz = qspi->max_speed_hz;
1141 bcm_qspi_hw_set_parms(qspi, &parms);
1142
1143 if (has_bspi(qspi))
1144 bcm_qspi_bspi_init(qspi);
1145}
1146
1147static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1148{
1149 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1150 if (has_bspi(qspi))
1151 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1152
1153}
1154
1155static const struct of_device_id bcm_qspi_of_match[] = {
1156 { .compatible = "brcm,spi-bcm-qspi" },
1157 {},
1158};
1159MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1160
1161int bcm_qspi_probe(struct platform_device *pdev,
1162 struct bcm_qspi_soc_intc *soc_intc)
1163{
1164 struct device *dev = &pdev->dev;
1165 struct bcm_qspi *qspi;
1166 struct spi_master *master;
1167 struct resource *res;
1168 int irq, ret = 0, num_ints = 0;
1169 u32 val;
1170 const char *name = NULL;
1171 int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1172
1173 /* We only support device-tree instantiation */
1174 if (!dev->of_node)
1175 return -ENODEV;
1176
1177 if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1178 return -ENODEV;
1179
1180 master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
1181 if (!master) {
1182 dev_err(dev, "error allocating spi_master\n");
1183 return -ENOMEM;
1184 }
1185
1186 qspi = spi_master_get_devdata(master);
1187 qspi->pdev = pdev;
1188 qspi->trans_pos.trans = NULL;
1189 qspi->trans_pos.byte = 0;
1190 qspi->master = master;
1191
1192 master->bus_num = -1;
1193 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1194 master->setup = bcm_qspi_setup;
1195 master->transfer_one = bcm_qspi_transfer_one;
1196 master->spi_flash_read = bcm_qspi_flash_read;
1197 master->cleanup = bcm_qspi_cleanup;
1198 master->dev.of_node = dev->of_node;
1199 master->num_chipselect = NUM_CHIPSELECT;
1200
1201 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1202
1203 if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1204 master->num_chipselect = val;
1205
1206 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1207 if (!res)
1208 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1209 "mspi");
1210
1211 if (res) {
1212 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1213 if (IS_ERR(qspi->base[MSPI])) {
1214 ret = PTR_ERR(qspi->base[MSPI]);
1215 goto qspi_probe_err;
1216 }
1217 } else {
1218 goto qspi_probe_err;
1219 }
1220
1221 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1222 if (res) {
1223 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1224 if (IS_ERR(qspi->base[BSPI])) {
1225 ret = PTR_ERR(qspi->base[BSPI]);
1226 goto qspi_probe_err;
1227 }
1228 qspi->bspi_mode = true;
1229 } else {
1230 qspi->bspi_mode = false;
1231 }
1232
1233 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1234
1235 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1236 if (res) {
1237 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1238 if (IS_ERR(qspi->base[CHIP_SELECT])) {
1239 ret = PTR_ERR(qspi->base[CHIP_SELECT]);
1240 goto qspi_probe_err;
1241 }
1242 }
1243
1244 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1245 GFP_KERNEL);
1246 if (!qspi->dev_ids) {
1247 ret = -ENOMEM;
1248 goto qspi_probe_err;
1249 }
1250
1251 for (val = 0; val < num_irqs; val++) {
1252 irq = -1;
1253 name = qspi_irq_tab[val].irq_name;
1254 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1255 /* get the l2 interrupts */
1256 irq = platform_get_irq_byname(pdev, name);
1257 } else if (!num_ints && soc_intc) {
1258 /* all mspi, bspi intrs muxed to one L1 intr */
1259 irq = platform_get_irq(pdev, 0);
1260 }
1261
1262 if (irq >= 0) {
1263 ret = devm_request_irq(&pdev->dev, irq,
1264 qspi_irq_tab[val].irq_handler, 0,
1265 name,
1266 &qspi->dev_ids[val]);
1267 if (ret < 0) {
1268 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1269 goto qspi_probe_err;
1270 }
1271
1272 qspi->dev_ids[val].dev = qspi;
1273 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1274 num_ints++;
1275 dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1276 qspi_irq_tab[val].irq_name,
1277 irq);
1278 }
1279 }
1280
1281 if (!num_ints) {
1282 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1283 ret = -EINVAL;
1284 goto qspi_probe_err;
1285 }
1286
1287 /*
1288 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1289 * in specific ways
1290 */
1291 if (soc_intc) {
1292 qspi->soc_intc = soc_intc;
1293 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1294 } else {
1295 qspi->soc_intc = NULL;
1296 }
1297
1298 qspi->clk = devm_clk_get(&pdev->dev, NULL);
1299 if (IS_ERR(qspi->clk)) {
1300 dev_warn(dev, "unable to get clock\n");
1301 ret = PTR_ERR(qspi->clk);
1302 goto qspi_probe_err;
1303 }
1304
1305 ret = clk_prepare_enable(qspi->clk);
1306 if (ret) {
1307 dev_err(dev, "failed to prepare clock\n");
1308 goto qspi_probe_err;
1309 }
1310
1311 qspi->base_clk = clk_get_rate(qspi->clk);
1312 qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
1313
1314 bcm_qspi_hw_init(qspi);
1315 init_completion(&qspi->mspi_done);
1316 init_completion(&qspi->bspi_done);
1317 qspi->curr_cs = -1;
1318
1319 platform_set_drvdata(pdev, qspi);
1320
1321 qspi->xfer_mode.width = -1;
1322 qspi->xfer_mode.addrlen = -1;
1323 qspi->xfer_mode.hp = -1;
1324
1325 ret = devm_spi_register_master(&pdev->dev, master);
1326 if (ret < 0) {
1327 dev_err(dev, "can't register master\n");
1328 goto qspi_reg_err;
1329 }
1330
1331 return 0;
1332
1333qspi_reg_err:
1334 bcm_qspi_hw_uninit(qspi);
1335 clk_disable_unprepare(qspi->clk);
1336qspi_probe_err:
1337 spi_master_put(master);
1338 kfree(qspi->dev_ids);
1339 return ret;
1340}
1341/* probe function to be called by SoC specific platform driver probe */
1342EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1343
1344int bcm_qspi_remove(struct platform_device *pdev)
1345{
1346 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1347
1348 platform_set_drvdata(pdev, NULL);
1349 bcm_qspi_hw_uninit(qspi);
1350 clk_disable_unprepare(qspi->clk);
1351 kfree(qspi->dev_ids);
1352 spi_unregister_master(qspi->master);
1353
1354 return 0;
1355}
1356/* function to be called by SoC specific platform driver remove() */
1357EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1358
1359static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1360{
1361 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1362
1363 spi_master_suspend(qspi->master);
1364 clk_disable(qspi->clk);
1365 bcm_qspi_hw_uninit(qspi);
1366
1367 return 0;
1368};
1369
1370static int __maybe_unused bcm_qspi_resume(struct device *dev)
1371{
1372 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1373 int ret = 0;
1374
1375 bcm_qspi_hw_init(qspi);
1376 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1377 if (qspi->soc_intc)
1378 /* enable MSPI interrupt */
1379 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1380 true);
1381
1382 ret = clk_enable(qspi->clk);
1383 if (!ret)
1384 spi_master_resume(qspi->master);
1385
1386 return ret;
1387}
1388
1389SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1390
1391/* pm_ops to be called by SoC specific platform driver */
1392EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1393
1394MODULE_AUTHOR("Kamal Dasu");
1395MODULE_DESCRIPTION("Broadcom QSPI driver");
1396MODULE_LICENSE("GPL v2");
1397MODULE_ALIAS("platform:" DRIVER_NAME);