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v6.2
  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * GPIO driver for the ACCES 104-DIO-48E series
  4 * Copyright (C) 2016 William Breathitt Gray
  5 *
 
 
 
 
 
 
 
 
 
  6 * This driver supports the following ACCES devices: 104-DIO-48E and
  7 * 104-DIO-24E.
  8 */
  9#include <linux/bits.h>
 10#include <linux/device.h>
 11#include <linux/errno.h>
 12#include <linux/gpio/driver.h>
 13#include <linux/io.h>
 14#include <linux/ioport.h>
 15#include <linux/interrupt.h>
 16#include <linux/irqdesc.h>
 17#include <linux/isa.h>
 18#include <linux/kernel.h>
 19#include <linux/module.h>
 20#include <linux/moduleparam.h>
 21#include <linux/spinlock.h>
 22#include <linux/types.h>
 23
 24#include "gpio-i8255.h"
 25
 26MODULE_IMPORT_NS(I8255);
 27
 28#define DIO48E_EXTENT 16
 29#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
 30
 31static unsigned int base[MAX_NUM_DIO48E];
 32static unsigned int num_dio48e;
 33module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
 34MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
 35
 36static unsigned int irq[MAX_NUM_DIO48E];
 37static unsigned int num_irq;
 38module_param_hw_array(irq, uint, irq, &num_irq, 0);
 39MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
 40
 41#define DIO48E_NUM_PPI 2
 42
 43/**
 44 * struct dio48e_reg - device register structure
 45 * @ppi:		Programmable Peripheral Interface groups
 46 * @enable_buffer:	Enable/Disable Buffer groups
 47 * @unused1:		Unused
 48 * @enable_interrupt:	Write: Enable Interrupt
 49 *			Read: Disable Interrupt
 50 * @unused2:		Unused
 51 * @enable_counter:	Write: Enable Counter/Timer Addressing
 52 *			Read: Disable Counter/Timer Addressing
 53 * @unused3:		Unused
 54 * @clear_interrupt:	Clear Interrupt
 55 */
 56struct dio48e_reg {
 57	struct i8255 ppi[DIO48E_NUM_PPI];
 58	u8 enable_buffer[DIO48E_NUM_PPI];
 59	u8 unused1;
 60	u8 enable_interrupt;
 61	u8 unused2;
 62	u8 enable_counter;
 63	u8 unused3;
 64	u8 clear_interrupt;
 65};
 66
 67/**
 68 * struct dio48e_gpio - GPIO device private data structure
 69 * @chip:		instance of the gpio_chip
 70 * @ppi_state:		PPI device states
 71 * @lock:		synchronization lock to prevent I/O race conditions
 72 * @reg:		I/O address offset for the device registers
 73 * @irq_mask:		I/O bits affected by interrupts
 
 
 
 74 */
 75struct dio48e_gpio {
 76	struct gpio_chip chip;
 77	struct i8255_state ppi_state[DIO48E_NUM_PPI];
 78	raw_spinlock_t lock;
 79	struct dio48e_reg __iomem *reg;
 
 
 
 80	unsigned char irq_mask;
 81};
 82
 83static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 84{
 85	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 86
 87	if (i8255_get_direction(dio48egpio->ppi_state, offset))
 88		return GPIO_LINE_DIRECTION_IN;
 89
 90	return GPIO_LINE_DIRECTION_OUT;
 91}
 92
 93static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 94{
 95	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 
 
 
 96
 97	i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state,
 98			      offset);
 99
100	return 0;
101}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
102
103static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
104					int value)
105{
106	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
107
108	i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state,
109			       offset, value);
110
111	return 0;
112}
113
114static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
 
115{
116	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 
 
 
 
 
117
118	return i8255_get(dio48egpio->reg->ppi, offset);
119}
120
121static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
122	unsigned long *bits)
123{
124	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
125
126	i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio);
 
 
 
127
128	return 0;
129}
130
131static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
132{
133	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
134
135	i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value);
136}
137
138static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
139	unsigned long *mask, unsigned long *bits)
140{
141	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 
 
 
 
 
 
 
 
 
 
 
 
 
142
143	i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask,
144			   bits, chip->ngpio);
145}
146
147static void dio48e_irq_ack(struct irq_data *data)
148{
149}
150
151static void dio48e_irq_mask(struct irq_data *data)
152{
153	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
154	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
155	const unsigned long offset = irqd_to_hwirq(data);
156	unsigned long flags;
157
158	/* only bit 3 on each respective Port C supports interrupts */
159	if (offset != 19 && offset != 43)
160		return;
161
162	raw_spin_lock_irqsave(&dio48egpio->lock, flags);
163
164	if (offset == 19)
165		dio48egpio->irq_mask &= ~BIT(0);
166	else
167		dio48egpio->irq_mask &= ~BIT(1);
168	gpiochip_disable_irq(chip, offset);
169
170	if (!dio48egpio->irq_mask)
171		/* disable interrupts */
172		ioread8(&dio48egpio->reg->enable_interrupt);
173
174	raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
175}
176
177static void dio48e_irq_unmask(struct irq_data *data)
178{
179	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
180	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
181	const unsigned long offset = irqd_to_hwirq(data);
182	unsigned long flags;
183
184	/* only bit 3 on each respective Port C supports interrupts */
185	if (offset != 19 && offset != 43)
186		return;
187
188	raw_spin_lock_irqsave(&dio48egpio->lock, flags);
189
190	if (!dio48egpio->irq_mask) {
191		/* enable interrupts */
192		iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
193		iowrite8(0x00, &dio48egpio->reg->enable_interrupt);
194	}
195
196	gpiochip_enable_irq(chip, offset);
197	if (offset == 19)
198		dio48egpio->irq_mask |= BIT(0);
199	else
200		dio48egpio->irq_mask |= BIT(1);
201
202	raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
203}
204
205static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type)
206{
207	const unsigned long offset = irqd_to_hwirq(data);
208
209	/* only bit 3 on each respective Port C supports interrupts */
210	if (offset != 19 && offset != 43)
211		return -EINVAL;
212
213	if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
214		return -EINVAL;
215
216	return 0;
217}
218
219static const struct irq_chip dio48e_irqchip = {
220	.name = "104-dio-48e",
221	.irq_ack = dio48e_irq_ack,
222	.irq_mask = dio48e_irq_mask,
223	.irq_unmask = dio48e_irq_unmask,
224	.irq_set_type = dio48e_irq_set_type,
225	.flags = IRQCHIP_IMMUTABLE,
226	GPIOCHIP_IRQ_RESOURCE_HELPERS,
227};
228
229static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
230{
231	struct dio48e_gpio *const dio48egpio = dev_id;
232	struct gpio_chip *const chip = &dio48egpio->chip;
233	const unsigned long irq_mask = dio48egpio->irq_mask;
234	unsigned long gpio;
235
236	for_each_set_bit(gpio, &irq_mask, 2)
237		generic_handle_domain_irq(chip->irq.domain,
238					  19 + gpio*24);
239
240	raw_spin_lock(&dio48egpio->lock);
241
242	iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
243
244	raw_spin_unlock(&dio48egpio->lock);
245
246	return IRQ_HANDLED;
247}
248
249#define DIO48E_NGPIO 48
250static const char *dio48e_names[DIO48E_NGPIO] = {
251	"PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
252	"PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
253	"PPI Group 0 Port A 6", "PPI Group 0 Port A 7",	"PPI Group 0 Port B 0",
254	"PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
255	"PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
256	"PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
257	"PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
258	"PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
259	"PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
260	"PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
261	"PPI Group 1 Port A 6", "PPI Group 1 Port A 7",	"PPI Group 1 Port B 0",
262	"PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
263	"PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
264	"PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
265	"PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
266	"PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
267};
268
269static int dio48e_irq_init_hw(struct gpio_chip *gc)
270{
271	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
272
273	/* Disable IRQ by default */
274	ioread8(&dio48egpio->reg->enable_interrupt);
275
276	return 0;
277}
278
279static void dio48e_init_ppi(struct i8255 __iomem *const ppi,
280			    struct i8255_state *const ppi_state)
281{
282	const unsigned long ngpio = 24;
283	const unsigned long mask = GENMASK(ngpio - 1, 0);
284	const unsigned long bits = 0;
285	unsigned long i;
286
287	/* Initialize all GPIO to output 0 */
288	for (i = 0; i < DIO48E_NUM_PPI; i++) {
289		i8255_mode0_output(&ppi[i]);
290		i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
291	}
292}
293
294static int dio48e_probe(struct device *dev, unsigned int id)
295{
296	struct dio48e_gpio *dio48egpio;
297	const char *const name = dev_name(dev);
298	struct gpio_irq_chip *girq;
299	int err;
300
301	dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
302	if (!dio48egpio)
303		return -ENOMEM;
304
305	if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
306		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
307			base[id], base[id] + DIO48E_EXTENT);
308		return -EBUSY;
309	}
310
311	dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
312	if (!dio48egpio->reg)
313		return -ENOMEM;
314
315	dio48egpio->chip.label = name;
316	dio48egpio->chip.parent = dev;
317	dio48egpio->chip.owner = THIS_MODULE;
318	dio48egpio->chip.base = -1;
319	dio48egpio->chip.ngpio = DIO48E_NGPIO;
320	dio48egpio->chip.names = dio48e_names;
321	dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
322	dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
323	dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
324	dio48egpio->chip.get = dio48e_gpio_get;
325	dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
326	dio48egpio->chip.set = dio48e_gpio_set;
327	dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
 
328
329	girq = &dio48egpio->chip.irq;
330	gpio_irq_chip_set_chip(girq, &dio48e_irqchip);
331	/* This will let us handle the parent IRQ in the driver */
332	girq->parent_handler = NULL;
333	girq->num_parents = 0;
334	girq->parents = NULL;
335	girq->default_type = IRQ_TYPE_NONE;
336	girq->handler = handle_edge_irq;
337	girq->init_hw = dio48e_irq_init_hw;
338
339	raw_spin_lock_init(&dio48egpio->lock);
340
341	i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI);
342	dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state);
343
344	err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
345	if (err) {
346		dev_err(dev, "GPIO registering failed (%d)\n", err);
347		return err;
348	}
349
350	err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
351		dio48egpio);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
352	if (err) {
353		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
354		return err;
355	}
356
357	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
358}
359
360static struct isa_driver dio48e_driver = {
361	.probe = dio48e_probe,
362	.driver = {
363		.name = "104-dio-48e"
364	},
 
365};
366module_isa_driver_with_irq(dio48e_driver, num_dio48e, num_irq);
367
368MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
369MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
370MODULE_LICENSE("GPL v2");
v4.10.11
 
  1/*
  2 * GPIO driver for the ACCES 104-DIO-48E series
  3 * Copyright (C) 2016 William Breathitt Gray
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License, version 2, as
  7 * published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful, but
 10 * WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 12 * General Public License for more details.
 13 *
 14 * This driver supports the following ACCES devices: 104-DIO-48E and
 15 * 104-DIO-24E.
 16 */
 17#include <linux/bitops.h>
 18#include <linux/device.h>
 19#include <linux/errno.h>
 20#include <linux/gpio/driver.h>
 21#include <linux/io.h>
 22#include <linux/ioport.h>
 23#include <linux/interrupt.h>
 24#include <linux/irqdesc.h>
 25#include <linux/isa.h>
 26#include <linux/kernel.h>
 27#include <linux/module.h>
 28#include <linux/moduleparam.h>
 29#include <linux/spinlock.h>
 
 
 
 
 
 30
 31#define DIO48E_EXTENT 16
 32#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
 33
 34static unsigned int base[MAX_NUM_DIO48E];
 35static unsigned int num_dio48e;
 36module_param_array(base, uint, &num_dio48e, 0);
 37MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
 38
 39static unsigned int irq[MAX_NUM_DIO48E];
 40module_param_array(irq, uint, NULL, 0);
 
 41MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
 42
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 43/**
 44 * struct dio48e_gpio - GPIO device private data structure
 45 * @chip:	instance of the gpio_chip
 46 * @io_state:	bit I/O state (whether bit is set to input or output)
 47 * @out_state:	output bits state
 48 * @control:	Control registers state
 49 * @lock:	synchronization lock to prevent I/O race conditions
 50 * @base:	base port address of the GPIO device
 51 * @irq:	Interrupt line number
 52 * @irq_mask:	I/O bits affected by interrupts
 53 */
 54struct dio48e_gpio {
 55	struct gpio_chip chip;
 56	unsigned char io_state[6];
 57	unsigned char out_state[6];
 58	unsigned char control[2];
 59	spinlock_t lock;
 60	unsigned base;
 61	unsigned irq;
 62	unsigned char irq_mask;
 63};
 64
 65static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 66{
 67	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 68	const unsigned port = offset / 8;
 69	const unsigned mask = BIT(offset % 8);
 70
 71	return !!(dio48egpio->io_state[port] & mask);
 
 
 
 72}
 73
 74static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 75{
 76	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
 77	const unsigned io_port = offset / 8;
 78	const unsigned int control_port = io_port / 3;
 79	const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
 80	unsigned long flags;
 81	unsigned control;
 82
 83	spin_lock_irqsave(&dio48egpio->lock, flags);
 
 84
 85	/* Check if configuring Port C */
 86	if (io_port == 2 || io_port == 5) {
 87		/* Port C can be configured by nibble */
 88		if (offset % 8 > 3) {
 89			dio48egpio->io_state[io_port] |= 0xF0;
 90			dio48egpio->control[control_port] |= BIT(3);
 91		} else {
 92			dio48egpio->io_state[io_port] |= 0x0F;
 93			dio48egpio->control[control_port] |= BIT(0);
 94		}
 95	} else {
 96		dio48egpio->io_state[io_port] |= 0xFF;
 97		if (io_port == 0 || io_port == 3)
 98			dio48egpio->control[control_port] |= BIT(4);
 99		else
100			dio48egpio->control[control_port] |= BIT(1);
101	}
102
103	control = BIT(7) | dio48egpio->control[control_port];
104	outb(control, control_addr);
105	control &= ~BIT(7);
106	outb(control, control_addr);
107
108	spin_unlock_irqrestore(&dio48egpio->lock, flags);
 
109
110	return 0;
111}
112
113static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
114	int value)
115{
116	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
117	const unsigned io_port = offset / 8;
118	const unsigned int control_port = io_port / 3;
119	const unsigned mask = BIT(offset % 8);
120	const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
121	const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
122	unsigned long flags;
123	unsigned control;
124
125	spin_lock_irqsave(&dio48egpio->lock, flags);
 
126
127	/* Check if configuring Port C */
128	if (io_port == 2 || io_port == 5) {
129		/* Port C can be configured by nibble */
130		if (offset % 8 > 3) {
131			dio48egpio->io_state[io_port] &= 0x0F;
132			dio48egpio->control[control_port] &= ~BIT(3);
133		} else {
134			dio48egpio->io_state[io_port] &= 0xF0;
135			dio48egpio->control[control_port] &= ~BIT(0);
136		}
137	} else {
138		dio48egpio->io_state[io_port] &= 0x00;
139		if (io_port == 0 || io_port == 3)
140			dio48egpio->control[control_port] &= ~BIT(4);
141		else
142			dio48egpio->control[control_port] &= ~BIT(1);
143	}
144
145	if (value)
146		dio48egpio->out_state[io_port] |= mask;
147	else
148		dio48egpio->out_state[io_port] &= ~mask;
149
150	control = BIT(7) | dio48egpio->control[control_port];
151	outb(control, control_addr);
152
153	outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
154
155	control &= ~BIT(7);
156	outb(control, control_addr);
157
158	spin_unlock_irqrestore(&dio48egpio->lock, flags);
159
160	return 0;
161}
162
163static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
164{
165	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
166	const unsigned port = offset / 8;
167	const unsigned mask = BIT(offset % 8);
168	const unsigned in_port = (port > 2) ? port + 1 : port;
169	unsigned long flags;
170	unsigned port_state;
171
172	spin_lock_irqsave(&dio48egpio->lock, flags);
173
174	/* ensure that GPIO is set for input */
175	if (!(dio48egpio->io_state[port] & mask)) {
176		spin_unlock_irqrestore(&dio48egpio->lock, flags);
177		return -EINVAL;
178	}
179
180	port_state = inb(dio48egpio->base + in_port);
181
182	spin_unlock_irqrestore(&dio48egpio->lock, flags);
183
184	return !!(port_state & mask);
185}
186
187static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 
188{
189	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
190	const unsigned port = offset / 8;
191	const unsigned mask = BIT(offset % 8);
192	const unsigned out_port = (port > 2) ? port + 1 : port;
193	unsigned long flags;
194
195	spin_lock_irqsave(&dio48egpio->lock, flags);
196
197	if (value)
198		dio48egpio->out_state[port] |= mask;
199	else
200		dio48egpio->out_state[port] &= ~mask;
201
202	outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
203
204	spin_unlock_irqrestore(&dio48egpio->lock, flags);
 
205}
206
207static void dio48e_irq_ack(struct irq_data *data)
208{
209}
210
211static void dio48e_irq_mask(struct irq_data *data)
212{
213	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
214	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
215	const unsigned long offset = irqd_to_hwirq(data);
216	unsigned long flags;
217
218	/* only bit 3 on each respective Port C supports interrupts */
219	if (offset != 19 && offset != 43)
220		return;
221
222	spin_lock_irqsave(&dio48egpio->lock, flags);
223
224	if (offset == 19)
225		dio48egpio->irq_mask &= ~BIT(0);
226	else
227		dio48egpio->irq_mask &= ~BIT(1);
 
228
229	if (!dio48egpio->irq_mask)
230		/* disable interrupts */
231		inb(dio48egpio->base + 0xB);
232
233	spin_unlock_irqrestore(&dio48egpio->lock, flags);
234}
235
236static void dio48e_irq_unmask(struct irq_data *data)
237{
238	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
239	struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
240	const unsigned long offset = irqd_to_hwirq(data);
241	unsigned long flags;
242
243	/* only bit 3 on each respective Port C supports interrupts */
244	if (offset != 19 && offset != 43)
245		return;
246
247	spin_lock_irqsave(&dio48egpio->lock, flags);
248
249	if (!dio48egpio->irq_mask) {
250		/* enable interrupts */
251		outb(0x00, dio48egpio->base + 0xF);
252		outb(0x00, dio48egpio->base + 0xB);
253	}
254
 
255	if (offset == 19)
256		dio48egpio->irq_mask |= BIT(0);
257	else
258		dio48egpio->irq_mask |= BIT(1);
259
260	spin_unlock_irqrestore(&dio48egpio->lock, flags);
261}
262
263static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
264{
265	const unsigned long offset = irqd_to_hwirq(data);
266
267	/* only bit 3 on each respective Port C supports interrupts */
268	if (offset != 19 && offset != 43)
269		return -EINVAL;
270
271	if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
272		return -EINVAL;
273
274	return 0;
275}
276
277static struct irq_chip dio48e_irqchip = {
278	.name = "104-dio-48e",
279	.irq_ack = dio48e_irq_ack,
280	.irq_mask = dio48e_irq_mask,
281	.irq_unmask = dio48e_irq_unmask,
282	.irq_set_type = dio48e_irq_set_type
 
 
283};
284
285static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
286{
287	struct dio48e_gpio *const dio48egpio = dev_id;
288	struct gpio_chip *const chip = &dio48egpio->chip;
289	const unsigned long irq_mask = dio48egpio->irq_mask;
290	unsigned long gpio;
291
292	for_each_set_bit(gpio, &irq_mask, 2)
293		generic_handle_irq(irq_find_mapping(chip->irqdomain,
294			19 + gpio*24));
295
296	spin_lock(&dio48egpio->lock);
297
298	outb(0x00, dio48egpio->base + 0xF);
299
300	spin_unlock(&dio48egpio->lock);
301
302	return IRQ_HANDLED;
303}
304
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
305static int dio48e_probe(struct device *dev, unsigned int id)
306{
307	struct dio48e_gpio *dio48egpio;
308	const char *const name = dev_name(dev);
 
309	int err;
310
311	dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
312	if (!dio48egpio)
313		return -ENOMEM;
314
315	if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
316		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
317			base[id], base[id] + DIO48E_EXTENT);
318		return -EBUSY;
319	}
320
 
 
 
 
321	dio48egpio->chip.label = name;
322	dio48egpio->chip.parent = dev;
323	dio48egpio->chip.owner = THIS_MODULE;
324	dio48egpio->chip.base = -1;
325	dio48egpio->chip.ngpio = 48;
 
326	dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
327	dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
328	dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
329	dio48egpio->chip.get = dio48e_gpio_get;
 
330	dio48egpio->chip.set = dio48e_gpio_set;
331	dio48egpio->base = base[id];
332	dio48egpio->irq = irq[id];
333
334	spin_lock_init(&dio48egpio->lock);
 
 
 
 
 
 
 
 
335
336	dev_set_drvdata(dev, dio48egpio);
337
338	err = gpiochip_add_data(&dio48egpio->chip, dio48egpio);
 
 
 
339	if (err) {
340		dev_err(dev, "GPIO registering failed (%d)\n", err);
341		return err;
342	}
343
344	/* initialize all GPIO as output */
345	outb(0x80, base[id] + 3);
346	outb(0x00, base[id]);
347	outb(0x00, base[id] + 1);
348	outb(0x00, base[id] + 2);
349	outb(0x00, base[id] + 3);
350	outb(0x80, base[id] + 7);
351	outb(0x00, base[id] + 4);
352	outb(0x00, base[id] + 5);
353	outb(0x00, base[id] + 6);
354	outb(0x00, base[id] + 7);
355
356	/* disable IRQ by default */
357	inb(base[id] + 0xB);
358
359	err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0,
360		handle_edge_irq, IRQ_TYPE_NONE);
361	if (err) {
362		dev_err(dev, "Could not add irqchip (%d)\n", err);
363		goto err_gpiochip_remove;
364	}
365
366	err = request_irq(irq[id], dio48e_irq_handler, 0, name, dio48egpio);
367	if (err) {
368		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
369		goto err_gpiochip_remove;
370	}
371
372	return 0;
373
374err_gpiochip_remove:
375	gpiochip_remove(&dio48egpio->chip);
376	return err;
377}
378
379static int dio48e_remove(struct device *dev, unsigned int id)
380{
381	struct dio48e_gpio *const dio48egpio = dev_get_drvdata(dev);
382
383	free_irq(dio48egpio->irq, dio48egpio);
384	gpiochip_remove(&dio48egpio->chip);
385
386	return 0;
387}
388
389static struct isa_driver dio48e_driver = {
390	.probe = dio48e_probe,
391	.driver = {
392		.name = "104-dio-48e"
393	},
394	.remove = dio48e_remove
395};
396module_isa_driver(dio48e_driver, num_dio48e);
397
398MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
399MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
400MODULE_LICENSE("GPL v2");