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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6*/
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10
11#include <linux/i2c.h>
12#include <linux/time.h>
13#include <linux/interrupt.h>
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/spinlock.h>
25
26/*
27 * HSI2C controller from Samsung supports 2 modes of operation
28 * 1. Auto mode: Where in master automatically controls the whole transaction
29 * 2. Manual mode: Software controls the transaction by issuing commands
30 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
31 *
32 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
33 *
34 * Special bits are available for both modes of operation to set commands
35 * and for checking transfer status
36 */
37
38/* Register Map */
39#define HSI2C_CTL 0x00
40#define HSI2C_FIFO_CTL 0x04
41#define HSI2C_TRAILIG_CTL 0x08
42#define HSI2C_CLK_CTL 0x0C
43#define HSI2C_CLK_SLOT 0x10
44#define HSI2C_INT_ENABLE 0x20
45#define HSI2C_INT_STATUS 0x24
46#define HSI2C_ERR_STATUS 0x2C
47#define HSI2C_FIFO_STATUS 0x30
48#define HSI2C_TX_DATA 0x34
49#define HSI2C_RX_DATA 0x38
50#define HSI2C_CONF 0x40
51#define HSI2C_AUTO_CONF 0x44
52#define HSI2C_TIMEOUT 0x48
53#define HSI2C_MANUAL_CMD 0x4C
54#define HSI2C_TRANS_STATUS 0x50
55#define HSI2C_TIMING_HS1 0x54
56#define HSI2C_TIMING_HS2 0x58
57#define HSI2C_TIMING_HS3 0x5C
58#define HSI2C_TIMING_FS1 0x60
59#define HSI2C_TIMING_FS2 0x64
60#define HSI2C_TIMING_FS3 0x68
61#define HSI2C_TIMING_SLA 0x6C
62#define HSI2C_ADDR 0x70
63
64/* I2C_CTL Register bits */
65#define HSI2C_FUNC_MODE_I2C (1u << 0)
66#define HSI2C_MASTER (1u << 3)
67#define HSI2C_RXCHON (1u << 6)
68#define HSI2C_TXCHON (1u << 7)
69#define HSI2C_SW_RST (1u << 31)
70
71/* I2C_FIFO_CTL Register bits */
72#define HSI2C_RXFIFO_EN (1u << 0)
73#define HSI2C_TXFIFO_EN (1u << 1)
74#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
75#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
76
77/* I2C_TRAILING_CTL Register bits */
78#define HSI2C_TRAILING_COUNT (0xf)
79
80/* I2C_INT_EN Register bits */
81#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
82#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
83#define HSI2C_INT_TRAILING_EN (1u << 6)
84
85/* I2C_INT_STAT Register bits */
86#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
87#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
88#define HSI2C_INT_TX_UNDERRUN (1u << 2)
89#define HSI2C_INT_TX_OVERRUN (1u << 3)
90#define HSI2C_INT_RX_UNDERRUN (1u << 4)
91#define HSI2C_INT_RX_OVERRUN (1u << 5)
92#define HSI2C_INT_TRAILING (1u << 6)
93#define HSI2C_INT_I2C (1u << 9)
94
95#define HSI2C_INT_TRANS_DONE (1u << 7)
96#define HSI2C_INT_TRANS_ABORT (1u << 8)
97#define HSI2C_INT_NO_DEV_ACK (1u << 9)
98#define HSI2C_INT_NO_DEV (1u << 10)
99#define HSI2C_INT_TIMEOUT (1u << 11)
100#define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
101 HSI2C_INT_TRANS_ABORT | \
102 HSI2C_INT_NO_DEV_ACK | \
103 HSI2C_INT_NO_DEV | \
104 HSI2C_INT_TIMEOUT)
105
106/* I2C_FIFO_STAT Register bits */
107#define HSI2C_RX_FIFO_EMPTY (1u << 24)
108#define HSI2C_RX_FIFO_FULL (1u << 23)
109#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
110#define HSI2C_TX_FIFO_EMPTY (1u << 8)
111#define HSI2C_TX_FIFO_FULL (1u << 7)
112#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
113
114/* I2C_CONF Register bits */
115#define HSI2C_AUTO_MODE (1u << 31)
116#define HSI2C_10BIT_ADDR_MODE (1u << 30)
117#define HSI2C_HS_MODE (1u << 29)
118
119/* I2C_AUTO_CONF Register bits */
120#define HSI2C_READ_WRITE (1u << 16)
121#define HSI2C_STOP_AFTER_TRANS (1u << 17)
122#define HSI2C_MASTER_RUN (1u << 31)
123
124/* I2C_TIMEOUT Register bits */
125#define HSI2C_TIMEOUT_EN (1u << 31)
126#define HSI2C_TIMEOUT_MASK 0xff
127
128/* I2C_MANUAL_CMD register bits */
129#define HSI2C_CMD_READ_DATA (1u << 4)
130#define HSI2C_CMD_SEND_STOP (1u << 2)
131
132/* I2C_TRANS_STATUS register bits */
133#define HSI2C_MASTER_BUSY (1u << 17)
134#define HSI2C_SLAVE_BUSY (1u << 16)
135
136/* I2C_TRANS_STATUS register bits for Exynos5 variant */
137#define HSI2C_TIMEOUT_AUTO (1u << 4)
138#define HSI2C_NO_DEV (1u << 3)
139#define HSI2C_NO_DEV_ACK (1u << 2)
140#define HSI2C_TRANS_ABORT (1u << 1)
141#define HSI2C_TRANS_DONE (1u << 0)
142
143/* I2C_TRANS_STATUS register bits for Exynos7 variant */
144#define HSI2C_MASTER_ST_MASK 0xf
145#define HSI2C_MASTER_ST_IDLE 0x0
146#define HSI2C_MASTER_ST_START 0x1
147#define HSI2C_MASTER_ST_RESTART 0x2
148#define HSI2C_MASTER_ST_STOP 0x3
149#define HSI2C_MASTER_ST_MASTER_ID 0x4
150#define HSI2C_MASTER_ST_ADDR0 0x5
151#define HSI2C_MASTER_ST_ADDR1 0x6
152#define HSI2C_MASTER_ST_ADDR2 0x7
153#define HSI2C_MASTER_ST_ADDR_SR 0x8
154#define HSI2C_MASTER_ST_READ 0x9
155#define HSI2C_MASTER_ST_WRITE 0xa
156#define HSI2C_MASTER_ST_NO_ACK 0xb
157#define HSI2C_MASTER_ST_LOSE 0xc
158#define HSI2C_MASTER_ST_WAIT 0xd
159#define HSI2C_MASTER_ST_WAIT_CMD 0xe
160
161/* I2C_ADDR register bits */
162#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
163#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
164#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
165#define MASTER_ID(x) ((x & 0x7) + 0x08)
166
167#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
168
169enum i2c_type_exynos {
170 I2C_TYPE_EXYNOS5,
171 I2C_TYPE_EXYNOS7,
172 I2C_TYPE_EXYNOSAUTOV9,
173};
174
175struct exynos5_i2c {
176 struct i2c_adapter adap;
177
178 struct i2c_msg *msg;
179 struct completion msg_complete;
180 unsigned int msg_ptr;
181
182 unsigned int irq;
183
184 void __iomem *regs;
185 struct clk *clk; /* operating clock */
186 struct clk *pclk; /* bus clock */
187 struct device *dev;
188 int state;
189
190 spinlock_t lock; /* IRQ synchronization */
191
192 /*
193 * Since the TRANS_DONE bit is cleared on read, and we may read it
194 * either during an IRQ or after a transaction, keep track of its
195 * state here.
196 */
197 int trans_done;
198
199 /* Controller operating frequency */
200 unsigned int op_clock;
201
202 /* Version of HS-I2C Hardware */
203 const struct exynos_hsi2c_variant *variant;
204};
205
206/**
207 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
208 * @fifo_depth: the fifo depth supported by the HSI2C module
209 * @hw: the hardware variant of Exynos I2C controller
210 *
211 * Specifies platform specific configuration of HSI2C module.
212 * Note: A structure for driver specific platform data is used for future
213 * expansion of its usage.
214 */
215struct exynos_hsi2c_variant {
216 unsigned int fifo_depth;
217 enum i2c_type_exynos hw;
218};
219
220static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
221 .fifo_depth = 64,
222 .hw = I2C_TYPE_EXYNOS5,
223};
224
225static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
226 .fifo_depth = 16,
227 .hw = I2C_TYPE_EXYNOS5,
228};
229
230static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
231 .fifo_depth = 16,
232 .hw = I2C_TYPE_EXYNOS7,
233};
234
235static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
236 .fifo_depth = 64,
237 .hw = I2C_TYPE_EXYNOSAUTOV9,
238};
239
240static const struct of_device_id exynos5_i2c_match[] = {
241 {
242 .compatible = "samsung,exynos5-hsi2c",
243 .data = &exynos5250_hsi2c_data
244 }, {
245 .compatible = "samsung,exynos5250-hsi2c",
246 .data = &exynos5250_hsi2c_data
247 }, {
248 .compatible = "samsung,exynos5260-hsi2c",
249 .data = &exynos5260_hsi2c_data
250 }, {
251 .compatible = "samsung,exynos7-hsi2c",
252 .data = &exynos7_hsi2c_data
253 }, {
254 .compatible = "samsung,exynosautov9-hsi2c",
255 .data = &exynosautov9_hsi2c_data
256 }, {},
257};
258MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
259
260static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
261{
262 writel(readl(i2c->regs + HSI2C_INT_STATUS),
263 i2c->regs + HSI2C_INT_STATUS);
264}
265
266/*
267 * exynos5_i2c_set_timing: updates the registers with appropriate
268 * timing values calculated
269 *
270 * Timing values for operation are calculated against either 100kHz
271 * or 1MHz controller operating frequency.
272 *
273 * Returns 0 on success, -EINVAL if the cycle length cannot
274 * be calculated.
275 */
276static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
277{
278 u32 i2c_timing_s1;
279 u32 i2c_timing_s2;
280 u32 i2c_timing_s3;
281 u32 i2c_timing_sla;
282 unsigned int t_start_su, t_start_hd;
283 unsigned int t_stop_su;
284 unsigned int t_data_su, t_data_hd;
285 unsigned int t_scl_l, t_scl_h;
286 unsigned int t_sr_release;
287 unsigned int t_ftl_cycle;
288 unsigned int clkin = clk_get_rate(i2c->clk);
289 unsigned int op_clk = hs_timings ? i2c->op_clock :
290 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
291 i2c->op_clock;
292 int div, clk_cycle, temp;
293
294 /*
295 * In case of HSI2C controllers in ExynosAutoV9:
296 *
297 * FSCL = IPCLK / ((CLK_DIV + 1) * 16)
298 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M)
299 * [N : number of 0's in the TSCL_H_HS]
300 * [M : number of 0's in the TSCL_L_HS]
301 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M)
302 * [N : number of 1's in the TSCL_H_HS]
303 * [M : number of 1's in the TSCL_L_HS]
304 *
305 * Result of (N + M) is always 8.
306 * In general case, we don't need to control timing_s1 and timing_s2.
307 */
308 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
309 div = ((clkin / (16 * i2c->op_clock)) - 1);
310 i2c_timing_s3 = div << 16;
311 if (hs_timings)
312 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
313 else
314 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
315
316 return 0;
317 }
318
319 /*
320 * In case of HSI2C controller in Exynos5 series
321 * FPCLK / FI2C =
322 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
323 *
324 * In case of HSI2C controllers in Exynos7 series
325 * FPCLK / FI2C =
326 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
327 *
328 * clk_cycle := TSCLK_L + TSCLK_H
329 * temp := (CLK_DIV + 1) * (clk_cycle + 2)
330 *
331 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
332 *
333 */
334 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
335 temp = clkin / op_clk - 8 - t_ftl_cycle;
336 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
337 temp -= t_ftl_cycle;
338 div = temp / 512;
339 clk_cycle = temp / (div + 1) - 2;
340 if (temp < 4 || div >= 256 || clk_cycle < 2) {
341 dev_err(i2c->dev, "%s clock set-up failed\n",
342 hs_timings ? "HS" : "FS");
343 return -EINVAL;
344 }
345
346 t_scl_l = clk_cycle / 2;
347 t_scl_h = clk_cycle / 2;
348 t_start_su = t_scl_l;
349 t_start_hd = t_scl_l;
350 t_stop_su = t_scl_l;
351 t_data_su = t_scl_l / 2;
352 t_data_hd = t_scl_l / 2;
353 t_sr_release = clk_cycle;
354
355 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
356 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
357 i2c_timing_s3 = div << 16 | t_sr_release << 0;
358 i2c_timing_sla = t_data_hd << 0;
359
360 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
361 t_start_su, t_start_hd, t_stop_su);
362 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
363 t_data_su, t_scl_l, t_scl_h);
364 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
365 div, t_sr_release);
366 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
367
368 if (hs_timings) {
369 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
370 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
371 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
372 } else {
373 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
374 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
375 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
376 }
377 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
378
379 return 0;
380}
381
382static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
383{
384 /* always set Fast Speed timings */
385 int ret = exynos5_i2c_set_timing(i2c, false);
386
387 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
388 return ret;
389
390 return exynos5_i2c_set_timing(i2c, true);
391}
392
393/*
394 * exynos5_i2c_init: configures the controller for I2C functionality
395 * Programs I2C controller for Master mode operation
396 */
397static void exynos5_i2c_init(struct exynos5_i2c *i2c)
398{
399 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
400 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
401
402 /* Clear to disable Timeout */
403 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
404 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
405
406 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
407 i2c->regs + HSI2C_CTL);
408 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
409
410 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
411 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
412 i2c->regs + HSI2C_ADDR);
413 i2c_conf |= HSI2C_HS_MODE;
414 }
415
416 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
417}
418
419static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
420{
421 u32 i2c_ctl;
422
423 /* Set and clear the bit for reset */
424 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
425 i2c_ctl |= HSI2C_SW_RST;
426 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
427
428 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
429 i2c_ctl &= ~HSI2C_SW_RST;
430 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
431
432 /* We don't expect calculations to fail during the run */
433 exynos5_hsi2c_clock_setup(i2c);
434 /* Initialize the configure registers */
435 exynos5_i2c_init(i2c);
436}
437
438/*
439 * exynos5_i2c_irq: top level IRQ servicing routine
440 *
441 * INT_STATUS registers gives the interrupt details. Further,
442 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
443 * state of the bus.
444 */
445static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
446{
447 struct exynos5_i2c *i2c = dev_id;
448 u32 fifo_level, int_status, fifo_status, trans_status;
449 unsigned char byte;
450 int len = 0;
451
452 i2c->state = -EINVAL;
453
454 spin_lock(&i2c->lock);
455
456 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
457 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
458
459 /* handle interrupt related to the transfer status */
460 switch (i2c->variant->hw) {
461 case I2C_TYPE_EXYNOSAUTOV9:
462 fallthrough;
463 case I2C_TYPE_EXYNOS7:
464 if (int_status & HSI2C_INT_TRANS_DONE) {
465 i2c->trans_done = 1;
466 i2c->state = 0;
467 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
468 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
469 i2c->state = -EAGAIN;
470 goto stop;
471 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
472 dev_dbg(i2c->dev, "No ACK from device\n");
473 i2c->state = -ENXIO;
474 goto stop;
475 } else if (int_status & HSI2C_INT_NO_DEV) {
476 dev_dbg(i2c->dev, "No device\n");
477 i2c->state = -ENXIO;
478 goto stop;
479 } else if (int_status & HSI2C_INT_TIMEOUT) {
480 dev_dbg(i2c->dev, "Accessing device timed out\n");
481 i2c->state = -ETIMEDOUT;
482 goto stop;
483 }
484
485 break;
486 case I2C_TYPE_EXYNOS5:
487 if (!(int_status & HSI2C_INT_I2C))
488 break;
489
490 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
491 if (trans_status & HSI2C_NO_DEV_ACK) {
492 dev_dbg(i2c->dev, "No ACK from device\n");
493 i2c->state = -ENXIO;
494 goto stop;
495 } else if (trans_status & HSI2C_NO_DEV) {
496 dev_dbg(i2c->dev, "No device\n");
497 i2c->state = -ENXIO;
498 goto stop;
499 } else if (trans_status & HSI2C_TRANS_ABORT) {
500 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
501 i2c->state = -EAGAIN;
502 goto stop;
503 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
504 dev_dbg(i2c->dev, "Accessing device timed out\n");
505 i2c->state = -ETIMEDOUT;
506 goto stop;
507 } else if (trans_status & HSI2C_TRANS_DONE) {
508 i2c->trans_done = 1;
509 i2c->state = 0;
510 }
511
512 break;
513 }
514
515 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
516 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
517 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
518 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
519 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
520
521 while (len > 0) {
522 byte = (unsigned char)
523 readl(i2c->regs + HSI2C_RX_DATA);
524 i2c->msg->buf[i2c->msg_ptr++] = byte;
525 len--;
526 }
527 i2c->state = 0;
528 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
529 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
530 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
531
532 len = i2c->variant->fifo_depth - fifo_level;
533 if (len > (i2c->msg->len - i2c->msg_ptr)) {
534 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
535
536 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
537 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
538 len = i2c->msg->len - i2c->msg_ptr;
539 }
540
541 while (len > 0) {
542 byte = i2c->msg->buf[i2c->msg_ptr++];
543 writel(byte, i2c->regs + HSI2C_TX_DATA);
544 len--;
545 }
546 i2c->state = 0;
547 }
548
549 stop:
550 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
551 (i2c->state < 0)) {
552 writel(0, i2c->regs + HSI2C_INT_ENABLE);
553 exynos5_i2c_clr_pend_irq(i2c);
554 complete(&i2c->msg_complete);
555 }
556
557 spin_unlock(&i2c->lock);
558
559 return IRQ_HANDLED;
560}
561
562/*
563 * exynos5_i2c_wait_bus_idle
564 *
565 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
566 * cleared.
567 *
568 * Returns -EBUSY if the bus cannot be bought to idle
569 */
570static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
571{
572 unsigned long stop_time;
573 u32 trans_status;
574
575 /* wait for 100 milli seconds for the bus to be idle */
576 stop_time = jiffies + msecs_to_jiffies(100) + 1;
577 do {
578 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
579 if (!(trans_status & HSI2C_MASTER_BUSY))
580 return 0;
581
582 usleep_range(50, 200);
583 } while (time_before(jiffies, stop_time));
584
585 return -EBUSY;
586}
587
588static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
589{
590 u32 val;
591
592 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
593 writel(val, i2c->regs + HSI2C_CTL);
594 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
595 writel(val, i2c->regs + HSI2C_CONF);
596
597 /*
598 * Specification says master should send nine clock pulses. It can be
599 * emulated by sending manual read command (nine pulses for read eight
600 * bits + one pulse for NACK).
601 */
602 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
603 exynos5_i2c_wait_bus_idle(i2c);
604 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
605 exynos5_i2c_wait_bus_idle(i2c);
606
607 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
608 writel(val, i2c->regs + HSI2C_CTL);
609 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
610 writel(val, i2c->regs + HSI2C_CONF);
611}
612
613static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
614{
615 unsigned long timeout;
616
617 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
618 return;
619
620 /*
621 * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants)
622 * before transaction indicates that bus is stuck (SDA is low).
623 * In such case bus recovery can be performed.
624 */
625 timeout = jiffies + msecs_to_jiffies(100);
626 for (;;) {
627 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
628
629 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
630 return;
631
632 if (time_is_before_jiffies(timeout))
633 return;
634
635 exynos5_i2c_bus_recover(i2c);
636 }
637}
638
639/*
640 * exynos5_i2c_message_start: Configures the bus and starts the xfer
641 * i2c: struct exynos5_i2c pointer for the current bus
642 * stop: Enables stop after transfer if set. Set for last transfer of
643 * in the list of messages.
644 *
645 * Configures the bus for read/write function
646 * Sets chip address to talk to, message length to be sent.
647 * Enables appropriate interrupts and sends start xfer command.
648 */
649static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
650{
651 u32 i2c_ctl;
652 u32 int_en = 0;
653 u32 i2c_auto_conf = 0;
654 u32 i2c_addr = 0;
655 u32 fifo_ctl;
656 unsigned long flags;
657 unsigned short trig_lvl;
658
659 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
660 int_en |= HSI2C_INT_I2C;
661 else
662 int_en |= HSI2C_INT_I2C_TRANS;
663
664 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
665 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
666 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
667
668 if (i2c->msg->flags & I2C_M_RD) {
669 i2c_ctl |= HSI2C_RXCHON;
670
671 i2c_auto_conf |= HSI2C_READ_WRITE;
672
673 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
674 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
675 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
676
677 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
678 HSI2C_INT_TRAILING_EN);
679 } else {
680 i2c_ctl |= HSI2C_TXCHON;
681
682 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
683 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
684 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
685
686 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
687 }
688
689 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
690
691 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
692 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
693
694 writel(i2c_addr, i2c->regs + HSI2C_ADDR);
695
696 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
697 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
698
699 exynos5_i2c_bus_check(i2c);
700
701 /*
702 * Enable interrupts before starting the transfer so that we don't
703 * miss any INT_I2C interrupts.
704 */
705 spin_lock_irqsave(&i2c->lock, flags);
706 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
707
708 if (stop == 1)
709 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
710 i2c_auto_conf |= i2c->msg->len;
711 i2c_auto_conf |= HSI2C_MASTER_RUN;
712 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
713 spin_unlock_irqrestore(&i2c->lock, flags);
714}
715
716static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
717 struct i2c_msg *msgs, int stop)
718{
719 unsigned long timeout;
720 int ret;
721
722 i2c->msg = msgs;
723 i2c->msg_ptr = 0;
724 i2c->trans_done = 0;
725
726 reinit_completion(&i2c->msg_complete);
727
728 exynos5_i2c_message_start(i2c, stop);
729
730 timeout = wait_for_completion_timeout(&i2c->msg_complete,
731 EXYNOS5_I2C_TIMEOUT);
732 if (timeout == 0)
733 ret = -ETIMEDOUT;
734 else
735 ret = i2c->state;
736
737 /*
738 * If this is the last message to be transfered (stop == 1)
739 * Then check if the bus can be brought back to idle.
740 */
741 if (ret == 0 && stop)
742 ret = exynos5_i2c_wait_bus_idle(i2c);
743
744 if (ret < 0) {
745 exynos5_i2c_reset(i2c);
746 if (ret == -ETIMEDOUT)
747 dev_warn(i2c->dev, "%s timeout\n",
748 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
749 }
750
751 /* Return the state as in interrupt routine */
752 return ret;
753}
754
755static int exynos5_i2c_xfer(struct i2c_adapter *adap,
756 struct i2c_msg *msgs, int num)
757{
758 struct exynos5_i2c *i2c = adap->algo_data;
759 int i, ret;
760
761 ret = clk_enable(i2c->pclk);
762 if (ret)
763 return ret;
764
765 ret = clk_enable(i2c->clk);
766 if (ret)
767 goto err_pclk;
768
769 for (i = 0; i < num; ++i) {
770 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
771 if (ret)
772 break;
773 }
774
775 clk_disable(i2c->clk);
776err_pclk:
777 clk_disable(i2c->pclk);
778
779 return ret ?: num;
780}
781
782static u32 exynos5_i2c_func(struct i2c_adapter *adap)
783{
784 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
785}
786
787static const struct i2c_algorithm exynos5_i2c_algorithm = {
788 .master_xfer = exynos5_i2c_xfer,
789 .functionality = exynos5_i2c_func,
790};
791
792static int exynos5_i2c_probe(struct platform_device *pdev)
793{
794 struct device_node *np = pdev->dev.of_node;
795 struct exynos5_i2c *i2c;
796 int ret;
797
798 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
799 if (!i2c)
800 return -ENOMEM;
801
802 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
803 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
804
805 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
806 i2c->adap.owner = THIS_MODULE;
807 i2c->adap.algo = &exynos5_i2c_algorithm;
808 i2c->adap.retries = 3;
809
810 i2c->dev = &pdev->dev;
811 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
812 if (IS_ERR(i2c->clk)) {
813 dev_err(&pdev->dev, "cannot get clock\n");
814 return -ENOENT;
815 }
816
817 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");
818 if (IS_ERR(i2c->pclk)) {
819 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
820 "cannot get pclk");
821 }
822
823 ret = clk_prepare_enable(i2c->pclk);
824 if (ret)
825 return ret;
826
827 ret = clk_prepare_enable(i2c->clk);
828 if (ret)
829 goto err_pclk;
830
831 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
832 if (IS_ERR(i2c->regs)) {
833 ret = PTR_ERR(i2c->regs);
834 goto err_clk;
835 }
836
837 i2c->adap.dev.of_node = np;
838 i2c->adap.algo_data = i2c;
839 i2c->adap.dev.parent = &pdev->dev;
840
841 /* Clear pending interrupts from u-boot or misc causes */
842 exynos5_i2c_clr_pend_irq(i2c);
843
844 spin_lock_init(&i2c->lock);
845 init_completion(&i2c->msg_complete);
846
847 i2c->irq = ret = platform_get_irq(pdev, 0);
848 if (ret < 0)
849 goto err_clk;
850
851 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
852 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
853 if (ret != 0) {
854 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
855 goto err_clk;
856 }
857
858 i2c->variant = of_device_get_match_data(&pdev->dev);
859
860 ret = exynos5_hsi2c_clock_setup(i2c);
861 if (ret)
862 goto err_clk;
863
864 exynos5_i2c_reset(i2c);
865
866 ret = i2c_add_adapter(&i2c->adap);
867 if (ret < 0)
868 goto err_clk;
869
870 platform_set_drvdata(pdev, i2c);
871
872 clk_disable(i2c->clk);
873 clk_disable(i2c->pclk);
874
875 return 0;
876
877 err_clk:
878 clk_disable_unprepare(i2c->clk);
879
880 err_pclk:
881 clk_disable_unprepare(i2c->pclk);
882 return ret;
883}
884
885static int exynos5_i2c_remove(struct platform_device *pdev)
886{
887 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
888
889 i2c_del_adapter(&i2c->adap);
890
891 clk_unprepare(i2c->clk);
892 clk_unprepare(i2c->pclk);
893
894 return 0;
895}
896
897#ifdef CONFIG_PM_SLEEP
898static int exynos5_i2c_suspend_noirq(struct device *dev)
899{
900 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
901
902 i2c_mark_adapter_suspended(&i2c->adap);
903 clk_unprepare(i2c->clk);
904 clk_unprepare(i2c->pclk);
905
906 return 0;
907}
908
909static int exynos5_i2c_resume_noirq(struct device *dev)
910{
911 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
912 int ret = 0;
913
914 ret = clk_prepare_enable(i2c->pclk);
915 if (ret)
916 return ret;
917
918 ret = clk_prepare_enable(i2c->clk);
919 if (ret)
920 goto err_pclk;
921
922 ret = exynos5_hsi2c_clock_setup(i2c);
923 if (ret)
924 goto err_clk;
925
926 exynos5_i2c_init(i2c);
927 clk_disable(i2c->clk);
928 clk_disable(i2c->pclk);
929 i2c_mark_adapter_resumed(&i2c->adap);
930
931 return 0;
932
933err_clk:
934 clk_disable_unprepare(i2c->clk);
935err_pclk:
936 clk_disable_unprepare(i2c->pclk);
937 return ret;
938}
939#endif
940
941static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
942 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
943 exynos5_i2c_resume_noirq)
944};
945
946static struct platform_driver exynos5_i2c_driver = {
947 .probe = exynos5_i2c_probe,
948 .remove = exynos5_i2c_remove,
949 .driver = {
950 .name = "exynos5-hsi2c",
951 .pm = &exynos5_i2c_dev_pm_ops,
952 .of_match_table = exynos5_i2c_match,
953 },
954};
955
956module_platform_driver(exynos5_i2c_driver);
957
958MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
959MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
960MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
961MODULE_LICENSE("GPL v2");