1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 *  Copyright (C) 2011 - 2014 Xilinx
 4 *  Copyright (C) 2012 National Instruments Corp.
 
 
 
 
 
 
 
 
 
 
 5 */
 6/dts-v1/;
 7#include "zynq-7000.dtsi"
 8
 9/ {
10	model = "Avnet ZedBoard board";
11	compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
12
13	aliases {
14		ethernet0 = &gem0;
15		serial0 = &uart1;
16		mmc0 = &sdhci0;
17	};
18
19	memory@0 {
20		device_type = "memory";
21		reg = <0x0 0x20000000>;
22	};
23
24	chosen {
25		bootargs = "";
26		stdout-path = "serial0:115200n8";
27	};
28
29	usb_phy0: phy0 {
30		compatible = "usb-nop-xceiv";
31		#phy-cells = <0>;
32	};
33};
34
35&clkc {
36	ps-clk-frequency = <33333333>;
37};
38
39&gem0 {
40	status = "okay";
41	phy-mode = "rgmii-id";
42	phy-handle = <&ethernet_phy>;
43
44	ethernet_phy: ethernet-phy@0 {
45		reg = <0>;
46		device_type = "ethernet-phy";
47	};
48};
49
50&sdhci0 {
51	status = "okay";
52};
53
54&uart1 {
55	status = "okay";
56};
57
58&usb0 {
59	status = "okay";
60	dr_mode = "host";
61	usb-phy = <&usb_phy0>;
62};

 
 1/*
 2 *  Copyright (C) 2011 Xilinx
 3 *  Copyright (C) 2012 National Instruments Corp.
 4 *  Copyright (C) 2013 Xilinx
 5 *
 6 * This software is licensed under the terms of the GNU General Public
 7 * License version 2, as published by the Free Software Foundation, and
 8 * may be copied, distributed, and modified under those terms.
 9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15/dts-v1/;
16/include/ "zynq-7000.dtsi"
17
18/ {
19	model = "Zynq Zed Development Board";
20	compatible = "xlnx,zynq-7000";
21
22	memory {
 
 
 
 
 
 
23		device_type = "memory";
24		reg = <0 0x20000000>;
25	};
26
27	chosen {
28		bootargs = "console=ttyPS0,115200 earlyprintk";
 
29	};
30
 
 
 
 
 
 
 
 
31};
32
33&gem0 {
34	status = "okay";
35	phy-mode = "rgmii";
 
 
 
 
 
 
36};
37
38&sdhci0 {
39	status = "okay";
40};
41
42&uart1 {
43	status = "okay";
 
 
 
 
 
 
44};