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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale eSPI controller driver.
4 *
5 * Copyright 2010 Freescale Semiconductor, Inc.
6 */
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/fsl_devices.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/mm.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/pm_runtime.h>
20#include <sysdev/fsl_soc.h>
21
22/* eSPI Controller registers */
23#define ESPI_SPMODE 0x00 /* eSPI mode register */
24#define ESPI_SPIE 0x04 /* eSPI event register */
25#define ESPI_SPIM 0x08 /* eSPI mask register */
26#define ESPI_SPCOM 0x0c /* eSPI command register */
27#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
28#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
29#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
30
31#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
32
33/* eSPI Controller mode register definitions */
34#define SPMODE_ENABLE BIT(31)
35#define SPMODE_LOOP BIT(30)
36#define SPMODE_TXTHR(x) ((x) << 8)
37#define SPMODE_RXTHR(x) ((x) << 0)
38
39/* eSPI Controller CS mode register definitions */
40#define CSMODE_CI_INACTIVEHIGH BIT(31)
41#define CSMODE_CP_BEGIN_EDGECLK BIT(30)
42#define CSMODE_REV BIT(29)
43#define CSMODE_DIV16 BIT(28)
44#define CSMODE_PM(x) ((x) << 24)
45#define CSMODE_POL_1 BIT(20)
46#define CSMODE_LEN(x) ((x) << 16)
47#define CSMODE_BEF(x) ((x) << 12)
48#define CSMODE_AFT(x) ((x) << 8)
49#define CSMODE_CG(x) ((x) << 3)
50
51#define FSL_ESPI_FIFO_SIZE 32
52#define FSL_ESPI_RXTHR 15
53
54/* Default mode/csmode for eSPI controller */
55#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
56#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
57 | CSMODE_AFT(0) | CSMODE_CG(1))
58
59/* SPIE register values */
60#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
61#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
62#define SPIE_TXE BIT(15) /* TX FIFO empty */
63#define SPIE_DON BIT(14) /* TX done */
64#define SPIE_RXT BIT(13) /* RX FIFO threshold */
65#define SPIE_RXF BIT(12) /* RX FIFO full */
66#define SPIE_TXT BIT(11) /* TX FIFO threshold*/
67#define SPIE_RNE BIT(9) /* RX FIFO not empty */
68#define SPIE_TNF BIT(8) /* TX FIFO not full */
69
70/* SPIM register values */
71#define SPIM_TXE BIT(15) /* TX FIFO empty */
72#define SPIM_DON BIT(14) /* TX done */
73#define SPIM_RXT BIT(13) /* RX FIFO threshold */
74#define SPIM_RXF BIT(12) /* RX FIFO full */
75#define SPIM_TXT BIT(11) /* TX FIFO threshold*/
76#define SPIM_RNE BIT(9) /* RX FIFO not empty */
77#define SPIM_TNF BIT(8) /* TX FIFO not full */
78
79/* SPCOM register values */
80#define SPCOM_CS(x) ((x) << 30)
81#define SPCOM_DO BIT(28) /* Dual output */
82#define SPCOM_TO BIT(27) /* TX only */
83#define SPCOM_RXSKIP(x) ((x) << 16)
84#define SPCOM_TRANLEN(x) ((x) << 0)
85
86#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
87
88#define AUTOSUSPEND_TIMEOUT 2000
89
90struct fsl_espi {
91 struct device *dev;
92 void __iomem *reg_base;
93
94 struct list_head *m_transfers;
95 struct spi_transfer *tx_t;
96 unsigned int tx_pos;
97 bool tx_done;
98 struct spi_transfer *rx_t;
99 unsigned int rx_pos;
100 bool rx_done;
101
102 bool swab;
103 unsigned int rxskip;
104
105 spinlock_t lock;
106
107 u32 spibrg; /* SPIBRG input clock */
108
109 struct completion done;
110};
111
112struct fsl_espi_cs {
113 u32 hw_mode;
114};
115
116static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
117{
118 return ioread32be(espi->reg_base + offset);
119}
120
121static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
122{
123 return ioread16be(espi->reg_base + offset);
124}
125
126static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
127{
128 return ioread8(espi->reg_base + offset);
129}
130
131static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
132 u32 val)
133{
134 iowrite32be(val, espi->reg_base + offset);
135}
136
137static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
138 u16 val)
139{
140 iowrite16be(val, espi->reg_base + offset);
141}
142
143static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
144 u8 val)
145{
146 iowrite8(val, espi->reg_base + offset);
147}
148
149static int fsl_espi_check_message(struct spi_message *m)
150{
151 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
152 struct spi_transfer *t, *first;
153
154 if (m->frame_length > SPCOM_TRANLEN_MAX) {
155 dev_err(espi->dev, "message too long, size is %u bytes\n",
156 m->frame_length);
157 return -EMSGSIZE;
158 }
159
160 first = list_first_entry(&m->transfers, struct spi_transfer,
161 transfer_list);
162
163 list_for_each_entry(t, &m->transfers, transfer_list) {
164 if (first->bits_per_word != t->bits_per_word ||
165 first->speed_hz != t->speed_hz) {
166 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
167 return -EINVAL;
168 }
169 }
170
171 /* ESPI supports MSB-first transfers for word size 8 / 16 only */
172 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
173 first->bits_per_word != 16) {
174 dev_err(espi->dev,
175 "MSB-first transfer not supported for wordsize %u\n",
176 first->bits_per_word);
177 return -EINVAL;
178 }
179
180 return 0;
181}
182
183static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
184{
185 struct spi_transfer *t;
186 unsigned int i = 0, rxskip = 0;
187
188 /*
189 * prerequisites for ESPI rxskip mode:
190 * - message has two transfers
191 * - first transfer is a write and second is a read
192 *
193 * In addition the current low-level transfer mechanism requires
194 * that the rxskip bytes fit into the TX FIFO. Else the transfer
195 * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
196 * the TX FIFO isn't re-filled.
197 */
198 list_for_each_entry(t, &m->transfers, transfer_list) {
199 if (i == 0) {
200 if (!t->tx_buf || t->rx_buf ||
201 t->len > FSL_ESPI_FIFO_SIZE)
202 return 0;
203 rxskip = t->len;
204 } else if (i == 1) {
205 if (t->tx_buf || !t->rx_buf)
206 return 0;
207 }
208 i++;
209 }
210
211 return i == 2 ? rxskip : 0;
212}
213
214static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
215{
216 u32 tx_fifo_avail;
217 unsigned int tx_left;
218 const void *tx_buf;
219
220 /* if events is zero transfer has not started and tx fifo is empty */
221 tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
222start:
223 tx_left = espi->tx_t->len - espi->tx_pos;
224 tx_buf = espi->tx_t->tx_buf;
225 while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
226 if (tx_left >= 4) {
227 if (!tx_buf)
228 fsl_espi_write_reg(espi, ESPI_SPITF, 0);
229 else if (espi->swab)
230 fsl_espi_write_reg(espi, ESPI_SPITF,
231 swahb32p(tx_buf + espi->tx_pos));
232 else
233 fsl_espi_write_reg(espi, ESPI_SPITF,
234 *(u32 *)(tx_buf + espi->tx_pos));
235 espi->tx_pos += 4;
236 tx_left -= 4;
237 tx_fifo_avail -= 4;
238 } else if (tx_left >= 2 && tx_buf && espi->swab) {
239 fsl_espi_write_reg16(espi, ESPI_SPITF,
240 swab16p(tx_buf + espi->tx_pos));
241 espi->tx_pos += 2;
242 tx_left -= 2;
243 tx_fifo_avail -= 2;
244 } else {
245 if (!tx_buf)
246 fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
247 else
248 fsl_espi_write_reg8(espi, ESPI_SPITF,
249 *(u8 *)(tx_buf + espi->tx_pos));
250 espi->tx_pos += 1;
251 tx_left -= 1;
252 tx_fifo_avail -= 1;
253 }
254 }
255
256 if (!tx_left) {
257 /* Last transfer finished, in rxskip mode only one is needed */
258 if (list_is_last(&espi->tx_t->transfer_list,
259 espi->m_transfers) || espi->rxskip) {
260 espi->tx_done = true;
261 return;
262 }
263 espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
264 espi->tx_pos = 0;
265 /* continue with next transfer if tx fifo is not full */
266 if (tx_fifo_avail)
267 goto start;
268 }
269}
270
271static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
272{
273 u32 rx_fifo_avail = SPIE_RXCNT(events);
274 unsigned int rx_left;
275 void *rx_buf;
276
277start:
278 rx_left = espi->rx_t->len - espi->rx_pos;
279 rx_buf = espi->rx_t->rx_buf;
280 while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
281 if (rx_left >= 4) {
282 u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
283
284 if (rx_buf && espi->swab)
285 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
286 else if (rx_buf)
287 *(u32 *)(rx_buf + espi->rx_pos) = val;
288 espi->rx_pos += 4;
289 rx_left -= 4;
290 rx_fifo_avail -= 4;
291 } else if (rx_left >= 2 && rx_buf && espi->swab) {
292 u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
293
294 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
295 espi->rx_pos += 2;
296 rx_left -= 2;
297 rx_fifo_avail -= 2;
298 } else {
299 u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
300
301 if (rx_buf)
302 *(u8 *)(rx_buf + espi->rx_pos) = val;
303 espi->rx_pos += 1;
304 rx_left -= 1;
305 rx_fifo_avail -= 1;
306 }
307 }
308
309 if (!rx_left) {
310 if (list_is_last(&espi->rx_t->transfer_list,
311 espi->m_transfers)) {
312 espi->rx_done = true;
313 return;
314 }
315 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
316 espi->rx_pos = 0;
317 /* continue with next transfer if rx fifo is not empty */
318 if (rx_fifo_avail)
319 goto start;
320 }
321}
322
323static void fsl_espi_setup_transfer(struct spi_device *spi,
324 struct spi_transfer *t)
325{
326 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
327 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
328 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
329 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
330 u32 hw_mode_old = cs->hw_mode;
331
332 /* mask out bits we are going to set */
333 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
334
335 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
336
337 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
338
339 if (pm > 15) {
340 cs->hw_mode |= CSMODE_DIV16;
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
342 }
343
344 cs->hw_mode |= CSMODE_PM(pm);
345
346 /* don't write the mode register if the mode doesn't change */
347 if (cs->hw_mode != hw_mode_old)
348 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
349 cs->hw_mode);
350}
351
352static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
353{
354 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
355 unsigned int rx_len = t->len;
356 u32 mask, spcom;
357 int ret;
358
359 reinit_completion(&espi->done);
360
361 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
362 spcom = SPCOM_CS(spi->chip_select);
363 spcom |= SPCOM_TRANLEN(t->len - 1);
364
365 /* configure RXSKIP mode */
366 if (espi->rxskip) {
367 spcom |= SPCOM_RXSKIP(espi->rxskip);
368 rx_len = t->len - espi->rxskip;
369 if (t->rx_nbits == SPI_NBITS_DUAL)
370 spcom |= SPCOM_DO;
371 }
372
373 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
374
375 /* enable interrupts */
376 mask = SPIM_DON;
377 if (rx_len > FSL_ESPI_FIFO_SIZE)
378 mask |= SPIM_RXT;
379 fsl_espi_write_reg(espi, ESPI_SPIM, mask);
380
381 /* Prevent filling the fifo from getting interrupted */
382 spin_lock_irq(&espi->lock);
383 fsl_espi_fill_tx_fifo(espi, 0);
384 spin_unlock_irq(&espi->lock);
385
386 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
387 ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
388 if (ret == 0)
389 dev_err(espi->dev, "Transfer timed out!\n");
390
391 /* disable rx ints */
392 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
393
394 return ret == 0 ? -ETIMEDOUT : 0;
395}
396
397static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
398{
399 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
400 struct spi_device *spi = m->spi;
401 int ret;
402
403 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
404 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
405
406 espi->m_transfers = &m->transfers;
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
408 transfer_list);
409 espi->tx_pos = 0;
410 espi->tx_done = false;
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
412 transfer_list);
413 espi->rx_pos = 0;
414 espi->rx_done = false;
415
416 espi->rxskip = fsl_espi_check_rxskip_mode(m);
417 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
418 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
419 return -EINVAL;
420 }
421
422 /* In RXSKIP mode skip first transfer for reads */
423 if (espi->rxskip)
424 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
425
426 fsl_espi_setup_transfer(spi, trans);
427
428 ret = fsl_espi_bufs(spi, trans);
429
430 spi_transfer_delay_exec(trans);
431
432 return ret;
433}
434
435static int fsl_espi_do_one_msg(struct spi_master *master,
436 struct spi_message *m)
437{
438 unsigned int rx_nbits = 0, delay_nsecs = 0;
439 struct spi_transfer *t, trans = {};
440 int ret;
441
442 ret = fsl_espi_check_message(m);
443 if (ret)
444 goto out;
445
446 list_for_each_entry(t, &m->transfers, transfer_list) {
447 unsigned int delay = spi_delay_to_ns(&t->delay, t);
448
449 if (delay > delay_nsecs)
450 delay_nsecs = delay;
451 if (t->rx_nbits > rx_nbits)
452 rx_nbits = t->rx_nbits;
453 }
454
455 t = list_first_entry(&m->transfers, struct spi_transfer,
456 transfer_list);
457
458 trans.len = m->frame_length;
459 trans.speed_hz = t->speed_hz;
460 trans.bits_per_word = t->bits_per_word;
461 trans.delay.value = delay_nsecs;
462 trans.delay.unit = SPI_DELAY_UNIT_NSECS;
463 trans.rx_nbits = rx_nbits;
464
465 if (trans.len)
466 ret = fsl_espi_trans(m, &trans);
467
468 m->actual_length = ret ? 0 : trans.len;
469out:
470 if (m->status == -EINPROGRESS)
471 m->status = ret;
472
473 spi_finalize_current_message(master);
474
475 return ret;
476}
477
478static int fsl_espi_setup(struct spi_device *spi)
479{
480 struct fsl_espi *espi;
481 u32 loop_mode;
482 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
483
484 if (!cs) {
485 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
486 if (!cs)
487 return -ENOMEM;
488 spi_set_ctldata(spi, cs);
489 }
490
491 espi = spi_master_get_devdata(spi->master);
492
493 pm_runtime_get_sync(espi->dev);
494
495 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
496 /* mask out bits we are going to set */
497 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
498 | CSMODE_REV);
499
500 if (spi->mode & SPI_CPHA)
501 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
502 if (spi->mode & SPI_CPOL)
503 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
504 if (!(spi->mode & SPI_LSB_FIRST))
505 cs->hw_mode |= CSMODE_REV;
506
507 /* Handle the loop mode */
508 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
509 loop_mode &= ~SPMODE_LOOP;
510 if (spi->mode & SPI_LOOP)
511 loop_mode |= SPMODE_LOOP;
512 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
513
514 fsl_espi_setup_transfer(spi, NULL);
515
516 pm_runtime_mark_last_busy(espi->dev);
517 pm_runtime_put_autosuspend(espi->dev);
518
519 return 0;
520}
521
522static void fsl_espi_cleanup(struct spi_device *spi)
523{
524 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
525
526 kfree(cs);
527 spi_set_ctldata(spi, NULL);
528}
529
530static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
531{
532 if (!espi->rx_done)
533 fsl_espi_read_rx_fifo(espi, events);
534
535 if (!espi->tx_done)
536 fsl_espi_fill_tx_fifo(espi, events);
537
538 if (!espi->tx_done || !espi->rx_done)
539 return;
540
541 /* we're done, but check for errors before returning */
542 events = fsl_espi_read_reg(espi, ESPI_SPIE);
543
544 if (!(events & SPIE_DON))
545 dev_err(espi->dev,
546 "Transfer done but SPIE_DON isn't set!\n");
547
548 if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
549 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
550 dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
551 SPIE_RXCNT(events), SPIE_TXCNT(events));
552 }
553
554 complete(&espi->done);
555}
556
557static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
558{
559 struct fsl_espi *espi = context_data;
560 u32 events, mask;
561
562 spin_lock(&espi->lock);
563
564 /* Get interrupt events(tx/rx) */
565 events = fsl_espi_read_reg(espi, ESPI_SPIE);
566 mask = fsl_espi_read_reg(espi, ESPI_SPIM);
567 if (!(events & mask)) {
568 spin_unlock(&espi->lock);
569 return IRQ_NONE;
570 }
571
572 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
573
574 fsl_espi_cpu_irq(espi, events);
575
576 /* Clear the events */
577 fsl_espi_write_reg(espi, ESPI_SPIE, events);
578
579 spin_unlock(&espi->lock);
580
581 return IRQ_HANDLED;
582}
583
584#ifdef CONFIG_PM
585static int fsl_espi_runtime_suspend(struct device *dev)
586{
587 struct spi_master *master = dev_get_drvdata(dev);
588 struct fsl_espi *espi = spi_master_get_devdata(master);
589 u32 regval;
590
591 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
592 regval &= ~SPMODE_ENABLE;
593 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
594
595 return 0;
596}
597
598static int fsl_espi_runtime_resume(struct device *dev)
599{
600 struct spi_master *master = dev_get_drvdata(dev);
601 struct fsl_espi *espi = spi_master_get_devdata(master);
602 u32 regval;
603
604 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
605 regval |= SPMODE_ENABLE;
606 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
607
608 return 0;
609}
610#endif
611
612static size_t fsl_espi_max_message_size(struct spi_device *spi)
613{
614 return SPCOM_TRANLEN_MAX;
615}
616
617static void fsl_espi_init_regs(struct device *dev, bool initial)
618{
619 struct spi_master *master = dev_get_drvdata(dev);
620 struct fsl_espi *espi = spi_master_get_devdata(master);
621 struct device_node *nc;
622 u32 csmode, cs, prop;
623 int ret;
624
625 /* SPI controller initializations */
626 fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
627 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
628 fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
629 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
630
631 /* Init eSPI CS mode register */
632 for_each_available_child_of_node(master->dev.of_node, nc) {
633 /* get chip select */
634 ret = of_property_read_u32(nc, "reg", &cs);
635 if (ret || cs >= master->num_chipselect)
636 continue;
637
638 csmode = CSMODE_INIT_VAL;
639
640 /* check if CSBEF is set in device tree */
641 ret = of_property_read_u32(nc, "fsl,csbef", &prop);
642 if (!ret) {
643 csmode &= ~(CSMODE_BEF(0xf));
644 csmode |= CSMODE_BEF(prop);
645 }
646
647 /* check if CSAFT is set in device tree */
648 ret = of_property_read_u32(nc, "fsl,csaft", &prop);
649 if (!ret) {
650 csmode &= ~(CSMODE_AFT(0xf));
651 csmode |= CSMODE_AFT(prop);
652 }
653
654 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
655
656 if (initial)
657 dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
658 }
659
660 /* Enable SPI interface */
661 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
662}
663
664static int fsl_espi_probe(struct device *dev, struct resource *mem,
665 unsigned int irq, unsigned int num_cs)
666{
667 struct spi_master *master;
668 struct fsl_espi *espi;
669 int ret;
670
671 master = spi_alloc_master(dev, sizeof(struct fsl_espi));
672 if (!master)
673 return -ENOMEM;
674
675 dev_set_drvdata(dev, master);
676
677 master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
678 SPI_LSB_FIRST | SPI_LOOP;
679 master->dev.of_node = dev->of_node;
680 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
681 master->setup = fsl_espi_setup;
682 master->cleanup = fsl_espi_cleanup;
683 master->transfer_one_message = fsl_espi_do_one_msg;
684 master->auto_runtime_pm = true;
685 master->max_message_size = fsl_espi_max_message_size;
686 master->num_chipselect = num_cs;
687
688 espi = spi_master_get_devdata(master);
689 spin_lock_init(&espi->lock);
690
691 espi->dev = dev;
692 espi->spibrg = fsl_get_sys_freq();
693 if (espi->spibrg == -1) {
694 dev_err(dev, "Can't get sys frequency!\n");
695 ret = -EINVAL;
696 goto err_probe;
697 }
698 /* determined by clock divider fields DIV16/PM in register SPMODEx */
699 master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
700 master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
701
702 init_completion(&espi->done);
703
704 espi->reg_base = devm_ioremap_resource(dev, mem);
705 if (IS_ERR(espi->reg_base)) {
706 ret = PTR_ERR(espi->reg_base);
707 goto err_probe;
708 }
709
710 /* Register for SPI Interrupt */
711 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
712 if (ret)
713 goto err_probe;
714
715 fsl_espi_init_regs(dev, true);
716
717 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
718 pm_runtime_use_autosuspend(dev);
719 pm_runtime_set_active(dev);
720 pm_runtime_enable(dev);
721 pm_runtime_get_sync(dev);
722
723 ret = devm_spi_register_master(dev, master);
724 if (ret < 0)
725 goto err_pm;
726
727 dev_info(dev, "irq = %u\n", irq);
728
729 pm_runtime_mark_last_busy(dev);
730 pm_runtime_put_autosuspend(dev);
731
732 return 0;
733
734err_pm:
735 pm_runtime_put_noidle(dev);
736 pm_runtime_disable(dev);
737 pm_runtime_set_suspended(dev);
738err_probe:
739 spi_master_put(master);
740 return ret;
741}
742
743static int of_fsl_espi_get_chipselects(struct device *dev)
744{
745 struct device_node *np = dev->of_node;
746 u32 num_cs;
747 int ret;
748
749 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
750 if (ret) {
751 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
752 return 0;
753 }
754
755 return num_cs;
756}
757
758static int of_fsl_espi_probe(struct platform_device *ofdev)
759{
760 struct device *dev = &ofdev->dev;
761 struct device_node *np = ofdev->dev.of_node;
762 struct resource mem;
763 unsigned int irq, num_cs;
764 int ret;
765
766 if (of_property_read_bool(np, "mode")) {
767 dev_err(dev, "mode property is not supported on ESPI!\n");
768 return -EINVAL;
769 }
770
771 num_cs = of_fsl_espi_get_chipselects(dev);
772 if (!num_cs)
773 return -EINVAL;
774
775 ret = of_address_to_resource(np, 0, &mem);
776 if (ret)
777 return ret;
778
779 irq = irq_of_parse_and_map(np, 0);
780 if (!irq)
781 return -EINVAL;
782
783 return fsl_espi_probe(dev, &mem, irq, num_cs);
784}
785
786static int of_fsl_espi_remove(struct platform_device *dev)
787{
788 pm_runtime_disable(&dev->dev);
789
790 return 0;
791}
792
793#ifdef CONFIG_PM_SLEEP
794static int of_fsl_espi_suspend(struct device *dev)
795{
796 struct spi_master *master = dev_get_drvdata(dev);
797 int ret;
798
799 ret = spi_master_suspend(master);
800 if (ret)
801 return ret;
802
803 return pm_runtime_force_suspend(dev);
804}
805
806static int of_fsl_espi_resume(struct device *dev)
807{
808 struct spi_master *master = dev_get_drvdata(dev);
809 int ret;
810
811 fsl_espi_init_regs(dev, false);
812
813 ret = pm_runtime_force_resume(dev);
814 if (ret < 0)
815 return ret;
816
817 return spi_master_resume(master);
818}
819#endif /* CONFIG_PM_SLEEP */
820
821static const struct dev_pm_ops espi_pm = {
822 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
823 fsl_espi_runtime_resume, NULL)
824 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
825};
826
827static const struct of_device_id of_fsl_espi_match[] = {
828 { .compatible = "fsl,mpc8536-espi" },
829 {}
830};
831MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
832
833static struct platform_driver fsl_espi_driver = {
834 .driver = {
835 .name = "fsl_espi",
836 .of_match_table = of_fsl_espi_match,
837 .pm = &espi_pm,
838 },
839 .probe = of_fsl_espi_probe,
840 .remove = of_fsl_espi_remove,
841};
842module_platform_driver(fsl_espi_driver);
843
844MODULE_AUTHOR("Mingkai Hu");
845MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
846MODULE_LICENSE("GPL");
1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/interrupt.h>
23#include <linux/err.h>
24#include <sysdev/fsl_soc.h>
25
26#include "spi-fsl-lib.h"
27
28/* eSPI Controller registers */
29struct fsl_espi_reg {
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38};
39
40struct fsl_espi_transfer {
41 const void *tx_buf;
42 void *rx_buf;
43 unsigned len;
44 unsigned n_tx;
45 unsigned n_rx;
46 unsigned actual_length;
47 int status;
48};
49
50/* eSPI Controller mode register definitions */
51#define SPMODE_ENABLE (1 << 31)
52#define SPMODE_LOOP (1 << 30)
53#define SPMODE_TXTHR(x) ((x) << 8)
54#define SPMODE_RXTHR(x) ((x) << 0)
55
56/* eSPI Controller CS mode register definitions */
57#define CSMODE_CI_INACTIVEHIGH (1 << 31)
58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59#define CSMODE_REV (1 << 29)
60#define CSMODE_DIV16 (1 << 28)
61#define CSMODE_PM(x) ((x) << 24)
62#define CSMODE_POL_1 (1 << 20)
63#define CSMODE_LEN(x) ((x) << 16)
64#define CSMODE_BEF(x) ((x) << 12)
65#define CSMODE_AFT(x) ((x) << 8)
66#define CSMODE_CG(x) ((x) << 3)
67
68/* Default mode/csmode for eSPI controller */
69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
72
73/* SPIE register values */
74#define SPIE_NE 0x00000200 /* Not empty */
75#define SPIE_NF 0x00000100 /* Not full */
76
77/* SPIM register values */
78#define SPIM_NE 0x00000200 /* Not empty */
79#define SPIM_NF 0x00000100 /* Not full */
80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
82
83/* SPCOM register values */
84#define SPCOM_CS(x) ((x) << 30)
85#define SPCOM_TRANLEN(x) ((x) << 0)
86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87
88static void fsl_espi_change_mode(struct spi_device *spi)
89{
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = ®_base->mode;
95 u32 tmp;
96 unsigned long flags;
97
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
100
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
106
107 local_irq_restore(flags);
108}
109
110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
111{
112 u32 data;
113 u16 data_h;
114 u16 data_l;
115 const u32 *tx = mpc8xxx_spi->tx;
116
117 if (!tx)
118 return 0;
119
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
123 swab16s(&data_l);
124 swab16s(&data_h);
125 data = data_h | data_l;
126
127 mpc8xxx_spi->tx = tx;
128 return data;
129}
130
131static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
133{
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
136 u8 pm;
137 u32 hz = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139
140 if (t) {
141 bits_per_word = t->bits_per_word;
142 hz = t->speed_hz;
143 }
144
145 /* spi_transfer level calls that work per-word */
146 if (!bits_per_word)
147 bits_per_word = spi->bits_per_word;
148
149 if (!hz)
150 hz = spi->max_speed_hz;
151
152 cs->rx_shift = 0;
153 cs->tx_shift = 0;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
158 } else {
159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
162 }
163
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
168
169 bits_per_word = bits_per_word - 1;
170
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
173
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
175
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
179
180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
183 if (pm > 33)
184 pm = 33;
185 } else {
186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
187 }
188 if (pm)
189 pm--;
190 if (pm < 2)
191 pm = 2;
192
193 cs->hw_mode |= CSMODE_PM(pm);
194
195 fsl_espi_change_mode(spi);
196 return 0;
197}
198
199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
200 unsigned int len)
201{
202 u32 word;
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
204
205 mspi->count = len;
206
207 /* enable rx ints */
208 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
209
210 /* transmit word */
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(®_base->transmit, word);
213
214 return 0;
215}
216
217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218{
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
222 int ret;
223
224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
226
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
229
230 reinit_completion(&mpc8xxx_spi->done);
231
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
236 return -EINVAL;
237 }
238 mpc8xxx_spi_write_reg(®_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 if (ret)
243 return ret;
244
245 wait_for_completion(&mpc8xxx_spi->done);
246
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(®_base->mask, 0);
249
250 return mpc8xxx_spi->count;
251}
252
253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
254{
255 if (cmd) {
256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
259 }
260}
261
262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
263{
264 if (cmd)
265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
266
267 return 0;
268}
269
270static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
272{
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
278 int status = 0;
279
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
282
283 first = list_first_entry(&m->transfers, struct spi_transfer,
284 transfer_list);
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
289 dev_err(mspi->dev,
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
291 return;
292 }
293
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
297 }
298
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
303
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
306 status = -EINVAL;
307
308 status = fsl_espi_setup_transfer(spi, t);
309 if (status < 0)
310 break;
311 }
312
313 if (t->len)
314 status = fsl_espi_bufs(spi, t);
315
316 if (status) {
317 status = -EMSGSIZE;
318 break;
319 }
320
321 if (t->delay_usecs)
322 udelay(t->delay_usecs);
323 }
324
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
327}
328
329static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
331{
332 struct spi_transfer *t;
333 u8 *local_buf;
334 int i = 0;
335 struct fsl_espi_transfer *espi_trans = trans;
336
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
338 if (!local_buf) {
339 espi_trans->status = -ENOMEM;
340 return;
341 }
342
343 list_for_each_entry(t, &m->transfers, transfer_list) {
344 if (t->tx_buf) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
346 i += t->len;
347 }
348 }
349
350 espi_trans->tx_buf = local_buf;
351 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
352 fsl_espi_do_trans(m, espi_trans);
353
354 espi_trans->actual_length = espi_trans->len;
355 kfree(local_buf);
356}
357
358static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
360{
361 struct fsl_espi_transfer *espi_trans = trans;
362 unsigned int n_tx = espi_trans->n_tx;
363 unsigned int n_rx = espi_trans->n_rx;
364 struct spi_transfer *t;
365 u8 *local_buf;
366 u8 *rx_buf = rx_buff;
367 unsigned int trans_len;
368 unsigned int addr;
369 int i, pos, loop;
370
371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
372 if (!local_buf) {
373 espi_trans->status = -ENOMEM;
374 return;
375 }
376
377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
378 trans_len = n_rx - pos;
379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
380 trans_len = SPCOM_TRANLEN_MAX - n_tx;
381
382 i = 0;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
384 if (t->tx_buf) {
385 memcpy(local_buf + i, t->tx_buf, t->len);
386 i += t->len;
387 }
388 }
389
390 if (pos > 0) {
391 addr = fsl_espi_cmd2addr(local_buf);
392 addr += pos;
393 fsl_espi_addr2cmd(addr, local_buf);
394 }
395
396 espi_trans->n_tx = n_tx;
397 espi_trans->n_rx = trans_len;
398 espi_trans->len = trans_len + n_tx;
399 espi_trans->tx_buf = local_buf;
400 espi_trans->rx_buf = local_buf + n_tx;
401 fsl_espi_do_trans(m, espi_trans);
402
403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
404
405 if (loop > 0)
406 espi_trans->actual_length += espi_trans->len - n_tx;
407 else
408 espi_trans->actual_length += espi_trans->len;
409 }
410
411 kfree(local_buf);
412}
413
414static void fsl_espi_do_one_msg(struct spi_message *m)
415{
416 struct spi_transfer *t;
417 u8 *rx_buf = NULL;
418 unsigned int n_tx = 0;
419 unsigned int n_rx = 0;
420 struct fsl_espi_transfer espi_trans;
421
422 list_for_each_entry(t, &m->transfers, transfer_list) {
423 if (t->tx_buf)
424 n_tx += t->len;
425 if (t->rx_buf) {
426 n_rx += t->len;
427 rx_buf = t->rx_buf;
428 }
429 }
430
431 espi_trans.n_tx = n_tx;
432 espi_trans.n_rx = n_rx;
433 espi_trans.len = n_tx + n_rx;
434 espi_trans.actual_length = 0;
435 espi_trans.status = 0;
436
437 if (!rx_buf)
438 fsl_espi_cmd_trans(m, &espi_trans, NULL);
439 else
440 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
441
442 m->actual_length = espi_trans.actual_length;
443 m->status = espi_trans.status;
444 if (m->complete)
445 m->complete(m->context);
446}
447
448static int fsl_espi_setup(struct spi_device *spi)
449{
450 struct mpc8xxx_spi *mpc8xxx_spi;
451 struct fsl_espi_reg *reg_base;
452 int retval;
453 u32 hw_mode;
454 u32 loop_mode;
455 struct spi_mpc8xxx_cs *cs = spi->controller_state;
456
457 if (!spi->max_speed_hz)
458 return -EINVAL;
459
460 if (!cs) {
461 cs = kzalloc(sizeof *cs, GFP_KERNEL);
462 if (!cs)
463 return -ENOMEM;
464 spi->controller_state = cs;
465 }
466
467 mpc8xxx_spi = spi_master_get_devdata(spi->master);
468 reg_base = mpc8xxx_spi->reg_base;
469
470 hw_mode = cs->hw_mode; /* Save original settings */
471 cs->hw_mode = mpc8xxx_spi_read_reg(
472 ®_base->csmode[spi->chip_select]);
473 /* mask out bits we are going to set */
474 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
475 | CSMODE_REV);
476
477 if (spi->mode & SPI_CPHA)
478 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
479 if (spi->mode & SPI_CPOL)
480 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
481 if (!(spi->mode & SPI_LSB_FIRST))
482 cs->hw_mode |= CSMODE_REV;
483
484 /* Handle the loop mode */
485 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
486 loop_mode &= ~SPMODE_LOOP;
487 if (spi->mode & SPI_LOOP)
488 loop_mode |= SPMODE_LOOP;
489 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
490
491 retval = fsl_espi_setup_transfer(spi, NULL);
492 if (retval < 0) {
493 cs->hw_mode = hw_mode; /* Restore settings */
494 return retval;
495 }
496 return 0;
497}
498
499void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
500{
501 struct fsl_espi_reg *reg_base = mspi->reg_base;
502
503 /* We need handle RX first */
504 if (events & SPIE_NE) {
505 u32 rx_data, tmp;
506 u8 rx_data_8;
507
508 /* Spin until RX is done */
509 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
510 cpu_relax();
511 events = mpc8xxx_spi_read_reg(®_base->event);
512 }
513
514 if (mspi->len >= 4) {
515 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
516 } else {
517 tmp = mspi->len;
518 rx_data = 0;
519 while (tmp--) {
520 rx_data_8 = in_8((u8 *)®_base->receive);
521 rx_data |= (rx_data_8 << (tmp * 8));
522 }
523
524 rx_data <<= (4 - mspi->len) * 8;
525 }
526
527 mspi->len -= 4;
528
529 if (mspi->rx)
530 mspi->get_rx(rx_data, mspi);
531 }
532
533 if (!(events & SPIE_NF)) {
534 int ret;
535
536 /* spin until TX is done */
537 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
538 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
539 if (!ret) {
540 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
541 return;
542 }
543 }
544
545 /* Clear the events */
546 mpc8xxx_spi_write_reg(®_base->event, events);
547
548 mspi->count -= 1;
549 if (mspi->count) {
550 u32 word = mspi->get_tx(mspi);
551
552 mpc8xxx_spi_write_reg(®_base->transmit, word);
553 } else {
554 complete(&mspi->done);
555 }
556}
557
558static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
559{
560 struct mpc8xxx_spi *mspi = context_data;
561 struct fsl_espi_reg *reg_base = mspi->reg_base;
562 irqreturn_t ret = IRQ_NONE;
563 u32 events;
564
565 /* Get interrupt events(tx/rx) */
566 events = mpc8xxx_spi_read_reg(®_base->event);
567 if (events)
568 ret = IRQ_HANDLED;
569
570 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
571
572 fsl_espi_cpu_irq(mspi, events);
573
574 return ret;
575}
576
577static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
578{
579 iounmap(mspi->reg_base);
580}
581
582static struct spi_master * fsl_espi_probe(struct device *dev,
583 struct resource *mem, unsigned int irq)
584{
585 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
586 struct spi_master *master;
587 struct mpc8xxx_spi *mpc8xxx_spi;
588 struct fsl_espi_reg *reg_base;
589 u32 regval;
590 int i, ret = 0;
591
592 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
593 if (!master) {
594 ret = -ENOMEM;
595 goto err;
596 }
597
598 dev_set_drvdata(dev, master);
599
600 ret = mpc8xxx_spi_probe(dev, mem, irq);
601 if (ret)
602 goto err_probe;
603
604 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
605 master->setup = fsl_espi_setup;
606
607 mpc8xxx_spi = spi_master_get_devdata(master);
608 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
609 mpc8xxx_spi->spi_remove = fsl_espi_remove;
610
611 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
612 if (!mpc8xxx_spi->reg_base) {
613 ret = -ENOMEM;
614 goto err_probe;
615 }
616
617 reg_base = mpc8xxx_spi->reg_base;
618
619 /* Register for SPI Interrupt */
620 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
621 0, "fsl_espi", mpc8xxx_spi);
622 if (ret)
623 goto free_irq;
624
625 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
626 mpc8xxx_spi->rx_shift = 16;
627 mpc8xxx_spi->tx_shift = 24;
628 }
629
630 /* SPI controller initializations */
631 mpc8xxx_spi_write_reg(®_base->mode, 0);
632 mpc8xxx_spi_write_reg(®_base->mask, 0);
633 mpc8xxx_spi_write_reg(®_base->command, 0);
634 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
635
636 /* Init eSPI CS mode register */
637 for (i = 0; i < pdata->max_chipselect; i++)
638 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
639
640 /* Enable SPI interface */
641 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
642
643 mpc8xxx_spi_write_reg(®_base->mode, regval);
644
645 ret = spi_register_master(master);
646 if (ret < 0)
647 goto unreg_master;
648
649 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
650
651 return master;
652
653unreg_master:
654 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
655free_irq:
656 iounmap(mpc8xxx_spi->reg_base);
657err_probe:
658 spi_master_put(master);
659err:
660 return ERR_PTR(ret);
661}
662
663static int of_fsl_espi_get_chipselects(struct device *dev)
664{
665 struct device_node *np = dev->of_node;
666 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
667 const u32 *prop;
668 int len;
669
670 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
671 if (!prop || len < sizeof(*prop)) {
672 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
673 return -EINVAL;
674 }
675
676 pdata->max_chipselect = *prop;
677 pdata->cs_control = NULL;
678
679 return 0;
680}
681
682static int of_fsl_espi_probe(struct platform_device *ofdev)
683{
684 struct device *dev = &ofdev->dev;
685 struct device_node *np = ofdev->dev.of_node;
686 struct spi_master *master;
687 struct resource mem;
688 unsigned int irq;
689 int ret = -ENOMEM;
690
691 ret = of_mpc8xxx_spi_probe(ofdev);
692 if (ret)
693 return ret;
694
695 ret = of_fsl_espi_get_chipselects(dev);
696 if (ret)
697 goto err;
698
699 ret = of_address_to_resource(np, 0, &mem);
700 if (ret)
701 goto err;
702
703 irq = irq_of_parse_and_map(np, 0);
704 if (!irq) {
705 ret = -EINVAL;
706 goto err;
707 }
708
709 master = fsl_espi_probe(dev, &mem, irq);
710 if (IS_ERR(master)) {
711 ret = PTR_ERR(master);
712 goto err;
713 }
714
715 return 0;
716
717err:
718 return ret;
719}
720
721static int of_fsl_espi_remove(struct platform_device *dev)
722{
723 return mpc8xxx_spi_remove(&dev->dev);
724}
725
726#ifdef CONFIG_PM_SLEEP
727static int of_fsl_espi_suspend(struct device *dev)
728{
729 struct spi_master *master = dev_get_drvdata(dev);
730 struct mpc8xxx_spi *mpc8xxx_spi;
731 struct fsl_espi_reg *reg_base;
732 u32 regval;
733 int ret;
734
735 mpc8xxx_spi = spi_master_get_devdata(master);
736 reg_base = mpc8xxx_spi->reg_base;
737
738 ret = spi_master_suspend(master);
739 if (ret) {
740 dev_warn(dev, "cannot suspend master\n");
741 return ret;
742 }
743
744 regval = mpc8xxx_spi_read_reg(®_base->mode);
745 regval &= ~SPMODE_ENABLE;
746 mpc8xxx_spi_write_reg(®_base->mode, regval);
747
748 return 0;
749}
750
751static int of_fsl_espi_resume(struct device *dev)
752{
753 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
754 struct spi_master *master = dev_get_drvdata(dev);
755 struct mpc8xxx_spi *mpc8xxx_spi;
756 struct fsl_espi_reg *reg_base;
757 u32 regval;
758 int i;
759
760 mpc8xxx_spi = spi_master_get_devdata(master);
761 reg_base = mpc8xxx_spi->reg_base;
762
763 /* SPI controller initializations */
764 mpc8xxx_spi_write_reg(®_base->mode, 0);
765 mpc8xxx_spi_write_reg(®_base->mask, 0);
766 mpc8xxx_spi_write_reg(®_base->command, 0);
767 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
768
769 /* Init eSPI CS mode register */
770 for (i = 0; i < pdata->max_chipselect; i++)
771 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
772
773 /* Enable SPI interface */
774 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
775
776 mpc8xxx_spi_write_reg(®_base->mode, regval);
777
778 return spi_master_resume(master);
779}
780#endif /* CONFIG_PM_SLEEP */
781
782static const struct dev_pm_ops espi_pm = {
783 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
784};
785
786static const struct of_device_id of_fsl_espi_match[] = {
787 { .compatible = "fsl,mpc8536-espi" },
788 {}
789};
790MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
791
792static struct platform_driver fsl_espi_driver = {
793 .driver = {
794 .name = "fsl_espi",
795 .owner = THIS_MODULE,
796 .of_match_table = of_fsl_espi_match,
797 .pm = &espi_pm,
798 },
799 .probe = of_fsl_espi_probe,
800 .remove = of_fsl_espi_remove,
801};
802module_platform_driver(fsl_espi_driver);
803
804MODULE_AUTHOR("Mingkai Hu");
805MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
806MODULE_LICENSE("GPL");