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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SoC core Device Tree for the ARM Integrator platforms
4 */
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9
10 memory {
11 device_type = "memory";
12 reg = <0x0 0x0>;
13 };
14
15 core-module@10000000 {
16 compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 /* Use core module LED to indicate CPU load */
23 led@c,0 {
24 compatible = "register-bit-led";
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
28 label = "integrator:core_module";
29 linux,default-trigger = "cpu0";
30 default-state = "on";
31 };
32 };
33
34 ebi@12000000 {
35 compatible = "arm,external-bus-interface";
36 reg = <0x12000000 0x100>;
37 };
38
39 timer@13000000 {
40 reg = <0x13000000 0x100>;
41 interrupt-parent = <&pic>;
42 interrupts = <5>;
43 };
44
45 timer@13000100 {
46 reg = <0x13000100 0x100>;
47 interrupt-parent = <&pic>;
48 interrupts = <6>;
49 };
50
51 timer@13000200 {
52 reg = <0x13000200 0x100>;
53 interrupt-parent = <&pic>;
54 interrupts = <7>;
55 };
56
57 pic@14000000 {
58 compatible = "arm,versatile-fpga-irq";
59 #interrupt-cells = <1>;
60 interrupt-controller;
61 reg = <0x14000000 0x100>;
62 clear-mask = <0xffffffff>;
63 };
64
65 flash@24000000 {
66 compatible = "arm,versatile-flash", "cfi-flash";
67 reg = <0x24000000 0x02000000>;
68 bank-width = <4>;
69 partitions {
70 compatible = "arm,arm-firmware-suite";
71 };
72 };
73
74 fpga {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79 interrupt-parent = <&pic>;
80
81 /*
82 * These PrimeCells are in the same locations and using the
83 * same interrupts in all Integrators, however the silicon
84 * version deployed is different.
85 */
86 rtc@15000000 {
87 reg = <0x15000000 0x1000>;
88 interrupts = <8>;
89 };
90
91 uart@16000000 {
92 reg = <0x16000000 0x1000>;
93 interrupts = <1>;
94 };
95
96 uart@17000000 {
97 reg = <0x17000000 0x1000>;
98 interrupts = <2>;
99 };
100
101 kmi@18000000 {
102 reg = <0x18000000 0x1000>;
103 interrupts = <3>;
104 };
105
106 kmi@19000000 {
107 reg = <0x19000000 0x1000>;
108 interrupts = <4>;
109 };
110
111 syscon@1a000000 {
112 /* Debug registers mapped as syscon */
113 compatible = "syscon", "simple-mfd";
114 reg = <0x1a000000 0x10>;
115 ranges = <0x0 0x1a000000 0x10>;
116 #address-cells = <1>;
117 #size-cells = <1>;
118
119 led@4,0 {
120 compatible = "register-bit-led";
121 reg = <0x04 0x04>;
122 offset = <0x04>;
123 mask = <0x01>;
124 label = "integrator:green0";
125 linux,default-trigger = "heartbeat";
126 default-state = "on";
127 };
128 led@4,1 {
129 compatible = "register-bit-led";
130 reg = <0x04 0x04>;
131 offset = <0x04>;
132 mask = <0x02>;
133 label = "integrator:yellow";
134 default-state = "off";
135 };
136 led@4,2 {
137 compatible = "register-bit-led";
138 reg = <0x04 0x04>;
139 offset = <0x04>;
140 mask = <0x04>;
141 label = "integrator:red";
142 default-state = "off";
143 };
144 led@4,3 {
145 compatible = "register-bit-led";
146 reg = <0x04 0x04>;
147 offset = <0x04>;
148 mask = <0x08>;
149 label = "integrator:green1";
150 default-state = "off";
151 };
152 };
153 };
154};
1/*
2 * SoC core Device Tree for the ARM Integrator platforms
3 */
4
5/include/ "skeleton.dtsi"
6
7/ {
8 core-module@10000000 {
9 compatible = "arm,core-module-integrator";
10 reg = <0x10000000 0x200>;
11 };
12
13 ebi@12000000 {
14 compatible = "arm,external-bus-interface";
15 reg = <0x12000000 0x100>;
16 };
17
18 timer@13000000 {
19 reg = <0x13000000 0x100>;
20 interrupt-parent = <&pic>;
21 interrupts = <5>;
22 };
23
24 timer@13000100 {
25 reg = <0x13000100 0x100>;
26 interrupt-parent = <&pic>;
27 interrupts = <6>;
28 };
29
30 timer@13000200 {
31 reg = <0x13000200 0x100>;
32 interrupt-parent = <&pic>;
33 interrupts = <7>;
34 };
35
36 pic@14000000 {
37 compatible = "arm,versatile-fpga-irq";
38 #interrupt-cells = <1>;
39 interrupt-controller;
40 reg = <0x14000000 0x100>;
41 clear-mask = <0xffffffff>;
42 };
43
44 flash@24000000 {
45 compatible = "cfi-flash";
46 reg = <0x24000000 0x02000000>;
47 };
48
49 fpga {
50 compatible = "arm,amba-bus", "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54 interrupt-parent = <&pic>;
55
56 /*
57 * These PrimeCells are in the same locations and using the
58 * same interrupts in all Integrators, however the silicon
59 * version deployed is different.
60 */
61 rtc@15000000 {
62 reg = <0x15000000 0x1000>;
63 interrupts = <8>;
64 };
65
66 uart@16000000 {
67 reg = <0x16000000 0x1000>;
68 interrupts = <1>;
69 };
70
71 uart@17000000 {
72 reg = <0x17000000 0x1000>;
73 interrupts = <2>;
74 };
75
76 kmi@18000000 {
77 reg = <0x18000000 0x1000>;
78 interrupts = <3>;
79 };
80
81 kmi@19000000 {
82 reg = <0x19000000 0x1000>;
83 interrupts = <4>;
84 };
85 };
86};