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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60
61static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65/*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
69dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71{
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81}
82
83static bool trb_is_noop(union xhci_trb *trb)
84{
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86}
87
88static bool trb_is_link(union xhci_trb *trb)
89{
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91}
92
93static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94{
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96}
97
98static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100{
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102}
103
104static bool link_trb_toggles_cycle(union xhci_trb *trb)
105{
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107}
108
109static bool last_td_in_urb(struct xhci_td *td)
110{
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114}
115
116static void inc_td_cnt(struct urb *urb)
117{
118 struct urb_priv *urb_priv = urb->hcpriv;
119
120 urb_priv->num_tds_done++;
121}
122
123static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
124{
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
128 } else {
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 }
136}
137
138/* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
141 */
142static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
146{
147 if (trb_is_link(*trb)) {
148 *seg = (*seg)->next;
149 *trb = ((*seg)->trbs);
150 } else {
151 (*trb)++;
152 }
153}
154
155/*
156 * See Cycle bit rules. SW is the consumer for the event ring only.
157 */
158void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
159{
160 unsigned int link_trb_count = 0;
161
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 ring->dequeue++;
166 goto out;
167 }
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
172 goto out;
173 }
174
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
179 } else {
180 ring->dequeue++;
181 ring->num_trbs_free++;
182 }
183 }
184
185 while (trb_is_link(ring->dequeue)) {
186 ring->deq_seg = ring->deq_seg->next;
187 ring->dequeue = ring->deq_seg->trbs;
188
189 if (link_trb_count++ > ring->num_segs) {
190 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
191 break;
192 }
193 }
194out:
195 trace_xhci_inc_deq(ring);
196
197 return;
198}
199
200/*
201 * See Cycle bit rules. SW is the consumer for the event ring only.
202 *
203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
204 * chain bit is set), then set the chain bit in all the following link TRBs.
205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
206 * have their chain bit cleared (so that each Link TRB is a separate TD).
207 *
208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
209 * set, but other sections talk about dealing with the chain bit set. This was
210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
211 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
212 *
213 * @more_trbs_coming: Will you enqueue more TRBs before calling
214 * prepare_transfer()?
215 */
216static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
217 bool more_trbs_coming)
218{
219 u32 chain;
220 union xhci_trb *next;
221 unsigned int link_trb_count = 0;
222
223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
224 /* If this is not event ring, there is one less usable TRB */
225 if (!trb_is_link(ring->enqueue))
226 ring->num_trbs_free--;
227
228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
229 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
230 return;
231 }
232
233 next = ++(ring->enqueue);
234
235 /* Update the dequeue pointer further if that was a link TRB */
236 while (trb_is_link(next)) {
237
238 /*
239 * If the caller doesn't plan on enqueueing more TDs before
240 * ringing the doorbell, then we don't want to give the link TRB
241 * to the hardware just yet. We'll give the link TRB back in
242 * prepare_ring() just before we enqueue the TD at the top of
243 * the ring.
244 */
245 if (!chain && !more_trbs_coming)
246 break;
247
248 /* If we're not dealing with 0.95 hardware or isoc rings on
249 * AMD 0.96 host, carry over the chain bit of the previous TRB
250 * (which may mean the chain bit is cleared).
251 */
252 if (!(ring->type == TYPE_ISOC &&
253 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
254 !xhci_link_trb_quirk(xhci)) {
255 next->link.control &= cpu_to_le32(~TRB_CHAIN);
256 next->link.control |= cpu_to_le32(chain);
257 }
258 /* Give this link TRB to the hardware */
259 wmb();
260 next->link.control ^= cpu_to_le32(TRB_CYCLE);
261
262 /* Toggle the cycle bit after the last ring segment. */
263 if (link_trb_toggles_cycle(next))
264 ring->cycle_state ^= 1;
265
266 ring->enq_seg = ring->enq_seg->next;
267 ring->enqueue = ring->enq_seg->trbs;
268 next = ring->enqueue;
269
270 if (link_trb_count++ > ring->num_segs) {
271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
272 break;
273 }
274 }
275
276 trace_xhci_inc_enq(ring);
277}
278
279/*
280 * Check to see if there's room to enqueue num_trbs on the ring and make sure
281 * enqueue pointer will not advance into dequeue segment. See rules above.
282 */
283static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
284 unsigned int num_trbs)
285{
286 int num_trbs_in_deq_seg;
287
288 if (ring->num_trbs_free < num_trbs)
289 return 0;
290
291 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
292 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
293 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
294 return 0;
295 }
296
297 return 1;
298}
299
300/* Ring the host controller doorbell after placing a command on the ring */
301void xhci_ring_cmd_db(struct xhci_hcd *xhci)
302{
303 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
304 return;
305
306 xhci_dbg(xhci, "// Ding dong!\n");
307
308 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
309
310 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
311 /* Flush PCI posted writes */
312 readl(&xhci->dba->doorbell[0]);
313}
314
315static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
316{
317 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
318}
319
320static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
321{
322 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
323 cmd_list);
324}
325
326/*
327 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
328 * If there are other commands waiting then restart the ring and kick the timer.
329 * This must be called with command ring stopped and xhci->lock held.
330 */
331static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
332 struct xhci_command *cur_cmd)
333{
334 struct xhci_command *i_cmd;
335
336 /* Turn all aborted commands in list to no-ops, then restart */
337 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
338
339 if (i_cmd->status != COMP_COMMAND_ABORTED)
340 continue;
341
342 i_cmd->status = COMP_COMMAND_RING_STOPPED;
343
344 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
345 i_cmd->command_trb);
346
347 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
348
349 /*
350 * caller waiting for completion is called when command
351 * completion event is received for these no-op commands
352 */
353 }
354
355 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
356
357 /* ring command ring doorbell to restart the command ring */
358 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
359 !(xhci->xhc_state & XHCI_STATE_DYING)) {
360 xhci->current_cmd = cur_cmd;
361 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
362 xhci_ring_cmd_db(xhci);
363 }
364}
365
366/* Must be called with xhci->lock held, releases and aquires lock back */
367static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
368{
369 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
370 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
371 u64 crcr;
372 int ret;
373
374 xhci_dbg(xhci, "Abort command ring\n");
375
376 reinit_completion(&xhci->cmd_ring_stop_completion);
377
378 /*
379 * The control bits like command stop, abort are located in lower
380 * dword of the command ring control register.
381 * Some controllers require all 64 bits to be written to abort the ring.
382 * Make sure the upper dword is valid, pointing to the next command,
383 * avoiding corrupting the command ring pointer in case the command ring
384 * is stopped by the time the upper dword is written.
385 */
386 next_trb(xhci, NULL, &new_seg, &new_deq);
387 if (trb_is_link(new_deq))
388 next_trb(xhci, NULL, &new_seg, &new_deq);
389
390 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
391 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
392
393 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
394 * completion of the Command Abort operation. If CRR is not negated in 5
395 * seconds then driver handles it as if host died (-ENODEV).
396 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
397 * and try to recover a -ETIMEDOUT with a host controller reset.
398 */
399 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
400 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
401 if (ret < 0) {
402 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
403 xhci_halt(xhci);
404 xhci_hc_died(xhci);
405 return ret;
406 }
407 /*
408 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
409 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
410 * but the completion event in never sent. Wait 2 secs (arbitrary
411 * number) to handle those cases after negation of CMD_RING_RUNNING.
412 */
413 spin_unlock_irqrestore(&xhci->lock, flags);
414 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
415 msecs_to_jiffies(2000));
416 spin_lock_irqsave(&xhci->lock, flags);
417 if (!ret) {
418 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
419 xhci_cleanup_command_queue(xhci);
420 } else {
421 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
422 }
423 return 0;
424}
425
426void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
427 unsigned int slot_id,
428 unsigned int ep_index,
429 unsigned int stream_id)
430{
431 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
432 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
433 unsigned int ep_state = ep->ep_state;
434
435 /* Don't ring the doorbell for this endpoint if there are pending
436 * cancellations because we don't want to interrupt processing.
437 * We don't want to restart any stream rings if there's a set dequeue
438 * pointer command pending because the device can choose to start any
439 * stream once the endpoint is on the HW schedule.
440 */
441 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
442 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
443 return;
444
445 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
446
447 writel(DB_VALUE(ep_index, stream_id), db_addr);
448 /* flush the write */
449 readl(db_addr);
450}
451
452/* Ring the doorbell for any rings with pending URBs */
453static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
454 unsigned int slot_id,
455 unsigned int ep_index)
456{
457 unsigned int stream_id;
458 struct xhci_virt_ep *ep;
459
460 ep = &xhci->devs[slot_id]->eps[ep_index];
461
462 /* A ring has pending URBs if its TD list is not empty */
463 if (!(ep->ep_state & EP_HAS_STREAMS)) {
464 if (ep->ring && !(list_empty(&ep->ring->td_list)))
465 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
466 return;
467 }
468
469 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
470 stream_id++) {
471 struct xhci_stream_info *stream_info = ep->stream_info;
472 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
473 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
474 stream_id);
475 }
476}
477
478void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
479 unsigned int slot_id,
480 unsigned int ep_index)
481{
482 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
483}
484
485static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
486 unsigned int slot_id,
487 unsigned int ep_index)
488{
489 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
490 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
491 return NULL;
492 }
493 if (ep_index >= EP_CTX_PER_DEV) {
494 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
495 return NULL;
496 }
497 if (!xhci->devs[slot_id]) {
498 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
499 return NULL;
500 }
501
502 return &xhci->devs[slot_id]->eps[ep_index];
503}
504
505static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
506 struct xhci_virt_ep *ep,
507 unsigned int stream_id)
508{
509 /* common case, no streams */
510 if (!(ep->ep_state & EP_HAS_STREAMS))
511 return ep->ring;
512
513 if (!ep->stream_info)
514 return NULL;
515
516 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
517 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
518 stream_id, ep->vdev->slot_id, ep->ep_index);
519 return NULL;
520 }
521
522 return ep->stream_info->stream_rings[stream_id];
523}
524
525/* Get the right ring for the given slot_id, ep_index and stream_id.
526 * If the endpoint supports streams, boundary check the URB's stream ID.
527 * If the endpoint doesn't support streams, return the singular endpoint ring.
528 */
529struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
530 unsigned int slot_id, unsigned int ep_index,
531 unsigned int stream_id)
532{
533 struct xhci_virt_ep *ep;
534
535 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
536 if (!ep)
537 return NULL;
538
539 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
540}
541
542
543/*
544 * Get the hw dequeue pointer xHC stopped on, either directly from the
545 * endpoint context, or if streams are in use from the stream context.
546 * The returned hw_dequeue contains the lowest four bits with cycle state
547 * and possbile stream context type.
548 */
549static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
550 unsigned int ep_index, unsigned int stream_id)
551{
552 struct xhci_ep_ctx *ep_ctx;
553 struct xhci_stream_ctx *st_ctx;
554 struct xhci_virt_ep *ep;
555
556 ep = &vdev->eps[ep_index];
557
558 if (ep->ep_state & EP_HAS_STREAMS) {
559 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
560 return le64_to_cpu(st_ctx->stream_ring);
561 }
562 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
563 return le64_to_cpu(ep_ctx->deq);
564}
565
566static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
567 unsigned int slot_id, unsigned int ep_index,
568 unsigned int stream_id, struct xhci_td *td)
569{
570 struct xhci_virt_device *dev = xhci->devs[slot_id];
571 struct xhci_virt_ep *ep = &dev->eps[ep_index];
572 struct xhci_ring *ep_ring;
573 struct xhci_command *cmd;
574 struct xhci_segment *new_seg;
575 struct xhci_segment *halted_seg = NULL;
576 union xhci_trb *new_deq;
577 int new_cycle;
578 union xhci_trb *halted_trb;
579 int index = 0;
580 dma_addr_t addr;
581 u64 hw_dequeue;
582 bool cycle_found = false;
583 bool td_last_trb_found = false;
584 u32 trb_sct = 0;
585 int ret;
586
587 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
588 ep_index, stream_id);
589 if (!ep_ring) {
590 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
591 stream_id);
592 return -ENODEV;
593 }
594 /*
595 * A cancelled TD can complete with a stall if HW cached the trb.
596 * In this case driver can't find td, but if the ring is empty we
597 * can move the dequeue pointer to the current enqueue position.
598 * We shouldn't hit this anymore as cached cancelled TRBs are given back
599 * after clearing the cache, but be on the safe side and keep it anyway
600 */
601 if (!td) {
602 if (list_empty(&ep_ring->td_list)) {
603 new_seg = ep_ring->enq_seg;
604 new_deq = ep_ring->enqueue;
605 new_cycle = ep_ring->cycle_state;
606 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
607 goto deq_found;
608 } else {
609 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
610 return -EINVAL;
611 }
612 }
613
614 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
615 new_seg = ep_ring->deq_seg;
616 new_deq = ep_ring->dequeue;
617
618 /*
619 * Quirk: xHC write-back of the DCS field in the hardware dequeue
620 * pointer is wrong - use the cycle state of the TRB pointed to by
621 * the dequeue pointer.
622 */
623 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
624 !(ep->ep_state & EP_HAS_STREAMS))
625 halted_seg = trb_in_td(xhci, td->start_seg,
626 td->first_trb, td->last_trb,
627 hw_dequeue & ~0xf, false);
628 if (halted_seg) {
629 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
630 sizeof(*halted_trb);
631 halted_trb = &halted_seg->trbs[index];
632 new_cycle = halted_trb->generic.field[3] & 0x1;
633 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
634 (u8)(hw_dequeue & 0x1), index, new_cycle);
635 } else {
636 new_cycle = hw_dequeue & 0x1;
637 }
638
639 /*
640 * We want to find the pointer, segment and cycle state of the new trb
641 * (the one after current TD's last_trb). We know the cycle state at
642 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
643 * found.
644 */
645 do {
646 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
647 == (dma_addr_t)(hw_dequeue & ~0xf)) {
648 cycle_found = true;
649 if (td_last_trb_found)
650 break;
651 }
652 if (new_deq == td->last_trb)
653 td_last_trb_found = true;
654
655 if (cycle_found && trb_is_link(new_deq) &&
656 link_trb_toggles_cycle(new_deq))
657 new_cycle ^= 0x1;
658
659 next_trb(xhci, ep_ring, &new_seg, &new_deq);
660
661 /* Search wrapped around, bail out */
662 if (new_deq == ep->ring->dequeue) {
663 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
664 return -EINVAL;
665 }
666
667 } while (!cycle_found || !td_last_trb_found);
668
669deq_found:
670
671 /* Don't update the ring cycle state for the producer (us). */
672 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
673 if (addr == 0) {
674 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
675 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
676 return -EINVAL;
677 }
678
679 if ((ep->ep_state & SET_DEQ_PENDING)) {
680 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
681 &addr);
682 return -EBUSY;
683 }
684
685 /* This function gets called from contexts where it cannot sleep */
686 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
687 if (!cmd) {
688 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
689 return -ENOMEM;
690 }
691
692 if (stream_id)
693 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
694 ret = queue_command(xhci, cmd,
695 lower_32_bits(addr) | trb_sct | new_cycle,
696 upper_32_bits(addr),
697 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
698 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
699 if (ret < 0) {
700 xhci_free_command(xhci, cmd);
701 return ret;
702 }
703 ep->queued_deq_seg = new_seg;
704 ep->queued_deq_ptr = new_deq;
705
706 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
707 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
708
709 /* Stop the TD queueing code from ringing the doorbell until
710 * this command completes. The HC won't set the dequeue pointer
711 * if the ring is running, and ringing the doorbell starts the
712 * ring running.
713 */
714 ep->ep_state |= SET_DEQ_PENDING;
715 xhci_ring_cmd_db(xhci);
716 return 0;
717}
718
719/* flip_cycle means flip the cycle bit of all but the first and last TRB.
720 * (The last TRB actually points to the ring enqueue pointer, which is not part
721 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
722 */
723static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
724 struct xhci_td *td, bool flip_cycle)
725{
726 struct xhci_segment *seg = td->start_seg;
727 union xhci_trb *trb = td->first_trb;
728
729 while (1) {
730 trb_to_noop(trb, TRB_TR_NOOP);
731
732 /* flip cycle if asked to */
733 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
734 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
735
736 if (trb == td->last_trb)
737 break;
738
739 next_trb(xhci, ep_ring, &seg, &trb);
740 }
741}
742
743/*
744 * Must be called with xhci->lock held in interrupt context,
745 * releases and re-acquires xhci->lock
746 */
747static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
748 struct xhci_td *cur_td, int status)
749{
750 struct urb *urb = cur_td->urb;
751 struct urb_priv *urb_priv = urb->hcpriv;
752 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
753
754 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
755 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
756 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
757 if (xhci->quirks & XHCI_AMD_PLL_FIX)
758 usb_amd_quirk_pll_enable();
759 }
760 }
761 xhci_urb_free_priv(urb_priv);
762 usb_hcd_unlink_urb_from_ep(hcd, urb);
763 trace_xhci_urb_giveback(urb);
764 usb_hcd_giveback_urb(hcd, urb, status);
765}
766
767static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
768 struct xhci_ring *ring, struct xhci_td *td)
769{
770 struct device *dev = xhci_to_hcd(xhci)->self.controller;
771 struct xhci_segment *seg = td->bounce_seg;
772 struct urb *urb = td->urb;
773 size_t len;
774
775 if (!ring || !seg || !urb)
776 return;
777
778 if (usb_urb_dir_out(urb)) {
779 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
780 DMA_TO_DEVICE);
781 return;
782 }
783
784 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
785 DMA_FROM_DEVICE);
786 /* for in tranfers we need to copy the data from bounce to sg */
787 if (urb->num_sgs) {
788 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
789 seg->bounce_len, seg->bounce_offs);
790 if (len != seg->bounce_len)
791 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
792 len, seg->bounce_len);
793 } else {
794 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
795 seg->bounce_len);
796 }
797 seg->bounce_len = 0;
798 seg->bounce_offs = 0;
799}
800
801static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
802 struct xhci_ring *ep_ring, int status)
803{
804 struct urb *urb = NULL;
805
806 /* Clean up the endpoint's TD list */
807 urb = td->urb;
808
809 /* if a bounce buffer was used to align this td then unmap it */
810 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
811
812 /* Do one last check of the actual transfer length.
813 * If the host controller said we transferred more data than the buffer
814 * length, urb->actual_length will be a very big number (since it's
815 * unsigned). Play it safe and say we didn't transfer anything.
816 */
817 if (urb->actual_length > urb->transfer_buffer_length) {
818 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
819 urb->transfer_buffer_length, urb->actual_length);
820 urb->actual_length = 0;
821 status = 0;
822 }
823 /* TD might be removed from td_list if we are giving back a cancelled URB */
824 if (!list_empty(&td->td_list))
825 list_del_init(&td->td_list);
826 /* Giving back a cancelled URB, or if a slated TD completed anyway */
827 if (!list_empty(&td->cancelled_td_list))
828 list_del_init(&td->cancelled_td_list);
829
830 inc_td_cnt(urb);
831 /* Giveback the urb when all the tds are completed */
832 if (last_td_in_urb(td)) {
833 if ((urb->actual_length != urb->transfer_buffer_length &&
834 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
835 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
836 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
837 urb, urb->actual_length,
838 urb->transfer_buffer_length, status);
839
840 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
841 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
842 status = 0;
843 xhci_giveback_urb_in_irq(xhci, td, status);
844 }
845
846 return 0;
847}
848
849
850/* Complete the cancelled URBs we unlinked from td_list. */
851static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
852{
853 struct xhci_ring *ring;
854 struct xhci_td *td, *tmp_td;
855
856 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
857 cancelled_td_list) {
858
859 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
860
861 if (td->cancel_status == TD_CLEARED) {
862 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
863 __func__, td->urb);
864 xhci_td_cleanup(ep->xhci, td, ring, td->status);
865 } else {
866 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
867 __func__, td->urb, td->cancel_status);
868 }
869 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
870 return;
871 }
872}
873
874static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
875 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
876{
877 struct xhci_command *command;
878 int ret = 0;
879
880 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
881 if (!command) {
882 ret = -ENOMEM;
883 goto done;
884 }
885
886 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
887 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
888 ep_index, slot_id);
889
890 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
891done:
892 if (ret)
893 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
894 slot_id, ep_index, ret);
895 return ret;
896}
897
898static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
899 struct xhci_virt_ep *ep,
900 struct xhci_td *td,
901 enum xhci_ep_reset_type reset_type)
902{
903 unsigned int slot_id = ep->vdev->slot_id;
904 int err;
905
906 /*
907 * Avoid resetting endpoint if link is inactive. Can cause host hang.
908 * Device will be reset soon to recover the link so don't do anything
909 */
910 if (ep->vdev->flags & VDEV_PORT_ERROR)
911 return -ENODEV;
912
913 /* add td to cancelled list and let reset ep handler take care of it */
914 if (reset_type == EP_HARD_RESET) {
915 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
916 if (td && list_empty(&td->cancelled_td_list)) {
917 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
918 td->cancel_status = TD_HALTED;
919 }
920 }
921
922 if (ep->ep_state & EP_HALTED) {
923 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
924 ep->ep_index);
925 return 0;
926 }
927
928 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
929 if (err)
930 return err;
931
932 ep->ep_state |= EP_HALTED;
933
934 xhci_ring_cmd_db(xhci);
935
936 return 0;
937}
938
939/*
940 * Fix up the ep ring first, so HW stops executing cancelled TDs.
941 * We have the xHCI lock, so nothing can modify this list until we drop it.
942 * We're also in the event handler, so we can't get re-interrupted if another
943 * Stop Endpoint command completes.
944 *
945 * only call this when ring is not in a running state
946 */
947
948static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
949{
950 struct xhci_hcd *xhci;
951 struct xhci_td *td = NULL;
952 struct xhci_td *tmp_td = NULL;
953 struct xhci_td *cached_td = NULL;
954 struct xhci_ring *ring;
955 u64 hw_deq;
956 unsigned int slot_id = ep->vdev->slot_id;
957 int err;
958
959 xhci = ep->xhci;
960
961 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
962 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
963 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
964 (unsigned long long)xhci_trb_virt_to_dma(
965 td->start_seg, td->first_trb),
966 td->urb->stream_id, td->urb);
967 list_del_init(&td->td_list);
968 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
969 if (!ring) {
970 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
971 td->urb, td->urb->stream_id);
972 continue;
973 }
974 /*
975 * If a ring stopped on the TD we need to cancel then we have to
976 * move the xHC endpoint ring dequeue pointer past this TD.
977 * Rings halted due to STALL may show hw_deq is past the stalled
978 * TD, but still require a set TR Deq command to flush xHC cache.
979 */
980 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
981 td->urb->stream_id);
982 hw_deq &= ~0xf;
983
984 if (td->cancel_status == TD_HALTED ||
985 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
986 switch (td->cancel_status) {
987 case TD_CLEARED: /* TD is already no-op */
988 case TD_CLEARING_CACHE: /* set TR deq command already queued */
989 break;
990 case TD_DIRTY: /* TD is cached, clear it */
991 case TD_HALTED:
992 td->cancel_status = TD_CLEARING_CACHE;
993 if (cached_td)
994 /* FIXME stream case, several stopped rings */
995 xhci_dbg(xhci,
996 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
997 td->urb->stream_id, td->urb,
998 cached_td->urb->stream_id, cached_td->urb);
999 cached_td = td;
1000 break;
1001 }
1002 } else {
1003 td_to_noop(xhci, ring, td, false);
1004 td->cancel_status = TD_CLEARED;
1005 }
1006 }
1007
1008 /* If there's no need to move the dequeue pointer then we're done */
1009 if (!cached_td)
1010 return 0;
1011
1012 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1013 cached_td->urb->stream_id,
1014 cached_td);
1015 if (err) {
1016 /* Failed to move past cached td, just set cached TDs to no-op */
1017 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1018 if (td->cancel_status != TD_CLEARING_CACHE)
1019 continue;
1020 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1021 td->urb);
1022 td_to_noop(xhci, ring, td, false);
1023 td->cancel_status = TD_CLEARED;
1024 }
1025 }
1026 return 0;
1027}
1028
1029/*
1030 * Returns the TD the endpoint ring halted on.
1031 * Only call for non-running rings without streams.
1032 */
1033static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1034{
1035 struct xhci_td *td;
1036 u64 hw_deq;
1037
1038 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1039 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1040 hw_deq &= ~0xf;
1041 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1042 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1043 td->last_trb, hw_deq, false))
1044 return td;
1045 }
1046 return NULL;
1047}
1048
1049/*
1050 * When we get a command completion for a Stop Endpoint Command, we need to
1051 * unlink any cancelled TDs from the ring. There are two ways to do that:
1052 *
1053 * 1. If the HW was in the middle of processing the TD that needs to be
1054 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1055 * in the TD with a Set Dequeue Pointer Command.
1056 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1057 * bit cleared) so that the HW will skip over them.
1058 */
1059static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1060 union xhci_trb *trb, u32 comp_code)
1061{
1062 unsigned int ep_index;
1063 struct xhci_virt_ep *ep;
1064 struct xhci_ep_ctx *ep_ctx;
1065 struct xhci_td *td = NULL;
1066 enum xhci_ep_reset_type reset_type;
1067 struct xhci_command *command;
1068 int err;
1069
1070 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1071 if (!xhci->devs[slot_id])
1072 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1073 slot_id);
1074 return;
1075 }
1076
1077 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1078 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1079 if (!ep)
1080 return;
1081
1082 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1083
1084 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1085
1086 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1087 /*
1088 * If stop endpoint command raced with a halting endpoint we need to
1089 * reset the host side endpoint first.
1090 * If the TD we halted on isn't cancelled the TD should be given back
1091 * with a proper error code, and the ring dequeue moved past the TD.
1092 * If streams case we can't find hw_deq, or the TD we halted on so do a
1093 * soft reset.
1094 *
1095 * Proper error code is unknown here, it would be -EPIPE if device side
1096 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1097 * We use -EPROTO, if device is stalled it should return a stall error on
1098 * next transfer, which then will return -EPIPE, and device side stall is
1099 * noted and cleared by class driver.
1100 */
1101 switch (GET_EP_CTX_STATE(ep_ctx)) {
1102 case EP_STATE_HALTED:
1103 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1104 if (ep->ep_state & EP_HAS_STREAMS) {
1105 reset_type = EP_SOFT_RESET;
1106 } else {
1107 reset_type = EP_HARD_RESET;
1108 td = find_halted_td(ep);
1109 if (td)
1110 td->status = -EPROTO;
1111 }
1112 /* reset ep, reset handler cleans up cancelled tds */
1113 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1114 if (err)
1115 break;
1116 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1117 return;
1118 case EP_STATE_RUNNING:
1119 /* Race, HW handled stop ep cmd before ep was running */
1120 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1121
1122 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1123 if (!command) {
1124 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1125 return;
1126 }
1127 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1128 xhci_ring_cmd_db(xhci);
1129
1130 return;
1131 default:
1132 break;
1133 }
1134 }
1135
1136 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1137 xhci_invalidate_cancelled_tds(ep);
1138 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1139
1140 /* Otherwise ring the doorbell(s) to restart queued transfers */
1141 xhci_giveback_invalidated_tds(ep);
1142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143}
1144
1145static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1146{
1147 struct xhci_td *cur_td;
1148 struct xhci_td *tmp;
1149
1150 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1151 list_del_init(&cur_td->td_list);
1152
1153 if (!list_empty(&cur_td->cancelled_td_list))
1154 list_del_init(&cur_td->cancelled_td_list);
1155
1156 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1157
1158 inc_td_cnt(cur_td->urb);
1159 if (last_td_in_urb(cur_td))
1160 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1161 }
1162}
1163
1164static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1165 int slot_id, int ep_index)
1166{
1167 struct xhci_td *cur_td;
1168 struct xhci_td *tmp;
1169 struct xhci_virt_ep *ep;
1170 struct xhci_ring *ring;
1171
1172 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1173 if (!ep)
1174 return;
1175
1176 if ((ep->ep_state & EP_HAS_STREAMS) ||
1177 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1178 int stream_id;
1179
1180 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1181 stream_id++) {
1182 ring = ep->stream_info->stream_rings[stream_id];
1183 if (!ring)
1184 continue;
1185
1186 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1187 "Killing URBs for slot ID %u, ep index %u, stream %u",
1188 slot_id, ep_index, stream_id);
1189 xhci_kill_ring_urbs(xhci, ring);
1190 }
1191 } else {
1192 ring = ep->ring;
1193 if (!ring)
1194 return;
1195 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1196 "Killing URBs for slot ID %u, ep index %u",
1197 slot_id, ep_index);
1198 xhci_kill_ring_urbs(xhci, ring);
1199 }
1200
1201 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1202 cancelled_td_list) {
1203 list_del_init(&cur_td->cancelled_td_list);
1204 inc_td_cnt(cur_td->urb);
1205
1206 if (last_td_in_urb(cur_td))
1207 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1208 }
1209}
1210
1211/*
1212 * host controller died, register read returns 0xffffffff
1213 * Complete pending commands, mark them ABORTED.
1214 * URBs need to be given back as usb core might be waiting with device locks
1215 * held for the URBs to finish during device disconnect, blocking host remove.
1216 *
1217 * Call with xhci->lock held.
1218 * lock is relased and re-acquired while giving back urb.
1219 */
1220void xhci_hc_died(struct xhci_hcd *xhci)
1221{
1222 int i, j;
1223
1224 if (xhci->xhc_state & XHCI_STATE_DYING)
1225 return;
1226
1227 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1228 xhci->xhc_state |= XHCI_STATE_DYING;
1229
1230 xhci_cleanup_command_queue(xhci);
1231
1232 /* return any pending urbs, remove may be waiting for them */
1233 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1234 if (!xhci->devs[i])
1235 continue;
1236 for (j = 0; j < 31; j++)
1237 xhci_kill_endpoint_urbs(xhci, i, j);
1238 }
1239
1240 /* inform usb core hc died if PCI remove isn't already handling it */
1241 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1242 usb_hc_died(xhci_to_hcd(xhci));
1243}
1244
1245static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1246 struct xhci_virt_device *dev,
1247 struct xhci_ring *ep_ring,
1248 unsigned int ep_index)
1249{
1250 union xhci_trb *dequeue_temp;
1251 int num_trbs_free_temp;
1252 bool revert = false;
1253
1254 num_trbs_free_temp = ep_ring->num_trbs_free;
1255 dequeue_temp = ep_ring->dequeue;
1256
1257 /* If we get two back-to-back stalls, and the first stalled transfer
1258 * ends just before a link TRB, the dequeue pointer will be left on
1259 * the link TRB by the code in the while loop. So we have to update
1260 * the dequeue pointer one segment further, or we'll jump off
1261 * the segment into la-la-land.
1262 */
1263 if (trb_is_link(ep_ring->dequeue)) {
1264 ep_ring->deq_seg = ep_ring->deq_seg->next;
1265 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1266 }
1267
1268 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1269 /* We have more usable TRBs */
1270 ep_ring->num_trbs_free++;
1271 ep_ring->dequeue++;
1272 if (trb_is_link(ep_ring->dequeue)) {
1273 if (ep_ring->dequeue ==
1274 dev->eps[ep_index].queued_deq_ptr)
1275 break;
1276 ep_ring->deq_seg = ep_ring->deq_seg->next;
1277 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1278 }
1279 if (ep_ring->dequeue == dequeue_temp) {
1280 revert = true;
1281 break;
1282 }
1283 }
1284
1285 if (revert) {
1286 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1287 ep_ring->num_trbs_free = num_trbs_free_temp;
1288 }
1289}
1290
1291/*
1292 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1293 * we need to clear the set deq pending flag in the endpoint ring state, so that
1294 * the TD queueing code can ring the doorbell again. We also need to ring the
1295 * endpoint doorbell to restart the ring, but only if there aren't more
1296 * cancellations pending.
1297 */
1298static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1299 union xhci_trb *trb, u32 cmd_comp_code)
1300{
1301 unsigned int ep_index;
1302 unsigned int stream_id;
1303 struct xhci_ring *ep_ring;
1304 struct xhci_virt_ep *ep;
1305 struct xhci_ep_ctx *ep_ctx;
1306 struct xhci_slot_ctx *slot_ctx;
1307 struct xhci_td *td, *tmp_td;
1308
1309 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1310 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1311 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1312 if (!ep)
1313 return;
1314
1315 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1316 if (!ep_ring) {
1317 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1318 stream_id);
1319 /* XXX: Harmless??? */
1320 goto cleanup;
1321 }
1322
1323 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1324 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1325 trace_xhci_handle_cmd_set_deq(slot_ctx);
1326 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1327
1328 if (cmd_comp_code != COMP_SUCCESS) {
1329 unsigned int ep_state;
1330 unsigned int slot_state;
1331
1332 switch (cmd_comp_code) {
1333 case COMP_TRB_ERROR:
1334 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1335 break;
1336 case COMP_CONTEXT_STATE_ERROR:
1337 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1338 ep_state = GET_EP_CTX_STATE(ep_ctx);
1339 slot_state = le32_to_cpu(slot_ctx->dev_state);
1340 slot_state = GET_SLOT_STATE(slot_state);
1341 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1342 "Slot state = %u, EP state = %u",
1343 slot_state, ep_state);
1344 break;
1345 case COMP_SLOT_NOT_ENABLED_ERROR:
1346 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1347 slot_id);
1348 break;
1349 default:
1350 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1351 cmd_comp_code);
1352 break;
1353 }
1354 /* OK what do we do now? The endpoint state is hosed, and we
1355 * should never get to this point if the synchronization between
1356 * queueing, and endpoint state are correct. This might happen
1357 * if the device gets disconnected after we've finished
1358 * cancelling URBs, which might not be an error...
1359 */
1360 } else {
1361 u64 deq;
1362 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1363 if (ep->ep_state & EP_HAS_STREAMS) {
1364 struct xhci_stream_ctx *ctx =
1365 &ep->stream_info->stream_ctx_array[stream_id];
1366 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1367 } else {
1368 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1369 }
1370 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1371 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1372 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1373 ep->queued_deq_ptr) == deq) {
1374 /* Update the ring's dequeue segment and dequeue pointer
1375 * to reflect the new position.
1376 */
1377 update_ring_for_set_deq_completion(xhci, ep->vdev,
1378 ep_ring, ep_index);
1379 } else {
1380 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1381 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1382 ep->queued_deq_seg, ep->queued_deq_ptr);
1383 }
1384 }
1385 /* HW cached TDs cleared from cache, give them back */
1386 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1387 cancelled_td_list) {
1388 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1389 if (td->cancel_status == TD_CLEARING_CACHE) {
1390 td->cancel_status = TD_CLEARED;
1391 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1392 __func__, td->urb);
1393 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1394 } else {
1395 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1396 __func__, td->urb, td->cancel_status);
1397 }
1398 }
1399cleanup:
1400 ep->ep_state &= ~SET_DEQ_PENDING;
1401 ep->queued_deq_seg = NULL;
1402 ep->queued_deq_ptr = NULL;
1403 /* Restart any rings with pending URBs */
1404 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1405}
1406
1407static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1408 union xhci_trb *trb, u32 cmd_comp_code)
1409{
1410 struct xhci_virt_ep *ep;
1411 struct xhci_ep_ctx *ep_ctx;
1412 unsigned int ep_index;
1413
1414 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1415 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1416 if (!ep)
1417 return;
1418
1419 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1420 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1421
1422 /* This command will only fail if the endpoint wasn't halted,
1423 * but we don't care.
1424 */
1425 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1426 "Ignoring reset ep completion code of %u", cmd_comp_code);
1427
1428 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1429 xhci_invalidate_cancelled_tds(ep);
1430
1431 /* Clear our internal halted state */
1432 ep->ep_state &= ~EP_HALTED;
1433
1434 xhci_giveback_invalidated_tds(ep);
1435
1436 /* if this was a soft reset, then restart */
1437 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1438 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1439}
1440
1441static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1442 struct xhci_command *command, u32 cmd_comp_code)
1443{
1444 if (cmd_comp_code == COMP_SUCCESS)
1445 command->slot_id = slot_id;
1446 else
1447 command->slot_id = 0;
1448}
1449
1450static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1451{
1452 struct xhci_virt_device *virt_dev;
1453 struct xhci_slot_ctx *slot_ctx;
1454
1455 virt_dev = xhci->devs[slot_id];
1456 if (!virt_dev)
1457 return;
1458
1459 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1460 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1461
1462 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1463 /* Delete default control endpoint resources */
1464 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1465}
1466
1467static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1468 u32 cmd_comp_code)
1469{
1470 struct xhci_virt_device *virt_dev;
1471 struct xhci_input_control_ctx *ctrl_ctx;
1472 struct xhci_ep_ctx *ep_ctx;
1473 unsigned int ep_index;
1474 u32 add_flags;
1475
1476 /*
1477 * Configure endpoint commands can come from the USB core configuration
1478 * or alt setting changes, or when streams were being configured.
1479 */
1480
1481 virt_dev = xhci->devs[slot_id];
1482 if (!virt_dev)
1483 return;
1484 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1485 if (!ctrl_ctx) {
1486 xhci_warn(xhci, "Could not get input context, bad type.\n");
1487 return;
1488 }
1489
1490 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1491
1492 /* Input ctx add_flags are the endpoint index plus one */
1493 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1494
1495 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1496 trace_xhci_handle_cmd_config_ep(ep_ctx);
1497
1498 return;
1499}
1500
1501static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1502{
1503 struct xhci_virt_device *vdev;
1504 struct xhci_slot_ctx *slot_ctx;
1505
1506 vdev = xhci->devs[slot_id];
1507 if (!vdev)
1508 return;
1509 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1510 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1511}
1512
1513static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1514{
1515 struct xhci_virt_device *vdev;
1516 struct xhci_slot_ctx *slot_ctx;
1517
1518 vdev = xhci->devs[slot_id];
1519 if (!vdev) {
1520 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1521 slot_id);
1522 return;
1523 }
1524 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1525 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1526
1527 xhci_dbg(xhci, "Completed reset device command.\n");
1528}
1529
1530static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1531 struct xhci_event_cmd *event)
1532{
1533 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1534 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1535 return;
1536 }
1537 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1538 "NEC firmware version %2x.%02x",
1539 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1540 NEC_FW_MINOR(le32_to_cpu(event->status)));
1541}
1542
1543static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1544{
1545 list_del(&cmd->cmd_list);
1546
1547 if (cmd->completion) {
1548 cmd->status = status;
1549 complete(cmd->completion);
1550 } else {
1551 kfree(cmd);
1552 }
1553}
1554
1555void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1556{
1557 struct xhci_command *cur_cmd, *tmp_cmd;
1558 xhci->current_cmd = NULL;
1559 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1560 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1561}
1562
1563void xhci_handle_command_timeout(struct work_struct *work)
1564{
1565 struct xhci_hcd *xhci;
1566 unsigned long flags;
1567 char str[XHCI_MSG_MAX];
1568 u64 hw_ring_state;
1569 u32 cmd_field3;
1570 u32 usbsts;
1571
1572 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1573
1574 spin_lock_irqsave(&xhci->lock, flags);
1575
1576 /*
1577 * If timeout work is pending, or current_cmd is NULL, it means we
1578 * raced with command completion. Command is handled so just return.
1579 */
1580 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1581 spin_unlock_irqrestore(&xhci->lock, flags);
1582 return;
1583 }
1584
1585 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1586 usbsts = readl(&xhci->op_regs->status);
1587 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1588
1589 /* Bail out and tear down xhci if a stop endpoint command failed */
1590 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1591 struct xhci_virt_ep *ep;
1592
1593 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1594
1595 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1596 TRB_TO_EP_INDEX(cmd_field3));
1597 if (ep)
1598 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1599
1600 xhci_halt(xhci);
1601 xhci_hc_died(xhci);
1602 goto time_out_completed;
1603 }
1604
1605 /* mark this command to be cancelled */
1606 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1607
1608 /* Make sure command ring is running before aborting it */
1609 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1610 if (hw_ring_state == ~(u64)0) {
1611 xhci_hc_died(xhci);
1612 goto time_out_completed;
1613 }
1614
1615 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1616 (hw_ring_state & CMD_RING_RUNNING)) {
1617 /* Prevent new doorbell, and start command abort */
1618 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1619 xhci_dbg(xhci, "Command timeout\n");
1620 xhci_abort_cmd_ring(xhci, flags);
1621 goto time_out_completed;
1622 }
1623
1624 /* host removed. Bail out */
1625 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1626 xhci_dbg(xhci, "host removed, ring start fail?\n");
1627 xhci_cleanup_command_queue(xhci);
1628
1629 goto time_out_completed;
1630 }
1631
1632 /* command timeout on stopped ring, ring can't be aborted */
1633 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1634 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1635
1636time_out_completed:
1637 spin_unlock_irqrestore(&xhci->lock, flags);
1638 return;
1639}
1640
1641static void handle_cmd_completion(struct xhci_hcd *xhci,
1642 struct xhci_event_cmd *event)
1643{
1644 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1645 u64 cmd_dma;
1646 dma_addr_t cmd_dequeue_dma;
1647 u32 cmd_comp_code;
1648 union xhci_trb *cmd_trb;
1649 struct xhci_command *cmd;
1650 u32 cmd_type;
1651
1652 if (slot_id >= MAX_HC_SLOTS) {
1653 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1654 return;
1655 }
1656
1657 cmd_dma = le64_to_cpu(event->cmd_trb);
1658 cmd_trb = xhci->cmd_ring->dequeue;
1659
1660 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1661
1662 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1663 cmd_trb);
1664 /*
1665 * Check whether the completion event is for our internal kept
1666 * command.
1667 */
1668 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1669 xhci_warn(xhci,
1670 "ERROR mismatched command completion event\n");
1671 return;
1672 }
1673
1674 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1675
1676 cancel_delayed_work(&xhci->cmd_timer);
1677
1678 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1679
1680 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1681 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1682 complete_all(&xhci->cmd_ring_stop_completion);
1683 return;
1684 }
1685
1686 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1687 xhci_err(xhci,
1688 "Command completion event does not match command\n");
1689 return;
1690 }
1691
1692 /*
1693 * Host aborted the command ring, check if the current command was
1694 * supposed to be aborted, otherwise continue normally.
1695 * The command ring is stopped now, but the xHC will issue a Command
1696 * Ring Stopped event which will cause us to restart it.
1697 */
1698 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1699 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1700 if (cmd->status == COMP_COMMAND_ABORTED) {
1701 if (xhci->current_cmd == cmd)
1702 xhci->current_cmd = NULL;
1703 goto event_handled;
1704 }
1705 }
1706
1707 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1708 switch (cmd_type) {
1709 case TRB_ENABLE_SLOT:
1710 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1711 break;
1712 case TRB_DISABLE_SLOT:
1713 xhci_handle_cmd_disable_slot(xhci, slot_id);
1714 break;
1715 case TRB_CONFIG_EP:
1716 if (!cmd->completion)
1717 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1718 break;
1719 case TRB_EVAL_CONTEXT:
1720 break;
1721 case TRB_ADDR_DEV:
1722 xhci_handle_cmd_addr_dev(xhci, slot_id);
1723 break;
1724 case TRB_STOP_RING:
1725 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1726 le32_to_cpu(cmd_trb->generic.field[3])));
1727 if (!cmd->completion)
1728 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1729 cmd_comp_code);
1730 break;
1731 case TRB_SET_DEQ:
1732 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1733 le32_to_cpu(cmd_trb->generic.field[3])));
1734 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1735 break;
1736 case TRB_CMD_NOOP:
1737 /* Is this an aborted command turned to NO-OP? */
1738 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1739 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1740 break;
1741 case TRB_RESET_EP:
1742 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1743 le32_to_cpu(cmd_trb->generic.field[3])));
1744 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1745 break;
1746 case TRB_RESET_DEV:
1747 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1748 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1749 */
1750 slot_id = TRB_TO_SLOT_ID(
1751 le32_to_cpu(cmd_trb->generic.field[3]));
1752 xhci_handle_cmd_reset_dev(xhci, slot_id);
1753 break;
1754 case TRB_NEC_GET_FW:
1755 xhci_handle_cmd_nec_get_fw(xhci, event);
1756 break;
1757 default:
1758 /* Skip over unknown commands on the event ring */
1759 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1760 break;
1761 }
1762
1763 /* restart timer if this wasn't the last command */
1764 if (!list_is_singular(&xhci->cmd_list)) {
1765 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1766 struct xhci_command, cmd_list);
1767 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1768 } else if (xhci->current_cmd == cmd) {
1769 xhci->current_cmd = NULL;
1770 }
1771
1772event_handled:
1773 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1774
1775 inc_deq(xhci, xhci->cmd_ring);
1776}
1777
1778static void handle_vendor_event(struct xhci_hcd *xhci,
1779 union xhci_trb *event, u32 trb_type)
1780{
1781 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1782 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1783 handle_cmd_completion(xhci, &event->event_cmd);
1784}
1785
1786static void handle_device_notification(struct xhci_hcd *xhci,
1787 union xhci_trb *event)
1788{
1789 u32 slot_id;
1790 struct usb_device *udev;
1791
1792 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1793 if (!xhci->devs[slot_id]) {
1794 xhci_warn(xhci, "Device Notification event for "
1795 "unused slot %u\n", slot_id);
1796 return;
1797 }
1798
1799 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1800 slot_id);
1801 udev = xhci->devs[slot_id]->udev;
1802 if (udev && udev->parent)
1803 usb_wakeup_notification(udev->parent, udev->portnum);
1804}
1805
1806/*
1807 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1808 * Controller.
1809 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1810 * If a connection to a USB 1 device is followed by another connection
1811 * to a USB 2 device.
1812 *
1813 * Reset the PHY after the USB device is disconnected if device speed
1814 * is less than HCD_USB3.
1815 * Retry the reset sequence max of 4 times checking the PLL lock status.
1816 *
1817 */
1818static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1819{
1820 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1821 u32 pll_lock_check;
1822 u32 retry_count = 4;
1823
1824 do {
1825 /* Assert PHY reset */
1826 writel(0x6F, hcd->regs + 0x1048);
1827 udelay(10);
1828 /* De-assert the PHY reset */
1829 writel(0x7F, hcd->regs + 0x1048);
1830 udelay(200);
1831 pll_lock_check = readl(hcd->regs + 0x1070);
1832 } while (!(pll_lock_check & 0x1) && --retry_count);
1833}
1834
1835static void handle_port_status(struct xhci_hcd *xhci,
1836 union xhci_trb *event)
1837{
1838 struct usb_hcd *hcd;
1839 u32 port_id;
1840 u32 portsc, cmd_reg;
1841 int max_ports;
1842 int slot_id;
1843 unsigned int hcd_portnum;
1844 struct xhci_bus_state *bus_state;
1845 bool bogus_port_status = false;
1846 struct xhci_port *port;
1847
1848 /* Port status change events always have a successful completion code */
1849 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1850 xhci_warn(xhci,
1851 "WARN: xHC returned failed port status event\n");
1852
1853 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1854 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1855
1856 if ((port_id <= 0) || (port_id > max_ports)) {
1857 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1858 port_id);
1859 inc_deq(xhci, xhci->event_ring);
1860 return;
1861 }
1862
1863 port = &xhci->hw_ports[port_id - 1];
1864 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1865 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1866 port_id);
1867 bogus_port_status = true;
1868 goto cleanup;
1869 }
1870
1871 /* We might get interrupts after shared_hcd is removed */
1872 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1873 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1874 bogus_port_status = true;
1875 goto cleanup;
1876 }
1877
1878 hcd = port->rhub->hcd;
1879 bus_state = &port->rhub->bus_state;
1880 hcd_portnum = port->hcd_portnum;
1881 portsc = readl(port->addr);
1882
1883 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1884 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1885
1886 trace_xhci_handle_port_status(hcd_portnum, portsc);
1887
1888 if (hcd->state == HC_STATE_SUSPENDED) {
1889 xhci_dbg(xhci, "resume root hub\n");
1890 usb_hcd_resume_root_hub(hcd);
1891 }
1892
1893 if (hcd->speed >= HCD_USB3 &&
1894 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1895 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1896 if (slot_id && xhci->devs[slot_id])
1897 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1898 }
1899
1900 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1901 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1902
1903 cmd_reg = readl(&xhci->op_regs->command);
1904 if (!(cmd_reg & CMD_RUN)) {
1905 xhci_warn(xhci, "xHC is not running.\n");
1906 goto cleanup;
1907 }
1908
1909 if (DEV_SUPERSPEED_ANY(portsc)) {
1910 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1911 /* Set a flag to say the port signaled remote wakeup,
1912 * so we can tell the difference between the end of
1913 * device and host initiated resume.
1914 */
1915 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1916 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1917 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1918 xhci_set_link_state(xhci, port, XDEV_U0);
1919 /* Need to wait until the next link state change
1920 * indicates the device is actually in U0.
1921 */
1922 bogus_port_status = true;
1923 goto cleanup;
1924 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1925 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1926 bus_state->resume_done[hcd_portnum] = jiffies +
1927 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1928 set_bit(hcd_portnum, &bus_state->resuming_ports);
1929 /* Do the rest in GetPortStatus after resume time delay.
1930 * Avoid polling roothub status before that so that a
1931 * usb device auto-resume latency around ~40ms.
1932 */
1933 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1934 mod_timer(&hcd->rh_timer,
1935 bus_state->resume_done[hcd_portnum]);
1936 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1937 bogus_port_status = true;
1938 }
1939 }
1940
1941 if ((portsc & PORT_PLC) &&
1942 DEV_SUPERSPEED_ANY(portsc) &&
1943 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1944 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1945 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1946 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1947 complete(&bus_state->u3exit_done[hcd_portnum]);
1948 /* We've just brought the device into U0/1/2 through either the
1949 * Resume state after a device remote wakeup, or through the
1950 * U3Exit state after a host-initiated resume. If it's a device
1951 * initiated remote wake, don't pass up the link state change,
1952 * so the roothub behavior is consistent with external
1953 * USB 3.0 hub behavior.
1954 */
1955 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1956 if (slot_id && xhci->devs[slot_id])
1957 xhci_ring_device(xhci, slot_id);
1958 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1959 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1960 usb_wakeup_notification(hcd->self.root_hub,
1961 hcd_portnum + 1);
1962 bogus_port_status = true;
1963 goto cleanup;
1964 }
1965 }
1966
1967 /*
1968 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1969 * RExit to a disconnect state). If so, let the driver know it's
1970 * out of the RExit state.
1971 */
1972 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1973 test_and_clear_bit(hcd_portnum,
1974 &bus_state->rexit_ports)) {
1975 complete(&bus_state->rexit_done[hcd_portnum]);
1976 bogus_port_status = true;
1977 goto cleanup;
1978 }
1979
1980 if (hcd->speed < HCD_USB3) {
1981 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1982 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1983 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1984 xhci_cavium_reset_phy_quirk(xhci);
1985 }
1986
1987cleanup:
1988 /* Update event ring dequeue pointer before dropping the lock */
1989 inc_deq(xhci, xhci->event_ring);
1990
1991 /* Don't make the USB core poll the roothub if we got a bad port status
1992 * change event. Besides, at that point we can't tell which roothub
1993 * (USB 2.0 or USB 3.0) to kick.
1994 */
1995 if (bogus_port_status)
1996 return;
1997
1998 /*
1999 * xHCI port-status-change events occur when the "or" of all the
2000 * status-change bits in the portsc register changes from 0 to 1.
2001 * New status changes won't cause an event if any other change
2002 * bits are still set. When an event occurs, switch over to
2003 * polling to avoid losing status changes.
2004 */
2005 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2006 __func__, hcd->self.busnum);
2007 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2008 spin_unlock(&xhci->lock);
2009 /* Pass this up to the core */
2010 usb_hcd_poll_rh_status(hcd);
2011 spin_lock(&xhci->lock);
2012}
2013
2014/*
2015 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2016 * at end_trb, which may be in another segment. If the suspect DMA address is a
2017 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2018 * returns 0.
2019 */
2020struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2021 struct xhci_segment *start_seg,
2022 union xhci_trb *start_trb,
2023 union xhci_trb *end_trb,
2024 dma_addr_t suspect_dma,
2025 bool debug)
2026{
2027 dma_addr_t start_dma;
2028 dma_addr_t end_seg_dma;
2029 dma_addr_t end_trb_dma;
2030 struct xhci_segment *cur_seg;
2031
2032 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2033 cur_seg = start_seg;
2034
2035 do {
2036 if (start_dma == 0)
2037 return NULL;
2038 /* We may get an event for a Link TRB in the middle of a TD */
2039 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2040 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2041 /* If the end TRB isn't in this segment, this is set to 0 */
2042 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2043
2044 if (debug)
2045 xhci_warn(xhci,
2046 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2047 (unsigned long long)suspect_dma,
2048 (unsigned long long)start_dma,
2049 (unsigned long long)end_trb_dma,
2050 (unsigned long long)cur_seg->dma,
2051 (unsigned long long)end_seg_dma);
2052
2053 if (end_trb_dma > 0) {
2054 /* The end TRB is in this segment, so suspect should be here */
2055 if (start_dma <= end_trb_dma) {
2056 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2057 return cur_seg;
2058 } else {
2059 /* Case for one segment with
2060 * a TD wrapped around to the top
2061 */
2062 if ((suspect_dma >= start_dma &&
2063 suspect_dma <= end_seg_dma) ||
2064 (suspect_dma >= cur_seg->dma &&
2065 suspect_dma <= end_trb_dma))
2066 return cur_seg;
2067 }
2068 return NULL;
2069 } else {
2070 /* Might still be somewhere in this segment */
2071 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2072 return cur_seg;
2073 }
2074 cur_seg = cur_seg->next;
2075 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2076 } while (cur_seg != start_seg);
2077
2078 return NULL;
2079}
2080
2081static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2082 struct xhci_virt_ep *ep)
2083{
2084 /*
2085 * As part of low/full-speed endpoint-halt processing
2086 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2087 */
2088 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2089 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2090 !(ep->ep_state & EP_CLEARING_TT)) {
2091 ep->ep_state |= EP_CLEARING_TT;
2092 td->urb->ep->hcpriv = td->urb->dev;
2093 if (usb_hub_clear_tt_buffer(td->urb))
2094 ep->ep_state &= ~EP_CLEARING_TT;
2095 }
2096}
2097
2098/* Check if an error has halted the endpoint ring. The class driver will
2099 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2100 * However, a babble and other errors also halt the endpoint ring, and the class
2101 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2102 * Ring Dequeue Pointer command manually.
2103 */
2104static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2105 struct xhci_ep_ctx *ep_ctx,
2106 unsigned int trb_comp_code)
2107{
2108 /* TRB completion codes that may require a manual halt cleanup */
2109 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2110 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2111 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2112 /* The 0.95 spec says a babbling control endpoint
2113 * is not halted. The 0.96 spec says it is. Some HW
2114 * claims to be 0.95 compliant, but it halts the control
2115 * endpoint anyway. Check if a babble halted the
2116 * endpoint.
2117 */
2118 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2119 return 1;
2120
2121 return 0;
2122}
2123
2124int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2125{
2126 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2127 /* Vendor defined "informational" completion code,
2128 * treat as not-an-error.
2129 */
2130 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2131 trb_comp_code);
2132 xhci_dbg(xhci, "Treating code as success.\n");
2133 return 1;
2134 }
2135 return 0;
2136}
2137
2138static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2139 struct xhci_ring *ep_ring, struct xhci_td *td,
2140 u32 trb_comp_code)
2141{
2142 struct xhci_ep_ctx *ep_ctx;
2143
2144 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2145
2146 switch (trb_comp_code) {
2147 case COMP_STOPPED_LENGTH_INVALID:
2148 case COMP_STOPPED_SHORT_PACKET:
2149 case COMP_STOPPED:
2150 /*
2151 * The "Stop Endpoint" completion will take care of any
2152 * stopped TDs. A stopped TD may be restarted, so don't update
2153 * the ring dequeue pointer or take this TD off any lists yet.
2154 */
2155 return 0;
2156 case COMP_USB_TRANSACTION_ERROR:
2157 case COMP_BABBLE_DETECTED_ERROR:
2158 case COMP_SPLIT_TRANSACTION_ERROR:
2159 /*
2160 * If endpoint context state is not halted we might be
2161 * racing with a reset endpoint command issued by a unsuccessful
2162 * stop endpoint completion (context error). In that case the
2163 * td should be on the cancelled list, and EP_HALTED flag set.
2164 *
2165 * Or then it's not halted due to the 0.95 spec stating that a
2166 * babbling control endpoint should not halt. The 0.96 spec
2167 * again says it should. Some HW claims to be 0.95 compliant,
2168 * but it halts the control endpoint anyway.
2169 */
2170 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2171 /*
2172 * If EP_HALTED is set and TD is on the cancelled list
2173 * the TD and dequeue pointer will be handled by reset
2174 * ep command completion
2175 */
2176 if ((ep->ep_state & EP_HALTED) &&
2177 !list_empty(&td->cancelled_td_list)) {
2178 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2179 (unsigned long long)xhci_trb_virt_to_dma(
2180 td->start_seg, td->first_trb));
2181 return 0;
2182 }
2183 /* endpoint not halted, don't reset it */
2184 break;
2185 }
2186 /* Almost same procedure as for STALL_ERROR below */
2187 xhci_clear_hub_tt_buffer(xhci, td, ep);
2188 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2189 return 0;
2190 case COMP_STALL_ERROR:
2191 /*
2192 * xhci internal endpoint state will go to a "halt" state for
2193 * any stall, including default control pipe protocol stall.
2194 * To clear the host side halt we need to issue a reset endpoint
2195 * command, followed by a set dequeue command to move past the
2196 * TD.
2197 * Class drivers clear the device side halt from a functional
2198 * stall later. Hub TT buffer should only be cleared for FS/LS
2199 * devices behind HS hubs for functional stalls.
2200 */
2201 if (ep->ep_index != 0)
2202 xhci_clear_hub_tt_buffer(xhci, td, ep);
2203
2204 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2205
2206 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2207 default:
2208 break;
2209 }
2210
2211 /* Update ring dequeue pointer */
2212 ep_ring->dequeue = td->last_trb;
2213 ep_ring->deq_seg = td->last_trb_seg;
2214 ep_ring->num_trbs_free += td->num_trbs - 1;
2215 inc_deq(xhci, ep_ring);
2216
2217 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2218}
2219
2220/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2221static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2222 union xhci_trb *stop_trb)
2223{
2224 u32 sum;
2225 union xhci_trb *trb = ring->dequeue;
2226 struct xhci_segment *seg = ring->deq_seg;
2227
2228 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2229 if (!trb_is_noop(trb) && !trb_is_link(trb))
2230 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2231 }
2232 return sum;
2233}
2234
2235/*
2236 * Process control tds, update urb status and actual_length.
2237 */
2238static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2239 struct xhci_ring *ep_ring, struct xhci_td *td,
2240 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2241{
2242 struct xhci_ep_ctx *ep_ctx;
2243 u32 trb_comp_code;
2244 u32 remaining, requested;
2245 u32 trb_type;
2246
2247 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2248 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2249 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2250 requested = td->urb->transfer_buffer_length;
2251 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2252
2253 switch (trb_comp_code) {
2254 case COMP_SUCCESS:
2255 if (trb_type != TRB_STATUS) {
2256 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2257 (trb_type == TRB_DATA) ? "data" : "setup");
2258 td->status = -ESHUTDOWN;
2259 break;
2260 }
2261 td->status = 0;
2262 break;
2263 case COMP_SHORT_PACKET:
2264 td->status = 0;
2265 break;
2266 case COMP_STOPPED_SHORT_PACKET:
2267 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2268 td->urb->actual_length = remaining;
2269 else
2270 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2271 goto finish_td;
2272 case COMP_STOPPED:
2273 switch (trb_type) {
2274 case TRB_SETUP:
2275 td->urb->actual_length = 0;
2276 goto finish_td;
2277 case TRB_DATA:
2278 case TRB_NORMAL:
2279 td->urb->actual_length = requested - remaining;
2280 goto finish_td;
2281 case TRB_STATUS:
2282 td->urb->actual_length = requested;
2283 goto finish_td;
2284 default:
2285 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2286 trb_type);
2287 goto finish_td;
2288 }
2289 case COMP_STOPPED_LENGTH_INVALID:
2290 goto finish_td;
2291 default:
2292 if (!xhci_requires_manual_halt_cleanup(xhci,
2293 ep_ctx, trb_comp_code))
2294 break;
2295 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2296 trb_comp_code, ep->ep_index);
2297 fallthrough;
2298 case COMP_STALL_ERROR:
2299 /* Did we transfer part of the data (middle) phase? */
2300 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2301 td->urb->actual_length = requested - remaining;
2302 else if (!td->urb_length_set)
2303 td->urb->actual_length = 0;
2304 goto finish_td;
2305 }
2306
2307 /* stopped at setup stage, no data transferred */
2308 if (trb_type == TRB_SETUP)
2309 goto finish_td;
2310
2311 /*
2312 * if on data stage then update the actual_length of the URB and flag it
2313 * as set, so it won't be overwritten in the event for the last TRB.
2314 */
2315 if (trb_type == TRB_DATA ||
2316 trb_type == TRB_NORMAL) {
2317 td->urb_length_set = true;
2318 td->urb->actual_length = requested - remaining;
2319 xhci_dbg(xhci, "Waiting for status stage event\n");
2320 return 0;
2321 }
2322
2323 /* at status stage */
2324 if (!td->urb_length_set)
2325 td->urb->actual_length = requested;
2326
2327finish_td:
2328 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2329}
2330
2331/*
2332 * Process isochronous tds, update urb packet status and actual_length.
2333 */
2334static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2335 struct xhci_ring *ep_ring, struct xhci_td *td,
2336 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2337{
2338 struct urb_priv *urb_priv;
2339 int idx;
2340 struct usb_iso_packet_descriptor *frame;
2341 u32 trb_comp_code;
2342 bool sum_trbs_for_length = false;
2343 u32 remaining, requested, ep_trb_len;
2344 int short_framestatus;
2345
2346 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2347 urb_priv = td->urb->hcpriv;
2348 idx = urb_priv->num_tds_done;
2349 frame = &td->urb->iso_frame_desc[idx];
2350 requested = frame->length;
2351 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2352 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2353 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2354 -EREMOTEIO : 0;
2355
2356 /* handle completion code */
2357 switch (trb_comp_code) {
2358 case COMP_SUCCESS:
2359 if (remaining) {
2360 frame->status = short_framestatus;
2361 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2362 sum_trbs_for_length = true;
2363 break;
2364 }
2365 frame->status = 0;
2366 break;
2367 case COMP_SHORT_PACKET:
2368 frame->status = short_framestatus;
2369 sum_trbs_for_length = true;
2370 break;
2371 case COMP_BANDWIDTH_OVERRUN_ERROR:
2372 frame->status = -ECOMM;
2373 break;
2374 case COMP_ISOCH_BUFFER_OVERRUN:
2375 case COMP_BABBLE_DETECTED_ERROR:
2376 frame->status = -EOVERFLOW;
2377 break;
2378 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2379 case COMP_STALL_ERROR:
2380 frame->status = -EPROTO;
2381 break;
2382 case COMP_USB_TRANSACTION_ERROR:
2383 frame->status = -EPROTO;
2384 if (ep_trb != td->last_trb)
2385 return 0;
2386 break;
2387 case COMP_STOPPED:
2388 sum_trbs_for_length = true;
2389 break;
2390 case COMP_STOPPED_SHORT_PACKET:
2391 /* field normally containing residue now contains tranferred */
2392 frame->status = short_framestatus;
2393 requested = remaining;
2394 break;
2395 case COMP_STOPPED_LENGTH_INVALID:
2396 requested = 0;
2397 remaining = 0;
2398 break;
2399 default:
2400 sum_trbs_for_length = true;
2401 frame->status = -1;
2402 break;
2403 }
2404
2405 if (sum_trbs_for_length)
2406 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2407 ep_trb_len - remaining;
2408 else
2409 frame->actual_length = requested;
2410
2411 td->urb->actual_length += frame->actual_length;
2412
2413 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2414}
2415
2416static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2417 struct xhci_virt_ep *ep, int status)
2418{
2419 struct urb_priv *urb_priv;
2420 struct usb_iso_packet_descriptor *frame;
2421 int idx;
2422
2423 urb_priv = td->urb->hcpriv;
2424 idx = urb_priv->num_tds_done;
2425 frame = &td->urb->iso_frame_desc[idx];
2426
2427 /* The transfer is partly done. */
2428 frame->status = -EXDEV;
2429
2430 /* calc actual length */
2431 frame->actual_length = 0;
2432
2433 /* Update ring dequeue pointer */
2434 ep->ring->dequeue = td->last_trb;
2435 ep->ring->deq_seg = td->last_trb_seg;
2436 ep->ring->num_trbs_free += td->num_trbs - 1;
2437 inc_deq(xhci, ep->ring);
2438
2439 return xhci_td_cleanup(xhci, td, ep->ring, status);
2440}
2441
2442/*
2443 * Process bulk and interrupt tds, update urb status and actual_length.
2444 */
2445static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2446 struct xhci_ring *ep_ring, struct xhci_td *td,
2447 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2448{
2449 struct xhci_slot_ctx *slot_ctx;
2450 u32 trb_comp_code;
2451 u32 remaining, requested, ep_trb_len;
2452
2453 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2454 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2455 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2456 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2457 requested = td->urb->transfer_buffer_length;
2458
2459 switch (trb_comp_code) {
2460 case COMP_SUCCESS:
2461 ep->err_count = 0;
2462 /* handle success with untransferred data as short packet */
2463 if (ep_trb != td->last_trb || remaining) {
2464 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2465 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2466 td->urb->ep->desc.bEndpointAddress,
2467 requested, remaining);
2468 }
2469 td->status = 0;
2470 break;
2471 case COMP_SHORT_PACKET:
2472 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2473 td->urb->ep->desc.bEndpointAddress,
2474 requested, remaining);
2475 td->status = 0;
2476 break;
2477 case COMP_STOPPED_SHORT_PACKET:
2478 td->urb->actual_length = remaining;
2479 goto finish_td;
2480 case COMP_STOPPED_LENGTH_INVALID:
2481 /* stopped on ep trb with invalid length, exclude it */
2482 ep_trb_len = 0;
2483 remaining = 0;
2484 break;
2485 case COMP_USB_TRANSACTION_ERROR:
2486 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2487 (ep->err_count++ > MAX_SOFT_RETRY) ||
2488 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2489 break;
2490
2491 td->status = 0;
2492
2493 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2494 return 0;
2495 default:
2496 /* do nothing */
2497 break;
2498 }
2499
2500 if (ep_trb == td->last_trb)
2501 td->urb->actual_length = requested - remaining;
2502 else
2503 td->urb->actual_length =
2504 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2505 ep_trb_len - remaining;
2506finish_td:
2507 if (remaining > requested) {
2508 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2509 remaining);
2510 td->urb->actual_length = 0;
2511 }
2512
2513 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2514}
2515
2516/*
2517 * If this function returns an error condition, it means it got a Transfer
2518 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2519 * At this point, the host controller is probably hosed and should be reset.
2520 */
2521static int handle_tx_event(struct xhci_hcd *xhci,
2522 struct xhci_transfer_event *event)
2523{
2524 struct xhci_virt_ep *ep;
2525 struct xhci_ring *ep_ring;
2526 unsigned int slot_id;
2527 int ep_index;
2528 struct xhci_td *td = NULL;
2529 dma_addr_t ep_trb_dma;
2530 struct xhci_segment *ep_seg;
2531 union xhci_trb *ep_trb;
2532 int status = -EINPROGRESS;
2533 struct xhci_ep_ctx *ep_ctx;
2534 struct list_head *tmp;
2535 u32 trb_comp_code;
2536 int td_num = 0;
2537 bool handling_skipped_tds = false;
2538
2539 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2540 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2541 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2542 ep_trb_dma = le64_to_cpu(event->buffer);
2543
2544 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2545 if (!ep) {
2546 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2547 goto err_out;
2548 }
2549
2550 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2551 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2552
2553 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2554 xhci_err(xhci,
2555 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2556 slot_id, ep_index);
2557 goto err_out;
2558 }
2559
2560 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2561 if (!ep_ring) {
2562 switch (trb_comp_code) {
2563 case COMP_STALL_ERROR:
2564 case COMP_USB_TRANSACTION_ERROR:
2565 case COMP_INVALID_STREAM_TYPE_ERROR:
2566 case COMP_INVALID_STREAM_ID_ERROR:
2567 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2568 ep_index);
2569 if (ep->err_count++ > MAX_SOFT_RETRY)
2570 xhci_handle_halted_endpoint(xhci, ep, NULL,
2571 EP_HARD_RESET);
2572 else
2573 xhci_handle_halted_endpoint(xhci, ep, NULL,
2574 EP_SOFT_RESET);
2575 goto cleanup;
2576 case COMP_RING_UNDERRUN:
2577 case COMP_RING_OVERRUN:
2578 case COMP_STOPPED_LENGTH_INVALID:
2579 goto cleanup;
2580 default:
2581 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2582 slot_id, ep_index);
2583 goto err_out;
2584 }
2585 }
2586
2587 /* Count current td numbers if ep->skip is set */
2588 if (ep->skip) {
2589 list_for_each(tmp, &ep_ring->td_list)
2590 td_num++;
2591 }
2592
2593 /* Look for common error cases */
2594 switch (trb_comp_code) {
2595 /* Skip codes that require special handling depending on
2596 * transfer type
2597 */
2598 case COMP_SUCCESS:
2599 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2600 break;
2601 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2602 ep_ring->last_td_was_short)
2603 trb_comp_code = COMP_SHORT_PACKET;
2604 else
2605 xhci_warn_ratelimited(xhci,
2606 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2607 slot_id, ep_index);
2608 break;
2609 case COMP_SHORT_PACKET:
2610 break;
2611 /* Completion codes for endpoint stopped state */
2612 case COMP_STOPPED:
2613 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2614 slot_id, ep_index);
2615 break;
2616 case COMP_STOPPED_LENGTH_INVALID:
2617 xhci_dbg(xhci,
2618 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2619 slot_id, ep_index);
2620 break;
2621 case COMP_STOPPED_SHORT_PACKET:
2622 xhci_dbg(xhci,
2623 "Stopped with short packet transfer detected for slot %u ep %u\n",
2624 slot_id, ep_index);
2625 break;
2626 /* Completion codes for endpoint halted state */
2627 case COMP_STALL_ERROR:
2628 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2629 ep_index);
2630 status = -EPIPE;
2631 break;
2632 case COMP_SPLIT_TRANSACTION_ERROR:
2633 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2634 slot_id, ep_index);
2635 status = -EPROTO;
2636 break;
2637 case COMP_USB_TRANSACTION_ERROR:
2638 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2639 slot_id, ep_index);
2640 status = -EPROTO;
2641 break;
2642 case COMP_BABBLE_DETECTED_ERROR:
2643 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2644 slot_id, ep_index);
2645 status = -EOVERFLOW;
2646 break;
2647 /* Completion codes for endpoint error state */
2648 case COMP_TRB_ERROR:
2649 xhci_warn(xhci,
2650 "WARN: TRB error for slot %u ep %u on endpoint\n",
2651 slot_id, ep_index);
2652 status = -EILSEQ;
2653 break;
2654 /* completion codes not indicating endpoint state change */
2655 case COMP_DATA_BUFFER_ERROR:
2656 xhci_warn(xhci,
2657 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2658 slot_id, ep_index);
2659 status = -ENOSR;
2660 break;
2661 case COMP_BANDWIDTH_OVERRUN_ERROR:
2662 xhci_warn(xhci,
2663 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2664 slot_id, ep_index);
2665 break;
2666 case COMP_ISOCH_BUFFER_OVERRUN:
2667 xhci_warn(xhci,
2668 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2669 slot_id, ep_index);
2670 break;
2671 case COMP_RING_UNDERRUN:
2672 /*
2673 * When the Isoch ring is empty, the xHC will generate
2674 * a Ring Overrun Event for IN Isoch endpoint or Ring
2675 * Underrun Event for OUT Isoch endpoint.
2676 */
2677 xhci_dbg(xhci, "underrun event on endpoint\n");
2678 if (!list_empty(&ep_ring->td_list))
2679 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2680 "still with TDs queued?\n",
2681 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2682 ep_index);
2683 goto cleanup;
2684 case COMP_RING_OVERRUN:
2685 xhci_dbg(xhci, "overrun event on endpoint\n");
2686 if (!list_empty(&ep_ring->td_list))
2687 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2688 "still with TDs queued?\n",
2689 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2690 ep_index);
2691 goto cleanup;
2692 case COMP_MISSED_SERVICE_ERROR:
2693 /*
2694 * When encounter missed service error, one or more isoc tds
2695 * may be missed by xHC.
2696 * Set skip flag of the ep_ring; Complete the missed tds as
2697 * short transfer when process the ep_ring next time.
2698 */
2699 ep->skip = true;
2700 xhci_dbg(xhci,
2701 "Miss service interval error for slot %u ep %u, set skip flag\n",
2702 slot_id, ep_index);
2703 goto cleanup;
2704 case COMP_NO_PING_RESPONSE_ERROR:
2705 ep->skip = true;
2706 xhci_dbg(xhci,
2707 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2708 slot_id, ep_index);
2709 goto cleanup;
2710
2711 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2712 /* needs disable slot command to recover */
2713 xhci_warn(xhci,
2714 "WARN: detect an incompatible device for slot %u ep %u",
2715 slot_id, ep_index);
2716 status = -EPROTO;
2717 break;
2718 default:
2719 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2720 status = 0;
2721 break;
2722 }
2723 xhci_warn(xhci,
2724 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2725 trb_comp_code, slot_id, ep_index);
2726 goto cleanup;
2727 }
2728
2729 do {
2730 /* This TRB should be in the TD at the head of this ring's
2731 * TD list.
2732 */
2733 if (list_empty(&ep_ring->td_list)) {
2734 /*
2735 * Don't print wanings if it's due to a stopped endpoint
2736 * generating an extra completion event if the device
2737 * was suspended. Or, a event for the last TRB of a
2738 * short TD we already got a short event for.
2739 * The short TD is already removed from the TD list.
2740 */
2741
2742 if (!(trb_comp_code == COMP_STOPPED ||
2743 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2744 ep_ring->last_td_was_short)) {
2745 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2746 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2747 ep_index);
2748 }
2749 if (ep->skip) {
2750 ep->skip = false;
2751 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2752 slot_id, ep_index);
2753 }
2754 if (trb_comp_code == COMP_STALL_ERROR ||
2755 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2756 trb_comp_code)) {
2757 xhci_handle_halted_endpoint(xhci, ep, NULL,
2758 EP_HARD_RESET);
2759 }
2760 goto cleanup;
2761 }
2762
2763 /* We've skipped all the TDs on the ep ring when ep->skip set */
2764 if (ep->skip && td_num == 0) {
2765 ep->skip = false;
2766 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2767 slot_id, ep_index);
2768 goto cleanup;
2769 }
2770
2771 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2772 td_list);
2773 if (ep->skip)
2774 td_num--;
2775
2776 /* Is this a TRB in the currently executing TD? */
2777 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2778 td->last_trb, ep_trb_dma, false);
2779
2780 /*
2781 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2782 * is not in the current TD pointed by ep_ring->dequeue because
2783 * that the hardware dequeue pointer still at the previous TRB
2784 * of the current TD. The previous TRB maybe a Link TD or the
2785 * last TRB of the previous TD. The command completion handle
2786 * will take care the rest.
2787 */
2788 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2789 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2790 goto cleanup;
2791 }
2792
2793 if (!ep_seg) {
2794 if (!ep->skip ||
2795 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2796 /* Some host controllers give a spurious
2797 * successful event after a short transfer.
2798 * Ignore it.
2799 */
2800 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2801 ep_ring->last_td_was_short) {
2802 ep_ring->last_td_was_short = false;
2803 goto cleanup;
2804 }
2805 /* HC is busted, give up! */
2806 xhci_err(xhci,
2807 "ERROR Transfer event TRB DMA ptr not "
2808 "part of current TD ep_index %d "
2809 "comp_code %u\n", ep_index,
2810 trb_comp_code);
2811 trb_in_td(xhci, ep_ring->deq_seg,
2812 ep_ring->dequeue, td->last_trb,
2813 ep_trb_dma, true);
2814 return -ESHUTDOWN;
2815 }
2816
2817 skip_isoc_td(xhci, td, ep, status);
2818 goto cleanup;
2819 }
2820 if (trb_comp_code == COMP_SHORT_PACKET)
2821 ep_ring->last_td_was_short = true;
2822 else
2823 ep_ring->last_td_was_short = false;
2824
2825 if (ep->skip) {
2826 xhci_dbg(xhci,
2827 "Found td. Clear skip flag for slot %u ep %u.\n",
2828 slot_id, ep_index);
2829 ep->skip = false;
2830 }
2831
2832 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2833 sizeof(*ep_trb)];
2834
2835 trace_xhci_handle_transfer(ep_ring,
2836 (struct xhci_generic_trb *) ep_trb);
2837
2838 /*
2839 * No-op TRB could trigger interrupts in a case where
2840 * a URB was killed and a STALL_ERROR happens right
2841 * after the endpoint ring stopped. Reset the halted
2842 * endpoint. Otherwise, the endpoint remains stalled
2843 * indefinitely.
2844 */
2845
2846 if (trb_is_noop(ep_trb)) {
2847 if (trb_comp_code == COMP_STALL_ERROR ||
2848 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2849 trb_comp_code))
2850 xhci_handle_halted_endpoint(xhci, ep, td,
2851 EP_HARD_RESET);
2852 goto cleanup;
2853 }
2854
2855 td->status = status;
2856
2857 /* update the urb's actual_length and give back to the core */
2858 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2859 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2860 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2861 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2862 else
2863 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2864cleanup:
2865 handling_skipped_tds = ep->skip &&
2866 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2867 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2868
2869 /*
2870 * Do not update event ring dequeue pointer if we're in a loop
2871 * processing missed tds.
2872 */
2873 if (!handling_skipped_tds)
2874 inc_deq(xhci, xhci->event_ring);
2875
2876 /*
2877 * If ep->skip is set, it means there are missed tds on the
2878 * endpoint ring need to take care of.
2879 * Process them as short transfer until reach the td pointed by
2880 * the event.
2881 */
2882 } while (handling_skipped_tds);
2883
2884 return 0;
2885
2886err_out:
2887 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2888 (unsigned long long) xhci_trb_virt_to_dma(
2889 xhci->event_ring->deq_seg,
2890 xhci->event_ring->dequeue),
2891 lower_32_bits(le64_to_cpu(event->buffer)),
2892 upper_32_bits(le64_to_cpu(event->buffer)),
2893 le32_to_cpu(event->transfer_len),
2894 le32_to_cpu(event->flags));
2895 return -ENODEV;
2896}
2897
2898/*
2899 * This function handles all OS-owned events on the event ring. It may drop
2900 * xhci->lock between event processing (e.g. to pass up port status changes).
2901 * Returns >0 for "possibly more events to process" (caller should call again),
2902 * otherwise 0 if done. In future, <0 returns should indicate error code.
2903 */
2904static int xhci_handle_event(struct xhci_hcd *xhci)
2905{
2906 union xhci_trb *event;
2907 int update_ptrs = 1;
2908 u32 trb_type;
2909 int ret;
2910
2911 /* Event ring hasn't been allocated yet. */
2912 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2913 xhci_err(xhci, "ERROR event ring not ready\n");
2914 return -ENOMEM;
2915 }
2916
2917 event = xhci->event_ring->dequeue;
2918 /* Does the HC or OS own the TRB? */
2919 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2920 xhci->event_ring->cycle_state)
2921 return 0;
2922
2923 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2924
2925 /*
2926 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2927 * speculative reads of the event's flags/data below.
2928 */
2929 rmb();
2930 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2931 /* FIXME: Handle more event types. */
2932
2933 switch (trb_type) {
2934 case TRB_COMPLETION:
2935 handle_cmd_completion(xhci, &event->event_cmd);
2936 break;
2937 case TRB_PORT_STATUS:
2938 handle_port_status(xhci, event);
2939 update_ptrs = 0;
2940 break;
2941 case TRB_TRANSFER:
2942 ret = handle_tx_event(xhci, &event->trans_event);
2943 if (ret >= 0)
2944 update_ptrs = 0;
2945 break;
2946 case TRB_DEV_NOTE:
2947 handle_device_notification(xhci, event);
2948 break;
2949 default:
2950 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2951 handle_vendor_event(xhci, event, trb_type);
2952 else
2953 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2954 }
2955 /* Any of the above functions may drop and re-acquire the lock, so check
2956 * to make sure a watchdog timer didn't mark the host as non-responsive.
2957 */
2958 if (xhci->xhc_state & XHCI_STATE_DYING) {
2959 xhci_dbg(xhci, "xHCI host dying, returning from "
2960 "event handler.\n");
2961 return 0;
2962 }
2963
2964 if (update_ptrs)
2965 /* Update SW event ring dequeue pointer */
2966 inc_deq(xhci, xhci->event_ring);
2967
2968 /* Are there more items on the event ring? Caller will call us again to
2969 * check.
2970 */
2971 return 1;
2972}
2973
2974/*
2975 * Update Event Ring Dequeue Pointer:
2976 * - When all events have finished
2977 * - To avoid "Event Ring Full Error" condition
2978 */
2979static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2980 union xhci_trb *event_ring_deq)
2981{
2982 u64 temp_64;
2983 dma_addr_t deq;
2984
2985 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2986 /* If necessary, update the HW's version of the event ring deq ptr. */
2987 if (event_ring_deq != xhci->event_ring->dequeue) {
2988 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2989 xhci->event_ring->dequeue);
2990 if (deq == 0)
2991 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2992 /*
2993 * Per 4.9.4, Software writes to the ERDP register shall
2994 * always advance the Event Ring Dequeue Pointer value.
2995 */
2996 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2997 ((u64) deq & (u64) ~ERST_PTR_MASK))
2998 return;
2999
3000 /* Update HC event ring dequeue pointer */
3001 temp_64 &= ERST_PTR_MASK;
3002 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3003 }
3004
3005 /* Clear the event handler busy flag (RW1C) */
3006 temp_64 |= ERST_EHB;
3007 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3008}
3009
3010/*
3011 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3012 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3013 * indicators of an event TRB error, but we check the status *first* to be safe.
3014 */
3015irqreturn_t xhci_irq(struct usb_hcd *hcd)
3016{
3017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3018 union xhci_trb *event_ring_deq;
3019 irqreturn_t ret = IRQ_NONE;
3020 u64 temp_64;
3021 u32 status;
3022 int event_loop = 0;
3023
3024 spin_lock(&xhci->lock);
3025 /* Check if the xHC generated the interrupt, or the irq is shared */
3026 status = readl(&xhci->op_regs->status);
3027 if (status == ~(u32)0) {
3028 xhci_hc_died(xhci);
3029 ret = IRQ_HANDLED;
3030 goto out;
3031 }
3032
3033 if (!(status & STS_EINT))
3034 goto out;
3035
3036 if (status & STS_HCE) {
3037 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3038 goto out;
3039 }
3040
3041 if (status & STS_FATAL) {
3042 xhci_warn(xhci, "WARNING: Host System Error\n");
3043 xhci_halt(xhci);
3044 ret = IRQ_HANDLED;
3045 goto out;
3046 }
3047
3048 /*
3049 * Clear the op reg interrupt status first,
3050 * so we can receive interrupts from other MSI-X interrupters.
3051 * Write 1 to clear the interrupt status.
3052 */
3053 status |= STS_EINT;
3054 writel(status, &xhci->op_regs->status);
3055
3056 if (!hcd->msi_enabled) {
3057 u32 irq_pending;
3058 irq_pending = readl(&xhci->ir_set->irq_pending);
3059 irq_pending |= IMAN_IP;
3060 writel(irq_pending, &xhci->ir_set->irq_pending);
3061 }
3062
3063 if (xhci->xhc_state & XHCI_STATE_DYING ||
3064 xhci->xhc_state & XHCI_STATE_HALTED) {
3065 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3066 "Shouldn't IRQs be disabled?\n");
3067 /* Clear the event handler busy flag (RW1C);
3068 * the event ring should be empty.
3069 */
3070 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3071 xhci_write_64(xhci, temp_64 | ERST_EHB,
3072 &xhci->ir_set->erst_dequeue);
3073 ret = IRQ_HANDLED;
3074 goto out;
3075 }
3076
3077 event_ring_deq = xhci->event_ring->dequeue;
3078 /* FIXME this should be a delayed service routine
3079 * that clears the EHB.
3080 */
3081 while (xhci_handle_event(xhci) > 0) {
3082 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3083 continue;
3084 xhci_update_erst_dequeue(xhci, event_ring_deq);
3085 event_ring_deq = xhci->event_ring->dequeue;
3086
3087 /* ring is half-full, force isoc trbs to interrupt more often */
3088 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3089 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3090
3091 event_loop = 0;
3092 }
3093
3094 xhci_update_erst_dequeue(xhci, event_ring_deq);
3095 ret = IRQ_HANDLED;
3096
3097out:
3098 spin_unlock(&xhci->lock);
3099
3100 return ret;
3101}
3102
3103irqreturn_t xhci_msi_irq(int irq, void *hcd)
3104{
3105 return xhci_irq(hcd);
3106}
3107
3108/**** Endpoint Ring Operations ****/
3109
3110/*
3111 * Generic function for queueing a TRB on a ring.
3112 * The caller must have checked to make sure there's room on the ring.
3113 *
3114 * @more_trbs_coming: Will you enqueue more TRBs before calling
3115 * prepare_transfer()?
3116 */
3117static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3118 bool more_trbs_coming,
3119 u32 field1, u32 field2, u32 field3, u32 field4)
3120{
3121 struct xhci_generic_trb *trb;
3122
3123 trb = &ring->enqueue->generic;
3124 trb->field[0] = cpu_to_le32(field1);
3125 trb->field[1] = cpu_to_le32(field2);
3126 trb->field[2] = cpu_to_le32(field3);
3127 /* make sure TRB is fully written before giving it to the controller */
3128 wmb();
3129 trb->field[3] = cpu_to_le32(field4);
3130
3131 trace_xhci_queue_trb(ring, trb);
3132
3133 inc_enq(xhci, ring, more_trbs_coming);
3134}
3135
3136/*
3137 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3138 * FIXME allocate segments if the ring is full.
3139 */
3140static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3141 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3142{
3143 unsigned int num_trbs_needed;
3144 unsigned int link_trb_count = 0;
3145
3146 /* Make sure the endpoint has been added to xHC schedule */
3147 switch (ep_state) {
3148 case EP_STATE_DISABLED:
3149 /*
3150 * USB core changed config/interfaces without notifying us,
3151 * or hardware is reporting the wrong state.
3152 */
3153 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3154 return -ENOENT;
3155 case EP_STATE_ERROR:
3156 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3157 /* FIXME event handling code for error needs to clear it */
3158 /* XXX not sure if this should be -ENOENT or not */
3159 return -EINVAL;
3160 case EP_STATE_HALTED:
3161 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3162 break;
3163 case EP_STATE_STOPPED:
3164 case EP_STATE_RUNNING:
3165 break;
3166 default:
3167 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3168 /*
3169 * FIXME issue Configure Endpoint command to try to get the HC
3170 * back into a known state.
3171 */
3172 return -EINVAL;
3173 }
3174
3175 while (1) {
3176 if (room_on_ring(xhci, ep_ring, num_trbs))
3177 break;
3178
3179 if (ep_ring == xhci->cmd_ring) {
3180 xhci_err(xhci, "Do not support expand command ring\n");
3181 return -ENOMEM;
3182 }
3183
3184 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3185 "ERROR no room on ep ring, try ring expansion");
3186 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3187 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3188 mem_flags)) {
3189 xhci_err(xhci, "Ring expansion failed\n");
3190 return -ENOMEM;
3191 }
3192 }
3193
3194 while (trb_is_link(ep_ring->enqueue)) {
3195 /* If we're not dealing with 0.95 hardware or isoc rings
3196 * on AMD 0.96 host, clear the chain bit.
3197 */
3198 if (!xhci_link_trb_quirk(xhci) &&
3199 !(ep_ring->type == TYPE_ISOC &&
3200 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3201 ep_ring->enqueue->link.control &=
3202 cpu_to_le32(~TRB_CHAIN);
3203 else
3204 ep_ring->enqueue->link.control |=
3205 cpu_to_le32(TRB_CHAIN);
3206
3207 wmb();
3208 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3209
3210 /* Toggle the cycle bit after the last ring segment. */
3211 if (link_trb_toggles_cycle(ep_ring->enqueue))
3212 ep_ring->cycle_state ^= 1;
3213
3214 ep_ring->enq_seg = ep_ring->enq_seg->next;
3215 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3216
3217 /* prevent infinite loop if all first trbs are link trbs */
3218 if (link_trb_count++ > ep_ring->num_segs) {
3219 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3220 return -EINVAL;
3221 }
3222 }
3223
3224 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3225 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3226 return -EINVAL;
3227 }
3228
3229 return 0;
3230}
3231
3232static int prepare_transfer(struct xhci_hcd *xhci,
3233 struct xhci_virt_device *xdev,
3234 unsigned int ep_index,
3235 unsigned int stream_id,
3236 unsigned int num_trbs,
3237 struct urb *urb,
3238 unsigned int td_index,
3239 gfp_t mem_flags)
3240{
3241 int ret;
3242 struct urb_priv *urb_priv;
3243 struct xhci_td *td;
3244 struct xhci_ring *ep_ring;
3245 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3246
3247 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3248 stream_id);
3249 if (!ep_ring) {
3250 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3251 stream_id);
3252 return -EINVAL;
3253 }
3254
3255 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3256 num_trbs, mem_flags);
3257 if (ret)
3258 return ret;
3259
3260 urb_priv = urb->hcpriv;
3261 td = &urb_priv->td[td_index];
3262
3263 INIT_LIST_HEAD(&td->td_list);
3264 INIT_LIST_HEAD(&td->cancelled_td_list);
3265
3266 if (td_index == 0) {
3267 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3268 if (unlikely(ret))
3269 return ret;
3270 }
3271
3272 td->urb = urb;
3273 /* Add this TD to the tail of the endpoint ring's TD list */
3274 list_add_tail(&td->td_list, &ep_ring->td_list);
3275 td->start_seg = ep_ring->enq_seg;
3276 td->first_trb = ep_ring->enqueue;
3277
3278 return 0;
3279}
3280
3281unsigned int count_trbs(u64 addr, u64 len)
3282{
3283 unsigned int num_trbs;
3284
3285 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3286 TRB_MAX_BUFF_SIZE);
3287 if (num_trbs == 0)
3288 num_trbs++;
3289
3290 return num_trbs;
3291}
3292
3293static inline unsigned int count_trbs_needed(struct urb *urb)
3294{
3295 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3296}
3297
3298static unsigned int count_sg_trbs_needed(struct urb *urb)
3299{
3300 struct scatterlist *sg;
3301 unsigned int i, len, full_len, num_trbs = 0;
3302
3303 full_len = urb->transfer_buffer_length;
3304
3305 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3306 len = sg_dma_len(sg);
3307 num_trbs += count_trbs(sg_dma_address(sg), len);
3308 len = min_t(unsigned int, len, full_len);
3309 full_len -= len;
3310 if (full_len == 0)
3311 break;
3312 }
3313
3314 return num_trbs;
3315}
3316
3317static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3318{
3319 u64 addr, len;
3320
3321 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3322 len = urb->iso_frame_desc[i].length;
3323
3324 return count_trbs(addr, len);
3325}
3326
3327static void check_trb_math(struct urb *urb, int running_total)
3328{
3329 if (unlikely(running_total != urb->transfer_buffer_length))
3330 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3331 "queued %#x (%d), asked for %#x (%d)\n",
3332 __func__,
3333 urb->ep->desc.bEndpointAddress,
3334 running_total, running_total,
3335 urb->transfer_buffer_length,
3336 urb->transfer_buffer_length);
3337}
3338
3339static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3340 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3341 struct xhci_generic_trb *start_trb)
3342{
3343 /*
3344 * Pass all the TRBs to the hardware at once and make sure this write
3345 * isn't reordered.
3346 */
3347 wmb();
3348 if (start_cycle)
3349 start_trb->field[3] |= cpu_to_le32(start_cycle);
3350 else
3351 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3352 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3353}
3354
3355static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3356 struct xhci_ep_ctx *ep_ctx)
3357{
3358 int xhci_interval;
3359 int ep_interval;
3360
3361 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3362 ep_interval = urb->interval;
3363
3364 /* Convert to microframes */
3365 if (urb->dev->speed == USB_SPEED_LOW ||
3366 urb->dev->speed == USB_SPEED_FULL)
3367 ep_interval *= 8;
3368
3369 /* FIXME change this to a warning and a suggestion to use the new API
3370 * to set the polling interval (once the API is added).
3371 */
3372 if (xhci_interval != ep_interval) {
3373 dev_dbg_ratelimited(&urb->dev->dev,
3374 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3375 ep_interval, ep_interval == 1 ? "" : "s",
3376 xhci_interval, xhci_interval == 1 ? "" : "s");
3377 urb->interval = xhci_interval;
3378 /* Convert back to frames for LS/FS devices */
3379 if (urb->dev->speed == USB_SPEED_LOW ||
3380 urb->dev->speed == USB_SPEED_FULL)
3381 urb->interval /= 8;
3382 }
3383}
3384
3385/*
3386 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3387 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3388 * (comprised of sg list entries) can take several service intervals to
3389 * transmit.
3390 */
3391int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3392 struct urb *urb, int slot_id, unsigned int ep_index)
3393{
3394 struct xhci_ep_ctx *ep_ctx;
3395
3396 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3397 check_interval(xhci, urb, ep_ctx);
3398
3399 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3400}
3401
3402/*
3403 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3404 * packets remaining in the TD (*not* including this TRB).
3405 *
3406 * Total TD packet count = total_packet_count =
3407 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3408 *
3409 * Packets transferred up to and including this TRB = packets_transferred =
3410 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3411 *
3412 * TD size = total_packet_count - packets_transferred
3413 *
3414 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3415 * including this TRB, right shifted by 10
3416 *
3417 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3418 * This is taken care of in the TRB_TD_SIZE() macro
3419 *
3420 * The last TRB in a TD must have the TD size set to zero.
3421 */
3422static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3423 int trb_buff_len, unsigned int td_total_len,
3424 struct urb *urb, bool more_trbs_coming)
3425{
3426 u32 maxp, total_packet_count;
3427
3428 /* MTK xHCI 0.96 contains some features from 1.0 */
3429 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3430 return ((td_total_len - transferred) >> 10);
3431
3432 /* One TRB with a zero-length data packet. */
3433 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3434 trb_buff_len == td_total_len)
3435 return 0;
3436
3437 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3438 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3439 trb_buff_len = 0;
3440
3441 maxp = usb_endpoint_maxp(&urb->ep->desc);
3442 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3443
3444 /* Queueing functions don't count the current TRB into transferred */
3445 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3446}
3447
3448
3449static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3450 u32 *trb_buff_len, struct xhci_segment *seg)
3451{
3452 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3453 unsigned int unalign;
3454 unsigned int max_pkt;
3455 u32 new_buff_len;
3456 size_t len;
3457
3458 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3459 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3460
3461 /* we got lucky, last normal TRB data on segment is packet aligned */
3462 if (unalign == 0)
3463 return 0;
3464
3465 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3466 unalign, *trb_buff_len);
3467
3468 /* is the last nornal TRB alignable by splitting it */
3469 if (*trb_buff_len > unalign) {
3470 *trb_buff_len -= unalign;
3471 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3472 return 0;
3473 }
3474
3475 /*
3476 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3477 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3478 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3479 */
3480 new_buff_len = max_pkt - (enqd_len % max_pkt);
3481
3482 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3483 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3484
3485 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3486 if (usb_urb_dir_out(urb)) {
3487 if (urb->num_sgs) {
3488 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3489 seg->bounce_buf, new_buff_len, enqd_len);
3490 if (len != new_buff_len)
3491 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3492 len, new_buff_len);
3493 } else {
3494 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3495 }
3496
3497 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3498 max_pkt, DMA_TO_DEVICE);
3499 } else {
3500 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3501 max_pkt, DMA_FROM_DEVICE);
3502 }
3503
3504 if (dma_mapping_error(dev, seg->bounce_dma)) {
3505 /* try without aligning. Some host controllers survive */
3506 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3507 return 0;
3508 }
3509 *trb_buff_len = new_buff_len;
3510 seg->bounce_len = new_buff_len;
3511 seg->bounce_offs = enqd_len;
3512
3513 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3514
3515 return 1;
3516}
3517
3518/* This is very similar to what ehci-q.c qtd_fill() does */
3519int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3520 struct urb *urb, int slot_id, unsigned int ep_index)
3521{
3522 struct xhci_ring *ring;
3523 struct urb_priv *urb_priv;
3524 struct xhci_td *td;
3525 struct xhci_generic_trb *start_trb;
3526 struct scatterlist *sg = NULL;
3527 bool more_trbs_coming = true;
3528 bool need_zero_pkt = false;
3529 bool first_trb = true;
3530 unsigned int num_trbs;
3531 unsigned int start_cycle, num_sgs = 0;
3532 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3533 int sent_len, ret;
3534 u32 field, length_field, remainder;
3535 u64 addr, send_addr;
3536
3537 ring = xhci_urb_to_transfer_ring(xhci, urb);
3538 if (!ring)
3539 return -EINVAL;
3540
3541 full_len = urb->transfer_buffer_length;
3542 /* If we have scatter/gather list, we use it. */
3543 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3544 num_sgs = urb->num_mapped_sgs;
3545 sg = urb->sg;
3546 addr = (u64) sg_dma_address(sg);
3547 block_len = sg_dma_len(sg);
3548 num_trbs = count_sg_trbs_needed(urb);
3549 } else {
3550 num_trbs = count_trbs_needed(urb);
3551 addr = (u64) urb->transfer_dma;
3552 block_len = full_len;
3553 }
3554 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3555 ep_index, urb->stream_id,
3556 num_trbs, urb, 0, mem_flags);
3557 if (unlikely(ret < 0))
3558 return ret;
3559
3560 urb_priv = urb->hcpriv;
3561
3562 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3563 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3564 need_zero_pkt = true;
3565
3566 td = &urb_priv->td[0];
3567
3568 /*
3569 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3570 * until we've finished creating all the other TRBs. The ring's cycle
3571 * state may change as we enqueue the other TRBs, so save it too.
3572 */
3573 start_trb = &ring->enqueue->generic;
3574 start_cycle = ring->cycle_state;
3575 send_addr = addr;
3576
3577 /* Queue the TRBs, even if they are zero-length */
3578 for (enqd_len = 0; first_trb || enqd_len < full_len;
3579 enqd_len += trb_buff_len) {
3580 field = TRB_TYPE(TRB_NORMAL);
3581
3582 /* TRB buffer should not cross 64KB boundaries */
3583 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3584 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3585
3586 if (enqd_len + trb_buff_len > full_len)
3587 trb_buff_len = full_len - enqd_len;
3588
3589 /* Don't change the cycle bit of the first TRB until later */
3590 if (first_trb) {
3591 first_trb = false;
3592 if (start_cycle == 0)
3593 field |= TRB_CYCLE;
3594 } else
3595 field |= ring->cycle_state;
3596
3597 /* Chain all the TRBs together; clear the chain bit in the last
3598 * TRB to indicate it's the last TRB in the chain.
3599 */
3600 if (enqd_len + trb_buff_len < full_len) {
3601 field |= TRB_CHAIN;
3602 if (trb_is_link(ring->enqueue + 1)) {
3603 if (xhci_align_td(xhci, urb, enqd_len,
3604 &trb_buff_len,
3605 ring->enq_seg)) {
3606 send_addr = ring->enq_seg->bounce_dma;
3607 /* assuming TD won't span 2 segs */
3608 td->bounce_seg = ring->enq_seg;
3609 }
3610 }
3611 }
3612 if (enqd_len + trb_buff_len >= full_len) {
3613 field &= ~TRB_CHAIN;
3614 field |= TRB_IOC;
3615 more_trbs_coming = false;
3616 td->last_trb = ring->enqueue;
3617 td->last_trb_seg = ring->enq_seg;
3618 if (xhci_urb_suitable_for_idt(urb)) {
3619 memcpy(&send_addr, urb->transfer_buffer,
3620 trb_buff_len);
3621 le64_to_cpus(&send_addr);
3622 field |= TRB_IDT;
3623 }
3624 }
3625
3626 /* Only set interrupt on short packet for IN endpoints */
3627 if (usb_urb_dir_in(urb))
3628 field |= TRB_ISP;
3629
3630 /* Set the TRB length, TD size, and interrupter fields. */
3631 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3632 full_len, urb, more_trbs_coming);
3633
3634 length_field = TRB_LEN(trb_buff_len) |
3635 TRB_TD_SIZE(remainder) |
3636 TRB_INTR_TARGET(0);
3637
3638 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3639 lower_32_bits(send_addr),
3640 upper_32_bits(send_addr),
3641 length_field,
3642 field);
3643 td->num_trbs++;
3644 addr += trb_buff_len;
3645 sent_len = trb_buff_len;
3646
3647 while (sg && sent_len >= block_len) {
3648 /* New sg entry */
3649 --num_sgs;
3650 sent_len -= block_len;
3651 sg = sg_next(sg);
3652 if (num_sgs != 0 && sg) {
3653 block_len = sg_dma_len(sg);
3654 addr = (u64) sg_dma_address(sg);
3655 addr += sent_len;
3656 }
3657 }
3658 block_len -= sent_len;
3659 send_addr = addr;
3660 }
3661
3662 if (need_zero_pkt) {
3663 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3664 ep_index, urb->stream_id,
3665 1, urb, 1, mem_flags);
3666 urb_priv->td[1].last_trb = ring->enqueue;
3667 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3668 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3669 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3670 urb_priv->td[1].num_trbs++;
3671 }
3672
3673 check_trb_math(urb, enqd_len);
3674 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3675 start_cycle, start_trb);
3676 return 0;
3677}
3678
3679/* Caller must have locked xhci->lock */
3680int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3681 struct urb *urb, int slot_id, unsigned int ep_index)
3682{
3683 struct xhci_ring *ep_ring;
3684 int num_trbs;
3685 int ret;
3686 struct usb_ctrlrequest *setup;
3687 struct xhci_generic_trb *start_trb;
3688 int start_cycle;
3689 u32 field;
3690 struct urb_priv *urb_priv;
3691 struct xhci_td *td;
3692
3693 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3694 if (!ep_ring)
3695 return -EINVAL;
3696
3697 /*
3698 * Need to copy setup packet into setup TRB, so we can't use the setup
3699 * DMA address.
3700 */
3701 if (!urb->setup_packet)
3702 return -EINVAL;
3703
3704 /* 1 TRB for setup, 1 for status */
3705 num_trbs = 2;
3706 /*
3707 * Don't need to check if we need additional event data and normal TRBs,
3708 * since data in control transfers will never get bigger than 16MB
3709 * XXX: can we get a buffer that crosses 64KB boundaries?
3710 */
3711 if (urb->transfer_buffer_length > 0)
3712 num_trbs++;
3713 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3714 ep_index, urb->stream_id,
3715 num_trbs, urb, 0, mem_flags);
3716 if (ret < 0)
3717 return ret;
3718
3719 urb_priv = urb->hcpriv;
3720 td = &urb_priv->td[0];
3721 td->num_trbs = num_trbs;
3722
3723 /*
3724 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3725 * until we've finished creating all the other TRBs. The ring's cycle
3726 * state may change as we enqueue the other TRBs, so save it too.
3727 */
3728 start_trb = &ep_ring->enqueue->generic;
3729 start_cycle = ep_ring->cycle_state;
3730
3731 /* Queue setup TRB - see section 6.4.1.2.1 */
3732 /* FIXME better way to translate setup_packet into two u32 fields? */
3733 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3734 field = 0;
3735 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3736 if (start_cycle == 0)
3737 field |= 0x1;
3738
3739 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3740 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3741 if (urb->transfer_buffer_length > 0) {
3742 if (setup->bRequestType & USB_DIR_IN)
3743 field |= TRB_TX_TYPE(TRB_DATA_IN);
3744 else
3745 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3746 }
3747 }
3748
3749 queue_trb(xhci, ep_ring, true,
3750 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3751 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3752 TRB_LEN(8) | TRB_INTR_TARGET(0),
3753 /* Immediate data in pointer */
3754 field);
3755
3756 /* If there's data, queue data TRBs */
3757 /* Only set interrupt on short packet for IN endpoints */
3758 if (usb_urb_dir_in(urb))
3759 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3760 else
3761 field = TRB_TYPE(TRB_DATA);
3762
3763 if (urb->transfer_buffer_length > 0) {
3764 u32 length_field, remainder;
3765 u64 addr;
3766
3767 if (xhci_urb_suitable_for_idt(urb)) {
3768 memcpy(&addr, urb->transfer_buffer,
3769 urb->transfer_buffer_length);
3770 le64_to_cpus(&addr);
3771 field |= TRB_IDT;
3772 } else {
3773 addr = (u64) urb->transfer_dma;
3774 }
3775
3776 remainder = xhci_td_remainder(xhci, 0,
3777 urb->transfer_buffer_length,
3778 urb->transfer_buffer_length,
3779 urb, 1);
3780 length_field = TRB_LEN(urb->transfer_buffer_length) |
3781 TRB_TD_SIZE(remainder) |
3782 TRB_INTR_TARGET(0);
3783 if (setup->bRequestType & USB_DIR_IN)
3784 field |= TRB_DIR_IN;
3785 queue_trb(xhci, ep_ring, true,
3786 lower_32_bits(addr),
3787 upper_32_bits(addr),
3788 length_field,
3789 field | ep_ring->cycle_state);
3790 }
3791
3792 /* Save the DMA address of the last TRB in the TD */
3793 td->last_trb = ep_ring->enqueue;
3794 td->last_trb_seg = ep_ring->enq_seg;
3795
3796 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3797 /* If the device sent data, the status stage is an OUT transfer */
3798 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3799 field = 0;
3800 else
3801 field = TRB_DIR_IN;
3802 queue_trb(xhci, ep_ring, false,
3803 0,
3804 0,
3805 TRB_INTR_TARGET(0),
3806 /* Event on completion */
3807 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3808
3809 giveback_first_trb(xhci, slot_id, ep_index, 0,
3810 start_cycle, start_trb);
3811 return 0;
3812}
3813
3814/*
3815 * The transfer burst count field of the isochronous TRB defines the number of
3816 * bursts that are required to move all packets in this TD. Only SuperSpeed
3817 * devices can burst up to bMaxBurst number of packets per service interval.
3818 * This field is zero based, meaning a value of zero in the field means one
3819 * burst. Basically, for everything but SuperSpeed devices, this field will be
3820 * zero. Only xHCI 1.0 host controllers support this field.
3821 */
3822static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3823 struct urb *urb, unsigned int total_packet_count)
3824{
3825 unsigned int max_burst;
3826
3827 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3828 return 0;
3829
3830 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3831 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3832}
3833
3834/*
3835 * Returns the number of packets in the last "burst" of packets. This field is
3836 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3837 * the last burst packet count is equal to the total number of packets in the
3838 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3839 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3840 * contain 1 to (bMaxBurst + 1) packets.
3841 */
3842static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3843 struct urb *urb, unsigned int total_packet_count)
3844{
3845 unsigned int max_burst;
3846 unsigned int residue;
3847
3848 if (xhci->hci_version < 0x100)
3849 return 0;
3850
3851 if (urb->dev->speed >= USB_SPEED_SUPER) {
3852 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3853 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3854 residue = total_packet_count % (max_burst + 1);
3855 /* If residue is zero, the last burst contains (max_burst + 1)
3856 * number of packets, but the TLBPC field is zero-based.
3857 */
3858 if (residue == 0)
3859 return max_burst;
3860 return residue - 1;
3861 }
3862 if (total_packet_count == 0)
3863 return 0;
3864 return total_packet_count - 1;
3865}
3866
3867/*
3868 * Calculates Frame ID field of the isochronous TRB identifies the
3869 * target frame that the Interval associated with this Isochronous
3870 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3871 *
3872 * Returns actual frame id on success, negative value on error.
3873 */
3874static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3875 struct urb *urb, int index)
3876{
3877 int start_frame, ist, ret = 0;
3878 int start_frame_id, end_frame_id, current_frame_id;
3879
3880 if (urb->dev->speed == USB_SPEED_LOW ||
3881 urb->dev->speed == USB_SPEED_FULL)
3882 start_frame = urb->start_frame + index * urb->interval;
3883 else
3884 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3885
3886 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3887 *
3888 * If bit [3] of IST is cleared to '0', software can add a TRB no
3889 * later than IST[2:0] Microframes before that TRB is scheduled to
3890 * be executed.
3891 * If bit [3] of IST is set to '1', software can add a TRB no later
3892 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3893 */
3894 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3895 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3896 ist <<= 3;
3897
3898 /* Software shall not schedule an Isoch TD with a Frame ID value that
3899 * is less than the Start Frame ID or greater than the End Frame ID,
3900 * where:
3901 *
3902 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3903 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3904 *
3905 * Both the End Frame ID and Start Frame ID values are calculated
3906 * in microframes. When software determines the valid Frame ID value;
3907 * The End Frame ID value should be rounded down to the nearest Frame
3908 * boundary, and the Start Frame ID value should be rounded up to the
3909 * nearest Frame boundary.
3910 */
3911 current_frame_id = readl(&xhci->run_regs->microframe_index);
3912 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3913 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3914
3915 start_frame &= 0x7ff;
3916 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3917 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3918
3919 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3920 __func__, index, readl(&xhci->run_regs->microframe_index),
3921 start_frame_id, end_frame_id, start_frame);
3922
3923 if (start_frame_id < end_frame_id) {
3924 if (start_frame > end_frame_id ||
3925 start_frame < start_frame_id)
3926 ret = -EINVAL;
3927 } else if (start_frame_id > end_frame_id) {
3928 if ((start_frame > end_frame_id &&
3929 start_frame < start_frame_id))
3930 ret = -EINVAL;
3931 } else {
3932 ret = -EINVAL;
3933 }
3934
3935 if (index == 0) {
3936 if (ret == -EINVAL || start_frame == start_frame_id) {
3937 start_frame = start_frame_id + 1;
3938 if (urb->dev->speed == USB_SPEED_LOW ||
3939 urb->dev->speed == USB_SPEED_FULL)
3940 urb->start_frame = start_frame;
3941 else
3942 urb->start_frame = start_frame << 3;
3943 ret = 0;
3944 }
3945 }
3946
3947 if (ret) {
3948 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3949 start_frame, current_frame_id, index,
3950 start_frame_id, end_frame_id);
3951 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3952 return ret;
3953 }
3954
3955 return start_frame;
3956}
3957
3958/* Check if we should generate event interrupt for a TD in an isoc URB */
3959static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3960{
3961 if (xhci->hci_version < 0x100)
3962 return false;
3963 /* always generate an event interrupt for the last TD */
3964 if (i == num_tds - 1)
3965 return false;
3966 /*
3967 * If AVOID_BEI is set the host handles full event rings poorly,
3968 * generate an event at least every 8th TD to clear the event ring
3969 */
3970 if (i && xhci->quirks & XHCI_AVOID_BEI)
3971 return !!(i % xhci->isoc_bei_interval);
3972
3973 return true;
3974}
3975
3976/* This is for isoc transfer */
3977static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3978 struct urb *urb, int slot_id, unsigned int ep_index)
3979{
3980 struct xhci_ring *ep_ring;
3981 struct urb_priv *urb_priv;
3982 struct xhci_td *td;
3983 int num_tds, trbs_per_td;
3984 struct xhci_generic_trb *start_trb;
3985 bool first_trb;
3986 int start_cycle;
3987 u32 field, length_field;
3988 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3989 u64 start_addr, addr;
3990 int i, j;
3991 bool more_trbs_coming;
3992 struct xhci_virt_ep *xep;
3993 int frame_id;
3994
3995 xep = &xhci->devs[slot_id]->eps[ep_index];
3996 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3997
3998 num_tds = urb->number_of_packets;
3999 if (num_tds < 1) {
4000 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4001 return -EINVAL;
4002 }
4003 start_addr = (u64) urb->transfer_dma;
4004 start_trb = &ep_ring->enqueue->generic;
4005 start_cycle = ep_ring->cycle_state;
4006
4007 urb_priv = urb->hcpriv;
4008 /* Queue the TRBs for each TD, even if they are zero-length */
4009 for (i = 0; i < num_tds; i++) {
4010 unsigned int total_pkt_count, max_pkt;
4011 unsigned int burst_count, last_burst_pkt_count;
4012 u32 sia_frame_id;
4013
4014 first_trb = true;
4015 running_total = 0;
4016 addr = start_addr + urb->iso_frame_desc[i].offset;
4017 td_len = urb->iso_frame_desc[i].length;
4018 td_remain_len = td_len;
4019 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4020 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4021
4022 /* A zero-length transfer still involves at least one packet. */
4023 if (total_pkt_count == 0)
4024 total_pkt_count++;
4025 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4026 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4027 urb, total_pkt_count);
4028
4029 trbs_per_td = count_isoc_trbs_needed(urb, i);
4030
4031 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4032 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4033 if (ret < 0) {
4034 if (i == 0)
4035 return ret;
4036 goto cleanup;
4037 }
4038 td = &urb_priv->td[i];
4039 td->num_trbs = trbs_per_td;
4040 /* use SIA as default, if frame id is used overwrite it */
4041 sia_frame_id = TRB_SIA;
4042 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4043 HCC_CFC(xhci->hcc_params)) {
4044 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4045 if (frame_id >= 0)
4046 sia_frame_id = TRB_FRAME_ID(frame_id);
4047 }
4048 /*
4049 * Set isoc specific data for the first TRB in a TD.
4050 * Prevent HW from getting the TRBs by keeping the cycle state
4051 * inverted in the first TDs isoc TRB.
4052 */
4053 field = TRB_TYPE(TRB_ISOC) |
4054 TRB_TLBPC(last_burst_pkt_count) |
4055 sia_frame_id |
4056 (i ? ep_ring->cycle_state : !start_cycle);
4057
4058 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4059 if (!xep->use_extended_tbc)
4060 field |= TRB_TBC(burst_count);
4061
4062 /* fill the rest of the TRB fields, and remaining normal TRBs */
4063 for (j = 0; j < trbs_per_td; j++) {
4064 u32 remainder = 0;
4065
4066 /* only first TRB is isoc, overwrite otherwise */
4067 if (!first_trb)
4068 field = TRB_TYPE(TRB_NORMAL) |
4069 ep_ring->cycle_state;
4070
4071 /* Only set interrupt on short packet for IN EPs */
4072 if (usb_urb_dir_in(urb))
4073 field |= TRB_ISP;
4074
4075 /* Set the chain bit for all except the last TRB */
4076 if (j < trbs_per_td - 1) {
4077 more_trbs_coming = true;
4078 field |= TRB_CHAIN;
4079 } else {
4080 more_trbs_coming = false;
4081 td->last_trb = ep_ring->enqueue;
4082 td->last_trb_seg = ep_ring->enq_seg;
4083 field |= TRB_IOC;
4084 if (trb_block_event_intr(xhci, num_tds, i))
4085 field |= TRB_BEI;
4086 }
4087 /* Calculate TRB length */
4088 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4089 if (trb_buff_len > td_remain_len)
4090 trb_buff_len = td_remain_len;
4091
4092 /* Set the TRB length, TD size, & interrupter fields. */
4093 remainder = xhci_td_remainder(xhci, running_total,
4094 trb_buff_len, td_len,
4095 urb, more_trbs_coming);
4096
4097 length_field = TRB_LEN(trb_buff_len) |
4098 TRB_INTR_TARGET(0);
4099
4100 /* xhci 1.1 with ETE uses TD Size field for TBC */
4101 if (first_trb && xep->use_extended_tbc)
4102 length_field |= TRB_TD_SIZE_TBC(burst_count);
4103 else
4104 length_field |= TRB_TD_SIZE(remainder);
4105 first_trb = false;
4106
4107 queue_trb(xhci, ep_ring, more_trbs_coming,
4108 lower_32_bits(addr),
4109 upper_32_bits(addr),
4110 length_field,
4111 field);
4112 running_total += trb_buff_len;
4113
4114 addr += trb_buff_len;
4115 td_remain_len -= trb_buff_len;
4116 }
4117
4118 /* Check TD length */
4119 if (running_total != td_len) {
4120 xhci_err(xhci, "ISOC TD length unmatch\n");
4121 ret = -EINVAL;
4122 goto cleanup;
4123 }
4124 }
4125
4126 /* store the next frame id */
4127 if (HCC_CFC(xhci->hcc_params))
4128 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4129
4130 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4131 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4132 usb_amd_quirk_pll_disable();
4133 }
4134 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4135
4136 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4137 start_cycle, start_trb);
4138 return 0;
4139cleanup:
4140 /* Clean up a partially enqueued isoc transfer. */
4141
4142 for (i--; i >= 0; i--)
4143 list_del_init(&urb_priv->td[i].td_list);
4144
4145 /* Use the first TD as a temporary variable to turn the TDs we've queued
4146 * into No-ops with a software-owned cycle bit. That way the hardware
4147 * won't accidentally start executing bogus TDs when we partially
4148 * overwrite them. td->first_trb and td->start_seg are already set.
4149 */
4150 urb_priv->td[0].last_trb = ep_ring->enqueue;
4151 /* Every TRB except the first & last will have its cycle bit flipped. */
4152 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4153
4154 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4155 ep_ring->enqueue = urb_priv->td[0].first_trb;
4156 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4157 ep_ring->cycle_state = start_cycle;
4158 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4159 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4160 return ret;
4161}
4162
4163/*
4164 * Check transfer ring to guarantee there is enough room for the urb.
4165 * Update ISO URB start_frame and interval.
4166 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4167 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4168 * Contiguous Frame ID is not supported by HC.
4169 */
4170int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4171 struct urb *urb, int slot_id, unsigned int ep_index)
4172{
4173 struct xhci_virt_device *xdev;
4174 struct xhci_ring *ep_ring;
4175 struct xhci_ep_ctx *ep_ctx;
4176 int start_frame;
4177 int num_tds, num_trbs, i;
4178 int ret;
4179 struct xhci_virt_ep *xep;
4180 int ist;
4181
4182 xdev = xhci->devs[slot_id];
4183 xep = &xhci->devs[slot_id]->eps[ep_index];
4184 ep_ring = xdev->eps[ep_index].ring;
4185 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4186
4187 num_trbs = 0;
4188 num_tds = urb->number_of_packets;
4189 for (i = 0; i < num_tds; i++)
4190 num_trbs += count_isoc_trbs_needed(urb, i);
4191
4192 /* Check the ring to guarantee there is enough room for the whole urb.
4193 * Do not insert any td of the urb to the ring if the check failed.
4194 */
4195 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4196 num_trbs, mem_flags);
4197 if (ret)
4198 return ret;
4199
4200 /*
4201 * Check interval value. This should be done before we start to
4202 * calculate the start frame value.
4203 */
4204 check_interval(xhci, urb, ep_ctx);
4205
4206 /* Calculate the start frame and put it in urb->start_frame. */
4207 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4208 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4209 urb->start_frame = xep->next_frame_id;
4210 goto skip_start_over;
4211 }
4212 }
4213
4214 start_frame = readl(&xhci->run_regs->microframe_index);
4215 start_frame &= 0x3fff;
4216 /*
4217 * Round up to the next frame and consider the time before trb really
4218 * gets scheduled by hardare.
4219 */
4220 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4221 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4222 ist <<= 3;
4223 start_frame += ist + XHCI_CFC_DELAY;
4224 start_frame = roundup(start_frame, 8);
4225
4226 /*
4227 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4228 * is greate than 8 microframes.
4229 */
4230 if (urb->dev->speed == USB_SPEED_LOW ||
4231 urb->dev->speed == USB_SPEED_FULL) {
4232 start_frame = roundup(start_frame, urb->interval << 3);
4233 urb->start_frame = start_frame >> 3;
4234 } else {
4235 start_frame = roundup(start_frame, urb->interval);
4236 urb->start_frame = start_frame;
4237 }
4238
4239skip_start_over:
4240 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4241
4242 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4243}
4244
4245/**** Command Ring Operations ****/
4246
4247/* Generic function for queueing a command TRB on the command ring.
4248 * Check to make sure there's room on the command ring for one command TRB.
4249 * Also check that there's room reserved for commands that must not fail.
4250 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4251 * then only check for the number of reserved spots.
4252 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4253 * because the command event handler may want to resubmit a failed command.
4254 */
4255static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4256 u32 field1, u32 field2,
4257 u32 field3, u32 field4, bool command_must_succeed)
4258{
4259 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4260 int ret;
4261
4262 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4263 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4264 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4265 return -ESHUTDOWN;
4266 }
4267
4268 if (!command_must_succeed)
4269 reserved_trbs++;
4270
4271 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4272 reserved_trbs, GFP_ATOMIC);
4273 if (ret < 0) {
4274 xhci_err(xhci, "ERR: No room for command on command ring\n");
4275 if (command_must_succeed)
4276 xhci_err(xhci, "ERR: Reserved TRB counting for "
4277 "unfailable commands failed.\n");
4278 return ret;
4279 }
4280
4281 cmd->command_trb = xhci->cmd_ring->enqueue;
4282
4283 /* if there are no other commands queued we start the timeout timer */
4284 if (list_empty(&xhci->cmd_list)) {
4285 xhci->current_cmd = cmd;
4286 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4287 }
4288
4289 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4290
4291 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4292 field4 | xhci->cmd_ring->cycle_state);
4293 return 0;
4294}
4295
4296/* Queue a slot enable or disable request on the command ring */
4297int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4298 u32 trb_type, u32 slot_id)
4299{
4300 return queue_command(xhci, cmd, 0, 0, 0,
4301 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4302}
4303
4304/* Queue an address device command TRB */
4305int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4306 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4307{
4308 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4309 upper_32_bits(in_ctx_ptr), 0,
4310 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4311 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4312}
4313
4314int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4315 u32 field1, u32 field2, u32 field3, u32 field4)
4316{
4317 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4318}
4319
4320/* Queue a reset device command TRB */
4321int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4322 u32 slot_id)
4323{
4324 return queue_command(xhci, cmd, 0, 0, 0,
4325 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4326 false);
4327}
4328
4329/* Queue a configure endpoint command TRB */
4330int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4331 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4332 u32 slot_id, bool command_must_succeed)
4333{
4334 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4335 upper_32_bits(in_ctx_ptr), 0,
4336 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4337 command_must_succeed);
4338}
4339
4340/* Queue an evaluate context command TRB */
4341int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4342 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4343{
4344 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4345 upper_32_bits(in_ctx_ptr), 0,
4346 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4347 command_must_succeed);
4348}
4349
4350/*
4351 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4352 * activity on an endpoint that is about to be suspended.
4353 */
4354int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4355 int slot_id, unsigned int ep_index, int suspend)
4356{
4357 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4358 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4359 u32 type = TRB_TYPE(TRB_STOP_RING);
4360 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4361
4362 return queue_command(xhci, cmd, 0, 0, 0,
4363 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4364}
4365
4366int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4367 int slot_id, unsigned int ep_index,
4368 enum xhci_ep_reset_type reset_type)
4369{
4370 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4371 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4372 u32 type = TRB_TYPE(TRB_RESET_EP);
4373
4374 if (reset_type == EP_SOFT_RESET)
4375 type |= TRB_TSP;
4376
4377 return queue_command(xhci, cmd, 0, 0, 0,
4378 trb_slot_id | trb_ep_index | type, false);
4379}
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117}
118
119static int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123}
124
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
150
151 ring->deq_updates++;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
154 */
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168}
169
170/*
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
173 *
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
178 *
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
183 *
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
186 */
187static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
188 bool consumer, bool more_trbs_coming)
189{
190 u32 chain;
191 union xhci_trb *next;
192 unsigned long long addr;
193
194 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
195 next = ++(ring->enqueue);
196
197 ring->enq_updates++;
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
200 */
201 while (last_trb(xhci, ring, ring->enq_seg, next)) {
202 if (!consumer) {
203 if (ring != xhci->event_ring) {
204 /*
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
211 */
212 if (!chain && !more_trbs_coming)
213 break;
214
215 /* If we're not dealing with 0.95 hardware,
216 * carry over the chain bit of the previous TRB
217 * (which may mean the chain bit is cleared).
218 */
219 if (!xhci_link_trb_quirk(xhci)) {
220 next->link.control &=
221 cpu_to_le32(~TRB_CHAIN);
222 next->link.control |=
223 cpu_to_le32(chain);
224 }
225 /* Give this link TRB to the hardware */
226 wmb();
227 next->link.control ^= cpu_to_le32(TRB_CYCLE);
228 }
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
232 if (!in_interrupt())
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
234 ring,
235 (unsigned int) ring->cycle_state);
236 }
237 }
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
241 }
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243}
244
245/*
246 * Check to see if there's room to enqueue num_trbs on the ring. See rules
247 * above.
248 * FIXME: this would be simpler and faster if we just kept track of the number
249 * of free TRBs in a ring.
250 */
251static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
252 unsigned int num_trbs)
253{
254 int i;
255 union xhci_trb *enq = ring->enqueue;
256 struct xhci_segment *enq_seg = ring->enq_seg;
257 struct xhci_segment *cur_seg;
258 unsigned int left_on_ring;
259
260 /* If we are currently pointing to a link TRB, advance the
261 * enqueue pointer before checking for space */
262 while (last_trb(xhci, ring, enq_seg, enq)) {
263 enq_seg = enq_seg->next;
264 enq = enq_seg->trbs;
265 }
266
267 /* Check if ring is empty */
268 if (enq == ring->dequeue) {
269 /* Can't use link trbs */
270 left_on_ring = TRBS_PER_SEGMENT - 1;
271 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
272 cur_seg = cur_seg->next)
273 left_on_ring += TRBS_PER_SEGMENT - 1;
274
275 /* Always need one TRB free in the ring. */
276 left_on_ring -= 1;
277 if (num_trbs > left_on_ring) {
278 xhci_warn(xhci, "Not enough room on ring; "
279 "need %u TRBs, %u TRBs left\n",
280 num_trbs, left_on_ring);
281 return 0;
282 }
283 return 1;
284 }
285 /* Make sure there's an extra empty TRB available */
286 for (i = 0; i <= num_trbs; ++i) {
287 if (enq == ring->dequeue)
288 return 0;
289 enq++;
290 while (last_trb(xhci, ring, enq_seg, enq)) {
291 enq_seg = enq_seg->next;
292 enq = enq_seg->trbs;
293 }
294 }
295 return 1;
296}
297
298/* Ring the host controller doorbell after placing a command on the ring */
299void xhci_ring_cmd_db(struct xhci_hcd *xhci)
300{
301 xhci_dbg(xhci, "// Ding dong!\n");
302 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
303 /* Flush PCI posted writes */
304 xhci_readl(xhci, &xhci->dba->doorbell[0]);
305}
306
307void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
308 unsigned int slot_id,
309 unsigned int ep_index,
310 unsigned int stream_id)
311{
312 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
313 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
314 unsigned int ep_state = ep->ep_state;
315
316 /* Don't ring the doorbell for this endpoint if there are pending
317 * cancellations because we don't want to interrupt processing.
318 * We don't want to restart any stream rings if there's a set dequeue
319 * pointer command pending because the device can choose to start any
320 * stream once the endpoint is on the HW schedule.
321 * FIXME - check all the stream rings for pending cancellations.
322 */
323 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
324 (ep_state & EP_HALTED))
325 return;
326 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
327 /* The CPU has better things to do at this point than wait for a
328 * write-posting flush. It'll get there soon enough.
329 */
330}
331
332/* Ring the doorbell for any rings with pending URBs */
333static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
334 unsigned int slot_id,
335 unsigned int ep_index)
336{
337 unsigned int stream_id;
338 struct xhci_virt_ep *ep;
339
340 ep = &xhci->devs[slot_id]->eps[ep_index];
341
342 /* A ring has pending URBs if its TD list is not empty */
343 if (!(ep->ep_state & EP_HAS_STREAMS)) {
344 if (!(list_empty(&ep->ring->td_list)))
345 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
346 return;
347 }
348
349 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
350 stream_id++) {
351 struct xhci_stream_info *stream_info = ep->stream_info;
352 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
354 stream_id);
355 }
356}
357
358/*
359 * Find the segment that trb is in. Start searching in start_seg.
360 * If we must move past a segment that has a link TRB with a toggle cycle state
361 * bit set, then we will toggle the value pointed at by cycle_state.
362 */
363static struct xhci_segment *find_trb_seg(
364 struct xhci_segment *start_seg,
365 union xhci_trb *trb, int *cycle_state)
366{
367 struct xhci_segment *cur_seg = start_seg;
368 struct xhci_generic_trb *generic_trb;
369
370 while (cur_seg->trbs > trb ||
371 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
372 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
373 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
374 *cycle_state ^= 0x1;
375 cur_seg = cur_seg->next;
376 if (cur_seg == start_seg)
377 /* Looped over the entire list. Oops! */
378 return NULL;
379 }
380 return cur_seg;
381}
382
383
384static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 unsigned int stream_id)
387{
388 struct xhci_virt_ep *ep;
389
390 ep = &xhci->devs[slot_id]->eps[ep_index];
391 /* Common case: no streams */
392 if (!(ep->ep_state & EP_HAS_STREAMS))
393 return ep->ring;
394
395 if (stream_id == 0) {
396 xhci_warn(xhci,
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
399 slot_id, ep_index);
400 return NULL;
401 }
402
403 if (stream_id < ep->stream_info->num_streams)
404 return ep->stream_info->stream_rings[stream_id];
405
406 xhci_warn(xhci,
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
410 slot_id, ep_index,
411 ep->stream_info->num_streams - 1,
412 stream_id);
413 return NULL;
414}
415
416/* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
419 */
420static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
421 struct urb *urb)
422{
423 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
424 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
425}
426
427/*
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
432 *
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
440 *
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
443 * in here.
444 */
445void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
446 unsigned int slot_id, unsigned int ep_index,
447 unsigned int stream_id, struct xhci_td *cur_td,
448 struct xhci_dequeue_state *state)
449{
450 struct xhci_virt_device *dev = xhci->devs[slot_id];
451 struct xhci_ring *ep_ring;
452 struct xhci_generic_trb *trb;
453 struct xhci_ep_ctx *ep_ctx;
454 dma_addr_t addr;
455
456 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
457 ep_index, stream_id);
458 if (!ep_ring) {
459 xhci_warn(xhci, "WARN can't find new dequeue state "
460 "for invalid stream ID %u.\n",
461 stream_id);
462 return;
463 }
464 state->new_cycle_state = 0;
465 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
466 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
467 dev->eps[ep_index].stopped_trb,
468 &state->new_cycle_state);
469 if (!state->new_deq_seg) {
470 WARN_ON(1);
471 return;
472 }
473
474 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
475 xhci_dbg(xhci, "Finding endpoint context\n");
476 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
477 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
478
479 state->new_deq_ptr = cur_td->last_trb;
480 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
481 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
482 state->new_deq_ptr,
483 &state->new_cycle_state);
484 if (!state->new_deq_seg) {
485 WARN_ON(1);
486 return;
487 }
488
489 trb = &state->new_deq_ptr->generic;
490 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
491 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
492 state->new_cycle_state ^= 0x1;
493 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
494
495 /*
496 * If there is only one segment in a ring, find_trb_seg()'s while loop
497 * will not run, and it will return before it has a chance to see if it
498 * needs to toggle the cycle bit. It can't tell if the stalled transfer
499 * ended just before the link TRB on a one-segment ring, or if the TD
500 * wrapped around the top of the ring, because it doesn't have the TD in
501 * question. Look for the one-segment case where stalled TRB's address
502 * is greater than the new dequeue pointer address.
503 */
504 if (ep_ring->first_seg == ep_ring->first_seg->next &&
505 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
506 state->new_cycle_state ^= 0x1;
507 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
508
509 /* Don't update the ring cycle state for the producer (us). */
510 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
511 state->new_deq_seg);
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
514 (unsigned long long) addr);
515}
516
517/* flip_cycle means flip the cycle bit of all but the first and last TRB.
518 * (The last TRB actually points to the ring enqueue pointer, which is not part
519 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
520 */
521static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
522 struct xhci_td *cur_td, bool flip_cycle)
523{
524 struct xhci_segment *cur_seg;
525 union xhci_trb *cur_trb;
526
527 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
528 true;
529 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
530 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
531 /* Unchain any chained Link TRBs, but
532 * leave the pointers intact.
533 */
534 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
535 /* Flip the cycle bit (link TRBs can't be the first
536 * or last TRB).
537 */
538 if (flip_cycle)
539 cur_trb->generic.field[3] ^=
540 cpu_to_le32(TRB_CYCLE);
541 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
542 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
543 "in seg %p (0x%llx dma)\n",
544 cur_trb,
545 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
546 cur_seg,
547 (unsigned long long)cur_seg->dma);
548 } else {
549 cur_trb->generic.field[0] = 0;
550 cur_trb->generic.field[1] = 0;
551 cur_trb->generic.field[2] = 0;
552 /* Preserve only the cycle bit of this TRB */
553 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
554 /* Flip the cycle bit except on the first or last TRB */
555 if (flip_cycle && cur_trb != cur_td->first_trb &&
556 cur_trb != cur_td->last_trb)
557 cur_trb->generic.field[3] ^=
558 cpu_to_le32(TRB_CYCLE);
559 cur_trb->generic.field[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP));
561 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
563 cur_trb,
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
565 cur_seg,
566 (unsigned long long)cur_seg->dma);
567 }
568 if (cur_trb == cur_td->last_trb)
569 break;
570 }
571}
572
573static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
574 unsigned int ep_index, unsigned int stream_id,
575 struct xhci_segment *deq_seg,
576 union xhci_trb *deq_ptr, u32 cycle_state);
577
578void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
579 unsigned int slot_id, unsigned int ep_index,
580 unsigned int stream_id,
581 struct xhci_dequeue_state *deq_state)
582{
583 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
584
585 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state->new_deq_seg,
588 (unsigned long long)deq_state->new_deq_seg->dma,
589 deq_state->new_deq_ptr,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
591 deq_state->new_cycle_state);
592 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
593 deq_state->new_deq_seg,
594 deq_state->new_deq_ptr,
595 (u32) deq_state->new_cycle_state);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
599 * ring running.
600 */
601 ep->ep_state |= SET_DEQ_PENDING;
602}
603
604static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
605 struct xhci_virt_ep *ep)
606{
607 ep->ep_state &= ~EP_HALT_PENDING;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
611 */
612 if (del_timer(&ep->stop_cmd_timer))
613 ep->stop_cmds_pending--;
614}
615
616/* Must be called with xhci->lock held in interrupt context */
617static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
618 struct xhci_td *cur_td, int status, char *adjective)
619{
620 struct usb_hcd *hcd;
621 struct urb *urb;
622 struct urb_priv *urb_priv;
623
624 urb = cur_td->urb;
625 urb_priv = urb->hcpriv;
626 urb_priv->td_cnt++;
627 hcd = bus_to_hcd(urb->dev->bus);
628
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv->td_cnt == urb_priv->length) {
631 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
632 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
633 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
634 if (xhci->quirks & XHCI_AMD_PLL_FIX)
635 usb_amd_quirk_pll_enable();
636 }
637 }
638 usb_hcd_unlink_urb_from_ep(hcd, urb);
639
640 spin_unlock(&xhci->lock);
641 usb_hcd_giveback_urb(hcd, urb, status);
642 xhci_urb_free_priv(xhci, urb_priv);
643 spin_lock(&xhci->lock);
644 }
645}
646
647/*
648 * When we get a command completion for a Stop Endpoint Command, we need to
649 * unlink any cancelled TDs from the ring. There are two ways to do that:
650 *
651 * 1. If the HW was in the middle of processing the TD that needs to be
652 * cancelled, then we must move the ring's dequeue pointer past the last TRB
653 * in the TD with a Set Dequeue Pointer Command.
654 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
655 * bit cleared) so that the HW will skip over them.
656 */
657static void handle_stopped_endpoint(struct xhci_hcd *xhci,
658 union xhci_trb *trb, struct xhci_event_cmd *event)
659{
660 unsigned int slot_id;
661 unsigned int ep_index;
662 struct xhci_virt_device *virt_dev;
663 struct xhci_ring *ep_ring;
664 struct xhci_virt_ep *ep;
665 struct list_head *entry;
666 struct xhci_td *cur_td = NULL;
667 struct xhci_td *last_unlinked_td;
668
669 struct xhci_dequeue_state deq_state;
670
671 if (unlikely(TRB_TO_SUSPEND_PORT(
672 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
673 slot_id = TRB_TO_SLOT_ID(
674 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
675 virt_dev = xhci->devs[slot_id];
676 if (virt_dev)
677 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
678 event);
679 else
680 xhci_warn(xhci, "Stop endpoint command "
681 "completion for disabled slot %u\n",
682 slot_id);
683 return;
684 }
685
686 memset(&deq_state, 0, sizeof(deq_state));
687 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
688 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
689 ep = &xhci->devs[slot_id]->eps[ep_index];
690
691 if (list_empty(&ep->cancelled_td_list)) {
692 xhci_stop_watchdog_timer_in_irq(xhci, ep);
693 ep->stopped_td = NULL;
694 ep->stopped_trb = NULL;
695 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
696 return;
697 }
698
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
703 */
704 list_for_each(entry, &ep->cancelled_td_list) {
705 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
706 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
707 cur_td->first_trb,
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
709 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
710 if (!ep_ring) {
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
720 * submission.
721 */
722 xhci_warn(xhci, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
724 cur_td->urb,
725 cur_td->urb->stream_id);
726 goto remove_finished_td;
727 }
728 /*
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
731 */
732 if (cur_td == ep->stopped_td)
733 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
734 cur_td->urb->stream_id,
735 cur_td, &deq_state);
736 else
737 td_to_noop(xhci, ep_ring, cur_td, false);
738remove_finished_td:
739 /*
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
743 */
744 list_del_init(&cur_td->td_list);
745 }
746 last_unlinked_td = cur_td;
747 xhci_stop_watchdog_timer_in_irq(xhci, ep);
748
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
751 xhci_queue_new_dequeue_state(xhci,
752 slot_id, ep_index,
753 ep->stopped_td->urb->stream_id,
754 &deq_state);
755 xhci_ring_cmd_db(xhci);
756 } else {
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
759 }
760 ep->stopped_td = NULL;
761 ep->stopped_trb = NULL;
762
763 /*
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
768 */
769 do {
770 cur_td = list_entry(ep->cancelled_td_list.next,
771 struct xhci_td, cancelled_td_list);
772 list_del_init(&cur_td->cancelled_td_list);
773
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
777 */
778 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
779
780 /* Stop processing the cancelled list if the watchdog timer is
781 * running.
782 */
783 if (xhci->xhc_state & XHCI_STATE_DYING)
784 return;
785 } while (cur_td != last_unlinked_td);
786
787 /* Return to the event handler with xhci->lock re-acquired */
788}
789
790/* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
795 *
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
803 *
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
807 * the host is dying.
808 */
809void xhci_stop_endpoint_command_watchdog(unsigned long arg)
810{
811 struct xhci_hcd *xhci;
812 struct xhci_virt_ep *ep;
813 struct xhci_virt_ep *temp_ep;
814 struct xhci_ring *ring;
815 struct xhci_td *cur_td;
816 int ret, i, j;
817
818 ep = (struct xhci_virt_ep *) arg;
819 xhci = ep->xhci;
820
821 spin_lock(&xhci->lock);
822
823 ep->stop_cmds_pending--;
824 if (xhci->xhc_state & XHCI_STATE_DYING) {
825 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci->lock);
828 return;
829 }
830 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
831 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
832 "exiting.\n");
833 spin_unlock(&xhci->lock);
834 return;
835 }
836
837 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
840 * endpoint command.
841 */
842 xhci->xhc_state |= XHCI_STATE_DYING;
843 /* Disable interrupts from the host controller and start halting it */
844 xhci_quiesce(xhci);
845 spin_unlock(&xhci->lock);
846
847 ret = xhci_halt(xhci);
848
849 spin_lock(&xhci->lock);
850 if (ret < 0) {
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
857 */
858 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
864 */
865 }
866 for (i = 0; i < MAX_HC_SLOTS; i++) {
867 if (!xhci->devs[i])
868 continue;
869 for (j = 0; j < 31; j++) {
870 temp_ep = &xhci->devs[i]->eps[j];
871 ring = temp_ep->ring;
872 if (!ring)
873 continue;
874 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i, j);
876 while (!list_empty(&ring->td_list)) {
877 cur_td = list_first_entry(&ring->td_list,
878 struct xhci_td,
879 td_list);
880 list_del_init(&cur_td->td_list);
881 if (!list_empty(&cur_td->cancelled_td_list))
882 list_del_init(&cur_td->cancelled_td_list);
883 xhci_giveback_urb_in_irq(xhci, cur_td,
884 -ESHUTDOWN, "killed");
885 }
886 while (!list_empty(&temp_ep->cancelled_td_list)) {
887 cur_td = list_first_entry(
888 &temp_ep->cancelled_td_list,
889 struct xhci_td,
890 cancelled_td_list);
891 list_del_init(&cur_td->cancelled_td_list);
892 xhci_giveback_urb_in_irq(xhci, cur_td,
893 -ESHUTDOWN, "killed");
894 }
895 }
896 }
897 spin_unlock(&xhci->lock);
898 xhci_dbg(xhci, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
900 xhci_dbg(xhci, "xHCI host controller is dead.\n");
901}
902
903/*
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
909 */
910static void handle_set_deq_completion(struct xhci_hcd *xhci,
911 struct xhci_event_cmd *event,
912 union xhci_trb *trb)
913{
914 unsigned int slot_id;
915 unsigned int ep_index;
916 unsigned int stream_id;
917 struct xhci_ring *ep_ring;
918 struct xhci_virt_device *dev;
919 struct xhci_ep_ctx *ep_ctx;
920 struct xhci_slot_ctx *slot_ctx;
921
922 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
923 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
924 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
925 dev = xhci->devs[slot_id];
926
927 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
928 if (!ep_ring) {
929 xhci_warn(xhci, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
931 stream_id);
932 /* XXX: Harmless??? */
933 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
934 return;
935 }
936
937 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
938 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
939
940 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
941 unsigned int ep_state;
942 unsigned int slot_state;
943
944 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
945 case COMP_TRB_ERR:
946 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
948 break;
949 case COMP_CTX_STATE:
950 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state = le32_to_cpu(ep_ctx->ep_info);
953 ep_state &= EP_STATE_MASK;
954 slot_state = le32_to_cpu(slot_ctx->dev_state);
955 slot_state = GET_SLOT_STATE(slot_state);
956 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
957 slot_state, ep_state);
958 break;
959 case COMP_EBADSLT:
960 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id);
962 break;
963 default:
964 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event->status)));
967 break;
968 }
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
974 */
975 } else {
976 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx->deq));
978 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
979 dev->eps[ep_index].queued_deq_ptr) ==
980 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
983 */
984 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
985 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
986 } else {
987 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
990 dev->eps[ep_index].queued_deq_seg,
991 dev->eps[ep_index].queued_deq_ptr);
992 }
993 }
994
995 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
996 dev->eps[ep_index].queued_deq_seg = NULL;
997 dev->eps[ep_index].queued_deq_ptr = NULL;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1000}
1001
1002static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1003 struct xhci_event_cmd *event,
1004 union xhci_trb *trb)
1005{
1006 int slot_id;
1007 unsigned int ep_index;
1008
1009 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1010 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1013 */
1014 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1015 GET_COMP_CODE(le32_to_cpu(event->status)));
1016
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1020 */
1021 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1022 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci,
1024 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1025 false);
1026 xhci_ring_cmd_db(xhci);
1027 } else {
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1030 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031 }
1032}
1033
1034/* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1037 */
1038static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1039 struct xhci_virt_device *virt_dev,
1040 struct xhci_event_cmd *event)
1041{
1042 struct xhci_command *command;
1043
1044 if (list_empty(&virt_dev->cmd_list))
1045 return 0;
1046
1047 command = list_entry(virt_dev->cmd_list.next,
1048 struct xhci_command, cmd_list);
1049 if (xhci->cmd_ring->dequeue != command->command_trb)
1050 return 0;
1051
1052 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1053 list_del(&command->cmd_list);
1054 if (command->completion)
1055 complete(command->completion);
1056 else
1057 xhci_free_command(xhci, command);
1058 return 1;
1059}
1060
1061static void handle_cmd_completion(struct xhci_hcd *xhci,
1062 struct xhci_event_cmd *event)
1063{
1064 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1065 u64 cmd_dma;
1066 dma_addr_t cmd_dequeue_dma;
1067 struct xhci_input_control_ctx *ctrl_ctx;
1068 struct xhci_virt_device *virt_dev;
1069 unsigned int ep_index;
1070 struct xhci_ring *ep_ring;
1071 unsigned int ep_state;
1072
1073 cmd_dma = le64_to_cpu(event->cmd_trb);
1074 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1075 xhci->cmd_ring->dequeue);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma == 0) {
1078 xhci->error_bitmask |= 1 << 4;
1079 return;
1080 }
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma != (u64) cmd_dequeue_dma) {
1083 xhci->error_bitmask |= 1 << 5;
1084 return;
1085 }
1086 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1087 & TRB_TYPE_BITMASK) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT):
1089 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1090 xhci->slot_id = slot_id;
1091 else
1092 xhci->slot_id = 0;
1093 complete(&xhci->addr_dev);
1094 break;
1095 case TRB_TYPE(TRB_DISABLE_SLOT):
1096 if (xhci->devs[slot_id]) {
1097 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1098 /* Delete default control endpoint resources */
1099 xhci_free_device_endpoint_resources(xhci,
1100 xhci->devs[slot_id], true);
1101 xhci_free_virt_device(xhci, slot_id);
1102 }
1103 break;
1104 case TRB_TYPE(TRB_CONFIG_EP):
1105 virt_dev = xhci->devs[slot_id];
1106 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1107 break;
1108 /*
1109 * Configure endpoint commands can come from the USB core
1110 * configuration or alt setting changes, or because the HW
1111 * needed an extra configure endpoint command after a reset
1112 * endpoint command or streams were being configured.
1113 * If the command was for a halted endpoint, the xHCI driver
1114 * is not waiting on the configure endpoint command.
1115 */
1116 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1117 virt_dev->in_ctx);
1118 /* Input ctx add_flags are the endpoint index plus one */
1119 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1120 /* A usb_set_interface() call directly after clearing a halted
1121 * condition may race on this quirky hardware. Not worth
1122 * worrying about, since this is prototype hardware. Not sure
1123 * if this will work for streams, but streams support was
1124 * untested on this prototype.
1125 */
1126 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1127 ep_index != (unsigned int) -1 &&
1128 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1129 le32_to_cpu(ctrl_ctx->drop_flags)) {
1130 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1131 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1132 if (!(ep_state & EP_HALTED))
1133 goto bandwidth_change;
1134 xhci_dbg(xhci, "Completed config ep cmd - "
1135 "last ep index = %d, state = %d\n",
1136 ep_index, ep_state);
1137 /* Clear internal halted state and restart ring(s) */
1138 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1139 ~EP_HALTED;
1140 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1141 break;
1142 }
1143bandwidth_change:
1144 xhci_dbg(xhci, "Completed config ep cmd\n");
1145 xhci->devs[slot_id]->cmd_status =
1146 GET_COMP_CODE(le32_to_cpu(event->status));
1147 complete(&xhci->devs[slot_id]->cmd_completion);
1148 break;
1149 case TRB_TYPE(TRB_EVAL_CONTEXT):
1150 virt_dev = xhci->devs[slot_id];
1151 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1152 break;
1153 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1154 complete(&xhci->devs[slot_id]->cmd_completion);
1155 break;
1156 case TRB_TYPE(TRB_ADDR_DEV):
1157 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1158 complete(&xhci->addr_dev);
1159 break;
1160 case TRB_TYPE(TRB_STOP_RING):
1161 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1162 break;
1163 case TRB_TYPE(TRB_SET_DEQ):
1164 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1165 break;
1166 case TRB_TYPE(TRB_CMD_NOOP):
1167 break;
1168 case TRB_TYPE(TRB_RESET_EP):
1169 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1170 break;
1171 case TRB_TYPE(TRB_RESET_DEV):
1172 xhci_dbg(xhci, "Completed reset device command.\n");
1173 slot_id = TRB_TO_SLOT_ID(
1174 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1175 virt_dev = xhci->devs[slot_id];
1176 if (virt_dev)
1177 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1178 else
1179 xhci_warn(xhci, "Reset device command completion "
1180 "for disabled slot %u\n", slot_id);
1181 break;
1182 case TRB_TYPE(TRB_NEC_GET_FW):
1183 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1184 xhci->error_bitmask |= 1 << 6;
1185 break;
1186 }
1187 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1188 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1189 NEC_FW_MINOR(le32_to_cpu(event->status)));
1190 break;
1191 default:
1192 /* Skip over unknown commands on the event ring */
1193 xhci->error_bitmask |= 1 << 6;
1194 break;
1195 }
1196 inc_deq(xhci, xhci->cmd_ring, false);
1197}
1198
1199static void handle_vendor_event(struct xhci_hcd *xhci,
1200 union xhci_trb *event)
1201{
1202 u32 trb_type;
1203
1204 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1205 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1206 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1207 handle_cmd_completion(xhci, &event->event_cmd);
1208}
1209
1210/* @port_id: the one-based port ID from the hardware (indexed from array of all
1211 * port registers -- USB 3.0 and USB 2.0).
1212 *
1213 * Returns a zero-based port number, which is suitable for indexing into each of
1214 * the split roothubs' port arrays and bus state arrays.
1215 */
1216static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1217 struct xhci_hcd *xhci, u32 port_id)
1218{
1219 unsigned int i;
1220 unsigned int num_similar_speed_ports = 0;
1221
1222 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1223 * and usb2_ports are 0-based indexes. Count the number of similar
1224 * speed ports, up to 1 port before this port.
1225 */
1226 for (i = 0; i < (port_id - 1); i++) {
1227 u8 port_speed = xhci->port_array[i];
1228
1229 /*
1230 * Skip ports that don't have known speeds, or have duplicate
1231 * Extended Capabilities port speed entries.
1232 */
1233 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1234 continue;
1235
1236 /*
1237 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1238 * 1.1 ports are under the USB 2.0 hub. If the port speed
1239 * matches the device speed, it's a similar speed port.
1240 */
1241 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1242 num_similar_speed_ports++;
1243 }
1244 return num_similar_speed_ports;
1245}
1246
1247static void handle_port_status(struct xhci_hcd *xhci,
1248 union xhci_trb *event)
1249{
1250 struct usb_hcd *hcd;
1251 u32 port_id;
1252 u32 temp, temp1;
1253 int max_ports;
1254 int slot_id;
1255 unsigned int faked_port_index;
1256 u8 major_revision;
1257 struct xhci_bus_state *bus_state;
1258 __le32 __iomem **port_array;
1259 bool bogus_port_status = false;
1260
1261 /* Port status change events always have a successful completion code */
1262 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1263 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1264 xhci->error_bitmask |= 1 << 8;
1265 }
1266 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1267 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1268
1269 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1270 if ((port_id <= 0) || (port_id > max_ports)) {
1271 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1272 bogus_port_status = true;
1273 goto cleanup;
1274 }
1275
1276 /* Figure out which usb_hcd this port is attached to:
1277 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1278 */
1279 major_revision = xhci->port_array[port_id - 1];
1280 if (major_revision == 0) {
1281 xhci_warn(xhci, "Event for port %u not in "
1282 "Extended Capabilities, ignoring.\n",
1283 port_id);
1284 bogus_port_status = true;
1285 goto cleanup;
1286 }
1287 if (major_revision == DUPLICATE_ENTRY) {
1288 xhci_warn(xhci, "Event for port %u duplicated in"
1289 "Extended Capabilities, ignoring.\n",
1290 port_id);
1291 bogus_port_status = true;
1292 goto cleanup;
1293 }
1294
1295 /*
1296 * Hardware port IDs reported by a Port Status Change Event include USB
1297 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1298 * resume event, but we first need to translate the hardware port ID
1299 * into the index into the ports on the correct split roothub, and the
1300 * correct bus_state structure.
1301 */
1302 /* Find the right roothub. */
1303 hcd = xhci_to_hcd(xhci);
1304 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1305 hcd = xhci->shared_hcd;
1306 bus_state = &xhci->bus_state[hcd_index(hcd)];
1307 if (hcd->speed == HCD_USB3)
1308 port_array = xhci->usb3_ports;
1309 else
1310 port_array = xhci->usb2_ports;
1311 /* Find the faked port hub number */
1312 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1313 port_id);
1314
1315 temp = xhci_readl(xhci, port_array[faked_port_index]);
1316 if (hcd->state == HC_STATE_SUSPENDED) {
1317 xhci_dbg(xhci, "resume root hub\n");
1318 usb_hcd_resume_root_hub(hcd);
1319 }
1320
1321 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1322 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1323
1324 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1325 if (!(temp1 & CMD_RUN)) {
1326 xhci_warn(xhci, "xHC is not running.\n");
1327 goto cleanup;
1328 }
1329
1330 if (DEV_SUPERSPEED(temp)) {
1331 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1332 temp = xhci_port_state_to_neutral(temp);
1333 temp &= ~PORT_PLS_MASK;
1334 temp |= PORT_LINK_STROBE | XDEV_U0;
1335 xhci_writel(xhci, temp, port_array[faked_port_index]);
1336 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337 faked_port_index);
1338 if (!slot_id) {
1339 xhci_dbg(xhci, "slot_id is zero\n");
1340 goto cleanup;
1341 }
1342 xhci_ring_device(xhci, slot_id);
1343 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344 /* Clear PORT_PLC */
1345 temp = xhci_readl(xhci, port_array[faked_port_index]);
1346 temp = xhci_port_state_to_neutral(temp);
1347 temp |= PORT_PLC;
1348 xhci_writel(xhci, temp, port_array[faked_port_index]);
1349 } else {
1350 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1351 bus_state->resume_done[faked_port_index] = jiffies +
1352 msecs_to_jiffies(20);
1353 mod_timer(&hcd->rh_timer,
1354 bus_state->resume_done[faked_port_index]);
1355 /* Do the rest in GetPortStatus */
1356 }
1357 }
1358
1359cleanup:
1360 /* Update event ring dequeue pointer before dropping the lock */
1361 inc_deq(xhci, xhci->event_ring, true);
1362
1363 /* Don't make the USB core poll the roothub if we got a bad port status
1364 * change event. Besides, at that point we can't tell which roothub
1365 * (USB 2.0 or USB 3.0) to kick.
1366 */
1367 if (bogus_port_status)
1368 return;
1369
1370 spin_unlock(&xhci->lock);
1371 /* Pass this up to the core */
1372 usb_hcd_poll_rh_status(hcd);
1373 spin_lock(&xhci->lock);
1374}
1375
1376/*
1377 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1378 * at end_trb, which may be in another segment. If the suspect DMA address is a
1379 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1380 * returns 0.
1381 */
1382struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1383 union xhci_trb *start_trb,
1384 union xhci_trb *end_trb,
1385 dma_addr_t suspect_dma)
1386{
1387 dma_addr_t start_dma;
1388 dma_addr_t end_seg_dma;
1389 dma_addr_t end_trb_dma;
1390 struct xhci_segment *cur_seg;
1391
1392 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1393 cur_seg = start_seg;
1394
1395 do {
1396 if (start_dma == 0)
1397 return NULL;
1398 /* We may get an event for a Link TRB in the middle of a TD */
1399 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1400 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1401 /* If the end TRB isn't in this segment, this is set to 0 */
1402 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1403
1404 if (end_trb_dma > 0) {
1405 /* The end TRB is in this segment, so suspect should be here */
1406 if (start_dma <= end_trb_dma) {
1407 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1408 return cur_seg;
1409 } else {
1410 /* Case for one segment with
1411 * a TD wrapped around to the top
1412 */
1413 if ((suspect_dma >= start_dma &&
1414 suspect_dma <= end_seg_dma) ||
1415 (suspect_dma >= cur_seg->dma &&
1416 suspect_dma <= end_trb_dma))
1417 return cur_seg;
1418 }
1419 return NULL;
1420 } else {
1421 /* Might still be somewhere in this segment */
1422 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1423 return cur_seg;
1424 }
1425 cur_seg = cur_seg->next;
1426 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1427 } while (cur_seg != start_seg);
1428
1429 return NULL;
1430}
1431
1432static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1433 unsigned int slot_id, unsigned int ep_index,
1434 unsigned int stream_id,
1435 struct xhci_td *td, union xhci_trb *event_trb)
1436{
1437 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1438 ep->ep_state |= EP_HALTED;
1439 ep->stopped_td = td;
1440 ep->stopped_trb = event_trb;
1441 ep->stopped_stream = stream_id;
1442
1443 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1444 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1445
1446 ep->stopped_td = NULL;
1447 ep->stopped_trb = NULL;
1448 ep->stopped_stream = 0;
1449
1450 xhci_ring_cmd_db(xhci);
1451}
1452
1453/* Check if an error has halted the endpoint ring. The class driver will
1454 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1455 * However, a babble and other errors also halt the endpoint ring, and the class
1456 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1457 * Ring Dequeue Pointer command manually.
1458 */
1459static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1460 struct xhci_ep_ctx *ep_ctx,
1461 unsigned int trb_comp_code)
1462{
1463 /* TRB completion codes that may require a manual halt cleanup */
1464 if (trb_comp_code == COMP_TX_ERR ||
1465 trb_comp_code == COMP_BABBLE ||
1466 trb_comp_code == COMP_SPLIT_ERR)
1467 /* The 0.96 spec says a babbling control endpoint
1468 * is not halted. The 0.96 spec says it is. Some HW
1469 * claims to be 0.95 compliant, but it halts the control
1470 * endpoint anyway. Check if a babble halted the
1471 * endpoint.
1472 */
1473 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1474 cpu_to_le32(EP_STATE_HALTED))
1475 return 1;
1476
1477 return 0;
1478}
1479
1480int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1481{
1482 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1483 /* Vendor defined "informational" completion code,
1484 * treat as not-an-error.
1485 */
1486 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1487 trb_comp_code);
1488 xhci_dbg(xhci, "Treating code as success.\n");
1489 return 1;
1490 }
1491 return 0;
1492}
1493
1494/*
1495 * Finish the td processing, remove the td from td list;
1496 * Return 1 if the urb can be given back.
1497 */
1498static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1499 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1500 struct xhci_virt_ep *ep, int *status, bool skip)
1501{
1502 struct xhci_virt_device *xdev;
1503 struct xhci_ring *ep_ring;
1504 unsigned int slot_id;
1505 int ep_index;
1506 struct urb *urb = NULL;
1507 struct xhci_ep_ctx *ep_ctx;
1508 int ret = 0;
1509 struct urb_priv *urb_priv;
1510 u32 trb_comp_code;
1511
1512 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1513 xdev = xhci->devs[slot_id];
1514 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1515 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1516 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1517 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1518
1519 if (skip)
1520 goto td_cleanup;
1521
1522 if (trb_comp_code == COMP_STOP_INVAL ||
1523 trb_comp_code == COMP_STOP) {
1524 /* The Endpoint Stop Command completion will take care of any
1525 * stopped TDs. A stopped TD may be restarted, so don't update
1526 * the ring dequeue pointer or take this TD off any lists yet.
1527 */
1528 ep->stopped_td = td;
1529 ep->stopped_trb = event_trb;
1530 return 0;
1531 } else {
1532 if (trb_comp_code == COMP_STALL) {
1533 /* The transfer is completed from the driver's
1534 * perspective, but we need to issue a set dequeue
1535 * command for this stalled endpoint to move the dequeue
1536 * pointer past the TD. We can't do that here because
1537 * the halt condition must be cleared first. Let the
1538 * USB class driver clear the stall later.
1539 */
1540 ep->stopped_td = td;
1541 ep->stopped_trb = event_trb;
1542 ep->stopped_stream = ep_ring->stream_id;
1543 } else if (xhci_requires_manual_halt_cleanup(xhci,
1544 ep_ctx, trb_comp_code)) {
1545 /* Other types of errors halt the endpoint, but the
1546 * class driver doesn't call usb_reset_endpoint() unless
1547 * the error is -EPIPE. Clear the halted status in the
1548 * xHCI hardware manually.
1549 */
1550 xhci_cleanup_halted_endpoint(xhci,
1551 slot_id, ep_index, ep_ring->stream_id,
1552 td, event_trb);
1553 } else {
1554 /* Update ring dequeue pointer */
1555 while (ep_ring->dequeue != td->last_trb)
1556 inc_deq(xhci, ep_ring, false);
1557 inc_deq(xhci, ep_ring, false);
1558 }
1559
1560td_cleanup:
1561 /* Clean up the endpoint's TD list */
1562 urb = td->urb;
1563 urb_priv = urb->hcpriv;
1564
1565 /* Do one last check of the actual transfer length.
1566 * If the host controller said we transferred more data than
1567 * the buffer length, urb->actual_length will be a very big
1568 * number (since it's unsigned). Play it safe and say we didn't
1569 * transfer anything.
1570 */
1571 if (urb->actual_length > urb->transfer_buffer_length) {
1572 xhci_warn(xhci, "URB transfer length is wrong, "
1573 "xHC issue? req. len = %u, "
1574 "act. len = %u\n",
1575 urb->transfer_buffer_length,
1576 urb->actual_length);
1577 urb->actual_length = 0;
1578 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1579 *status = -EREMOTEIO;
1580 else
1581 *status = 0;
1582 }
1583 list_del_init(&td->td_list);
1584 /* Was this TD slated to be cancelled but completed anyway? */
1585 if (!list_empty(&td->cancelled_td_list))
1586 list_del_init(&td->cancelled_td_list);
1587
1588 urb_priv->td_cnt++;
1589 /* Giveback the urb when all the tds are completed */
1590 if (urb_priv->td_cnt == urb_priv->length) {
1591 ret = 1;
1592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1595 == 0) {
1596 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1597 usb_amd_quirk_pll_enable();
1598 }
1599 }
1600 }
1601 }
1602
1603 return ret;
1604}
1605
1606/*
1607 * Process control tds, update urb status and actual_length.
1608 */
1609static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1610 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1611 struct xhci_virt_ep *ep, int *status)
1612{
1613 struct xhci_virt_device *xdev;
1614 struct xhci_ring *ep_ring;
1615 unsigned int slot_id;
1616 int ep_index;
1617 struct xhci_ep_ctx *ep_ctx;
1618 u32 trb_comp_code;
1619
1620 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1621 xdev = xhci->devs[slot_id];
1622 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1623 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1624 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1625 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1626
1627 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1628 switch (trb_comp_code) {
1629 case COMP_SUCCESS:
1630 if (event_trb == ep_ring->dequeue) {
1631 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1632 "without IOC set??\n");
1633 *status = -ESHUTDOWN;
1634 } else if (event_trb != td->last_trb) {
1635 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1636 "without IOC set??\n");
1637 *status = -ESHUTDOWN;
1638 } else {
1639 *status = 0;
1640 }
1641 break;
1642 case COMP_SHORT_TX:
1643 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1644 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1645 *status = -EREMOTEIO;
1646 else
1647 *status = 0;
1648 break;
1649 case COMP_STOP_INVAL:
1650 case COMP_STOP:
1651 return finish_td(xhci, td, event_trb, event, ep, status, false);
1652 default:
1653 if (!xhci_requires_manual_halt_cleanup(xhci,
1654 ep_ctx, trb_comp_code))
1655 break;
1656 xhci_dbg(xhci, "TRB error code %u, "
1657 "halted endpoint index = %u\n",
1658 trb_comp_code, ep_index);
1659 /* else fall through */
1660 case COMP_STALL:
1661 /* Did we transfer part of the data (middle) phase? */
1662 if (event_trb != ep_ring->dequeue &&
1663 event_trb != td->last_trb)
1664 td->urb->actual_length =
1665 td->urb->transfer_buffer_length
1666 - TRB_LEN(le32_to_cpu(event->transfer_len));
1667 else
1668 td->urb->actual_length = 0;
1669
1670 xhci_cleanup_halted_endpoint(xhci,
1671 slot_id, ep_index, 0, td, event_trb);
1672 return finish_td(xhci, td, event_trb, event, ep, status, true);
1673 }
1674 /*
1675 * Did we transfer any data, despite the errors that might have
1676 * happened? I.e. did we get past the setup stage?
1677 */
1678 if (event_trb != ep_ring->dequeue) {
1679 /* The event was for the status stage */
1680 if (event_trb == td->last_trb) {
1681 if (td->urb->actual_length != 0) {
1682 /* Don't overwrite a previously set error code
1683 */
1684 if ((*status == -EINPROGRESS || *status == 0) &&
1685 (td->urb->transfer_flags
1686 & URB_SHORT_NOT_OK))
1687 /* Did we already see a short data
1688 * stage? */
1689 *status = -EREMOTEIO;
1690 } else {
1691 td->urb->actual_length =
1692 td->urb->transfer_buffer_length;
1693 }
1694 } else {
1695 /* Maybe the event was for the data stage? */
1696 td->urb->actual_length =
1697 td->urb->transfer_buffer_length -
1698 TRB_LEN(le32_to_cpu(event->transfer_len));
1699 xhci_dbg(xhci, "Waiting for status "
1700 "stage event\n");
1701 return 0;
1702 }
1703 }
1704
1705 return finish_td(xhci, td, event_trb, event, ep, status, false);
1706}
1707
1708/*
1709 * Process isochronous tds, update urb packet status and actual_length.
1710 */
1711static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1712 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1713 struct xhci_virt_ep *ep, int *status)
1714{
1715 struct xhci_ring *ep_ring;
1716 struct urb_priv *urb_priv;
1717 int idx;
1718 int len = 0;
1719 union xhci_trb *cur_trb;
1720 struct xhci_segment *cur_seg;
1721 struct usb_iso_packet_descriptor *frame;
1722 u32 trb_comp_code;
1723 bool skip_td = false;
1724
1725 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1726 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1727 urb_priv = td->urb->hcpriv;
1728 idx = urb_priv->td_cnt;
1729 frame = &td->urb->iso_frame_desc[idx];
1730
1731 /* handle completion code */
1732 switch (trb_comp_code) {
1733 case COMP_SUCCESS:
1734 frame->status = 0;
1735 break;
1736 case COMP_SHORT_TX:
1737 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1738 -EREMOTEIO : 0;
1739 break;
1740 case COMP_BW_OVER:
1741 frame->status = -ECOMM;
1742 skip_td = true;
1743 break;
1744 case COMP_BUFF_OVER:
1745 case COMP_BABBLE:
1746 frame->status = -EOVERFLOW;
1747 skip_td = true;
1748 break;
1749 case COMP_DEV_ERR:
1750 case COMP_STALL:
1751 frame->status = -EPROTO;
1752 skip_td = true;
1753 break;
1754 case COMP_STOP:
1755 case COMP_STOP_INVAL:
1756 break;
1757 default:
1758 frame->status = -1;
1759 break;
1760 }
1761
1762 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1763 frame->actual_length = frame->length;
1764 td->urb->actual_length += frame->length;
1765 } else {
1766 for (cur_trb = ep_ring->dequeue,
1767 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1768 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1769 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1770 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1771 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1772 }
1773 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1774 TRB_LEN(le32_to_cpu(event->transfer_len));
1775
1776 if (trb_comp_code != COMP_STOP_INVAL) {
1777 frame->actual_length = len;
1778 td->urb->actual_length += len;
1779 }
1780 }
1781
1782 return finish_td(xhci, td, event_trb, event, ep, status, false);
1783}
1784
1785static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1786 struct xhci_transfer_event *event,
1787 struct xhci_virt_ep *ep, int *status)
1788{
1789 struct xhci_ring *ep_ring;
1790 struct urb_priv *urb_priv;
1791 struct usb_iso_packet_descriptor *frame;
1792 int idx;
1793
1794 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1795 urb_priv = td->urb->hcpriv;
1796 idx = urb_priv->td_cnt;
1797 frame = &td->urb->iso_frame_desc[idx];
1798
1799 /* The transfer is partly done. */
1800 frame->status = -EXDEV;
1801
1802 /* calc actual length */
1803 frame->actual_length = 0;
1804
1805 /* Update ring dequeue pointer */
1806 while (ep_ring->dequeue != td->last_trb)
1807 inc_deq(xhci, ep_ring, false);
1808 inc_deq(xhci, ep_ring, false);
1809
1810 return finish_td(xhci, td, NULL, event, ep, status, true);
1811}
1812
1813/*
1814 * Process bulk and interrupt tds, update urb status and actual_length.
1815 */
1816static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1817 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1818 struct xhci_virt_ep *ep, int *status)
1819{
1820 struct xhci_ring *ep_ring;
1821 union xhci_trb *cur_trb;
1822 struct xhci_segment *cur_seg;
1823 u32 trb_comp_code;
1824
1825 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1826 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1827
1828 switch (trb_comp_code) {
1829 case COMP_SUCCESS:
1830 /* Double check that the HW transferred everything. */
1831 if (event_trb != td->last_trb) {
1832 xhci_warn(xhci, "WARN Successful completion "
1833 "on short TX\n");
1834 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1835 *status = -EREMOTEIO;
1836 else
1837 *status = 0;
1838 } else {
1839 *status = 0;
1840 }
1841 break;
1842 case COMP_SHORT_TX:
1843 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1844 *status = -EREMOTEIO;
1845 else
1846 *status = 0;
1847 break;
1848 default:
1849 /* Others already handled above */
1850 break;
1851 }
1852 if (trb_comp_code == COMP_SHORT_TX)
1853 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1854 "%d bytes untransferred\n",
1855 td->urb->ep->desc.bEndpointAddress,
1856 td->urb->transfer_buffer_length,
1857 TRB_LEN(le32_to_cpu(event->transfer_len)));
1858 /* Fast path - was this the last TRB in the TD for this URB? */
1859 if (event_trb == td->last_trb) {
1860 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1861 td->urb->actual_length =
1862 td->urb->transfer_buffer_length -
1863 TRB_LEN(le32_to_cpu(event->transfer_len));
1864 if (td->urb->transfer_buffer_length <
1865 td->urb->actual_length) {
1866 xhci_warn(xhci, "HC gave bad length "
1867 "of %d bytes left\n",
1868 TRB_LEN(le32_to_cpu(event->transfer_len)));
1869 td->urb->actual_length = 0;
1870 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1871 *status = -EREMOTEIO;
1872 else
1873 *status = 0;
1874 }
1875 /* Don't overwrite a previously set error code */
1876 if (*status == -EINPROGRESS) {
1877 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1878 *status = -EREMOTEIO;
1879 else
1880 *status = 0;
1881 }
1882 } else {
1883 td->urb->actual_length =
1884 td->urb->transfer_buffer_length;
1885 /* Ignore a short packet completion if the
1886 * untransferred length was zero.
1887 */
1888 if (*status == -EREMOTEIO)
1889 *status = 0;
1890 }
1891 } else {
1892 /* Slow path - walk the list, starting from the dequeue
1893 * pointer, to get the actual length transferred.
1894 */
1895 td->urb->actual_length = 0;
1896 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1897 cur_trb != event_trb;
1898 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1899 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1900 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1901 td->urb->actual_length +=
1902 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1903 }
1904 /* If the ring didn't stop on a Link or No-op TRB, add
1905 * in the actual bytes transferred from the Normal TRB
1906 */
1907 if (trb_comp_code != COMP_STOP_INVAL)
1908 td->urb->actual_length +=
1909 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1910 TRB_LEN(le32_to_cpu(event->transfer_len));
1911 }
1912
1913 return finish_td(xhci, td, event_trb, event, ep, status, false);
1914}
1915
1916/*
1917 * If this function returns an error condition, it means it got a Transfer
1918 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1919 * At this point, the host controller is probably hosed and should be reset.
1920 */
1921static int handle_tx_event(struct xhci_hcd *xhci,
1922 struct xhci_transfer_event *event)
1923{
1924 struct xhci_virt_device *xdev;
1925 struct xhci_virt_ep *ep;
1926 struct xhci_ring *ep_ring;
1927 unsigned int slot_id;
1928 int ep_index;
1929 struct xhci_td *td = NULL;
1930 dma_addr_t event_dma;
1931 struct xhci_segment *event_seg;
1932 union xhci_trb *event_trb;
1933 struct urb *urb = NULL;
1934 int status = -EINPROGRESS;
1935 struct urb_priv *urb_priv;
1936 struct xhci_ep_ctx *ep_ctx;
1937 struct list_head *tmp;
1938 u32 trb_comp_code;
1939 int ret = 0;
1940 int td_num = 0;
1941
1942 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1943 xdev = xhci->devs[slot_id];
1944 if (!xdev) {
1945 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1946 return -ENODEV;
1947 }
1948
1949 /* Endpoint ID is 1 based, our index is zero based */
1950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1951 ep = &xdev->eps[ep_index];
1952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1954 if (!ep_ring ||
1955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
1957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
1959 return -ENODEV;
1960 }
1961
1962 /* Count current td numbers if ep->skip is set */
1963 if (ep->skip) {
1964 list_for_each(tmp, &ep_ring->td_list)
1965 td_num++;
1966 }
1967
1968 event_dma = le64_to_cpu(event->buffer);
1969 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1970 /* Look for common error cases */
1971 switch (trb_comp_code) {
1972 /* Skip codes that require special handling depending on
1973 * transfer type
1974 */
1975 case COMP_SUCCESS:
1976 case COMP_SHORT_TX:
1977 break;
1978 case COMP_STOP:
1979 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1980 break;
1981 case COMP_STOP_INVAL:
1982 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1983 break;
1984 case COMP_STALL:
1985 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1986 ep->ep_state |= EP_HALTED;
1987 status = -EPIPE;
1988 break;
1989 case COMP_TRB_ERR:
1990 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1991 status = -EILSEQ;
1992 break;
1993 case COMP_SPLIT_ERR:
1994 case COMP_TX_ERR:
1995 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1996 status = -EPROTO;
1997 break;
1998 case COMP_BABBLE:
1999 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2000 status = -EOVERFLOW;
2001 break;
2002 case COMP_DB_ERR:
2003 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2004 status = -ENOSR;
2005 break;
2006 case COMP_BW_OVER:
2007 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2008 break;
2009 case COMP_BUFF_OVER:
2010 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2011 break;
2012 case COMP_UNDERRUN:
2013 /*
2014 * When the Isoch ring is empty, the xHC will generate
2015 * a Ring Overrun Event for IN Isoch endpoint or Ring
2016 * Underrun Event for OUT Isoch endpoint.
2017 */
2018 xhci_dbg(xhci, "underrun event on endpoint\n");
2019 if (!list_empty(&ep_ring->td_list))
2020 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2021 "still with TDs queued?\n",
2022 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2023 ep_index);
2024 goto cleanup;
2025 case COMP_OVERRUN:
2026 xhci_dbg(xhci, "overrun event on endpoint\n");
2027 if (!list_empty(&ep_ring->td_list))
2028 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2029 "still with TDs queued?\n",
2030 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2031 ep_index);
2032 goto cleanup;
2033 case COMP_DEV_ERR:
2034 xhci_warn(xhci, "WARN: detect an incompatible device");
2035 status = -EPROTO;
2036 break;
2037 case COMP_MISSED_INT:
2038 /*
2039 * When encounter missed service error, one or more isoc tds
2040 * may be missed by xHC.
2041 * Set skip flag of the ep_ring; Complete the missed tds as
2042 * short transfer when process the ep_ring next time.
2043 */
2044 ep->skip = true;
2045 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2046 goto cleanup;
2047 default:
2048 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2049 status = 0;
2050 break;
2051 }
2052 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2053 "busted\n");
2054 goto cleanup;
2055 }
2056
2057 do {
2058 /* This TRB should be in the TD at the head of this ring's
2059 * TD list.
2060 */
2061 if (list_empty(&ep_ring->td_list)) {
2062 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2063 "with no TDs queued?\n",
2064 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2065 ep_index);
2066 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2067 (le32_to_cpu(event->flags) &
2068 TRB_TYPE_BITMASK)>>10);
2069 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2070 if (ep->skip) {
2071 ep->skip = false;
2072 xhci_dbg(xhci, "td_list is empty while skip "
2073 "flag set. Clear skip flag.\n");
2074 }
2075 ret = 0;
2076 goto cleanup;
2077 }
2078
2079 /* We've skipped all the TDs on the ep ring when ep->skip set */
2080 if (ep->skip && td_num == 0) {
2081 ep->skip = false;
2082 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2083 "Clear skip flag.\n");
2084 ret = 0;
2085 goto cleanup;
2086 }
2087
2088 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2089 if (ep->skip)
2090 td_num--;
2091
2092 /* Is this a TRB in the currently executing TD? */
2093 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2094 td->last_trb, event_dma);
2095
2096 /*
2097 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2098 * is not in the current TD pointed by ep_ring->dequeue because
2099 * that the hardware dequeue pointer still at the previous TRB
2100 * of the current TD. The previous TRB maybe a Link TD or the
2101 * last TRB of the previous TD. The command completion handle
2102 * will take care the rest.
2103 */
2104 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2105 ret = 0;
2106 goto cleanup;
2107 }
2108
2109 if (!event_seg) {
2110 if (!ep->skip ||
2111 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2112 /* Some host controllers give a spurious
2113 * successful event after a short transfer.
2114 * Ignore it.
2115 */
2116 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2117 ep_ring->last_td_was_short) {
2118 ep_ring->last_td_was_short = false;
2119 ret = 0;
2120 goto cleanup;
2121 }
2122 /* HC is busted, give up! */
2123 xhci_err(xhci,
2124 "ERROR Transfer event TRB DMA ptr not "
2125 "part of current TD\n");
2126 return -ESHUTDOWN;
2127 }
2128
2129 ret = skip_isoc_td(xhci, td, event, ep, &status);
2130 goto cleanup;
2131 }
2132 if (trb_comp_code == COMP_SHORT_TX)
2133 ep_ring->last_td_was_short = true;
2134 else
2135 ep_ring->last_td_was_short = false;
2136
2137 if (ep->skip) {
2138 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2139 ep->skip = false;
2140 }
2141
2142 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2143 sizeof(*event_trb)];
2144 /*
2145 * No-op TRB should not trigger interrupts.
2146 * If event_trb is a no-op TRB, it means the
2147 * corresponding TD has been cancelled. Just ignore
2148 * the TD.
2149 */
2150 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2151 xhci_dbg(xhci,
2152 "event_trb is a no-op TRB. Skip it\n");
2153 goto cleanup;
2154 }
2155
2156 /* Now update the urb's actual_length and give back to
2157 * the core
2158 */
2159 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2160 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2161 &status);
2162 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2163 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2164 &status);
2165 else
2166 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2167 ep, &status);
2168
2169cleanup:
2170 /*
2171 * Do not update event ring dequeue pointer if ep->skip is set.
2172 * Will roll back to continue process missed tds.
2173 */
2174 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2175 inc_deq(xhci, xhci->event_ring, true);
2176 }
2177
2178 if (ret) {
2179 urb = td->urb;
2180 urb_priv = urb->hcpriv;
2181 /* Leave the TD around for the reset endpoint function
2182 * to use(but only if it's not a control endpoint,
2183 * since we already queued the Set TR dequeue pointer
2184 * command for stalled control endpoints).
2185 */
2186 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2187 (trb_comp_code != COMP_STALL &&
2188 trb_comp_code != COMP_BABBLE))
2189 xhci_urb_free_priv(xhci, urb_priv);
2190
2191 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2192 if ((urb->actual_length != urb->transfer_buffer_length &&
2193 (urb->transfer_flags &
2194 URB_SHORT_NOT_OK)) ||
2195 status != 0)
2196 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2197 "expected = %x, status = %d\n",
2198 urb, urb->actual_length,
2199 urb->transfer_buffer_length,
2200 status);
2201 spin_unlock(&xhci->lock);
2202 /* EHCI, UHCI, and OHCI always unconditionally set the
2203 * urb->status of an isochronous endpoint to 0.
2204 */
2205 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2206 status = 0;
2207 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2208 spin_lock(&xhci->lock);
2209 }
2210
2211 /*
2212 * If ep->skip is set, it means there are missed tds on the
2213 * endpoint ring need to take care of.
2214 * Process them as short transfer until reach the td pointed by
2215 * the event.
2216 */
2217 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2218
2219 return 0;
2220}
2221
2222/*
2223 * This function handles all OS-owned events on the event ring. It may drop
2224 * xhci->lock between event processing (e.g. to pass up port status changes).
2225 * Returns >0 for "possibly more events to process" (caller should call again),
2226 * otherwise 0 if done. In future, <0 returns should indicate error code.
2227 */
2228static int xhci_handle_event(struct xhci_hcd *xhci)
2229{
2230 union xhci_trb *event;
2231 int update_ptrs = 1;
2232 int ret;
2233
2234 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2235 xhci->error_bitmask |= 1 << 1;
2236 return 0;
2237 }
2238
2239 event = xhci->event_ring->dequeue;
2240 /* Does the HC or OS own the TRB? */
2241 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2242 xhci->event_ring->cycle_state) {
2243 xhci->error_bitmask |= 1 << 2;
2244 return 0;
2245 }
2246
2247 /*
2248 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2249 * speculative reads of the event's flags/data below.
2250 */
2251 rmb();
2252 /* FIXME: Handle more event types. */
2253 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2254 case TRB_TYPE(TRB_COMPLETION):
2255 handle_cmd_completion(xhci, &event->event_cmd);
2256 break;
2257 case TRB_TYPE(TRB_PORT_STATUS):
2258 handle_port_status(xhci, event);
2259 update_ptrs = 0;
2260 break;
2261 case TRB_TYPE(TRB_TRANSFER):
2262 ret = handle_tx_event(xhci, &event->trans_event);
2263 if (ret < 0)
2264 xhci->error_bitmask |= 1 << 9;
2265 else
2266 update_ptrs = 0;
2267 break;
2268 default:
2269 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2270 TRB_TYPE(48))
2271 handle_vendor_event(xhci, event);
2272 else
2273 xhci->error_bitmask |= 1 << 3;
2274 }
2275 /* Any of the above functions may drop and re-acquire the lock, so check
2276 * to make sure a watchdog timer didn't mark the host as non-responsive.
2277 */
2278 if (xhci->xhc_state & XHCI_STATE_DYING) {
2279 xhci_dbg(xhci, "xHCI host dying, returning from "
2280 "event handler.\n");
2281 return 0;
2282 }
2283
2284 if (update_ptrs)
2285 /* Update SW event ring dequeue pointer */
2286 inc_deq(xhci, xhci->event_ring, true);
2287
2288 /* Are there more items on the event ring? Caller will call us again to
2289 * check.
2290 */
2291 return 1;
2292}
2293
2294/*
2295 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2296 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2297 * indicators of an event TRB error, but we check the status *first* to be safe.
2298 */
2299irqreturn_t xhci_irq(struct usb_hcd *hcd)
2300{
2301 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2302 u32 status;
2303 union xhci_trb *trb;
2304 u64 temp_64;
2305 union xhci_trb *event_ring_deq;
2306 dma_addr_t deq;
2307
2308 spin_lock(&xhci->lock);
2309 trb = xhci->event_ring->dequeue;
2310 /* Check if the xHC generated the interrupt, or the irq is shared */
2311 status = xhci_readl(xhci, &xhci->op_regs->status);
2312 if (status == 0xffffffff)
2313 goto hw_died;
2314
2315 if (!(status & STS_EINT)) {
2316 spin_unlock(&xhci->lock);
2317 return IRQ_NONE;
2318 }
2319 if (status & STS_FATAL) {
2320 xhci_warn(xhci, "WARNING: Host System Error\n");
2321 xhci_halt(xhci);
2322hw_died:
2323 spin_unlock(&xhci->lock);
2324 return -ESHUTDOWN;
2325 }
2326
2327 /*
2328 * Clear the op reg interrupt status first,
2329 * so we can receive interrupts from other MSI-X interrupters.
2330 * Write 1 to clear the interrupt status.
2331 */
2332 status |= STS_EINT;
2333 xhci_writel(xhci, status, &xhci->op_regs->status);
2334 /* FIXME when MSI-X is supported and there are multiple vectors */
2335 /* Clear the MSI-X event interrupt status */
2336
2337 if (hcd->irq != -1) {
2338 u32 irq_pending;
2339 /* Acknowledge the PCI interrupt */
2340 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2341 irq_pending |= 0x3;
2342 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2343 }
2344
2345 if (xhci->xhc_state & XHCI_STATE_DYING) {
2346 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2347 "Shouldn't IRQs be disabled?\n");
2348 /* Clear the event handler busy flag (RW1C);
2349 * the event ring should be empty.
2350 */
2351 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2352 xhci_write_64(xhci, temp_64 | ERST_EHB,
2353 &xhci->ir_set->erst_dequeue);
2354 spin_unlock(&xhci->lock);
2355
2356 return IRQ_HANDLED;
2357 }
2358
2359 event_ring_deq = xhci->event_ring->dequeue;
2360 /* FIXME this should be a delayed service routine
2361 * that clears the EHB.
2362 */
2363 while (xhci_handle_event(xhci) > 0) {}
2364
2365 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2366 /* If necessary, update the HW's version of the event ring deq ptr. */
2367 if (event_ring_deq != xhci->event_ring->dequeue) {
2368 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2369 xhci->event_ring->dequeue);
2370 if (deq == 0)
2371 xhci_warn(xhci, "WARN something wrong with SW event "
2372 "ring dequeue ptr.\n");
2373 /* Update HC event ring dequeue pointer */
2374 temp_64 &= ERST_PTR_MASK;
2375 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2376 }
2377
2378 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2379 temp_64 |= ERST_EHB;
2380 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2381
2382 spin_unlock(&xhci->lock);
2383
2384 return IRQ_HANDLED;
2385}
2386
2387irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2388{
2389 irqreturn_t ret;
2390 struct xhci_hcd *xhci;
2391
2392 xhci = hcd_to_xhci(hcd);
2393 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2394 if (xhci->shared_hcd)
2395 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2396
2397 ret = xhci_irq(hcd);
2398
2399 return ret;
2400}
2401
2402/**** Endpoint Ring Operations ****/
2403
2404/*
2405 * Generic function for queueing a TRB on a ring.
2406 * The caller must have checked to make sure there's room on the ring.
2407 *
2408 * @more_trbs_coming: Will you enqueue more TRBs before calling
2409 * prepare_transfer()?
2410 */
2411static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2412 bool consumer, bool more_trbs_coming,
2413 u32 field1, u32 field2, u32 field3, u32 field4)
2414{
2415 struct xhci_generic_trb *trb;
2416
2417 trb = &ring->enqueue->generic;
2418 trb->field[0] = cpu_to_le32(field1);
2419 trb->field[1] = cpu_to_le32(field2);
2420 trb->field[2] = cpu_to_le32(field3);
2421 trb->field[3] = cpu_to_le32(field4);
2422 inc_enq(xhci, ring, consumer, more_trbs_coming);
2423}
2424
2425/*
2426 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2427 * FIXME allocate segments if the ring is full.
2428 */
2429static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2430 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2431{
2432 /* Make sure the endpoint has been added to xHC schedule */
2433 switch (ep_state) {
2434 case EP_STATE_DISABLED:
2435 /*
2436 * USB core changed config/interfaces without notifying us,
2437 * or hardware is reporting the wrong state.
2438 */
2439 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2440 return -ENOENT;
2441 case EP_STATE_ERROR:
2442 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2443 /* FIXME event handling code for error needs to clear it */
2444 /* XXX not sure if this should be -ENOENT or not */
2445 return -EINVAL;
2446 case EP_STATE_HALTED:
2447 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2448 case EP_STATE_STOPPED:
2449 case EP_STATE_RUNNING:
2450 break;
2451 default:
2452 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2453 /*
2454 * FIXME issue Configure Endpoint command to try to get the HC
2455 * back into a known state.
2456 */
2457 return -EINVAL;
2458 }
2459 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2460 /* FIXME allocate more room */
2461 xhci_err(xhci, "ERROR no room on ep ring\n");
2462 return -ENOMEM;
2463 }
2464
2465 if (enqueue_is_link_trb(ep_ring)) {
2466 struct xhci_ring *ring = ep_ring;
2467 union xhci_trb *next;
2468
2469 next = ring->enqueue;
2470
2471 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2472 /* If we're not dealing with 0.95 hardware,
2473 * clear the chain bit.
2474 */
2475 if (!xhci_link_trb_quirk(xhci))
2476 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2477 else
2478 next->link.control |= cpu_to_le32(TRB_CHAIN);
2479
2480 wmb();
2481 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2482
2483 /* Toggle the cycle bit after the last ring segment. */
2484 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2485 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2486 if (!in_interrupt()) {
2487 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2488 "state for ring %p = %i\n",
2489 ring, (unsigned int)ring->cycle_state);
2490 }
2491 }
2492 ring->enq_seg = ring->enq_seg->next;
2493 ring->enqueue = ring->enq_seg->trbs;
2494 next = ring->enqueue;
2495 }
2496 }
2497
2498 return 0;
2499}
2500
2501static int prepare_transfer(struct xhci_hcd *xhci,
2502 struct xhci_virt_device *xdev,
2503 unsigned int ep_index,
2504 unsigned int stream_id,
2505 unsigned int num_trbs,
2506 struct urb *urb,
2507 unsigned int td_index,
2508 gfp_t mem_flags)
2509{
2510 int ret;
2511 struct urb_priv *urb_priv;
2512 struct xhci_td *td;
2513 struct xhci_ring *ep_ring;
2514 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2515
2516 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2517 if (!ep_ring) {
2518 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2519 stream_id);
2520 return -EINVAL;
2521 }
2522
2523 ret = prepare_ring(xhci, ep_ring,
2524 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2525 num_trbs, mem_flags);
2526 if (ret)
2527 return ret;
2528
2529 urb_priv = urb->hcpriv;
2530 td = urb_priv->td[td_index];
2531
2532 INIT_LIST_HEAD(&td->td_list);
2533 INIT_LIST_HEAD(&td->cancelled_td_list);
2534
2535 if (td_index == 0) {
2536 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2537 if (unlikely(ret))
2538 return ret;
2539 }
2540
2541 td->urb = urb;
2542 /* Add this TD to the tail of the endpoint ring's TD list */
2543 list_add_tail(&td->td_list, &ep_ring->td_list);
2544 td->start_seg = ep_ring->enq_seg;
2545 td->first_trb = ep_ring->enqueue;
2546
2547 urb_priv->td[td_index] = td;
2548
2549 return 0;
2550}
2551
2552static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2553{
2554 int num_sgs, num_trbs, running_total, temp, i;
2555 struct scatterlist *sg;
2556
2557 sg = NULL;
2558 num_sgs = urb->num_sgs;
2559 temp = urb->transfer_buffer_length;
2560
2561 xhci_dbg(xhci, "count sg list trbs: \n");
2562 num_trbs = 0;
2563 for_each_sg(urb->sg, sg, num_sgs, i) {
2564 unsigned int previous_total_trbs = num_trbs;
2565 unsigned int len = sg_dma_len(sg);
2566
2567 /* Scatter gather list entries may cross 64KB boundaries */
2568 running_total = TRB_MAX_BUFF_SIZE -
2569 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2570 running_total &= TRB_MAX_BUFF_SIZE - 1;
2571 if (running_total != 0)
2572 num_trbs++;
2573
2574 /* How many more 64KB chunks to transfer, how many more TRBs? */
2575 while (running_total < sg_dma_len(sg) && running_total < temp) {
2576 num_trbs++;
2577 running_total += TRB_MAX_BUFF_SIZE;
2578 }
2579 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2580 i, (unsigned long long)sg_dma_address(sg),
2581 len, len, num_trbs - previous_total_trbs);
2582
2583 len = min_t(int, len, temp);
2584 temp -= len;
2585 if (temp == 0)
2586 break;
2587 }
2588 xhci_dbg(xhci, "\n");
2589 if (!in_interrupt())
2590 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2591 "num_trbs = %d\n",
2592 urb->ep->desc.bEndpointAddress,
2593 urb->transfer_buffer_length,
2594 num_trbs);
2595 return num_trbs;
2596}
2597
2598static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2599{
2600 if (num_trbs != 0)
2601 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2602 "TRBs, %d left\n", __func__,
2603 urb->ep->desc.bEndpointAddress, num_trbs);
2604 if (running_total != urb->transfer_buffer_length)
2605 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2606 "queued %#x (%d), asked for %#x (%d)\n",
2607 __func__,
2608 urb->ep->desc.bEndpointAddress,
2609 running_total, running_total,
2610 urb->transfer_buffer_length,
2611 urb->transfer_buffer_length);
2612}
2613
2614static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2615 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2616 struct xhci_generic_trb *start_trb)
2617{
2618 /*
2619 * Pass all the TRBs to the hardware at once and make sure this write
2620 * isn't reordered.
2621 */
2622 wmb();
2623 if (start_cycle)
2624 start_trb->field[3] |= cpu_to_le32(start_cycle);
2625 else
2626 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2627 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2628}
2629
2630/*
2631 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2632 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2633 * (comprised of sg list entries) can take several service intervals to
2634 * transmit.
2635 */
2636int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2637 struct urb *urb, int slot_id, unsigned int ep_index)
2638{
2639 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2640 xhci->devs[slot_id]->out_ctx, ep_index);
2641 int xhci_interval;
2642 int ep_interval;
2643
2644 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2645 ep_interval = urb->interval;
2646 /* Convert to microframes */
2647 if (urb->dev->speed == USB_SPEED_LOW ||
2648 urb->dev->speed == USB_SPEED_FULL)
2649 ep_interval *= 8;
2650 /* FIXME change this to a warning and a suggestion to use the new API
2651 * to set the polling interval (once the API is added).
2652 */
2653 if (xhci_interval != ep_interval) {
2654 if (printk_ratelimit())
2655 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2656 " (%d microframe%s) than xHCI "
2657 "(%d microframe%s)\n",
2658 ep_interval,
2659 ep_interval == 1 ? "" : "s",
2660 xhci_interval,
2661 xhci_interval == 1 ? "" : "s");
2662 urb->interval = xhci_interval;
2663 /* Convert back to frames for LS/FS devices */
2664 if (urb->dev->speed == USB_SPEED_LOW ||
2665 urb->dev->speed == USB_SPEED_FULL)
2666 urb->interval /= 8;
2667 }
2668 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2669}
2670
2671/*
2672 * The TD size is the number of bytes remaining in the TD (including this TRB),
2673 * right shifted by 10.
2674 * It must fit in bits 21:17, so it can't be bigger than 31.
2675 */
2676static u32 xhci_td_remainder(unsigned int remainder)
2677{
2678 u32 max = (1 << (21 - 17 + 1)) - 1;
2679
2680 if ((remainder >> 10) >= max)
2681 return max << 17;
2682 else
2683 return (remainder >> 10) << 17;
2684}
2685
2686/*
2687 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2688 * the TD (*not* including this TRB).
2689 *
2690 * Total TD packet count = total_packet_count =
2691 * roundup(TD size in bytes / wMaxPacketSize)
2692 *
2693 * Packets transferred up to and including this TRB = packets_transferred =
2694 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2695 *
2696 * TD size = total_packet_count - packets_transferred
2697 *
2698 * It must fit in bits 21:17, so it can't be bigger than 31.
2699 */
2700
2701static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2702 unsigned int total_packet_count, struct urb *urb)
2703{
2704 int packets_transferred;
2705
2706 /* One TRB with a zero-length data packet. */
2707 if (running_total == 0 && trb_buff_len == 0)
2708 return 0;
2709
2710 /* All the TRB queueing functions don't count the current TRB in
2711 * running_total.
2712 */
2713 packets_transferred = (running_total + trb_buff_len) /
2714 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
2715
2716 return xhci_td_remainder(total_packet_count - packets_transferred);
2717}
2718
2719static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2720 struct urb *urb, int slot_id, unsigned int ep_index)
2721{
2722 struct xhci_ring *ep_ring;
2723 unsigned int num_trbs;
2724 struct urb_priv *urb_priv;
2725 struct xhci_td *td;
2726 struct scatterlist *sg;
2727 int num_sgs;
2728 int trb_buff_len, this_sg_len, running_total;
2729 unsigned int total_packet_count;
2730 bool first_trb;
2731 u64 addr;
2732 bool more_trbs_coming;
2733
2734 struct xhci_generic_trb *start_trb;
2735 int start_cycle;
2736
2737 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2738 if (!ep_ring)
2739 return -EINVAL;
2740
2741 num_trbs = count_sg_trbs_needed(xhci, urb);
2742 num_sgs = urb->num_sgs;
2743 total_packet_count = roundup(urb->transfer_buffer_length,
2744 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2745
2746 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2747 ep_index, urb->stream_id,
2748 num_trbs, urb, 0, mem_flags);
2749 if (trb_buff_len < 0)
2750 return trb_buff_len;
2751
2752 urb_priv = urb->hcpriv;
2753 td = urb_priv->td[0];
2754
2755 /*
2756 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2757 * until we've finished creating all the other TRBs. The ring's cycle
2758 * state may change as we enqueue the other TRBs, so save it too.
2759 */
2760 start_trb = &ep_ring->enqueue->generic;
2761 start_cycle = ep_ring->cycle_state;
2762
2763 running_total = 0;
2764 /*
2765 * How much data is in the first TRB?
2766 *
2767 * There are three forces at work for TRB buffer pointers and lengths:
2768 * 1. We don't want to walk off the end of this sg-list entry buffer.
2769 * 2. The transfer length that the driver requested may be smaller than
2770 * the amount of memory allocated for this scatter-gather list.
2771 * 3. TRBs buffers can't cross 64KB boundaries.
2772 */
2773 sg = urb->sg;
2774 addr = (u64) sg_dma_address(sg);
2775 this_sg_len = sg_dma_len(sg);
2776 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2777 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2778 if (trb_buff_len > urb->transfer_buffer_length)
2779 trb_buff_len = urb->transfer_buffer_length;
2780 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2781 trb_buff_len);
2782
2783 first_trb = true;
2784 /* Queue the first TRB, even if it's zero-length */
2785 do {
2786 u32 field = 0;
2787 u32 length_field = 0;
2788 u32 remainder = 0;
2789
2790 /* Don't change the cycle bit of the first TRB until later */
2791 if (first_trb) {
2792 first_trb = false;
2793 if (start_cycle == 0)
2794 field |= 0x1;
2795 } else
2796 field |= ep_ring->cycle_state;
2797
2798 /* Chain all the TRBs together; clear the chain bit in the last
2799 * TRB to indicate it's the last TRB in the chain.
2800 */
2801 if (num_trbs > 1) {
2802 field |= TRB_CHAIN;
2803 } else {
2804 /* FIXME - add check for ZERO_PACKET flag before this */
2805 td->last_trb = ep_ring->enqueue;
2806 field |= TRB_IOC;
2807 }
2808
2809 /* Only set interrupt on short packet for IN endpoints */
2810 if (usb_urb_dir_in(urb))
2811 field |= TRB_ISP;
2812
2813 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2814 "64KB boundary at %#x, end dma = %#x\n",
2815 (unsigned int) addr, trb_buff_len, trb_buff_len,
2816 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2817 (unsigned int) addr + trb_buff_len);
2818 if (TRB_MAX_BUFF_SIZE -
2819 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2820 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2821 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2822 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2823 (unsigned int) addr + trb_buff_len);
2824 }
2825
2826 /* Set the TRB length, TD size, and interrupter fields. */
2827 if (xhci->hci_version < 0x100) {
2828 remainder = xhci_td_remainder(
2829 urb->transfer_buffer_length -
2830 running_total);
2831 } else {
2832 remainder = xhci_v1_0_td_remainder(running_total,
2833 trb_buff_len, total_packet_count, urb);
2834 }
2835 length_field = TRB_LEN(trb_buff_len) |
2836 remainder |
2837 TRB_INTR_TARGET(0);
2838
2839 if (num_trbs > 1)
2840 more_trbs_coming = true;
2841 else
2842 more_trbs_coming = false;
2843 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2844 lower_32_bits(addr),
2845 upper_32_bits(addr),
2846 length_field,
2847 field | TRB_TYPE(TRB_NORMAL));
2848 --num_trbs;
2849 running_total += trb_buff_len;
2850
2851 /* Calculate length for next transfer --
2852 * Are we done queueing all the TRBs for this sg entry?
2853 */
2854 this_sg_len -= trb_buff_len;
2855 if (this_sg_len == 0) {
2856 --num_sgs;
2857 if (num_sgs == 0)
2858 break;
2859 sg = sg_next(sg);
2860 addr = (u64) sg_dma_address(sg);
2861 this_sg_len = sg_dma_len(sg);
2862 } else {
2863 addr += trb_buff_len;
2864 }
2865
2866 trb_buff_len = TRB_MAX_BUFF_SIZE -
2867 (addr & (TRB_MAX_BUFF_SIZE - 1));
2868 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2869 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2870 trb_buff_len =
2871 urb->transfer_buffer_length - running_total;
2872 } while (running_total < urb->transfer_buffer_length);
2873
2874 check_trb_math(urb, num_trbs, running_total);
2875 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2876 start_cycle, start_trb);
2877 return 0;
2878}
2879
2880/* This is very similar to what ehci-q.c qtd_fill() does */
2881int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2882 struct urb *urb, int slot_id, unsigned int ep_index)
2883{
2884 struct xhci_ring *ep_ring;
2885 struct urb_priv *urb_priv;
2886 struct xhci_td *td;
2887 int num_trbs;
2888 struct xhci_generic_trb *start_trb;
2889 bool first_trb;
2890 bool more_trbs_coming;
2891 int start_cycle;
2892 u32 field, length_field;
2893
2894 int running_total, trb_buff_len, ret;
2895 unsigned int total_packet_count;
2896 u64 addr;
2897
2898 if (urb->num_sgs)
2899 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2900
2901 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2902 if (!ep_ring)
2903 return -EINVAL;
2904
2905 num_trbs = 0;
2906 /* How much data is (potentially) left before the 64KB boundary? */
2907 running_total = TRB_MAX_BUFF_SIZE -
2908 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2909 running_total &= TRB_MAX_BUFF_SIZE - 1;
2910
2911 /* If there's some data on this 64KB chunk, or we have to send a
2912 * zero-length transfer, we need at least one TRB
2913 */
2914 if (running_total != 0 || urb->transfer_buffer_length == 0)
2915 num_trbs++;
2916 /* How many more 64KB chunks to transfer, how many more TRBs? */
2917 while (running_total < urb->transfer_buffer_length) {
2918 num_trbs++;
2919 running_total += TRB_MAX_BUFF_SIZE;
2920 }
2921 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2922
2923 if (!in_interrupt())
2924 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2925 "addr = %#llx, num_trbs = %d\n",
2926 urb->ep->desc.bEndpointAddress,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length,
2929 (unsigned long long)urb->transfer_dma,
2930 num_trbs);
2931
2932 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2933 ep_index, urb->stream_id,
2934 num_trbs, urb, 0, mem_flags);
2935 if (ret < 0)
2936 return ret;
2937
2938 urb_priv = urb->hcpriv;
2939 td = urb_priv->td[0];
2940
2941 /*
2942 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2943 * until we've finished creating all the other TRBs. The ring's cycle
2944 * state may change as we enqueue the other TRBs, so save it too.
2945 */
2946 start_trb = &ep_ring->enqueue->generic;
2947 start_cycle = ep_ring->cycle_state;
2948
2949 running_total = 0;
2950 total_packet_count = roundup(urb->transfer_buffer_length,
2951 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2952 /* How much data is in the first TRB? */
2953 addr = (u64) urb->transfer_dma;
2954 trb_buff_len = TRB_MAX_BUFF_SIZE -
2955 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2956 if (trb_buff_len > urb->transfer_buffer_length)
2957 trb_buff_len = urb->transfer_buffer_length;
2958
2959 first_trb = true;
2960
2961 /* Queue the first TRB, even if it's zero-length */
2962 do {
2963 u32 remainder = 0;
2964 field = 0;
2965
2966 /* Don't change the cycle bit of the first TRB until later */
2967 if (first_trb) {
2968 first_trb = false;
2969 if (start_cycle == 0)
2970 field |= 0x1;
2971 } else
2972 field |= ep_ring->cycle_state;
2973
2974 /* Chain all the TRBs together; clear the chain bit in the last
2975 * TRB to indicate it's the last TRB in the chain.
2976 */
2977 if (num_trbs > 1) {
2978 field |= TRB_CHAIN;
2979 } else {
2980 /* FIXME - add check for ZERO_PACKET flag before this */
2981 td->last_trb = ep_ring->enqueue;
2982 field |= TRB_IOC;
2983 }
2984
2985 /* Only set interrupt on short packet for IN endpoints */
2986 if (usb_urb_dir_in(urb))
2987 field |= TRB_ISP;
2988
2989 /* Set the TRB length, TD size, and interrupter fields. */
2990 if (xhci->hci_version < 0x100) {
2991 remainder = xhci_td_remainder(
2992 urb->transfer_buffer_length -
2993 running_total);
2994 } else {
2995 remainder = xhci_v1_0_td_remainder(running_total,
2996 trb_buff_len, total_packet_count, urb);
2997 }
2998 length_field = TRB_LEN(trb_buff_len) |
2999 remainder |
3000 TRB_INTR_TARGET(0);
3001
3002 if (num_trbs > 1)
3003 more_trbs_coming = true;
3004 else
3005 more_trbs_coming = false;
3006 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3007 lower_32_bits(addr),
3008 upper_32_bits(addr),
3009 length_field,
3010 field | TRB_TYPE(TRB_NORMAL));
3011 --num_trbs;
3012 running_total += trb_buff_len;
3013
3014 /* Calculate length for next transfer */
3015 addr += trb_buff_len;
3016 trb_buff_len = urb->transfer_buffer_length - running_total;
3017 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3018 trb_buff_len = TRB_MAX_BUFF_SIZE;
3019 } while (running_total < urb->transfer_buffer_length);
3020
3021 check_trb_math(urb, num_trbs, running_total);
3022 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3023 start_cycle, start_trb);
3024 return 0;
3025}
3026
3027/* Caller must have locked xhci->lock */
3028int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3029 struct urb *urb, int slot_id, unsigned int ep_index)
3030{
3031 struct xhci_ring *ep_ring;
3032 int num_trbs;
3033 int ret;
3034 struct usb_ctrlrequest *setup;
3035 struct xhci_generic_trb *start_trb;
3036 int start_cycle;
3037 u32 field, length_field;
3038 struct urb_priv *urb_priv;
3039 struct xhci_td *td;
3040
3041 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3042 if (!ep_ring)
3043 return -EINVAL;
3044
3045 /*
3046 * Need to copy setup packet into setup TRB, so we can't use the setup
3047 * DMA address.
3048 */
3049 if (!urb->setup_packet)
3050 return -EINVAL;
3051
3052 if (!in_interrupt())
3053 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3054 slot_id, ep_index);
3055 /* 1 TRB for setup, 1 for status */
3056 num_trbs = 2;
3057 /*
3058 * Don't need to check if we need additional event data and normal TRBs,
3059 * since data in control transfers will never get bigger than 16MB
3060 * XXX: can we get a buffer that crosses 64KB boundaries?
3061 */
3062 if (urb->transfer_buffer_length > 0)
3063 num_trbs++;
3064 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3065 ep_index, urb->stream_id,
3066 num_trbs, urb, 0, mem_flags);
3067 if (ret < 0)
3068 return ret;
3069
3070 urb_priv = urb->hcpriv;
3071 td = urb_priv->td[0];
3072
3073 /*
3074 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3075 * until we've finished creating all the other TRBs. The ring's cycle
3076 * state may change as we enqueue the other TRBs, so save it too.
3077 */
3078 start_trb = &ep_ring->enqueue->generic;
3079 start_cycle = ep_ring->cycle_state;
3080
3081 /* Queue setup TRB - see section 6.4.1.2.1 */
3082 /* FIXME better way to translate setup_packet into two u32 fields? */
3083 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3084 field = 0;
3085 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3086 if (start_cycle == 0)
3087 field |= 0x1;
3088
3089 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3090 if (xhci->hci_version == 0x100) {
3091 if (urb->transfer_buffer_length > 0) {
3092 if (setup->bRequestType & USB_DIR_IN)
3093 field |= TRB_TX_TYPE(TRB_DATA_IN);
3094 else
3095 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3096 }
3097 }
3098
3099 queue_trb(xhci, ep_ring, false, true,
3100 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3101 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3102 TRB_LEN(8) | TRB_INTR_TARGET(0),
3103 /* Immediate data in pointer */
3104 field);
3105
3106 /* If there's data, queue data TRBs */
3107 /* Only set interrupt on short packet for IN endpoints */
3108 if (usb_urb_dir_in(urb))
3109 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3110 else
3111 field = TRB_TYPE(TRB_DATA);
3112
3113 length_field = TRB_LEN(urb->transfer_buffer_length) |
3114 xhci_td_remainder(urb->transfer_buffer_length) |
3115 TRB_INTR_TARGET(0);
3116 if (urb->transfer_buffer_length > 0) {
3117 if (setup->bRequestType & USB_DIR_IN)
3118 field |= TRB_DIR_IN;
3119 queue_trb(xhci, ep_ring, false, true,
3120 lower_32_bits(urb->transfer_dma),
3121 upper_32_bits(urb->transfer_dma),
3122 length_field,
3123 field | ep_ring->cycle_state);
3124 }
3125
3126 /* Save the DMA address of the last TRB in the TD */
3127 td->last_trb = ep_ring->enqueue;
3128
3129 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3130 /* If the device sent data, the status stage is an OUT transfer */
3131 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3132 field = 0;
3133 else
3134 field = TRB_DIR_IN;
3135 queue_trb(xhci, ep_ring, false, false,
3136 0,
3137 0,
3138 TRB_INTR_TARGET(0),
3139 /* Event on completion */
3140 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3141
3142 giveback_first_trb(xhci, slot_id, ep_index, 0,
3143 start_cycle, start_trb);
3144 return 0;
3145}
3146
3147static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3148 struct urb *urb, int i)
3149{
3150 int num_trbs = 0;
3151 u64 addr, td_len;
3152
3153 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3154 td_len = urb->iso_frame_desc[i].length;
3155
3156 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3157 TRB_MAX_BUFF_SIZE);
3158 if (num_trbs == 0)
3159 num_trbs++;
3160
3161 return num_trbs;
3162}
3163
3164/*
3165 * The transfer burst count field of the isochronous TRB defines the number of
3166 * bursts that are required to move all packets in this TD. Only SuperSpeed
3167 * devices can burst up to bMaxBurst number of packets per service interval.
3168 * This field is zero based, meaning a value of zero in the field means one
3169 * burst. Basically, for everything but SuperSpeed devices, this field will be
3170 * zero. Only xHCI 1.0 host controllers support this field.
3171 */
3172static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3173 struct usb_device *udev,
3174 struct urb *urb, unsigned int total_packet_count)
3175{
3176 unsigned int max_burst;
3177
3178 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3179 return 0;
3180
3181 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3182 return roundup(total_packet_count, max_burst + 1) - 1;
3183}
3184
3185/*
3186 * Returns the number of packets in the last "burst" of packets. This field is
3187 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3188 * the last burst packet count is equal to the total number of packets in the
3189 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3190 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3191 * contain 1 to (bMaxBurst + 1) packets.
3192 */
3193static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3194 struct usb_device *udev,
3195 struct urb *urb, unsigned int total_packet_count)
3196{
3197 unsigned int max_burst;
3198 unsigned int residue;
3199
3200 if (xhci->hci_version < 0x100)
3201 return 0;
3202
3203 switch (udev->speed) {
3204 case USB_SPEED_SUPER:
3205 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3206 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3207 residue = total_packet_count % (max_burst + 1);
3208 /* If residue is zero, the last burst contains (max_burst + 1)
3209 * number of packets, but the TLBPC field is zero-based.
3210 */
3211 if (residue == 0)
3212 return max_burst;
3213 return residue - 1;
3214 default:
3215 if (total_packet_count == 0)
3216 return 0;
3217 return total_packet_count - 1;
3218 }
3219}
3220
3221/* This is for isoc transfer */
3222static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3223 struct urb *urb, int slot_id, unsigned int ep_index)
3224{
3225 struct xhci_ring *ep_ring;
3226 struct urb_priv *urb_priv;
3227 struct xhci_td *td;
3228 int num_tds, trbs_per_td;
3229 struct xhci_generic_trb *start_trb;
3230 bool first_trb;
3231 int start_cycle;
3232 u32 field, length_field;
3233 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3234 u64 start_addr, addr;
3235 int i, j;
3236 bool more_trbs_coming;
3237
3238 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3239
3240 num_tds = urb->number_of_packets;
3241 if (num_tds < 1) {
3242 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3243 return -EINVAL;
3244 }
3245
3246 if (!in_interrupt())
3247 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3248 " addr = %#llx, num_tds = %d\n",
3249 urb->ep->desc.bEndpointAddress,
3250 urb->transfer_buffer_length,
3251 urb->transfer_buffer_length,
3252 (unsigned long long)urb->transfer_dma,
3253 num_tds);
3254
3255 start_addr = (u64) urb->transfer_dma;
3256 start_trb = &ep_ring->enqueue->generic;
3257 start_cycle = ep_ring->cycle_state;
3258
3259 urb_priv = urb->hcpriv;
3260 /* Queue the first TRB, even if it's zero-length */
3261 for (i = 0; i < num_tds; i++) {
3262 unsigned int total_packet_count;
3263 unsigned int burst_count;
3264 unsigned int residue;
3265
3266 first_trb = true;
3267 running_total = 0;
3268 addr = start_addr + urb->iso_frame_desc[i].offset;
3269 td_len = urb->iso_frame_desc[i].length;
3270 td_remain_len = td_len;
3271 total_packet_count = roundup(td_len,
3272 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3273 /* A zero-length transfer still involves at least one packet. */
3274 if (total_packet_count == 0)
3275 total_packet_count++;
3276 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3277 total_packet_count);
3278 residue = xhci_get_last_burst_packet_count(xhci,
3279 urb->dev, urb, total_packet_count);
3280
3281 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3282
3283 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3284 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3285 if (ret < 0) {
3286 if (i == 0)
3287 return ret;
3288 goto cleanup;
3289 }
3290
3291 td = urb_priv->td[i];
3292 for (j = 0; j < trbs_per_td; j++) {
3293 u32 remainder = 0;
3294 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3295
3296 if (first_trb) {
3297 /* Queue the isoc TRB */
3298 field |= TRB_TYPE(TRB_ISOC);
3299 /* Assume URB_ISO_ASAP is set */
3300 field |= TRB_SIA;
3301 if (i == 0) {
3302 if (start_cycle == 0)
3303 field |= 0x1;
3304 } else
3305 field |= ep_ring->cycle_state;
3306 first_trb = false;
3307 } else {
3308 /* Queue other normal TRBs */
3309 field |= TRB_TYPE(TRB_NORMAL);
3310 field |= ep_ring->cycle_state;
3311 }
3312
3313 /* Only set interrupt on short packet for IN EPs */
3314 if (usb_urb_dir_in(urb))
3315 field |= TRB_ISP;
3316
3317 /* Chain all the TRBs together; clear the chain bit in
3318 * the last TRB to indicate it's the last TRB in the
3319 * chain.
3320 */
3321 if (j < trbs_per_td - 1) {
3322 field |= TRB_CHAIN;
3323 more_trbs_coming = true;
3324 } else {
3325 td->last_trb = ep_ring->enqueue;
3326 field |= TRB_IOC;
3327 if (xhci->hci_version == 0x100) {
3328 /* Set BEI bit except for the last td */
3329 if (i < num_tds - 1)
3330 field |= TRB_BEI;
3331 }
3332 more_trbs_coming = false;
3333 }
3334
3335 /* Calculate TRB length */
3336 trb_buff_len = TRB_MAX_BUFF_SIZE -
3337 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3338 if (trb_buff_len > td_remain_len)
3339 trb_buff_len = td_remain_len;
3340
3341 /* Set the TRB length, TD size, & interrupter fields. */
3342 if (xhci->hci_version < 0x100) {
3343 remainder = xhci_td_remainder(
3344 td_len - running_total);
3345 } else {
3346 remainder = xhci_v1_0_td_remainder(
3347 running_total, trb_buff_len,
3348 total_packet_count, urb);
3349 }
3350 length_field = TRB_LEN(trb_buff_len) |
3351 remainder |
3352 TRB_INTR_TARGET(0);
3353
3354 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3355 lower_32_bits(addr),
3356 upper_32_bits(addr),
3357 length_field,
3358 field);
3359 running_total += trb_buff_len;
3360
3361 addr += trb_buff_len;
3362 td_remain_len -= trb_buff_len;
3363 }
3364
3365 /* Check TD length */
3366 if (running_total != td_len) {
3367 xhci_err(xhci, "ISOC TD length unmatch\n");
3368 return -EINVAL;
3369 }
3370 }
3371
3372 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3373 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3374 usb_amd_quirk_pll_disable();
3375 }
3376 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3377
3378 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3379 start_cycle, start_trb);
3380 return 0;
3381cleanup:
3382 /* Clean up a partially enqueued isoc transfer. */
3383
3384 for (i--; i >= 0; i--)
3385 list_del_init(&urb_priv->td[i]->td_list);
3386
3387 /* Use the first TD as a temporary variable to turn the TDs we've queued
3388 * into No-ops with a software-owned cycle bit. That way the hardware
3389 * won't accidentally start executing bogus TDs when we partially
3390 * overwrite them. td->first_trb and td->start_seg are already set.
3391 */
3392 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3393 /* Every TRB except the first & last will have its cycle bit flipped. */
3394 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3395
3396 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3397 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3398 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3399 ep_ring->cycle_state = start_cycle;
3400 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3401 return ret;
3402}
3403
3404/*
3405 * Check transfer ring to guarantee there is enough room for the urb.
3406 * Update ISO URB start_frame and interval.
3407 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3408 * update the urb->start_frame by now.
3409 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3410 */
3411int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3412 struct urb *urb, int slot_id, unsigned int ep_index)
3413{
3414 struct xhci_virt_device *xdev;
3415 struct xhci_ring *ep_ring;
3416 struct xhci_ep_ctx *ep_ctx;
3417 int start_frame;
3418 int xhci_interval;
3419 int ep_interval;
3420 int num_tds, num_trbs, i;
3421 int ret;
3422
3423 xdev = xhci->devs[slot_id];
3424 ep_ring = xdev->eps[ep_index].ring;
3425 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3426
3427 num_trbs = 0;
3428 num_tds = urb->number_of_packets;
3429 for (i = 0; i < num_tds; i++)
3430 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3431
3432 /* Check the ring to guarantee there is enough room for the whole urb.
3433 * Do not insert any td of the urb to the ring if the check failed.
3434 */
3435 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3436 num_trbs, mem_flags);
3437 if (ret)
3438 return ret;
3439
3440 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3441 start_frame &= 0x3fff;
3442
3443 urb->start_frame = start_frame;
3444 if (urb->dev->speed == USB_SPEED_LOW ||
3445 urb->dev->speed == USB_SPEED_FULL)
3446 urb->start_frame >>= 3;
3447
3448 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3449 ep_interval = urb->interval;
3450 /* Convert to microframes */
3451 if (urb->dev->speed == USB_SPEED_LOW ||
3452 urb->dev->speed == USB_SPEED_FULL)
3453 ep_interval *= 8;
3454 /* FIXME change this to a warning and a suggestion to use the new API
3455 * to set the polling interval (once the API is added).
3456 */
3457 if (xhci_interval != ep_interval) {
3458 if (printk_ratelimit())
3459 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3460 " (%d microframe%s) than xHCI "
3461 "(%d microframe%s)\n",
3462 ep_interval,
3463 ep_interval == 1 ? "" : "s",
3464 xhci_interval,
3465 xhci_interval == 1 ? "" : "s");
3466 urb->interval = xhci_interval;
3467 /* Convert back to frames for LS/FS devices */
3468 if (urb->dev->speed == USB_SPEED_LOW ||
3469 urb->dev->speed == USB_SPEED_FULL)
3470 urb->interval /= 8;
3471 }
3472 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3473}
3474
3475/**** Command Ring Operations ****/
3476
3477/* Generic function for queueing a command TRB on the command ring.
3478 * Check to make sure there's room on the command ring for one command TRB.
3479 * Also check that there's room reserved for commands that must not fail.
3480 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3481 * then only check for the number of reserved spots.
3482 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3483 * because the command event handler may want to resubmit a failed command.
3484 */
3485static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3486 u32 field3, u32 field4, bool command_must_succeed)
3487{
3488 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3489 int ret;
3490
3491 if (!command_must_succeed)
3492 reserved_trbs++;
3493
3494 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3495 reserved_trbs, GFP_ATOMIC);
3496 if (ret < 0) {
3497 xhci_err(xhci, "ERR: No room for command on command ring\n");
3498 if (command_must_succeed)
3499 xhci_err(xhci, "ERR: Reserved TRB counting for "
3500 "unfailable commands failed.\n");
3501 return ret;
3502 }
3503 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3504 field4 | xhci->cmd_ring->cycle_state);
3505 return 0;
3506}
3507
3508/* Queue a slot enable or disable request on the command ring */
3509int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3510{
3511 return queue_command(xhci, 0, 0, 0,
3512 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3513}
3514
3515/* Queue an address device command TRB */
3516int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3517 u32 slot_id)
3518{
3519 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3520 upper_32_bits(in_ctx_ptr), 0,
3521 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3522 false);
3523}
3524
3525int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3526 u32 field1, u32 field2, u32 field3, u32 field4)
3527{
3528 return queue_command(xhci, field1, field2, field3, field4, false);
3529}
3530
3531/* Queue a reset device command TRB */
3532int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3533{
3534 return queue_command(xhci, 0, 0, 0,
3535 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3536 false);
3537}
3538
3539/* Queue a configure endpoint command TRB */
3540int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3541 u32 slot_id, bool command_must_succeed)
3542{
3543 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3544 upper_32_bits(in_ctx_ptr), 0,
3545 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3546 command_must_succeed);
3547}
3548
3549/* Queue an evaluate context command TRB */
3550int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3551 u32 slot_id)
3552{
3553 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3554 upper_32_bits(in_ctx_ptr), 0,
3555 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3556 false);
3557}
3558
3559/*
3560 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3561 * activity on an endpoint that is about to be suspended.
3562 */
3563int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3564 unsigned int ep_index, int suspend)
3565{
3566 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3567 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3568 u32 type = TRB_TYPE(TRB_STOP_RING);
3569 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3570
3571 return queue_command(xhci, 0, 0, 0,
3572 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3573}
3574
3575/* Set Transfer Ring Dequeue Pointer command.
3576 * This should not be used for endpoints that have streams enabled.
3577 */
3578static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3579 unsigned int ep_index, unsigned int stream_id,
3580 struct xhci_segment *deq_seg,
3581 union xhci_trb *deq_ptr, u32 cycle_state)
3582{
3583 dma_addr_t addr;
3584 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3585 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3586 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3587 u32 type = TRB_TYPE(TRB_SET_DEQ);
3588 struct xhci_virt_ep *ep;
3589
3590 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3591 if (addr == 0) {
3592 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3593 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3594 deq_seg, deq_ptr);
3595 return 0;
3596 }
3597 ep = &xhci->devs[slot_id]->eps[ep_index];
3598 if ((ep->ep_state & SET_DEQ_PENDING)) {
3599 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3600 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3601 return 0;
3602 }
3603 ep->queued_deq_seg = deq_seg;
3604 ep->queued_deq_ptr = deq_ptr;
3605 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3606 upper_32_bits(addr), trb_stream_id,
3607 trb_slot_id | trb_ep_index | type, false);
3608}
3609
3610int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3611 unsigned int ep_index)
3612{
3613 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3614 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3615 u32 type = TRB_TYPE(TRB_RESET_EP);
3616
3617 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3618 false);
3619}