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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __ASM_OCTEON_OCTEON_H
9#define __ASM_OCTEON_OCTEON_H
10
11#include <asm/octeon/cvmx.h>
12#include <asm/bitfield.h>
13
14extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
15 uint64_t alignment,
16 uint64_t min_addr,
17 uint64_t max_addr,
18 int do_locking);
19extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
20 int do_locking);
21extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
22 uint64_t min_addr, uint64_t max_addr,
23 int do_locking);
24extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
25 char *name);
26extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
27 uint64_t max_addr, uint64_t align,
28 char *name);
29extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
30 char *name);
31extern int octeon_bootmem_free_named(char *name);
32extern void octeon_bootmem_lock(void);
33extern void octeon_bootmem_unlock(void);
34
35extern int octeon_is_simulation(void);
36extern int octeon_is_pci_host(void);
37extern int octeon_usb_is_ref_clk(void);
38extern uint64_t octeon_get_clock_rate(void);
39extern u64 octeon_get_io_clock_rate(void);
40extern const char *octeon_board_type_string(void);
41extern const char *octeon_get_pci_interrupts(void);
42extern int octeon_get_southbridge_interrupt(void);
43extern int octeon_get_boot_coremask(void);
44extern int octeon_get_boot_num_arguments(void);
45extern const char *octeon_get_boot_argument(int arg);
46extern void octeon_user_io_init(void);
47
48extern void octeon_init_cvmcount(void);
49extern void octeon_setup_delays(void);
50extern void octeon_io_clk_delay(unsigned long);
51
52#define OCTEON_ARGV_MAX_ARGS 64
53#define OCTEON_SERIAL_LEN 20
54
55struct octeon_boot_descriptor {
56#ifdef __BIG_ENDIAN_BITFIELD
57 /* Start of block referenced by assembly code - do not change! */
58 uint32_t desc_version;
59 uint32_t desc_size;
60 uint64_t stack_top;
61 uint64_t heap_base;
62 uint64_t heap_end;
63 /* Only used by bootloader */
64 uint64_t entry_point;
65 uint64_t desc_vaddr;
66 /* End of This block referenced by assembly code - do not change! */
67 uint32_t exception_base_addr;
68 uint32_t stack_size;
69 uint32_t heap_size;
70 /* Argc count for application. */
71 uint32_t argc;
72 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
73
74#define BOOT_FLAG_INIT_CORE (1 << 0)
75#define OCTEON_BL_FLAG_DEBUG (1 << 1)
76#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
77 /* If set, use uart1 for console */
78#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
79 /* If set, use PCI console */
80#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
81 /* Call exit on break on serial port */
82#define OCTEON_BL_FLAG_BREAK (1 << 5)
83
84 uint32_t flags;
85 uint32_t core_mask;
86 /* DRAM size in megabyes. */
87 uint32_t dram_size;
88 /* physical address of free memory descriptor block. */
89 uint32_t phy_mem_desc_addr;
90 /* used to pass flags from app to debugger. */
91 uint32_t debugger_flags_base_addr;
92 /* CPU clock speed, in hz. */
93 uint32_t eclock_hz;
94 /* DRAM clock speed, in hz. */
95 uint32_t dclock_hz;
96 /* SPI4 clock in hz. */
97 uint32_t spi_clock_hz;
98 uint16_t board_type;
99 uint8_t board_rev_major;
100 uint8_t board_rev_minor;
101 uint16_t chip_type;
102 uint8_t chip_rev_major;
103 uint8_t chip_rev_minor;
104 char board_serial_number[OCTEON_SERIAL_LEN];
105 uint8_t mac_addr_base[6];
106 uint8_t mac_addr_count;
107 uint64_t cvmx_desc_vaddr;
108#else
109 uint32_t desc_size;
110 uint32_t desc_version;
111 uint64_t stack_top;
112 uint64_t heap_base;
113 uint64_t heap_end;
114 /* Only used by bootloader */
115 uint64_t entry_point;
116 uint64_t desc_vaddr;
117 /* End of This block referenced by assembly code - do not change! */
118 uint32_t stack_size;
119 uint32_t exception_base_addr;
120 uint32_t argc;
121 uint32_t heap_size;
122 /*
123 * Argc count for application.
124 * Warning low bit scrambled in little-endian.
125 */
126 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
127
128#define BOOT_FLAG_INIT_CORE (1 << 0)
129#define OCTEON_BL_FLAG_DEBUG (1 << 1)
130#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
131 /* If set, use uart1 for console */
132#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
133 /* If set, use PCI console */
134#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
135 /* Call exit on break on serial port */
136#define OCTEON_BL_FLAG_BREAK (1 << 5)
137
138 uint32_t core_mask;
139 uint32_t flags;
140 /* physical address of free memory descriptor block. */
141 uint32_t phy_mem_desc_addr;
142 /* DRAM size in megabyes. */
143 uint32_t dram_size;
144 /* CPU clock speed, in hz. */
145 uint32_t eclock_hz;
146 /* used to pass flags from app to debugger. */
147 uint32_t debugger_flags_base_addr;
148 /* SPI4 clock in hz. */
149 uint32_t spi_clock_hz;
150 /* DRAM clock speed, in hz. */
151 uint32_t dclock_hz;
152 uint8_t chip_rev_minor;
153 uint8_t chip_rev_major;
154 uint16_t chip_type;
155 uint8_t board_rev_minor;
156 uint8_t board_rev_major;
157 uint16_t board_type;
158
159 uint64_t unused1[4]; /* Not even filled in by bootloader. */
160
161 uint64_t cvmx_desc_vaddr;
162#endif
163};
164
165union octeon_cvmemctl {
166 uint64_t u64;
167 struct {
168 /* RO 1 = BIST fail, 0 = BIST pass */
169 __BITFIELD_FIELD(uint64_t tlbbist:1,
170 /* RO 1 = BIST fail, 0 = BIST pass */
171 __BITFIELD_FIELD(uint64_t l1cbist:1,
172 /* RO 1 = BIST fail, 0 = BIST pass */
173 __BITFIELD_FIELD(uint64_t l1dbist:1,
174 /* RO 1 = BIST fail, 0 = BIST pass */
175 __BITFIELD_FIELD(uint64_t dcmbist:1,
176 /* RO 1 = BIST fail, 0 = BIST pass */
177 __BITFIELD_FIELD(uint64_t ptgbist:1,
178 /* RO 1 = BIST fail, 0 = BIST pass */
179 __BITFIELD_FIELD(uint64_t wbfbist:1,
180 /* Reserved */
181 __BITFIELD_FIELD(uint64_t reserved:17,
182 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
183 * This field selects between the TLB replacement policies:
184 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
185 * recently used TLB entries and avoids them as new entries
186 * are allocated. NLU simply guarantees that the next
187 * allocation is not the last used TLB entry. */
188 __BITFIELD_FIELD(uint64_t tlbnlu:1,
189 /* OCTEON II - Selects the bit in the counter used for
190 * releasing a PAUSE. This counter trips every 2(8+PAUSETIME)
191 * cycles. If not already released, the cnMIPS II core will
192 * always release a given PAUSE instruction within
193 * 2(8+PAUSETIME). If the counter trip happens to line up,
194 * the cnMIPS II core may release the PAUSE instantly. */
195 __BITFIELD_FIELD(uint64_t pausetime:3,
196 /* OCTEON II - This field is an extension of
197 * CvmMemCtl[DIDTTO] */
198 __BITFIELD_FIELD(uint64_t didtto2:1,
199 /* R/W If set, marked write-buffer entries time out
200 * the same as other entries; if clear, marked
201 * write-buffer entries use the maximum timeout. */
202 __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
203 /* R/W If set, a merged store does not clear the
204 * write-buffer entry timeout state. */
205 __BITFIELD_FIELD(uint64_t dismrgclrwbto:1,
206 /* R/W Two bits that are the MSBs of the resultant
207 * CVMSEG LM word location for an IOBDMA. The other 8
208 * bits come from the SCRADDR field of the IOBDMA. */
209 __BITFIELD_FIELD(uint64_t iobdmascrmsb:2,
210 /* R/W If set, SYNCWS and SYNCS only order marked
211 * stores; if clear, SYNCWS and SYNCS only order
212 * unmarked stores. SYNCWSMARKED has no effect when
213 * DISSYNCWS is set. */
214 __BITFIELD_FIELD(uint64_t syncwsmarked:1,
215 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
216 * SYNC. */
217 __BITFIELD_FIELD(uint64_t dissyncws:1,
218 /* R/W If set, no stall happens on write buffer
219 * full. */
220 __BITFIELD_FIELD(uint64_t diswbfst:1,
221 /* R/W If set (and SX set), supervisor-level
222 * loads/stores can use XKPHYS addresses with
223 * VA<48>==0 */
224 __BITFIELD_FIELD(uint64_t xkmemenas:1,
225 /* R/W If set (and UX set), user-level loads/stores
226 * can use XKPHYS addresses with VA<48>==0 */
227 __BITFIELD_FIELD(uint64_t xkmemenau:1,
228 /* R/W If set (and SX set), supervisor-level
229 * loads/stores can use XKPHYS addresses with
230 * VA<48>==1 */
231 __BITFIELD_FIELD(uint64_t xkioenas:1,
232 /* R/W If set (and UX set), user-level loads/stores
233 * can use XKPHYS addresses with VA<48>==1 */
234 __BITFIELD_FIELD(uint64_t xkioenau:1,
235 /* R/W If set, all stores act as SYNCW (NOMERGE must
236 * be set when this is set) RW, reset to 0. */
237 __BITFIELD_FIELD(uint64_t allsyncw:1,
238 /* R/W If set, no stores merge, and all stores reach
239 * the coherent bus in order. */
240 __BITFIELD_FIELD(uint64_t nomerge:1,
241 /* R/W Selects the bit in the counter used for DID
242 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
243 * 214. Actual time-out is between 1x and 2x this
244 * interval. For example, with DIDTTO=3, expiration
245 * interval is between 16K and 32K. */
246 __BITFIELD_FIELD(uint64_t didtto:2,
247 /* R/W If set, the (mem) CSR clock never turns off. */
248 __BITFIELD_FIELD(uint64_t csrckalwys:1,
249 /* R/W If set, mclk never turns off. */
250 __BITFIELD_FIELD(uint64_t mclkalwys:1,
251 /* R/W Selects the bit in the counter used for write
252 * buffer flush time-outs (WBFLT+11) is the bit
253 * position in an internal counter used to determine
254 * expiration. The write buffer expires between 1x and
255 * 2x this interval. For example, with WBFLT = 0, a
256 * write buffer expires between 2K and 4K cycles after
257 * the write buffer entry is allocated. */
258 __BITFIELD_FIELD(uint64_t wbfltime:3,
259 /* R/W If set, do not put Istream in the L2 cache. */
260 __BITFIELD_FIELD(uint64_t istrnol2:1,
261 /* R/W The write buffer threshold. */
262 __BITFIELD_FIELD(uint64_t wbthresh:4,
263 /* Reserved */
264 __BITFIELD_FIELD(uint64_t reserved2:2,
265 /* R/W If set, CVMSEG is available for loads/stores in
266 * kernel/debug mode. */
267 __BITFIELD_FIELD(uint64_t cvmsegenak:1,
268 /* R/W If set, CVMSEG is available for loads/stores in
269 * supervisor mode. */
270 __BITFIELD_FIELD(uint64_t cvmsegenas:1,
271 /* R/W If set, CVMSEG is available for loads/stores in
272 * user mode. */
273 __BITFIELD_FIELD(uint64_t cvmsegenau:1,
274 /* R/W Size of local memory in cache blocks, 54 (6912
275 * bytes) is max legal value. */
276 __BITFIELD_FIELD(uint64_t lmemsz:6,
277 ;)))))))))))))))))))))))))))))))))
278 } s;
279};
280
281extern void octeon_check_cpu_bist(void);
282
283int octeon_prune_device_tree(void);
284extern const char __dtb_octeon_3xxx_begin;
285extern const char __dtb_octeon_68xx_begin;
286
287/**
288 * Write a 32bit value to the Octeon NPI register space
289 *
290 * @address: Address to write to
291 * @val: Value to write
292 */
293static inline void octeon_npi_write32(uint64_t address, uint32_t val)
294{
295 cvmx_write64_uint32(address ^ 4, val);
296 cvmx_read64_uint32(address ^ 4);
297}
298
299#ifdef CONFIG_SMP
300void octeon_setup_smp(void);
301#else
302static inline void octeon_setup_smp(void) {}
303#endif
304
305struct irq_domain;
306struct device_node;
307struct irq_data;
308struct irq_chip;
309void octeon_ciu3_mbox_send(int cpu, unsigned int mbox);
310int octeon_irq_ciu3_xlat(struct irq_domain *d,
311 struct device_node *node,
312 const u32 *intspec,
313 unsigned int intsize,
314 unsigned long *out_hwirq,
315 unsigned int *out_type);
316void octeon_irq_ciu3_enable(struct irq_data *data);
317void octeon_irq_ciu3_disable(struct irq_data *data);
318void octeon_irq_ciu3_ack(struct irq_data *data);
319void octeon_irq_ciu3_mask(struct irq_data *data);
320void octeon_irq_ciu3_mask_ack(struct irq_data *data);
321int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
322 irq_hw_number_t hw, struct irq_chip *chip);
323
324/* Octeon multiplier save/restore routines from octeon_switch.S */
325void octeon_mult_save(void);
326void octeon_mult_restore(void);
327void octeon_mult_save_end(void);
328void octeon_mult_restore_end(void);
329void octeon_mult_save3(void);
330void octeon_mult_save3_end(void);
331void octeon_mult_save2(void);
332void octeon_mult_save2_end(void);
333void octeon_mult_restore3(void);
334void octeon_mult_restore3_end(void);
335void octeon_mult_restore2(void);
336void octeon_mult_restore2_end(void);
337
338/**
339 * Read a 32bit value from the Octeon NPI register space
340 *
341 * @address: Address to read
342 * Returns The result
343 */
344static inline uint32_t octeon_npi_read32(uint64_t address)
345{
346 return cvmx_read64_uint32(address ^ 4);
347}
348
349extern struct cvmx_bootinfo *octeon_bootinfo;
350
351extern uint64_t octeon_bootloader_entry_addr;
352
353extern void (*octeon_irq_setup_secondary)(void);
354
355typedef void (*octeon_irq_ip4_handler_t)(void);
356void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
357
358extern void octeon_fixup_irqs(void);
359
360extern struct semaphore octeon_bootbus_sem;
361
362struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);
363
364#endif /* __ASM_OCTEON_OCTEON_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __ASM_OCTEON_OCTEON_H
9#define __ASM_OCTEON_OCTEON_H
10
11#include "cvmx.h"
12
13extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 uint64_t alignment,
15 uint64_t min_addr,
16 uint64_t max_addr,
17 int do_locking);
18extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
19 int do_locking);
20extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 uint64_t min_addr, uint64_t max_addr,
22 int do_locking);
23extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
24 char *name);
25extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 uint64_t max_addr, uint64_t align,
27 char *name);
28extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
29 char *name);
30extern int octeon_bootmem_free_named(char *name);
31extern void octeon_bootmem_lock(void);
32extern void octeon_bootmem_unlock(void);
33
34extern int octeon_is_simulation(void);
35extern int octeon_is_pci_host(void);
36extern int octeon_usb_is_ref_clk(void);
37extern uint64_t octeon_get_clock_rate(void);
38extern u64 octeon_get_io_clock_rate(void);
39extern const char *octeon_board_type_string(void);
40extern const char *octeon_get_pci_interrupts(void);
41extern int octeon_get_southbridge_interrupt(void);
42extern int octeon_get_boot_coremask(void);
43extern int octeon_get_boot_num_arguments(void);
44extern const char *octeon_get_boot_argument(int arg);
45extern void octeon_hal_setup_reserved32(void);
46extern void octeon_user_io_init(void);
47struct octeon_cop2_state;
48extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
49extern void octeon_crypto_disable(struct octeon_cop2_state *state,
50 unsigned long flags);
51extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
52
53extern void octeon_init_cvmcount(void);
54extern void octeon_setup_delays(void);
55
56#define OCTEON_ARGV_MAX_ARGS 64
57#define OCTOEN_SERIAL_LEN 20
58
59struct octeon_boot_descriptor {
60 /* Start of block referenced by assembly code - do not change! */
61 uint32_t desc_version;
62 uint32_t desc_size;
63 uint64_t stack_top;
64 uint64_t heap_base;
65 uint64_t heap_end;
66 /* Only used by bootloader */
67 uint64_t entry_point;
68 uint64_t desc_vaddr;
69 /* End of This block referenced by assembly code - do not change! */
70 uint32_t exception_base_addr;
71 uint32_t stack_size;
72 uint32_t heap_size;
73 /* Argc count for application. */
74 uint32_t argc;
75 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
76
77#define BOOT_FLAG_INIT_CORE (1 << 0)
78#define OCTEON_BL_FLAG_DEBUG (1 << 1)
79#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
80 /* If set, use uart1 for console */
81#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
82 /* If set, use PCI console */
83#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
84 /* Call exit on break on serial port */
85#define OCTEON_BL_FLAG_BREAK (1 << 5)
86
87 uint32_t flags;
88 uint32_t core_mask;
89 /* DRAM size in megabyes. */
90 uint32_t dram_size;
91 /* physical address of free memory descriptor block. */
92 uint32_t phy_mem_desc_addr;
93 /* used to pass flags from app to debugger. */
94 uint32_t debugger_flags_base_addr;
95 /* CPU clock speed, in hz. */
96 uint32_t eclock_hz;
97 /* DRAM clock speed, in hz. */
98 uint32_t dclock_hz;
99 /* SPI4 clock in hz. */
100 uint32_t spi_clock_hz;
101 uint16_t board_type;
102 uint8_t board_rev_major;
103 uint8_t board_rev_minor;
104 uint16_t chip_type;
105 uint8_t chip_rev_major;
106 uint8_t chip_rev_minor;
107 char board_serial_number[OCTOEN_SERIAL_LEN];
108 uint8_t mac_addr_base[6];
109 uint8_t mac_addr_count;
110 uint64_t cvmx_desc_vaddr;
111};
112
113union octeon_cvmemctl {
114 uint64_t u64;
115 struct {
116 /* RO 1 = BIST fail, 0 = BIST pass */
117 uint64_t tlbbist:1;
118 /* RO 1 = BIST fail, 0 = BIST pass */
119 uint64_t l1cbist:1;
120 /* RO 1 = BIST fail, 0 = BIST pass */
121 uint64_t l1dbist:1;
122 /* RO 1 = BIST fail, 0 = BIST pass */
123 uint64_t dcmbist:1;
124 /* RO 1 = BIST fail, 0 = BIST pass */
125 uint64_t ptgbist:1;
126 /* RO 1 = BIST fail, 0 = BIST pass */
127 uint64_t wbfbist:1;
128 /* Reserved */
129 uint64_t reserved:22;
130 /* R/W If set, marked write-buffer entries time out
131 * the same as as other entries; if clear, marked
132 * write-buffer entries use the maximum timeout. */
133 uint64_t dismarkwblongto:1;
134 /* R/W If set, a merged store does not clear the
135 * write-buffer entry timeout state. */
136 uint64_t dismrgclrwbto:1;
137 /* R/W Two bits that are the MSBs of the resultant
138 * CVMSEG LM word location for an IOBDMA. The other 8
139 * bits come from the SCRADDR field of the IOBDMA. */
140 uint64_t iobdmascrmsb:2;
141 /* R/W If set, SYNCWS and SYNCS only order marked
142 * stores; if clear, SYNCWS and SYNCS only order
143 * unmarked stores. SYNCWSMARKED has no effect when
144 * DISSYNCWS is set. */
145 uint64_t syncwsmarked:1;
146 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
147 * SYNC. */
148 uint64_t dissyncws:1;
149 /* R/W If set, no stall happens on write buffer
150 * full. */
151 uint64_t diswbfst:1;
152 /* R/W If set (and SX set), supervisor-level
153 * loads/stores can use XKPHYS addresses with
154 * VA<48>==0 */
155 uint64_t xkmemenas:1;
156 /* R/W If set (and UX set), user-level loads/stores
157 * can use XKPHYS addresses with VA<48>==0 */
158 uint64_t xkmemenau:1;
159 /* R/W If set (and SX set), supervisor-level
160 * loads/stores can use XKPHYS addresses with
161 * VA<48>==1 */
162 uint64_t xkioenas:1;
163 /* R/W If set (and UX set), user-level loads/stores
164 * can use XKPHYS addresses with VA<48>==1 */
165 uint64_t xkioenau:1;
166 /* R/W If set, all stores act as SYNCW (NOMERGE must
167 * be set when this is set) RW, reset to 0. */
168 uint64_t allsyncw:1;
169 /* R/W If set, no stores merge, and all stores reach
170 * the coherent bus in order. */
171 uint64_t nomerge:1;
172 /* R/W Selects the bit in the counter used for DID
173 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
174 * 214. Actual time-out is between 1x and 2x this
175 * interval. For example, with DIDTTO=3, expiration
176 * interval is between 16K and 32K. */
177 uint64_t didtto:2;
178 /* R/W If set, the (mem) CSR clock never turns off. */
179 uint64_t csrckalwys:1;
180 /* R/W If set, mclk never turns off. */
181 uint64_t mclkalwys:1;
182 /* R/W Selects the bit in the counter used for write
183 * buffer flush time-outs (WBFLT+11) is the bit
184 * position in an internal counter used to determine
185 * expiration. The write buffer expires between 1x and
186 * 2x this interval. For example, with WBFLT = 0, a
187 * write buffer expires between 2K and 4K cycles after
188 * the write buffer entry is allocated. */
189 uint64_t wbfltime:3;
190 /* R/W If set, do not put Istream in the L2 cache. */
191 uint64_t istrnol2:1;
192 /* R/W The write buffer threshold. */
193 uint64_t wbthresh:4;
194 /* Reserved */
195 uint64_t reserved2:2;
196 /* R/W If set, CVMSEG is available for loads/stores in
197 * kernel/debug mode. */
198 uint64_t cvmsegenak:1;
199 /* R/W If set, CVMSEG is available for loads/stores in
200 * supervisor mode. */
201 uint64_t cvmsegenas:1;
202 /* R/W If set, CVMSEG is available for loads/stores in
203 * user mode. */
204 uint64_t cvmsegenau:1;
205 /* R/W Size of local memory in cache blocks, 54 (6912
206 * bytes) is max legal value. */
207 uint64_t lmemsz:6;
208 } s;
209};
210
211struct octeon_cf_data {
212 unsigned long base_region_bias;
213 unsigned int base_region; /* The chip select region used by CF */
214 int is16bit; /* 0 - 8bit, !0 - 16bit */
215 int dma_engine; /* -1 for no DMA */
216};
217
218struct octeon_i2c_data {
219 unsigned int sys_freq;
220 unsigned int i2c_freq;
221};
222
223extern void octeon_write_lcd(const char *s);
224extern void octeon_check_cpu_bist(void);
225extern int octeon_get_boot_debug_flag(void);
226extern int octeon_get_boot_uart(void);
227
228struct uart_port;
229extern unsigned int octeon_serial_in(struct uart_port *, int);
230extern void octeon_serial_out(struct uart_port *, int, int);
231
232/**
233 * Write a 32bit value to the Octeon NPI register space
234 *
235 * @address: Address to write to
236 * @val: Value to write
237 */
238static inline void octeon_npi_write32(uint64_t address, uint32_t val)
239{
240 cvmx_write64_uint32(address ^ 4, val);
241 cvmx_read64_uint32(address ^ 4);
242}
243
244
245/**
246 * Read a 32bit value from the Octeon NPI register space
247 *
248 * @address: Address to read
249 * Returns The result
250 */
251static inline uint32_t octeon_npi_read32(uint64_t address)
252{
253 return cvmx_read64_uint32(address ^ 4);
254}
255
256extern struct cvmx_bootinfo *octeon_bootinfo;
257
258extern uint64_t octeon_bootloader_entry_addr;
259
260extern void (*octeon_irq_setup_secondary)(void);
261
262#endif /* __ASM_OCTEON_OCTEON_H */