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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * simple driver for PWM (Pulse Width Modulator) controller
4 *
5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
6 *
7 * Limitations:
8 * - When disabled the output is driven to 0 independent of the configured
9 * polarity.
10 */
11
12#include <linux/bitfield.h>
13#include <linux/bitops.h>
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pwm.h>
23#include <linux/slab.h>
24
25#define MX3_PWMCR 0x00 /* PWM Control Register */
26#define MX3_PWMSR 0x04 /* PWM Status Register */
27#define MX3_PWMSAR 0x0C /* PWM Sample Register */
28#define MX3_PWMPR 0x10 /* PWM Period Register */
29
30#define MX3_PWMCR_FWM GENMASK(27, 26)
31#define MX3_PWMCR_STOPEN BIT(25)
32#define MX3_PWMCR_DOZEN BIT(24)
33#define MX3_PWMCR_WAITEN BIT(23)
34#define MX3_PWMCR_DBGEN BIT(22)
35#define MX3_PWMCR_BCTR BIT(21)
36#define MX3_PWMCR_HCTR BIT(20)
37
38#define MX3_PWMCR_POUTC GENMASK(19, 18)
39#define MX3_PWMCR_POUTC_NORMAL 0
40#define MX3_PWMCR_POUTC_INVERTED 1
41#define MX3_PWMCR_POUTC_OFF 2
42
43#define MX3_PWMCR_CLKSRC GENMASK(17, 16)
44#define MX3_PWMCR_CLKSRC_OFF 0
45#define MX3_PWMCR_CLKSRC_IPG 1
46#define MX3_PWMCR_CLKSRC_IPG_HIGH 2
47#define MX3_PWMCR_CLKSRC_IPG_32K 3
48
49#define MX3_PWMCR_PRESCALER GENMASK(15, 4)
50
51#define MX3_PWMCR_SWR BIT(3)
52
53#define MX3_PWMCR_REPEAT GENMASK(2, 1)
54#define MX3_PWMCR_REPEAT_1X 0
55#define MX3_PWMCR_REPEAT_2X 1
56#define MX3_PWMCR_REPEAT_4X 2
57#define MX3_PWMCR_REPEAT_8X 3
58
59#define MX3_PWMCR_EN BIT(0)
60
61#define MX3_PWMSR_FWE BIT(6)
62#define MX3_PWMSR_CMP BIT(5)
63#define MX3_PWMSR_ROV BIT(4)
64#define MX3_PWMSR_FE BIT(3)
65
66#define MX3_PWMSR_FIFOAV GENMASK(2, 0)
67#define MX3_PWMSR_FIFOAV_EMPTY 0
68#define MX3_PWMSR_FIFOAV_1WORD 1
69#define MX3_PWMSR_FIFOAV_2WORDS 2
70#define MX3_PWMSR_FIFOAV_3WORDS 3
71#define MX3_PWMSR_FIFOAV_4WORDS 4
72
73#define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
74#define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
75 (x)) + 1)
76
77#define MX3_PWM_SWR_LOOP 5
78
79/* PWMPR register value of 0xffff has the same effect as 0xfffe */
80#define MX3_PWMPR_MAX 0xfffe
81
82struct pwm_imx27_chip {
83 struct clk *clk_ipg;
84 struct clk *clk_per;
85 void __iomem *mmio_base;
86 struct pwm_chip chip;
87
88 /*
89 * The driver cannot read the current duty cycle from the hardware if
90 * the hardware is disabled. Cache the last programmed duty cycle
91 * value to return in that case.
92 */
93 unsigned int duty_cycle;
94};
95
96#define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
97
98static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
99{
100 int ret;
101
102 ret = clk_prepare_enable(imx->clk_ipg);
103 if (ret)
104 return ret;
105
106 ret = clk_prepare_enable(imx->clk_per);
107 if (ret) {
108 clk_disable_unprepare(imx->clk_ipg);
109 return ret;
110 }
111
112 return 0;
113}
114
115static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
116{
117 clk_disable_unprepare(imx->clk_per);
118 clk_disable_unprepare(imx->clk_ipg);
119}
120
121static int pwm_imx27_get_state(struct pwm_chip *chip,
122 struct pwm_device *pwm, struct pwm_state *state)
123{
124 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
125 u32 period, prescaler, pwm_clk, val;
126 u64 tmp;
127 int ret;
128
129 ret = pwm_imx27_clk_prepare_enable(imx);
130 if (ret < 0)
131 return ret;
132
133 val = readl(imx->mmio_base + MX3_PWMCR);
134
135 if (val & MX3_PWMCR_EN)
136 state->enabled = true;
137 else
138 state->enabled = false;
139
140 switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
141 case MX3_PWMCR_POUTC_NORMAL:
142 state->polarity = PWM_POLARITY_NORMAL;
143 break;
144 case MX3_PWMCR_POUTC_INVERTED:
145 state->polarity = PWM_POLARITY_INVERSED;
146 break;
147 default:
148 dev_warn(chip->dev, "can't set polarity, output disconnected");
149 }
150
151 prescaler = MX3_PWMCR_PRESCALER_GET(val);
152 pwm_clk = clk_get_rate(imx->clk_per);
153 val = readl(imx->mmio_base + MX3_PWMPR);
154 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
155
156 /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
157 tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
158 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
159
160 /*
161 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
162 * use the cached value.
163 */
164 if (state->enabled)
165 val = readl(imx->mmio_base + MX3_PWMSAR);
166 else
167 val = imx->duty_cycle;
168
169 tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
170 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
171
172 pwm_imx27_clk_disable_unprepare(imx);
173
174 return 0;
175}
176
177static void pwm_imx27_sw_reset(struct pwm_chip *chip)
178{
179 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
180 struct device *dev = chip->dev;
181 int wait_count = 0;
182 u32 cr;
183
184 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
185 do {
186 usleep_range(200, 1000);
187 cr = readl(imx->mmio_base + MX3_PWMCR);
188 } while ((cr & MX3_PWMCR_SWR) &&
189 (wait_count++ < MX3_PWM_SWR_LOOP));
190
191 if (cr & MX3_PWMCR_SWR)
192 dev_warn(dev, "software reset timeout\n");
193}
194
195static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
196 struct pwm_device *pwm)
197{
198 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
199 struct device *dev = chip->dev;
200 unsigned int period_ms;
201 int fifoav;
202 u32 sr;
203
204 sr = readl(imx->mmio_base + MX3_PWMSR);
205 fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
206 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
207 period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
208 NSEC_PER_MSEC);
209 msleep(period_ms);
210
211 sr = readl(imx->mmio_base + MX3_PWMSR);
212 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
213 dev_warn(dev, "there is no free FIFO slot\n");
214 }
215}
216
217static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
218 const struct pwm_state *state)
219{
220 unsigned long period_cycles, duty_cycles, prescale;
221 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
222 struct pwm_state cstate;
223 unsigned long long c;
224 unsigned long long clkrate;
225 int ret;
226 u32 cr;
227
228 pwm_get_state(pwm, &cstate);
229
230 clkrate = clk_get_rate(imx->clk_per);
231 c = clkrate * state->period;
232
233 do_div(c, NSEC_PER_SEC);
234 period_cycles = c;
235
236 prescale = period_cycles / 0x10000 + 1;
237
238 period_cycles /= prescale;
239 c = clkrate * state->duty_cycle;
240 do_div(c, NSEC_PER_SEC);
241 duty_cycles = c;
242 duty_cycles /= prescale;
243
244 /*
245 * according to imx pwm RM, the real period value should be PERIOD
246 * value in PWMPR plus 2.
247 */
248 if (period_cycles > 2)
249 period_cycles -= 2;
250 else
251 period_cycles = 0;
252
253 /*
254 * Wait for a free FIFO slot if the PWM is already enabled, and flush
255 * the FIFO if the PWM was disabled and is about to be enabled.
256 */
257 if (cstate.enabled) {
258 pwm_imx27_wait_fifo_slot(chip, pwm);
259 } else {
260 ret = pwm_imx27_clk_prepare_enable(imx);
261 if (ret)
262 return ret;
263
264 pwm_imx27_sw_reset(chip);
265 }
266
267 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
268 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
269
270 /*
271 * Store the duty cycle for future reference in cases where the
272 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
273 */
274 imx->duty_cycle = duty_cycles;
275
276 cr = MX3_PWMCR_PRESCALER_SET(prescale) |
277 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
278 FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
279 MX3_PWMCR_DBGEN;
280
281 if (state->polarity == PWM_POLARITY_INVERSED)
282 cr |= FIELD_PREP(MX3_PWMCR_POUTC,
283 MX3_PWMCR_POUTC_INVERTED);
284
285 if (state->enabled)
286 cr |= MX3_PWMCR_EN;
287
288 writel(cr, imx->mmio_base + MX3_PWMCR);
289
290 if (!state->enabled)
291 pwm_imx27_clk_disable_unprepare(imx);
292
293 return 0;
294}
295
296static const struct pwm_ops pwm_imx27_ops = {
297 .apply = pwm_imx27_apply,
298 .get_state = pwm_imx27_get_state,
299 .owner = THIS_MODULE,
300};
301
302static const struct of_device_id pwm_imx27_dt_ids[] = {
303 { .compatible = "fsl,imx27-pwm", },
304 { /* sentinel */ }
305};
306MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
307
308static int pwm_imx27_probe(struct platform_device *pdev)
309{
310 struct pwm_imx27_chip *imx;
311 int ret;
312 u32 pwmcr;
313
314 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
315 if (imx == NULL)
316 return -ENOMEM;
317
318 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
319 if (IS_ERR(imx->clk_ipg))
320 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
321 "getting ipg clock failed\n");
322
323 imx->clk_per = devm_clk_get(&pdev->dev, "per");
324 if (IS_ERR(imx->clk_per))
325 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
326 "failed to get peripheral clock\n");
327
328 imx->chip.ops = &pwm_imx27_ops;
329 imx->chip.dev = &pdev->dev;
330 imx->chip.npwm = 1;
331
332 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
333 if (IS_ERR(imx->mmio_base))
334 return PTR_ERR(imx->mmio_base);
335
336 ret = pwm_imx27_clk_prepare_enable(imx);
337 if (ret)
338 return ret;
339
340 /* keep clks on if pwm is running */
341 pwmcr = readl(imx->mmio_base + MX3_PWMCR);
342 if (!(pwmcr & MX3_PWMCR_EN))
343 pwm_imx27_clk_disable_unprepare(imx);
344
345 return devm_pwmchip_add(&pdev->dev, &imx->chip);
346}
347
348static struct platform_driver imx_pwm_driver = {
349 .driver = {
350 .name = "pwm-imx27",
351 .of_match_table = pwm_imx27_dt_ids,
352 },
353 .probe = pwm_imx27_probe,
354};
355module_platform_driver(imx_pwm_driver);
356
357MODULE_LICENSE("GPL v2");
358MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");