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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ZynqMP Display Controller Driver
4 *
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
6 *
7 * Authors:
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12#include <drm/drm_fb_dma_helper.h>
13#include <drm/drm_fourcc.h>
14#include <drm/drm_framebuffer.h>
15#include <drm/drm_plane.h>
16
17#include <linux/clk.h>
18#include <linux/dma/xilinx_dpdma.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/media-bus-format.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "zynqmp_disp.h"
28#include "zynqmp_disp_regs.h"
29#include "zynqmp_dp.h"
30#include "zynqmp_dpsub.h"
31
32/*
33 * Overview
34 * --------
35 *
36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
37 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer.
38 *
39 * +------------------------------------------------------------+
40 * +--------+ | +----------------+ +-----------+ |
41 * | DPDMA | --->| | --> | Video | Video +-------------+ |
42 * | 4x vid | | | | | Rendering | -+--> | | | +------+
43 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
44 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
45 * | | and STC | +-----------+ | | Controller | | +------+
46 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
47 * | | | | Mixer | --+-> | | | +------+
48 * Live Audio --->| | --> | | || +-------------+ |
49 * | +----------------+ +-----------+ || |
50 * +---------------------------------------||-------------------+
51 * vv
52 * Blended Video and
53 * Mixed Audio to PL
54 *
55 * Only non-live input from the DPDMA and output to the DisplayPort Source
56 * Controller are currently supported. Interface with the programmable logic
57 * for live streams is not implemented.
58 *
59 * The display controller code creates planes for the DPDMA video and graphics
60 * layers, and a CRTC for the Video Rendering Pipeline.
61 */
62
63#define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4
64#define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6
65
66#define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3
67
68/**
69 * enum zynqmp_dpsub_layer_mode - Layer mode
70 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
71 * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode
72 */
73enum zynqmp_dpsub_layer_mode {
74 ZYNQMP_DPSUB_LAYER_NONLIVE,
75 ZYNQMP_DPSUB_LAYER_LIVE,
76};
77
78/**
79 * struct zynqmp_disp_format - Display subsystem format information
80 * @drm_fmt: DRM format (4CC)
81 * @bus_fmt: Media bus format
82 * @buf_fmt: AV buffer format
83 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats
84 * @sf: Scaling factors for color components
85 */
86struct zynqmp_disp_format {
87 u32 drm_fmt;
88 u32 bus_fmt;
89 u32 buf_fmt;
90 bool swap;
91 const u32 *sf;
92};
93
94/**
95 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer
96 * @chan: DMA channel
97 * @xt: Interleaved DMA descriptor template
98 * @sgl: Data chunk for dma_interleaved_template
99 */
100struct zynqmp_disp_layer_dma {
101 struct dma_chan *chan;
102 struct dma_interleaved_template xt;
103 struct data_chunk sgl;
104};
105
106/**
107 * struct zynqmp_disp_layer_info - Static layer information
108 * @formats: Array of supported formats
109 * @num_formats: Number of formats in @formats array
110 * @num_channels: Number of DMA channels
111 */
112struct zynqmp_disp_layer_info {
113 const struct zynqmp_disp_format *formats;
114 unsigned int num_formats;
115 unsigned int num_channels;
116};
117
118/**
119 * struct zynqmp_disp_layer - Display layer
120 * @id: Layer ID
121 * @disp: Back pointer to struct zynqmp_disp
122 * @info: Static layer information
123 * @dmas: DMA channels
124 * @disp_fmt: Current format information
125 * @drm_fmt: Current DRM format information
126 * @mode: Current operation mode
127 */
128struct zynqmp_disp_layer {
129 enum zynqmp_dpsub_layer_id id;
130 struct zynqmp_disp *disp;
131 const struct zynqmp_disp_layer_info *info;
132
133 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES];
134
135 const struct zynqmp_disp_format *disp_fmt;
136 const struct drm_format_info *drm_fmt;
137 enum zynqmp_dpsub_layer_mode mode;
138};
139
140/**
141 * struct zynqmp_disp - Display controller
142 * @dev: Device structure
143 * @dpsub: Display subsystem
144 * @blend: Register I/O base address for the blender
145 * @avbuf: Register I/O base address for the audio/video buffer manager
146 * @audio: Registers I/O base address for the audio mixer
147 * @layers: Layers (planes)
148 */
149struct zynqmp_disp {
150 struct device *dev;
151 struct zynqmp_dpsub *dpsub;
152
153 void __iomem *blend;
154 void __iomem *avbuf;
155 void __iomem *audio;
156
157 struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS];
158};
159
160/* -----------------------------------------------------------------------------
161 * Audio/Video Buffer Manager
162 */
163
164static const u32 scaling_factors_444[] = {
165 ZYNQMP_DISP_AV_BUF_4BIT_SF,
166 ZYNQMP_DISP_AV_BUF_4BIT_SF,
167 ZYNQMP_DISP_AV_BUF_4BIT_SF,
168};
169
170static const u32 scaling_factors_555[] = {
171 ZYNQMP_DISP_AV_BUF_5BIT_SF,
172 ZYNQMP_DISP_AV_BUF_5BIT_SF,
173 ZYNQMP_DISP_AV_BUF_5BIT_SF,
174};
175
176static const u32 scaling_factors_565[] = {
177 ZYNQMP_DISP_AV_BUF_5BIT_SF,
178 ZYNQMP_DISP_AV_BUF_6BIT_SF,
179 ZYNQMP_DISP_AV_BUF_5BIT_SF,
180};
181
182static const u32 scaling_factors_666[] = {
183 ZYNQMP_DISP_AV_BUF_6BIT_SF,
184 ZYNQMP_DISP_AV_BUF_6BIT_SF,
185 ZYNQMP_DISP_AV_BUF_6BIT_SF,
186};
187
188static const u32 scaling_factors_888[] = {
189 ZYNQMP_DISP_AV_BUF_8BIT_SF,
190 ZYNQMP_DISP_AV_BUF_8BIT_SF,
191 ZYNQMP_DISP_AV_BUF_8BIT_SF,
192};
193
194static const u32 scaling_factors_101010[] = {
195 ZYNQMP_DISP_AV_BUF_10BIT_SF,
196 ZYNQMP_DISP_AV_BUF_10BIT_SF,
197 ZYNQMP_DISP_AV_BUF_10BIT_SF,
198};
199
200/* List of video layer formats */
201static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
202 {
203 .drm_fmt = DRM_FORMAT_VYUY,
204 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
205 .swap = true,
206 .sf = scaling_factors_888,
207 }, {
208 .drm_fmt = DRM_FORMAT_UYVY,
209 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
210 .swap = false,
211 .sf = scaling_factors_888,
212 }, {
213 .drm_fmt = DRM_FORMAT_YUYV,
214 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
215 .swap = false,
216 .sf = scaling_factors_888,
217 }, {
218 .drm_fmt = DRM_FORMAT_YVYU,
219 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
220 .swap = true,
221 .sf = scaling_factors_888,
222 }, {
223 .drm_fmt = DRM_FORMAT_YUV422,
224 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
225 .swap = false,
226 .sf = scaling_factors_888,
227 }, {
228 .drm_fmt = DRM_FORMAT_YVU422,
229 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
230 .swap = true,
231 .sf = scaling_factors_888,
232 }, {
233 .drm_fmt = DRM_FORMAT_YUV444,
234 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
235 .swap = false,
236 .sf = scaling_factors_888,
237 }, {
238 .drm_fmt = DRM_FORMAT_YVU444,
239 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
240 .swap = true,
241 .sf = scaling_factors_888,
242 }, {
243 .drm_fmt = DRM_FORMAT_NV16,
244 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
245 .swap = false,
246 .sf = scaling_factors_888,
247 }, {
248 .drm_fmt = DRM_FORMAT_NV61,
249 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
250 .swap = true,
251 .sf = scaling_factors_888,
252 }, {
253 .drm_fmt = DRM_FORMAT_BGR888,
254 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
255 .swap = false,
256 .sf = scaling_factors_888,
257 }, {
258 .drm_fmt = DRM_FORMAT_RGB888,
259 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
260 .swap = true,
261 .sf = scaling_factors_888,
262 }, {
263 .drm_fmt = DRM_FORMAT_XBGR8888,
264 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
265 .swap = false,
266 .sf = scaling_factors_888,
267 }, {
268 .drm_fmt = DRM_FORMAT_XRGB8888,
269 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
270 .swap = true,
271 .sf = scaling_factors_888,
272 }, {
273 .drm_fmt = DRM_FORMAT_XBGR2101010,
274 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
275 .swap = false,
276 .sf = scaling_factors_101010,
277 }, {
278 .drm_fmt = DRM_FORMAT_XRGB2101010,
279 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
280 .swap = true,
281 .sf = scaling_factors_101010,
282 }, {
283 .drm_fmt = DRM_FORMAT_YUV420,
284 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
285 .swap = false,
286 .sf = scaling_factors_888,
287 }, {
288 .drm_fmt = DRM_FORMAT_YVU420,
289 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
290 .swap = true,
291 .sf = scaling_factors_888,
292 }, {
293 .drm_fmt = DRM_FORMAT_NV12,
294 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
295 .swap = false,
296 .sf = scaling_factors_888,
297 }, {
298 .drm_fmt = DRM_FORMAT_NV21,
299 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
300 .swap = true,
301 .sf = scaling_factors_888,
302 },
303};
304
305/* List of graphics layer formats */
306static const struct zynqmp_disp_format avbuf_gfx_fmts[] = {
307 {
308 .drm_fmt = DRM_FORMAT_ABGR8888,
309 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
310 .swap = false,
311 .sf = scaling_factors_888,
312 }, {
313 .drm_fmt = DRM_FORMAT_ARGB8888,
314 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
315 .swap = true,
316 .sf = scaling_factors_888,
317 }, {
318 .drm_fmt = DRM_FORMAT_RGBA8888,
319 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
320 .swap = false,
321 .sf = scaling_factors_888,
322 }, {
323 .drm_fmt = DRM_FORMAT_BGRA8888,
324 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
325 .swap = true,
326 .sf = scaling_factors_888,
327 }, {
328 .drm_fmt = DRM_FORMAT_BGR888,
329 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888,
330 .swap = false,
331 .sf = scaling_factors_888,
332 }, {
333 .drm_fmt = DRM_FORMAT_RGB888,
334 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888,
335 .swap = false,
336 .sf = scaling_factors_888,
337 }, {
338 .drm_fmt = DRM_FORMAT_RGBA5551,
339 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
340 .swap = false,
341 .sf = scaling_factors_555,
342 }, {
343 .drm_fmt = DRM_FORMAT_BGRA5551,
344 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
345 .swap = true,
346 .sf = scaling_factors_555,
347 }, {
348 .drm_fmt = DRM_FORMAT_RGBA4444,
349 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
350 .swap = false,
351 .sf = scaling_factors_444,
352 }, {
353 .drm_fmt = DRM_FORMAT_BGRA4444,
354 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
355 .swap = true,
356 .sf = scaling_factors_444,
357 }, {
358 .drm_fmt = DRM_FORMAT_RGB565,
359 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
360 .swap = false,
361 .sf = scaling_factors_565,
362 }, {
363 .drm_fmt = DRM_FORMAT_BGR565,
364 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
365 .swap = true,
366 .sf = scaling_factors_565,
367 },
368};
369
370/* List of live video layer formats */
371static const struct zynqmp_disp_format avbuf_live_fmts[] = {
372 {
373 .drm_fmt = DRM_FORMAT_RGB565,
374 .bus_fmt = MEDIA_BUS_FMT_RGB666_1X18,
375 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 |
376 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB,
377 .sf = scaling_factors_666,
378 }, {
379 .drm_fmt = DRM_FORMAT_RGB888,
380 .bus_fmt = MEDIA_BUS_FMT_RGB888_1X24,
381 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 |
382 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB,
383 .sf = scaling_factors_888,
384 }, {
385 .drm_fmt = DRM_FORMAT_YUV422,
386 .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16,
387 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 |
388 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422,
389 .sf = scaling_factors_888,
390 }, {
391 .drm_fmt = DRM_FORMAT_YUV444,
392 .bus_fmt = MEDIA_BUS_FMT_VUY8_1X24,
393 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 |
394 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444,
395 .sf = scaling_factors_888,
396 }, {
397 .drm_fmt = DRM_FORMAT_P210,
398 .bus_fmt = MEDIA_BUS_FMT_UYVY10_1X20,
399 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 |
400 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422,
401 .sf = scaling_factors_101010,
402 },
403};
404
405static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg)
406{
407 return readl(disp->avbuf + reg);
408}
409
410static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val)
411{
412 writel(val, disp->avbuf + reg);
413}
414
415static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer)
416{
417 return layer->id == ZYNQMP_DPSUB_LAYER_VID;
418}
419
420/**
421 * zynqmp_disp_avbuf_set_format - Set the input format for a layer
422 * @disp: Display controller
423 * @layer: The layer
424 * @fmt: The format information
425 *
426 * Set the video buffer manager format for @layer to @fmt.
427 */
428static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp,
429 struct zynqmp_disp_layer *layer,
430 const struct zynqmp_disp_format *fmt)
431{
432 unsigned int i;
433 u32 val, reg;
434
435 layer->disp_fmt = fmt;
436 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) {
437 reg = ZYNQMP_DISP_AV_BUF_FMT;
438 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT);
439 val &= zynqmp_disp_layer_is_video(layer)
440 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK
441 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK;
442 val |= fmt->buf_fmt;
443 zynqmp_disp_avbuf_write(disp, reg, val);
444 } else {
445 reg = zynqmp_disp_layer_is_video(layer)
446 ? ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG
447 : ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG;
448 val = fmt->buf_fmt;
449 zynqmp_disp_avbuf_write(disp, reg, val);
450 }
451
452 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) {
453 reg = zynqmp_disp_layer_is_video(layer)
454 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i)
455 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i);
456
457 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]);
458 }
459}
460
461/**
462 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources
463 * @disp: Display controller
464 * @video_from_ps: True if the video clock originates from the PS
465 * @audio_from_ps: True if the audio clock originates from the PS
466 * @timings_internal: True if video timings are generated internally
467 *
468 * Set the source for the video and audio clocks, as well as for the video
469 * timings. Clocks can originate from the PS or PL, and timings can be
470 * generated internally or externally.
471 */
472static void
473zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp,
474 bool video_from_ps, bool audio_from_ps,
475 bool timings_internal)
476{
477 u32 val = 0;
478
479 if (video_from_ps)
480 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
481 if (audio_from_ps)
482 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
483 if (timings_internal)
484 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
485
486 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val);
487}
488
489/**
490 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels
491 * @disp: Display controller
492 *
493 * Enable all (video and audio) buffer channels.
494 */
495static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp)
496{
497 unsigned int i;
498 u32 val;
499
500 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
501 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX <<
502 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
503
504 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++)
505 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
506 val);
507
508 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
509 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX <<
510 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
511
512 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
513 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
514 val);
515}
516
517/**
518 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels
519 * @disp: Display controller
520 *
521 * Disable all (video and audio) buffer channels.
522 */
523static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)
524{
525 unsigned int i;
526
527 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
528 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
529 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH);
530}
531
532/**
533 * zynqmp_disp_avbuf_enable_audio - Enable audio
534 * @disp: Display controller
535 *
536 * Enable all audio buffers with a non-live (memory) source.
537 */
538static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)
539{
540 u32 val;
541
542 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
543 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
544 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM;
545 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
546 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
547}
548
549/**
550 * zynqmp_disp_avbuf_disable_audio - Disable audio
551 * @disp: Display controller
552 *
553 * Disable all audio buffers.
554 */
555static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)
556{
557 u32 val;
558
559 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
560 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
561 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE;
562 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
563 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
564}
565
566/**
567 * zynqmp_disp_avbuf_enable_video - Enable a video layer
568 * @disp: Display controller
569 * @layer: The layer
570 *
571 * Enable the video/graphics buffer for @layer.
572 */
573static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp,
574 struct zynqmp_disp_layer *layer)
575{
576 u32 val;
577
578 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
579 if (zynqmp_disp_layer_is_video(layer)) {
580 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
581 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE)
582 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM;
583 else
584 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE;
585 } else {
586 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
587 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
588 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE)
589 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
590 else
591 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE;
592 }
593 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
594}
595
596/**
597 * zynqmp_disp_avbuf_disable_video - Disable a video layer
598 * @disp: Display controller
599 * @layer: The layer
600 *
601 * Disable the video/graphics buffer for @layer.
602 */
603static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp,
604 struct zynqmp_disp_layer *layer)
605{
606 u32 val;
607
608 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
609 if (zynqmp_disp_layer_is_video(layer)) {
610 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
611 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE;
612 } else {
613 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
614 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE;
615 }
616 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
617}
618
619/**
620 * zynqmp_disp_avbuf_enable - Enable the video pipe
621 * @disp: Display controller
622 *
623 * De-assert the video pipe reset.
624 */
625static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)
626{
627 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
628}
629
630/**
631 * zynqmp_disp_avbuf_disable - Disable the video pipe
632 * @disp: Display controller
633 *
634 * Assert the video pipe reset.
635 */
636static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)
637{
638 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG,
639 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST);
640}
641
642/* -----------------------------------------------------------------------------
643 * Blender (Video Pipeline)
644 */
645
646static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val)
647{
648 writel(val, disp->blend + reg);
649}
650
651/*
652 * Colorspace conversion matrices.
653 *
654 * Hardcode RGB <-> YUV conversion to full-range SDTV for now.
655 */
656static const u16 csc_zero_matrix[] = {
657 0x0, 0x0, 0x0,
658 0x0, 0x0, 0x0,
659 0x0, 0x0, 0x0
660};
661
662static const u16 csc_identity_matrix[] = {
663 0x1000, 0x0, 0x0,
664 0x0, 0x1000, 0x0,
665 0x0, 0x0, 0x1000
666};
667
668static const u32 csc_zero_offsets[] = {
669 0, 0, 0
670};
671
672static const u16 csc_rgb_to_sdtv_matrix[] = {
673 0x4c9, 0x864, 0x1d3,
674 0x7d4d, 0x7ab3, 0x800,
675 0x800, 0x794d, 0x7eb3
676};
677
678static const u32 csc_rgb_to_sdtv_offsets[] = {
679 0x0, 0x8000000, 0x8000000
680};
681
682static const u16 csc_sdtv_to_rgb_matrix[] = {
683 0x1000, 0x166f, 0x0,
684 0x1000, 0x7483, 0x7a7f,
685 0x1000, 0x0, 0x1c5a
686};
687
688static const u32 csc_sdtv_to_rgb_offsets[] = {
689 0x0, 0x1800, 0x1800
690};
691
692/**
693 * zynqmp_disp_blend_set_output_format - Set the output format of the blender
694 * @disp: Display controller
695 * @format: Output format
696 *
697 * Set the output format of the blender to @format.
698 */
699static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp,
700 enum zynqmp_dpsub_format format)
701{
702 static const unsigned int blend_output_fmts[] = {
703 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB,
704 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444,
705 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422
706 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE,
707 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY,
708 };
709
710 u32 fmt = blend_output_fmts[format];
711 const u16 *coeffs;
712 const u32 *offsets;
713 unsigned int i;
714
715 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
716 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) {
717 coeffs = csc_identity_matrix;
718 offsets = csc_zero_offsets;
719 } else {
720 coeffs = csc_rgb_to_sdtv_matrix;
721 offsets = csc_rgb_to_sdtv_offsets;
722 }
723
724 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
725 zynqmp_disp_blend_write(disp,
726 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i),
727 coeffs[i]);
728
729 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
730 zynqmp_disp_blend_write(disp,
731 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i),
732 offsets[i]);
733}
734
735/**
736 * zynqmp_disp_blend_set_bg_color - Set the background color
737 * @disp: Display controller
738 * @rcr: Red/Cr color component
739 * @gy: Green/Y color component
740 * @bcb: Blue/Cb color component
741 *
742 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and
743 * B or Cr, Y and Cb components respectively depending on the selected output
744 * format.
745 */
746static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp,
747 u32 rcr, u32 gy, u32 bcb)
748{
749 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr);
750 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy);
751 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb);
752}
753
754/**
755 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending
756 * @disp: Display controller
757 * @enable: True to enable global alpha blending
758 * @alpha: Global alpha value (ignored if @enabled is false)
759 */
760void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
761 bool enable, u32 alpha)
762{
763 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
764 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) |
765 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0));
766}
767
768/**
769 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer
770 * @disp: Display controller
771 * @layer: The layer
772 * @coeffs: Colorspace conversion matrix
773 * @offsets: Colorspace conversion offsets
774 *
775 * Configure the input colorspace conversion matrix and offsets for the @layer.
776 * Columns of the matrix are automatically swapped based on the input format to
777 * handle RGB and YCrCb components permutations.
778 */
779static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp,
780 struct zynqmp_disp_layer *layer,
781 const u16 *coeffs,
782 const u32 *offsets)
783{
784 unsigned int swap[3] = { 0, 1, 2 };
785 unsigned int reg;
786 unsigned int i;
787
788 if (layer->disp_fmt->swap) {
789 if (layer->drm_fmt->is_yuv) {
790 /* Swap U and V. */
791 swap[1] = 2;
792 swap[2] = 1;
793 } else {
794 /* Swap R and B. */
795 swap[0] = 2;
796 swap[2] = 0;
797 }
798 }
799
800 if (zynqmp_disp_layer_is_video(layer))
801 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0);
802 else
803 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0);
804
805 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) {
806 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]);
807 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]);
808 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]);
809 }
810
811 if (zynqmp_disp_layer_is_video(layer))
812 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0);
813 else
814 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0);
815
816 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
817 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]);
818}
819
820/**
821 * zynqmp_disp_blend_layer_enable - Enable a layer
822 * @disp: Display controller
823 * @layer: The layer
824 */
825static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
826 struct zynqmp_disp_layer *layer)
827{
828 const u16 *coeffs;
829 const u32 *offsets;
830 u32 val;
831
832 val = (layer->drm_fmt->is_yuv ?
833 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) |
834 (layer->drm_fmt->hsub > 1 ?
835 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0);
836
837 zynqmp_disp_blend_write(disp,
838 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
839 val);
840
841 if (layer->drm_fmt->is_yuv) {
842 coeffs = csc_sdtv_to_rgb_matrix;
843 offsets = csc_sdtv_to_rgb_offsets;
844 } else {
845 coeffs = csc_identity_matrix;
846 offsets = csc_zero_offsets;
847 }
848
849 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets);
850}
851
852/**
853 * zynqmp_disp_blend_layer_disable - Disable a layer
854 * @disp: Display controller
855 * @layer: The layer
856 */
857static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp,
858 struct zynqmp_disp_layer *layer)
859{
860 zynqmp_disp_blend_write(disp,
861 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
862 0);
863
864 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix,
865 csc_zero_offsets);
866}
867
868/* -----------------------------------------------------------------------------
869 * Audio Mixer
870 */
871
872static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val)
873{
874 writel(val, disp->audio + reg);
875}
876
877/**
878 * zynqmp_disp_audio_enable - Enable the audio mixer
879 * @disp: Display controller
880 *
881 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to
882 * default values by the reset, set the default mixer volume explicitly.
883 */
884static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp)
885{
886 /* Clear the audio soft reset register as it's an non-reset flop. */
887 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
888 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME,
889 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE);
890}
891
892/**
893 * zynqmp_disp_audio_disable - Disable the audio mixer
894 * @disp: Display controller
895 *
896 * Disable the audio mixer by asserting its soft reset.
897 */
898static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp)
899{
900 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET,
901 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST);
902}
903
904/* -----------------------------------------------------------------------------
905 * ZynqMP Display Layer & DRM Plane
906 */
907
908/**
909 * zynqmp_disp_layer_find_format - Find format information for a DRM format
910 * @layer: The layer
911 * @drm_fmt: DRM format to search
912 *
913 * Search display subsystem format information corresponding to the given DRM
914 * format @drm_fmt for the @layer, and return a pointer to the format
915 * descriptor.
916 *
917 * Return: A pointer to the format descriptor if found, NULL otherwise
918 */
919static const struct zynqmp_disp_format *
920zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer,
921 u32 drm_fmt)
922{
923 unsigned int i;
924
925 for (i = 0; i < layer->info->num_formats; i++) {
926 if (layer->info->formats[i].drm_fmt == drm_fmt)
927 return &layer->info->formats[i];
928 }
929
930 return NULL;
931}
932
933/**
934 * zynqmp_disp_layer_find_live_format - Find format information for given
935 * media bus format
936 * @layer: The layer
937 * @media_bus_format: Media bus format to search
938 *
939 * Search display subsystem format information corresponding to the given media
940 * bus format @media_bus_format for the @layer, and return a pointer to the
941 * format descriptor.
942 *
943 * Return: A pointer to the format descriptor if found, NULL otherwise
944 */
945static const struct zynqmp_disp_format *
946zynqmp_disp_layer_find_live_format(struct zynqmp_disp_layer *layer,
947 u32 media_bus_format)
948{
949 unsigned int i;
950
951 for (i = 0; i < layer->info->num_formats; i++)
952 if (layer->info->formats[i].bus_fmt == media_bus_format)
953 return &layer->info->formats[i];
954
955 return NULL;
956}
957
958/**
959 * zynqmp_disp_layer_drm_formats - Return the DRM formats supported by the layer
960 * @layer: The layer
961 * @num_formats: Pointer to the returned number of formats
962 *
963 * NOTE: This function doesn't make sense for live video layers and will
964 * always return an empty list in such cases. zynqmp_disp_live_layer_formats()
965 * should be used to query a list of media bus formats supported by the live
966 * video input layer.
967 *
968 * Return: A newly allocated u32 array that stores all the DRM formats
969 * supported by the layer. The number of formats in the array is returned
970 * through the num_formats argument.
971 */
972u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
973 unsigned int *num_formats)
974{
975 unsigned int i;
976 u32 *formats;
977
978 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_NONLIVE)) {
979 *num_formats = 0;
980 return NULL;
981 }
982
983 formats = kcalloc(layer->info->num_formats, sizeof(*formats),
984 GFP_KERNEL);
985 if (!formats) {
986 *num_formats = 0;
987 return NULL;
988 }
989
990 for (i = 0; i < layer->info->num_formats; ++i)
991 formats[i] = layer->info->formats[i].drm_fmt;
992
993 *num_formats = layer->info->num_formats;
994 return formats;
995}
996
997/**
998 * zynqmp_disp_live_layer_formats - Return the media bus formats supported by
999 * the live video layer
1000 * @layer: The layer
1001 * @num_formats: Pointer to the returned number of formats
1002 *
1003 * NOTE: This function should be used only for live video input layers.
1004 *
1005 * Return: A newly allocated u32 array of media bus formats supported by the
1006 * layer. The number of formats in the array is returned through the
1007 * @num_formats argument.
1008 */
1009u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,
1010 unsigned int *num_formats)
1011{
1012 unsigned int i;
1013 u32 *formats;
1014
1015 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_LIVE)) {
1016 *num_formats = 0;
1017 return NULL;
1018 }
1019
1020 formats = kcalloc(layer->info->num_formats, sizeof(*formats),
1021 GFP_KERNEL);
1022 if (!formats) {
1023 *num_formats = 0;
1024 return NULL;
1025 }
1026
1027 for (i = 0; i < layer->info->num_formats; ++i)
1028 formats[i] = layer->info->formats[i].bus_fmt;
1029
1030 *num_formats = layer->info->num_formats;
1031 return formats;
1032}
1033
1034/**
1035 * zynqmp_disp_layer_enable - Enable a layer
1036 * @layer: The layer
1037 *
1038 * Enable the @layer in the audio/video buffer manager and the blender. DMA
1039 * channels are started separately by zynqmp_disp_layer_update().
1040 */
1041void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer)
1042{
1043 zynqmp_disp_avbuf_enable_video(layer->disp, layer);
1044 zynqmp_disp_blend_layer_enable(layer->disp, layer);
1045}
1046
1047/**
1048 * zynqmp_disp_layer_disable - Disable the layer
1049 * @layer: The layer
1050 *
1051 * Disable the layer by stopping its DMA channels and disabling it in the
1052 * audio/video buffer manager and the blender.
1053 */
1054void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)
1055{
1056 unsigned int i;
1057
1058 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) {
1059 for (i = 0; i < layer->drm_fmt->num_planes; i++)
1060 dmaengine_terminate_sync(layer->dmas[i].chan);
1061 }
1062
1063 zynqmp_disp_avbuf_disable_video(layer->disp, layer);
1064 zynqmp_disp_blend_layer_disable(layer->disp, layer);
1065}
1066
1067/**
1068 * zynqmp_disp_layer_set_format - Set the layer format
1069 * @layer: The layer
1070 * @info: The format info
1071 *
1072 * NOTE: Use zynqmp_disp_layer_set_live_format() to set media bus format for
1073 * live video layers.
1074 *
1075 * Set the format for @layer to @info. The layer must be disabled.
1076 */
1077void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
1078 const struct drm_format_info *info)
1079{
1080 unsigned int i;
1081
1082 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_NONLIVE))
1083 return;
1084
1085 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format);
1086 if (WARN_ON(!layer->disp_fmt))
1087 return;
1088 layer->drm_fmt = info;
1089
1090 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
1091
1092 /*
1093 * Set pconfig for each DMA channel to indicate they're part of a
1094 * video group.
1095 */
1096 for (i = 0; i < info->num_planes; i++) {
1097 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1098 struct xilinx_dpdma_peripheral_config pconfig = {
1099 .video_group = true,
1100 };
1101 struct dma_slave_config config = {
1102 .direction = DMA_MEM_TO_DEV,
1103 .peripheral_config = &pconfig,
1104 .peripheral_size = sizeof(pconfig),
1105 };
1106
1107 dmaengine_slave_config(dma->chan, &config);
1108 }
1109}
1110
1111/**
1112 * zynqmp_disp_layer_set_live_format - Set the live video layer format
1113 * @layer: The layer
1114 * @media_bus_format: Media bus format to set
1115 *
1116 * NOTE: This function should not be used to set format for non-live video
1117 * layer. Use zynqmp_disp_layer_set_format() instead.
1118 *
1119 * Set the display format for the live @layer. The layer must be disabled.
1120 */
1121void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,
1122 u32 media_bus_format)
1123{
1124 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_LIVE))
1125 return;
1126
1127 layer->disp_fmt = zynqmp_disp_layer_find_live_format(layer,
1128 media_bus_format);
1129 if (WARN_ON(!layer->disp_fmt))
1130 return;
1131
1132 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
1133
1134 layer->drm_fmt = drm_format_info(layer->disp_fmt->drm_fmt);
1135}
1136
1137/**
1138 * zynqmp_disp_layer_update - Update the layer framebuffer
1139 * @layer: The layer
1140 * @state: The plane state
1141 *
1142 * Update the framebuffer for the layer by issuing a new DMA engine transaction
1143 * for the new framebuffer.
1144 *
1145 * Return: 0 on success, or the DMA descriptor failure error otherwise
1146 */
1147int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
1148 struct drm_plane_state *state)
1149{
1150 const struct drm_format_info *info = layer->drm_fmt;
1151 unsigned int i;
1152
1153 if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE)
1154 return 0;
1155
1156 for (i = 0; i < info->num_planes; i++) {
1157 unsigned int width = state->crtc_w / (i ? info->hsub : 1);
1158 unsigned int height = state->crtc_h / (i ? info->vsub : 1);
1159 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1160 struct dma_async_tx_descriptor *desc;
1161 dma_addr_t dma_addr;
1162
1163 dma_addr = drm_fb_dma_get_gem_addr(state->fb, state, i);
1164
1165 dma->xt.numf = height;
1166 dma->sgl.size = width * info->cpp[i];
1167 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
1168 dma->xt.src_start = dma_addr;
1169 dma->xt.frame_size = 1;
1170 dma->xt.dir = DMA_MEM_TO_DEV;
1171 dma->xt.src_sgl = true;
1172 dma->xt.dst_sgl = false;
1173
1174 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt,
1175 DMA_CTRL_ACK |
1176 DMA_PREP_REPEAT |
1177 DMA_PREP_LOAD_EOT);
1178 if (!desc) {
1179 dev_err(layer->disp->dev,
1180 "failed to prepare DMA descriptor\n");
1181 return -ENOMEM;
1182 }
1183
1184 dmaengine_submit(desc);
1185 dma_async_issue_pending(dma->chan);
1186 }
1187
1188 return 0;
1189}
1190
1191/**
1192 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer
1193 * @disp: Display controller
1194 * @layer: The layer
1195 *
1196 * Release the DMA channels associated with @layer.
1197 */
1198static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
1199 struct zynqmp_disp_layer *layer)
1200{
1201 unsigned int i;
1202
1203 if (!layer->info)
1204 return;
1205
1206 for (i = 0; i < layer->info->num_channels; i++) {
1207 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1208
1209 if (!dma->chan)
1210 continue;
1211
1212 /* Make sure the channel is terminated before release. */
1213 dmaengine_terminate_sync(dma->chan);
1214 dma_release_channel(dma->chan);
1215 }
1216}
1217
1218/**
1219 * zynqmp_disp_destroy_layers - Destroy all layers
1220 * @disp: Display controller
1221 */
1222static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)
1223{
1224 unsigned int i;
1225
1226 for (i = 0; i < ARRAY_SIZE(disp->layers); i++)
1227 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1228}
1229
1230/**
1231 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer
1232 * @disp: Display controller
1233 * @layer: The layer
1234 *
1235 * Request all DMA engine channels needed by @layer.
1236 *
1237 * Return: 0 on success, or the DMA channel request error otherwise
1238 */
1239static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
1240 struct zynqmp_disp_layer *layer)
1241{
1242 static const char * const dma_names[] = { "vid", "gfx" };
1243 unsigned int i;
1244 int ret;
1245
1246 for (i = 0; i < layer->info->num_channels; i++) {
1247 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1248 char dma_channel_name[16];
1249
1250 snprintf(dma_channel_name, sizeof(dma_channel_name),
1251 "%s%u", dma_names[layer->id], i);
1252 dma->chan = dma_request_chan(disp->dev, dma_channel_name);
1253 if (IS_ERR(dma->chan)) {
1254 ret = dev_err_probe(disp->dev, PTR_ERR(dma->chan),
1255 "failed to request dma channel\n");
1256 dma->chan = NULL;
1257 return ret;
1258 }
1259 }
1260
1261 return 0;
1262}
1263
1264/**
1265 * zynqmp_disp_create_layers - Create and initialize all layers
1266 * @disp: Display controller
1267 *
1268 * Return: 0 on success, or the DMA channel request error otherwise
1269 */
1270static int zynqmp_disp_create_layers(struct zynqmp_disp *disp)
1271{
1272 static const struct zynqmp_disp_layer_info layer_info[] = {
1273 [ZYNQMP_DPSUB_LAYER_VID] = {
1274 .formats = avbuf_vid_fmts,
1275 .num_formats = ARRAY_SIZE(avbuf_vid_fmts),
1276 .num_channels = 3,
1277 },
1278 [ZYNQMP_DPSUB_LAYER_GFX] = {
1279 .formats = avbuf_gfx_fmts,
1280 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts),
1281 .num_channels = 1,
1282 },
1283 };
1284 static const struct zynqmp_disp_layer_info live_layer_info = {
1285 .formats = avbuf_live_fmts,
1286 .num_formats = ARRAY_SIZE(avbuf_live_fmts),
1287 .num_channels = 0,
1288 };
1289
1290 unsigned int i;
1291 int ret;
1292
1293 for (i = 0; i < ARRAY_SIZE(disp->layers); i++) {
1294 struct zynqmp_disp_layer *layer = &disp->layers[i];
1295
1296 layer->id = i;
1297 layer->disp = disp;
1298 /*
1299 * For now assume dpsub works in either live or non-live mode for both layers.
1300 * Hybrid mode is not supported yet.
1301 */
1302 if (disp->dpsub->dma_enabled) {
1303 layer->mode = ZYNQMP_DPSUB_LAYER_NONLIVE;
1304 layer->info = &layer_info[i];
1305 } else {
1306 layer->mode = ZYNQMP_DPSUB_LAYER_LIVE;
1307 layer->info = &live_layer_info;
1308 }
1309
1310 ret = zynqmp_disp_layer_request_dma(disp, layer);
1311 if (ret)
1312 goto err;
1313
1314 disp->dpsub->layers[i] = layer;
1315 }
1316
1317 return 0;
1318
1319err:
1320 zynqmp_disp_destroy_layers(disp);
1321 return ret;
1322}
1323
1324/* -----------------------------------------------------------------------------
1325 * ZynqMP Display
1326 */
1327
1328/**
1329 * zynqmp_disp_enable - Enable the display controller
1330 * @disp: Display controller
1331 */
1332void zynqmp_disp_enable(struct zynqmp_disp *disp)
1333{
1334 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB);
1335 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0);
1336
1337 zynqmp_disp_avbuf_enable(disp);
1338 /* Choose clock source based on the DT clock handle. */
1339 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->dpsub->vid_clk_from_ps,
1340 disp->dpsub->aud_clk_from_ps,
1341 disp->dpsub->vid_clk_from_ps);
1342 zynqmp_disp_avbuf_enable_channels(disp);
1343 zynqmp_disp_avbuf_enable_audio(disp);
1344
1345 zynqmp_disp_audio_enable(disp);
1346}
1347
1348/**
1349 * zynqmp_disp_disable - Disable the display controller
1350 * @disp: Display controller
1351 */
1352void zynqmp_disp_disable(struct zynqmp_disp *disp)
1353{
1354 zynqmp_disp_audio_disable(disp);
1355
1356 zynqmp_disp_avbuf_disable_audio(disp);
1357 zynqmp_disp_avbuf_disable_channels(disp);
1358 zynqmp_disp_avbuf_disable(disp);
1359}
1360
1361/**
1362 * zynqmp_disp_setup_clock - Configure the display controller pixel clock rate
1363 * @disp: Display controller
1364 * @mode_clock: The pixel clock rate, in Hz
1365 *
1366 * Return: 0 on success, or a negative error clock otherwise
1367 */
1368int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,
1369 unsigned long mode_clock)
1370{
1371 unsigned long rate;
1372 long diff;
1373 int ret;
1374
1375 ret = clk_set_rate(disp->dpsub->vid_clk, mode_clock);
1376 if (ret) {
1377 dev_err(disp->dev, "failed to set the video clock\n");
1378 return ret;
1379 }
1380
1381 rate = clk_get_rate(disp->dpsub->vid_clk);
1382 diff = rate - mode_clock;
1383 if (abs(diff) > mode_clock / 20)
1384 dev_info(disp->dev,
1385 "requested pixel rate: %lu actual rate: %lu\n",
1386 mode_clock, rate);
1387 else
1388 dev_dbg(disp->dev,
1389 "requested pixel rate: %lu actual rate: %lu\n",
1390 mode_clock, rate);
1391
1392 return 0;
1393}
1394
1395/* -----------------------------------------------------------------------------
1396 * Initialization & Cleanup
1397 */
1398
1399int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub)
1400{
1401 struct platform_device *pdev = to_platform_device(dpsub->dev);
1402 struct zynqmp_disp *disp;
1403 int ret;
1404
1405 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1406 if (!disp)
1407 return -ENOMEM;
1408
1409 disp->dev = &pdev->dev;
1410 disp->dpsub = dpsub;
1411
1412 disp->blend = devm_platform_ioremap_resource_byname(pdev, "blend");
1413 if (IS_ERR(disp->blend)) {
1414 ret = PTR_ERR(disp->blend);
1415 goto error;
1416 }
1417
1418 disp->avbuf = devm_platform_ioremap_resource_byname(pdev, "av_buf");
1419 if (IS_ERR(disp->avbuf)) {
1420 ret = PTR_ERR(disp->avbuf);
1421 goto error;
1422 }
1423
1424 disp->audio = devm_platform_ioremap_resource_byname(pdev, "aud");
1425 if (IS_ERR(disp->audio)) {
1426 ret = PTR_ERR(disp->audio);
1427 goto error;
1428 }
1429
1430 ret = zynqmp_disp_create_layers(disp);
1431 if (ret)
1432 goto error;
1433
1434 if (disp->dpsub->dma_enabled) {
1435 struct zynqmp_disp_layer *layer;
1436
1437 layer = &disp->layers[ZYNQMP_DPSUB_LAYER_VID];
1438 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align;
1439 }
1440
1441 dpsub->disp = disp;
1442
1443 return 0;
1444
1445error:
1446 kfree(disp);
1447 return ret;
1448}
1449
1450void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub)
1451{
1452 struct zynqmp_disp *disp = dpsub->disp;
1453
1454 zynqmp_disp_destroy_layers(disp);
1455}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ZynqMP Display Controller Driver
4 *
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
6 *
7 * Authors:
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12#include <drm/drm_fb_dma_helper.h>
13#include <drm/drm_fourcc.h>
14#include <drm/drm_framebuffer.h>
15#include <drm/drm_plane.h>
16
17#include <linux/clk.h>
18#include <linux/dma/xilinx_dpdma.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25
26#include "zynqmp_disp.h"
27#include "zynqmp_disp_regs.h"
28#include "zynqmp_dp.h"
29#include "zynqmp_dpsub.h"
30
31/*
32 * Overview
33 * --------
34 *
35 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
36 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer.
37 *
38 * +------------------------------------------------------------+
39 * +--------+ | +----------------+ +-----------+ |
40 * | DPDMA | --->| | --> | Video | Video +-------------+ |
41 * | 4x vid | | | | | Rendering | -+--> | | | +------+
42 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
43 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
44 * | | and STC | +-----------+ | | Controller | | +------+
45 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
46 * | | | | Mixer | --+-> | | | +------+
47 * Live Audio --->| | --> | | || +-------------+ |
48 * | +----------------+ +-----------+ || |
49 * +---------------------------------------||-------------------+
50 * vv
51 * Blended Video and
52 * Mixed Audio to PL
53 *
54 * Only non-live input from the DPDMA and output to the DisplayPort Source
55 * Controller are currently supported. Interface with the programmable logic
56 * for live streams is not implemented.
57 *
58 * The display controller code creates planes for the DPDMA video and graphics
59 * layers, and a CRTC for the Video Rendering Pipeline.
60 */
61
62#define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4
63#define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6
64
65#define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3
66
67/**
68 * struct zynqmp_disp_format - Display subsystem format information
69 * @drm_fmt: DRM format (4CC)
70 * @buf_fmt: AV buffer format
71 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats
72 * @sf: Scaling factors for color components
73 */
74struct zynqmp_disp_format {
75 u32 drm_fmt;
76 u32 buf_fmt;
77 bool swap;
78 const u32 *sf;
79};
80
81/**
82 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer
83 * @chan: DMA channel
84 * @xt: Interleaved DMA descriptor template
85 * @sgl: Data chunk for dma_interleaved_template
86 */
87struct zynqmp_disp_layer_dma {
88 struct dma_chan *chan;
89 struct dma_interleaved_template xt;
90 struct data_chunk sgl;
91};
92
93/**
94 * struct zynqmp_disp_layer_info - Static layer information
95 * @formats: Array of supported formats
96 * @num_formats: Number of formats in @formats array
97 * @num_channels: Number of DMA channels
98 */
99struct zynqmp_disp_layer_info {
100 const struct zynqmp_disp_format *formats;
101 unsigned int num_formats;
102 unsigned int num_channels;
103};
104
105/**
106 * struct zynqmp_disp_layer - Display layer
107 * @id: Layer ID
108 * @disp: Back pointer to struct zynqmp_disp
109 * @info: Static layer information
110 * @dmas: DMA channels
111 * @disp_fmt: Current format information
112 * @drm_fmt: Current DRM format information
113 * @mode: Current operation mode
114 */
115struct zynqmp_disp_layer {
116 enum zynqmp_dpsub_layer_id id;
117 struct zynqmp_disp *disp;
118 const struct zynqmp_disp_layer_info *info;
119
120 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES];
121
122 const struct zynqmp_disp_format *disp_fmt;
123 const struct drm_format_info *drm_fmt;
124 enum zynqmp_dpsub_layer_mode mode;
125};
126
127/**
128 * struct zynqmp_disp - Display controller
129 * @dev: Device structure
130 * @dpsub: Display subsystem
131 * @blend.base: Register I/O base address for the blender
132 * @avbuf.base: Register I/O base address for the audio/video buffer manager
133 * @audio.base: Registers I/O base address for the audio mixer
134 * @layers: Layers (planes)
135 */
136struct zynqmp_disp {
137 struct device *dev;
138 struct zynqmp_dpsub *dpsub;
139
140 struct {
141 void __iomem *base;
142 } blend;
143 struct {
144 void __iomem *base;
145 } avbuf;
146 struct {
147 void __iomem *base;
148 } audio;
149
150 struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS];
151};
152
153/* -----------------------------------------------------------------------------
154 * Audio/Video Buffer Manager
155 */
156
157static const u32 scaling_factors_444[] = {
158 ZYNQMP_DISP_AV_BUF_4BIT_SF,
159 ZYNQMP_DISP_AV_BUF_4BIT_SF,
160 ZYNQMP_DISP_AV_BUF_4BIT_SF,
161};
162
163static const u32 scaling_factors_555[] = {
164 ZYNQMP_DISP_AV_BUF_5BIT_SF,
165 ZYNQMP_DISP_AV_BUF_5BIT_SF,
166 ZYNQMP_DISP_AV_BUF_5BIT_SF,
167};
168
169static const u32 scaling_factors_565[] = {
170 ZYNQMP_DISP_AV_BUF_5BIT_SF,
171 ZYNQMP_DISP_AV_BUF_6BIT_SF,
172 ZYNQMP_DISP_AV_BUF_5BIT_SF,
173};
174
175static const u32 scaling_factors_888[] = {
176 ZYNQMP_DISP_AV_BUF_8BIT_SF,
177 ZYNQMP_DISP_AV_BUF_8BIT_SF,
178 ZYNQMP_DISP_AV_BUF_8BIT_SF,
179};
180
181static const u32 scaling_factors_101010[] = {
182 ZYNQMP_DISP_AV_BUF_10BIT_SF,
183 ZYNQMP_DISP_AV_BUF_10BIT_SF,
184 ZYNQMP_DISP_AV_BUF_10BIT_SF,
185};
186
187/* List of video layer formats */
188static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
189 {
190 .drm_fmt = DRM_FORMAT_VYUY,
191 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
192 .swap = true,
193 .sf = scaling_factors_888,
194 }, {
195 .drm_fmt = DRM_FORMAT_UYVY,
196 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
197 .swap = false,
198 .sf = scaling_factors_888,
199 }, {
200 .drm_fmt = DRM_FORMAT_YUYV,
201 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
202 .swap = false,
203 .sf = scaling_factors_888,
204 }, {
205 .drm_fmt = DRM_FORMAT_YVYU,
206 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
207 .swap = true,
208 .sf = scaling_factors_888,
209 }, {
210 .drm_fmt = DRM_FORMAT_YUV422,
211 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
212 .swap = false,
213 .sf = scaling_factors_888,
214 }, {
215 .drm_fmt = DRM_FORMAT_YVU422,
216 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
217 .swap = true,
218 .sf = scaling_factors_888,
219 }, {
220 .drm_fmt = DRM_FORMAT_YUV444,
221 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
222 .swap = false,
223 .sf = scaling_factors_888,
224 }, {
225 .drm_fmt = DRM_FORMAT_YVU444,
226 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
227 .swap = true,
228 .sf = scaling_factors_888,
229 }, {
230 .drm_fmt = DRM_FORMAT_NV16,
231 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
232 .swap = false,
233 .sf = scaling_factors_888,
234 }, {
235 .drm_fmt = DRM_FORMAT_NV61,
236 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
237 .swap = true,
238 .sf = scaling_factors_888,
239 }, {
240 .drm_fmt = DRM_FORMAT_BGR888,
241 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
242 .swap = false,
243 .sf = scaling_factors_888,
244 }, {
245 .drm_fmt = DRM_FORMAT_RGB888,
246 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
247 .swap = true,
248 .sf = scaling_factors_888,
249 }, {
250 .drm_fmt = DRM_FORMAT_XBGR8888,
251 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
252 .swap = false,
253 .sf = scaling_factors_888,
254 }, {
255 .drm_fmt = DRM_FORMAT_XRGB8888,
256 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
257 .swap = true,
258 .sf = scaling_factors_888,
259 }, {
260 .drm_fmt = DRM_FORMAT_XBGR2101010,
261 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
262 .swap = false,
263 .sf = scaling_factors_101010,
264 }, {
265 .drm_fmt = DRM_FORMAT_XRGB2101010,
266 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
267 .swap = true,
268 .sf = scaling_factors_101010,
269 }, {
270 .drm_fmt = DRM_FORMAT_YUV420,
271 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
272 .swap = false,
273 .sf = scaling_factors_888,
274 }, {
275 .drm_fmt = DRM_FORMAT_YVU420,
276 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
277 .swap = true,
278 .sf = scaling_factors_888,
279 }, {
280 .drm_fmt = DRM_FORMAT_NV12,
281 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
282 .swap = false,
283 .sf = scaling_factors_888,
284 }, {
285 .drm_fmt = DRM_FORMAT_NV21,
286 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
287 .swap = true,
288 .sf = scaling_factors_888,
289 },
290};
291
292/* List of graphics layer formats */
293static const struct zynqmp_disp_format avbuf_gfx_fmts[] = {
294 {
295 .drm_fmt = DRM_FORMAT_ABGR8888,
296 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
297 .swap = false,
298 .sf = scaling_factors_888,
299 }, {
300 .drm_fmt = DRM_FORMAT_ARGB8888,
301 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
302 .swap = true,
303 .sf = scaling_factors_888,
304 }, {
305 .drm_fmt = DRM_FORMAT_RGBA8888,
306 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
307 .swap = false,
308 .sf = scaling_factors_888,
309 }, {
310 .drm_fmt = DRM_FORMAT_BGRA8888,
311 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
312 .swap = true,
313 .sf = scaling_factors_888,
314 }, {
315 .drm_fmt = DRM_FORMAT_BGR888,
316 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888,
317 .swap = false,
318 .sf = scaling_factors_888,
319 }, {
320 .drm_fmt = DRM_FORMAT_RGB888,
321 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888,
322 .swap = false,
323 .sf = scaling_factors_888,
324 }, {
325 .drm_fmt = DRM_FORMAT_RGBA5551,
326 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
327 .swap = false,
328 .sf = scaling_factors_555,
329 }, {
330 .drm_fmt = DRM_FORMAT_BGRA5551,
331 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
332 .swap = true,
333 .sf = scaling_factors_555,
334 }, {
335 .drm_fmt = DRM_FORMAT_RGBA4444,
336 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
337 .swap = false,
338 .sf = scaling_factors_444,
339 }, {
340 .drm_fmt = DRM_FORMAT_BGRA4444,
341 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
342 .swap = true,
343 .sf = scaling_factors_444,
344 }, {
345 .drm_fmt = DRM_FORMAT_RGB565,
346 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
347 .swap = false,
348 .sf = scaling_factors_565,
349 }, {
350 .drm_fmt = DRM_FORMAT_BGR565,
351 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
352 .swap = true,
353 .sf = scaling_factors_565,
354 },
355};
356
357static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg)
358{
359 return readl(disp->avbuf.base + reg);
360}
361
362static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val)
363{
364 writel(val, disp->avbuf.base + reg);
365}
366
367static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer)
368{
369 return layer->id == ZYNQMP_DPSUB_LAYER_VID;
370}
371
372/**
373 * zynqmp_disp_avbuf_set_format - Set the input format for a layer
374 * @disp: Display controller
375 * @layer: The layer
376 * @fmt: The format information
377 *
378 * Set the video buffer manager format for @layer to @fmt.
379 */
380static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp,
381 struct zynqmp_disp_layer *layer,
382 const struct zynqmp_disp_format *fmt)
383{
384 unsigned int i;
385 u32 val;
386
387 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT);
388 val &= zynqmp_disp_layer_is_video(layer)
389 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK
390 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK;
391 val |= fmt->buf_fmt;
392 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val);
393
394 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) {
395 unsigned int reg = zynqmp_disp_layer_is_video(layer)
396 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i)
397 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i);
398
399 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]);
400 }
401}
402
403/**
404 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources
405 * @disp: Display controller
406 * @video_from_ps: True if the video clock originates from the PS
407 * @audio_from_ps: True if the audio clock originates from the PS
408 * @timings_internal: True if video timings are generated internally
409 *
410 * Set the source for the video and audio clocks, as well as for the video
411 * timings. Clocks can originate from the PS or PL, and timings can be
412 * generated internally or externally.
413 */
414static void
415zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp,
416 bool video_from_ps, bool audio_from_ps,
417 bool timings_internal)
418{
419 u32 val = 0;
420
421 if (video_from_ps)
422 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
423 if (audio_from_ps)
424 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
425 if (timings_internal)
426 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
427
428 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val);
429}
430
431/**
432 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels
433 * @disp: Display controller
434 *
435 * Enable all (video and audio) buffer channels.
436 */
437static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp)
438{
439 unsigned int i;
440 u32 val;
441
442 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
443 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX <<
444 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
445
446 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++)
447 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
448 val);
449
450 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
451 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX <<
452 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
453
454 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
455 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
456 val);
457}
458
459/**
460 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels
461 * @disp: Display controller
462 *
463 * Disable all (video and audio) buffer channels.
464 */
465static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)
466{
467 unsigned int i;
468
469 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
470 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
471 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH);
472}
473
474/**
475 * zynqmp_disp_avbuf_enable_audio - Enable audio
476 * @disp: Display controller
477 *
478 * Enable all audio buffers with a non-live (memory) source.
479 */
480static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)
481{
482 u32 val;
483
484 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
485 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
486 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM;
487 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
488 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
489}
490
491/**
492 * zynqmp_disp_avbuf_disable_audio - Disable audio
493 * @disp: Display controller
494 *
495 * Disable all audio buffers.
496 */
497static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)
498{
499 u32 val;
500
501 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
502 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
503 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE;
504 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
505 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
506}
507
508/**
509 * zynqmp_disp_avbuf_enable_video - Enable a video layer
510 * @disp: Display controller
511 * @layer: The layer
512 *
513 * Enable the video/graphics buffer for @layer.
514 */
515static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp,
516 struct zynqmp_disp_layer *layer)
517{
518 u32 val;
519
520 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
521 if (zynqmp_disp_layer_is_video(layer)) {
522 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
523 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE)
524 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM;
525 else
526 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE;
527 } else {
528 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
529 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
530 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE)
531 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
532 else
533 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE;
534 }
535 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
536}
537
538/**
539 * zynqmp_disp_avbuf_disable_video - Disable a video layer
540 * @disp: Display controller
541 * @layer: The layer
542 *
543 * Disable the video/graphics buffer for @layer.
544 */
545static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp,
546 struct zynqmp_disp_layer *layer)
547{
548 u32 val;
549
550 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
551 if (zynqmp_disp_layer_is_video(layer)) {
552 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
553 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE;
554 } else {
555 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
556 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE;
557 }
558 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
559}
560
561/**
562 * zynqmp_disp_avbuf_enable - Enable the video pipe
563 * @disp: Display controller
564 *
565 * De-assert the video pipe reset.
566 */
567static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)
568{
569 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
570}
571
572/**
573 * zynqmp_disp_avbuf_disable - Disable the video pipe
574 * @disp: Display controller
575 *
576 * Assert the video pipe reset.
577 */
578static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)
579{
580 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG,
581 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST);
582}
583
584/* -----------------------------------------------------------------------------
585 * Blender (Video Pipeline)
586 */
587
588static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val)
589{
590 writel(val, disp->blend.base + reg);
591}
592
593/*
594 * Colorspace conversion matrices.
595 *
596 * Hardcode RGB <-> YUV conversion to full-range SDTV for now.
597 */
598static const u16 csc_zero_matrix[] = {
599 0x0, 0x0, 0x0,
600 0x0, 0x0, 0x0,
601 0x0, 0x0, 0x0
602};
603
604static const u16 csc_identity_matrix[] = {
605 0x1000, 0x0, 0x0,
606 0x0, 0x1000, 0x0,
607 0x0, 0x0, 0x1000
608};
609
610static const u32 csc_zero_offsets[] = {
611 0, 0, 0
612};
613
614static const u16 csc_rgb_to_sdtv_matrix[] = {
615 0x4c9, 0x864, 0x1d3,
616 0x7d4d, 0x7ab3, 0x800,
617 0x800, 0x794d, 0x7eb3
618};
619
620static const u32 csc_rgb_to_sdtv_offsets[] = {
621 0x0, 0x8000000, 0x8000000
622};
623
624static const u16 csc_sdtv_to_rgb_matrix[] = {
625 0x1000, 0x166f, 0x0,
626 0x1000, 0x7483, 0x7a7f,
627 0x1000, 0x0, 0x1c5a
628};
629
630static const u32 csc_sdtv_to_rgb_offsets[] = {
631 0x0, 0x1800, 0x1800
632};
633
634/**
635 * zynqmp_disp_blend_set_output_format - Set the output format of the blender
636 * @disp: Display controller
637 * @format: Output format
638 *
639 * Set the output format of the blender to @format.
640 */
641static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp,
642 enum zynqmp_dpsub_format format)
643{
644 static const unsigned int blend_output_fmts[] = {
645 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB,
646 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444,
647 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422
648 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE,
649 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY,
650 };
651
652 u32 fmt = blend_output_fmts[format];
653 const u16 *coeffs;
654 const u32 *offsets;
655 unsigned int i;
656
657 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
658 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) {
659 coeffs = csc_identity_matrix;
660 offsets = csc_zero_offsets;
661 } else {
662 coeffs = csc_rgb_to_sdtv_matrix;
663 offsets = csc_rgb_to_sdtv_offsets;
664 }
665
666 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
667 zynqmp_disp_blend_write(disp,
668 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i),
669 coeffs[i]);
670
671 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
672 zynqmp_disp_blend_write(disp,
673 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i),
674 offsets[i]);
675}
676
677/**
678 * zynqmp_disp_blend_set_bg_color - Set the background color
679 * @disp: Display controller
680 * @rcr: Red/Cr color component
681 * @gy: Green/Y color component
682 * @bcb: Blue/Cb color component
683 *
684 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and
685 * B or Cr, Y and Cb components respectively depending on the selected output
686 * format.
687 */
688static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp,
689 u32 rcr, u32 gy, u32 bcb)
690{
691 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr);
692 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy);
693 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb);
694}
695
696/**
697 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending
698 * @disp: Display controller
699 * @enable: True to enable global alpha blending
700 * @alpha: Global alpha value (ignored if @enabled is false)
701 */
702void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
703 bool enable, u32 alpha)
704{
705 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
706 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) |
707 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0));
708}
709
710/**
711 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer
712 * @disp: Display controller
713 * @layer: The layer
714 * @coeffs: Colorspace conversion matrix
715 * @offsets: Colorspace conversion offsets
716 *
717 * Configure the input colorspace conversion matrix and offsets for the @layer.
718 * Columns of the matrix are automatically swapped based on the input format to
719 * handle RGB and YCrCb components permutations.
720 */
721static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp,
722 struct zynqmp_disp_layer *layer,
723 const u16 *coeffs,
724 const u32 *offsets)
725{
726 unsigned int swap[3] = { 0, 1, 2 };
727 unsigned int reg;
728 unsigned int i;
729
730 if (layer->disp_fmt->swap) {
731 if (layer->drm_fmt->is_yuv) {
732 /* Swap U and V. */
733 swap[1] = 2;
734 swap[2] = 1;
735 } else {
736 /* Swap R and B. */
737 swap[0] = 2;
738 swap[2] = 0;
739 }
740 }
741
742 if (zynqmp_disp_layer_is_video(layer))
743 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0);
744 else
745 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0);
746
747 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) {
748 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]);
749 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]);
750 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]);
751 }
752
753 if (zynqmp_disp_layer_is_video(layer))
754 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0);
755 else
756 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0);
757
758 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
759 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]);
760}
761
762/**
763 * zynqmp_disp_blend_layer_enable - Enable a layer
764 * @disp: Display controller
765 * @layer: The layer
766 */
767static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
768 struct zynqmp_disp_layer *layer)
769{
770 const u16 *coeffs;
771 const u32 *offsets;
772 u32 val;
773
774 val = (layer->drm_fmt->is_yuv ?
775 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) |
776 (layer->drm_fmt->hsub > 1 ?
777 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0);
778
779 zynqmp_disp_blend_write(disp,
780 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
781 val);
782
783 if (layer->drm_fmt->is_yuv) {
784 coeffs = csc_sdtv_to_rgb_matrix;
785 offsets = csc_sdtv_to_rgb_offsets;
786 } else {
787 coeffs = csc_identity_matrix;
788 offsets = csc_zero_offsets;
789 }
790
791 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets);
792}
793
794/**
795 * zynqmp_disp_blend_layer_disable - Disable a layer
796 * @disp: Display controller
797 * @layer: The layer
798 */
799static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp,
800 struct zynqmp_disp_layer *layer)
801{
802 zynqmp_disp_blend_write(disp,
803 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
804 0);
805
806 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix,
807 csc_zero_offsets);
808}
809
810/* -----------------------------------------------------------------------------
811 * Audio Mixer
812 */
813
814static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val)
815{
816 writel(val, disp->audio.base + reg);
817}
818
819/**
820 * zynqmp_disp_audio_enable - Enable the audio mixer
821 * @disp: Display controller
822 *
823 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to
824 * default values by the reset, set the default mixer volume explicitly.
825 */
826static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp)
827{
828 /* Clear the audio soft reset register as it's an non-reset flop. */
829 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
830 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME,
831 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE);
832}
833
834/**
835 * zynqmp_disp_audio_disable - Disable the audio mixer
836 * @disp: Display controller
837 *
838 * Disable the audio mixer by asserting its soft reset.
839 */
840static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp)
841{
842 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET,
843 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST);
844}
845
846/* -----------------------------------------------------------------------------
847 * ZynqMP Display Layer & DRM Plane
848 */
849
850/**
851 * zynqmp_disp_layer_find_format - Find format information for a DRM format
852 * @layer: The layer
853 * @drm_fmt: DRM format to search
854 *
855 * Search display subsystem format information corresponding to the given DRM
856 * format @drm_fmt for the @layer, and return a pointer to the format
857 * descriptor.
858 *
859 * Return: A pointer to the format descriptor if found, NULL otherwise
860 */
861static const struct zynqmp_disp_format *
862zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer,
863 u32 drm_fmt)
864{
865 unsigned int i;
866
867 for (i = 0; i < layer->info->num_formats; i++) {
868 if (layer->info->formats[i].drm_fmt == drm_fmt)
869 return &layer->info->formats[i];
870 }
871
872 return NULL;
873}
874
875/**
876 * zynqmp_disp_layer_drm_formats - Return the DRM formats supported by the layer
877 * @layer: The layer
878 * @num_formats: Pointer to the returned number of formats
879 *
880 * Return: A newly allocated u32 array that stores all the DRM formats
881 * supported by the layer. The number of formats in the array is returned
882 * through the num_formats argument.
883 */
884u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
885 unsigned int *num_formats)
886{
887 unsigned int i;
888 u32 *formats;
889
890 formats = kcalloc(layer->info->num_formats, sizeof(*formats),
891 GFP_KERNEL);
892 if (!formats)
893 return NULL;
894
895 for (i = 0; i < layer->info->num_formats; ++i)
896 formats[i] = layer->info->formats[i].drm_fmt;
897
898 *num_formats = layer->info->num_formats;
899 return formats;
900}
901
902/**
903 * zynqmp_disp_layer_enable - Enable a layer
904 * @layer: The layer
905 * @mode: Operating mode of layer
906 *
907 * Enable the @layer in the audio/video buffer manager and the blender. DMA
908 * channels are started separately by zynqmp_disp_layer_update().
909 */
910void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer,
911 enum zynqmp_dpsub_layer_mode mode)
912{
913 layer->mode = mode;
914 zynqmp_disp_avbuf_enable_video(layer->disp, layer);
915 zynqmp_disp_blend_layer_enable(layer->disp, layer);
916}
917
918/**
919 * zynqmp_disp_layer_disable - Disable the layer
920 * @layer: The layer
921 *
922 * Disable the layer by stopping its DMA channels and disabling it in the
923 * audio/video buffer manager and the blender.
924 */
925void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)
926{
927 unsigned int i;
928
929 if (layer->disp->dpsub->dma_enabled) {
930 for (i = 0; i < layer->drm_fmt->num_planes; i++)
931 dmaengine_terminate_sync(layer->dmas[i].chan);
932 }
933
934 zynqmp_disp_avbuf_disable_video(layer->disp, layer);
935 zynqmp_disp_blend_layer_disable(layer->disp, layer);
936}
937
938/**
939 * zynqmp_disp_layer_set_format - Set the layer format
940 * @layer: The layer
941 * @info: The format info
942 *
943 * Set the format for @layer to @info. The layer must be disabled.
944 */
945void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
946 const struct drm_format_info *info)
947{
948 unsigned int i;
949
950 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format);
951 layer->drm_fmt = info;
952
953 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
954
955 if (!layer->disp->dpsub->dma_enabled)
956 return;
957
958 /*
959 * Set pconfig for each DMA channel to indicate they're part of a
960 * video group.
961 */
962 for (i = 0; i < info->num_planes; i++) {
963 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
964 struct xilinx_dpdma_peripheral_config pconfig = {
965 .video_group = true,
966 };
967 struct dma_slave_config config = {
968 .direction = DMA_MEM_TO_DEV,
969 .peripheral_config = &pconfig,
970 .peripheral_size = sizeof(pconfig),
971 };
972
973 dmaengine_slave_config(dma->chan, &config);
974 }
975}
976
977/**
978 * zynqmp_disp_layer_update - Update the layer framebuffer
979 * @layer: The layer
980 * @state: The plane state
981 *
982 * Update the framebuffer for the layer by issuing a new DMA engine transaction
983 * for the new framebuffer.
984 *
985 * Return: 0 on success, or the DMA descriptor failure error otherwise
986 */
987int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
988 struct drm_plane_state *state)
989{
990 const struct drm_format_info *info = layer->drm_fmt;
991 unsigned int i;
992
993 if (!layer->disp->dpsub->dma_enabled)
994 return 0;
995
996 for (i = 0; i < info->num_planes; i++) {
997 unsigned int width = state->crtc_w / (i ? info->hsub : 1);
998 unsigned int height = state->crtc_h / (i ? info->vsub : 1);
999 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1000 struct dma_async_tx_descriptor *desc;
1001 dma_addr_t dma_addr;
1002
1003 dma_addr = drm_fb_dma_get_gem_addr(state->fb, state, i);
1004
1005 dma->xt.numf = height;
1006 dma->sgl.size = width * info->cpp[i];
1007 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
1008 dma->xt.src_start = dma_addr;
1009 dma->xt.frame_size = 1;
1010 dma->xt.dir = DMA_MEM_TO_DEV;
1011 dma->xt.src_sgl = true;
1012 dma->xt.dst_sgl = false;
1013
1014 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt,
1015 DMA_CTRL_ACK |
1016 DMA_PREP_REPEAT |
1017 DMA_PREP_LOAD_EOT);
1018 if (!desc) {
1019 dev_err(layer->disp->dev,
1020 "failed to prepare DMA descriptor\n");
1021 return -ENOMEM;
1022 }
1023
1024 dmaengine_submit(desc);
1025 dma_async_issue_pending(dma->chan);
1026 }
1027
1028 return 0;
1029}
1030
1031/**
1032 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer
1033 * @disp: Display controller
1034 * @layer: The layer
1035 *
1036 * Release the DMA channels associated with @layer.
1037 */
1038static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
1039 struct zynqmp_disp_layer *layer)
1040{
1041 unsigned int i;
1042
1043 if (!layer->info || !disp->dpsub->dma_enabled)
1044 return;
1045
1046 for (i = 0; i < layer->info->num_channels; i++) {
1047 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1048
1049 if (!dma->chan)
1050 continue;
1051
1052 /* Make sure the channel is terminated before release. */
1053 dmaengine_terminate_sync(dma->chan);
1054 dma_release_channel(dma->chan);
1055 }
1056}
1057
1058/**
1059 * zynqmp_disp_destroy_layers - Destroy all layers
1060 * @disp: Display controller
1061 */
1062static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)
1063{
1064 unsigned int i;
1065
1066 for (i = 0; i < ARRAY_SIZE(disp->layers); i++)
1067 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1068}
1069
1070/**
1071 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer
1072 * @disp: Display controller
1073 * @layer: The layer
1074 *
1075 * Request all DMA engine channels needed by @layer.
1076 *
1077 * Return: 0 on success, or the DMA channel request error otherwise
1078 */
1079static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
1080 struct zynqmp_disp_layer *layer)
1081{
1082 static const char * const dma_names[] = { "vid", "gfx" };
1083 unsigned int i;
1084 int ret;
1085
1086 if (!disp->dpsub->dma_enabled)
1087 return 0;
1088
1089 for (i = 0; i < layer->info->num_channels; i++) {
1090 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1091 char dma_channel_name[16];
1092
1093 snprintf(dma_channel_name, sizeof(dma_channel_name),
1094 "%s%u", dma_names[layer->id], i);
1095 dma->chan = dma_request_chan(disp->dev, dma_channel_name);
1096 if (IS_ERR(dma->chan)) {
1097 ret = dev_err_probe(disp->dev, PTR_ERR(dma->chan),
1098 "failed to request dma channel\n");
1099 dma->chan = NULL;
1100 return ret;
1101 }
1102 }
1103
1104 return 0;
1105}
1106
1107/**
1108 * zynqmp_disp_create_layers - Create and initialize all layers
1109 * @disp: Display controller
1110 *
1111 * Return: 0 on success, or the DMA channel request error otherwise
1112 */
1113static int zynqmp_disp_create_layers(struct zynqmp_disp *disp)
1114{
1115 static const struct zynqmp_disp_layer_info layer_info[] = {
1116 [ZYNQMP_DPSUB_LAYER_VID] = {
1117 .formats = avbuf_vid_fmts,
1118 .num_formats = ARRAY_SIZE(avbuf_vid_fmts),
1119 .num_channels = 3,
1120 },
1121 [ZYNQMP_DPSUB_LAYER_GFX] = {
1122 .formats = avbuf_gfx_fmts,
1123 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts),
1124 .num_channels = 1,
1125 },
1126 };
1127
1128 unsigned int i;
1129 int ret;
1130
1131 for (i = 0; i < ARRAY_SIZE(disp->layers); i++) {
1132 struct zynqmp_disp_layer *layer = &disp->layers[i];
1133
1134 layer->id = i;
1135 layer->disp = disp;
1136 layer->info = &layer_info[i];
1137
1138 ret = zynqmp_disp_layer_request_dma(disp, layer);
1139 if (ret)
1140 goto err;
1141
1142 disp->dpsub->layers[i] = layer;
1143 }
1144
1145 return 0;
1146
1147err:
1148 zynqmp_disp_destroy_layers(disp);
1149 return ret;
1150}
1151
1152/* -----------------------------------------------------------------------------
1153 * ZynqMP Display
1154 */
1155
1156/**
1157 * zynqmp_disp_enable - Enable the display controller
1158 * @disp: Display controller
1159 */
1160void zynqmp_disp_enable(struct zynqmp_disp *disp)
1161{
1162 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB);
1163 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0);
1164
1165 zynqmp_disp_avbuf_enable(disp);
1166 /* Choose clock source based on the DT clock handle. */
1167 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->dpsub->vid_clk_from_ps,
1168 disp->dpsub->aud_clk_from_ps,
1169 disp->dpsub->vid_clk_from_ps);
1170 zynqmp_disp_avbuf_enable_channels(disp);
1171 zynqmp_disp_avbuf_enable_audio(disp);
1172
1173 zynqmp_disp_audio_enable(disp);
1174}
1175
1176/**
1177 * zynqmp_disp_disable - Disable the display controller
1178 * @disp: Display controller
1179 */
1180void zynqmp_disp_disable(struct zynqmp_disp *disp)
1181{
1182 zynqmp_disp_audio_disable(disp);
1183
1184 zynqmp_disp_avbuf_disable_audio(disp);
1185 zynqmp_disp_avbuf_disable_channels(disp);
1186 zynqmp_disp_avbuf_disable(disp);
1187}
1188
1189/**
1190 * zynqmp_disp_setup_clock - Configure the display controller pixel clock rate
1191 * @disp: Display controller
1192 * @mode_clock: The pixel clock rate, in Hz
1193 *
1194 * Return: 0 on success, or a negative error clock otherwise
1195 */
1196int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,
1197 unsigned long mode_clock)
1198{
1199 unsigned long rate;
1200 long diff;
1201 int ret;
1202
1203 ret = clk_set_rate(disp->dpsub->vid_clk, mode_clock);
1204 if (ret) {
1205 dev_err(disp->dev, "failed to set the video clock\n");
1206 return ret;
1207 }
1208
1209 rate = clk_get_rate(disp->dpsub->vid_clk);
1210 diff = rate - mode_clock;
1211 if (abs(diff) > mode_clock / 20)
1212 dev_info(disp->dev,
1213 "requested pixel rate: %lu actual rate: %lu\n",
1214 mode_clock, rate);
1215 else
1216 dev_dbg(disp->dev,
1217 "requested pixel rate: %lu actual rate: %lu\n",
1218 mode_clock, rate);
1219
1220 return 0;
1221}
1222
1223/* -----------------------------------------------------------------------------
1224 * Initialization & Cleanup
1225 */
1226
1227int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub)
1228{
1229 struct platform_device *pdev = to_platform_device(dpsub->dev);
1230 struct zynqmp_disp *disp;
1231 int ret;
1232
1233 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1234 if (!disp)
1235 return -ENOMEM;
1236
1237 disp->dev = &pdev->dev;
1238 disp->dpsub = dpsub;
1239
1240 disp->blend.base = devm_platform_ioremap_resource_byname(pdev, "blend");
1241 if (IS_ERR(disp->blend.base)) {
1242 ret = PTR_ERR(disp->blend.base);
1243 goto error;
1244 }
1245
1246 disp->avbuf.base = devm_platform_ioremap_resource_byname(pdev, "av_buf");
1247 if (IS_ERR(disp->avbuf.base)) {
1248 ret = PTR_ERR(disp->avbuf.base);
1249 goto error;
1250 }
1251
1252 disp->audio.base = devm_platform_ioremap_resource_byname(pdev, "aud");
1253 if (IS_ERR(disp->audio.base)) {
1254 ret = PTR_ERR(disp->audio.base);
1255 goto error;
1256 }
1257
1258 ret = zynqmp_disp_create_layers(disp);
1259 if (ret)
1260 goto error;
1261
1262 if (disp->dpsub->dma_enabled) {
1263 struct zynqmp_disp_layer *layer;
1264
1265 layer = &disp->layers[ZYNQMP_DPSUB_LAYER_VID];
1266 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align;
1267 }
1268
1269 dpsub->disp = disp;
1270
1271 return 0;
1272
1273error:
1274 kfree(disp);
1275 return ret;
1276}
1277
1278void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub)
1279{
1280 struct zynqmp_disp *disp = dpsub->disp;
1281
1282 zynqmp_disp_destroy_layers(disp);
1283}