1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * ZynqMP Display Driver
 4 *
 5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
 6 *
 7 * Authors:
 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12#ifndef _ZYNQMP_DISP_H_
13#define _ZYNQMP_DISP_H_
14
15#include <linux/types.h>
16
17/*
18 * 3840x2160 is advertised as the maximum resolution, but almost any
19 * resolutions under a 300Mhz pixel rate would work. Pick 4096x4096.
20 */
21#define ZYNQMP_DISP_MAX_WIDTH				4096
22#define ZYNQMP_DISP_MAX_HEIGHT				4096
23
24/* The DPDMA is limited to 44 bit addressing. */
25#define ZYNQMP_DISP_MAX_DMA_BIT				44
26
27struct device;
28struct drm_format_info;
29struct drm_plane_state;
30struct platform_device;
31struct zynqmp_disp;
32struct zynqmp_disp_layer;
33struct zynqmp_dpsub;
34
35/**
36 * enum zynqmp_dpsub_layer_id - Layer identifier
37 * @ZYNQMP_DPSUB_LAYER_VID: Video layer
38 * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer
39 */
40enum zynqmp_dpsub_layer_id {
41	ZYNQMP_DPSUB_LAYER_VID,
42	ZYNQMP_DPSUB_LAYER_GFX,
43};
44
45/**
46 * enum zynqmp_dpsub_layer_mode - Layer mode
47 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
48 * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode
49 */
50enum zynqmp_dpsub_layer_mode {
51	ZYNQMP_DPSUB_LAYER_NONLIVE,
52	ZYNQMP_DPSUB_LAYER_LIVE,
53};
54
55void zynqmp_disp_enable(struct zynqmp_disp *disp);
56void zynqmp_disp_disable(struct zynqmp_disp *disp);
57int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,
58			    unsigned long mode_clock);
59
60void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
61					bool enable, u32 alpha);
62
63u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
64				   unsigned int *num_formats);
65void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer,
66			      enum zynqmp_dpsub_layer_mode mode);
67void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
68void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
69				  const struct drm_format_info *info);
70int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
71			     struct drm_plane_state *state);
72
73int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub);
74void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub);
75
76#endif /* _ZYNQMP_DISP_H_ */