Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/kernel_stat.h>
13#include <linux/module.h>
14#include <linux/ktime.h>
15#include <linux/hrtimer.h>
16#include <linux/tick.h>
17#include <linux/slab.h>
18#include <linux/sched/cpufreq.h>
19#include <linux/sched/smt.h>
20#include <linux/list.h>
21#include <linux/cpu.h>
22#include <linux/cpufreq.h>
23#include <linux/sysfs.h>
24#include <linux/types.h>
25#include <linux/fs.h>
26#include <linux/acpi.h>
27#include <linux/vmalloc.h>
28#include <linux/pm_qos.h>
29#include <linux/bitfield.h>
30#include <trace/events/power.h>
31
32#include <asm/cpu.h>
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
36#include <asm/cpufeature.h>
37#include <asm/intel-family.h>
38#include "../drivers/thermal/intel/thermal_interrupt.h"
39
40#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41
42#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
44#define INTEL_CPUFREQ_TRANSITION_DELAY 500
45
46#ifdef CONFIG_ACPI
47#include <acpi/processor.h>
48#include <acpi/cppc_acpi.h>
49#endif
50
51#define FRAC_BITS 8
52#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53#define fp_toint(X) ((X) >> FRAC_BITS)
54
55#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
56
57#define EXT_BITS 6
58#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
59#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
60#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
61
62static inline int32_t mul_fp(int32_t x, int32_t y)
63{
64 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
65}
66
67static inline int32_t div_fp(s64 x, s64 y)
68{
69 return div64_s64((int64_t)x << FRAC_BITS, y);
70}
71
72static inline int ceiling_fp(int32_t x)
73{
74 int mask, ret;
75
76 ret = fp_toint(x);
77 mask = (1 << FRAC_BITS) - 1;
78 if (x & mask)
79 ret += 1;
80 return ret;
81}
82
83static inline u64 mul_ext_fp(u64 x, u64 y)
84{
85 return (x * y) >> EXT_FRAC_BITS;
86}
87
88static inline u64 div_ext_fp(u64 x, u64 y)
89{
90 return div64_u64(x << EXT_FRAC_BITS, y);
91}
92
93/**
94 * struct sample - Store performance sample
95 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
96 * performance during last sample period
97 * @busy_scaled: Scaled busy value which is used to calculate next
98 * P state. This can be different than core_avg_perf
99 * to account for cpu idle period
100 * @aperf: Difference of actual performance frequency clock count
101 * read from APERF MSR between last and current sample
102 * @mperf: Difference of maximum performance frequency clock count
103 * read from MPERF MSR between last and current sample
104 * @tsc: Difference of time stamp counter between last and
105 * current sample
106 * @time: Current time from scheduler
107 *
108 * This structure is used in the cpudata structure to store performance sample
109 * data for choosing next P State.
110 */
111struct sample {
112 int32_t core_avg_perf;
113 int32_t busy_scaled;
114 u64 aperf;
115 u64 mperf;
116 u64 tsc;
117 u64 time;
118};
119
120/**
121 * struct pstate_data - Store P state data
122 * @current_pstate: Current requested P state
123 * @min_pstate: Min P state possible for this platform
124 * @max_pstate: Max P state possible for this platform
125 * @max_pstate_physical:This is physical Max P state for a processor
126 * This can be higher than the max_pstate which can
127 * be limited by platform thermal design power limits
128 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
129 * @scaling: Scaling factor between performance and frequency
130 * @turbo_pstate: Max Turbo P state possible for this platform
131 * @min_freq: @min_pstate frequency in cpufreq units
132 * @max_freq: @max_pstate frequency in cpufreq units
133 * @turbo_freq: @turbo_pstate frequency in cpufreq units
134 *
135 * Stores the per cpu model P state limits and current P state.
136 */
137struct pstate_data {
138 int current_pstate;
139 int min_pstate;
140 int max_pstate;
141 int max_pstate_physical;
142 int perf_ctl_scaling;
143 int scaling;
144 int turbo_pstate;
145 unsigned int min_freq;
146 unsigned int max_freq;
147 unsigned int turbo_freq;
148};
149
150/**
151 * struct vid_data - Stores voltage information data
152 * @min: VID data for this platform corresponding to
153 * the lowest P state
154 * @max: VID data corresponding to the highest P State.
155 * @turbo: VID data for turbo P state
156 * @ratio: Ratio of (vid max - vid min) /
157 * (max P state - Min P State)
158 *
159 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
160 * This data is used in Atom platforms, where in addition to target P state,
161 * the voltage data needs to be specified to select next P State.
162 */
163struct vid_data {
164 int min;
165 int max;
166 int turbo;
167 int32_t ratio;
168};
169
170/**
171 * struct global_params - Global parameters, mostly tunable via sysfs.
172 * @no_turbo: Whether or not to use turbo P-states.
173 * @turbo_disabled: Whether or not turbo P-states are available at all,
174 * based on the MSR_IA32_MISC_ENABLE value and whether or
175 * not the maximum reported turbo P-state is different from
176 * the maximum reported non-turbo one.
177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * P-state capacity.
179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
180 * P-state capacity.
181 */
182struct global_params {
183 bool no_turbo;
184 bool turbo_disabled;
185 int max_perf_pct;
186 int min_perf_pct;
187};
188
189/**
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @sample: Storage for storing last Sample data
205 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
206 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
207 * @acpi_perf_data: Stores ACPI perf information read from _PSS
208 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
209 * @epp_powersave: Last saved HWP energy performance preference
210 * (EPP) or energy performance bias (EPB),
211 * when policy switched to performance
212 * @epp_policy: Last saved policy used to set EPP/EPB
213 * @epp_default: Power on default HWP energy performance
214 * preference/bias
215 * @epp_cached: Cached HWP energy-performance preference value
216 * @hwp_req_cached: Cached value of the last HWP Request MSR
217 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
218 * @last_io_update: Last time when IO wake flag was set
219 * @capacity_perf: Highest perf used for scale invariance
220 * @sched_flags: Store scheduler flags for possible cross CPU update
221 * @hwp_boost_min: Last HWP boosted min performance
222 * @suspended: Whether or not the driver has been suspended.
223 * @hwp_notify_work: workqueue for HWP notifications.
224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
227struct cpudata {
228 int cpu;
229
230 unsigned int policy;
231 struct update_util_data update_util;
232 bool update_util_set;
233
234 struct pstate_data pstate;
235 struct vid_data vid;
236
237 u64 last_update;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
240 u64 prev_aperf;
241 u64 prev_mperf;
242 u64 prev_tsc;
243 struct sample sample;
244 int32_t min_perf_ratio;
245 int32_t max_perf_ratio;
246#ifdef CONFIG_ACPI
247 struct acpi_processor_performance acpi_perf_data;
248 bool valid_pss_table;
249#endif
250 unsigned int iowait_boost;
251 s16 epp_powersave;
252 s16 epp_policy;
253 s16 epp_default;
254 s16 epp_cached;
255 u64 hwp_req_cached;
256 u64 hwp_cap_cached;
257 u64 last_io_update;
258 unsigned int capacity_perf;
259 unsigned int sched_flags;
260 u32 hwp_boost_min;
261 bool suspended;
262 struct delayed_work hwp_notify_work;
263};
264
265static struct cpudata **all_cpu_data;
266
267/**
268 * struct pstate_funcs - Per CPU model specific callbacks
269 * @get_max: Callback to get maximum non turbo effective P state
270 * @get_max_physical: Callback to get maximum non turbo physical P state
271 * @get_min: Callback to get minimum P state
272 * @get_turbo: Callback to get turbo P state
273 * @get_scaling: Callback to get frequency scaling factor
274 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
275 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
276 * @get_val: Callback to convert P state to actual MSR write value
277 * @get_vid: Callback to get VID data for Atom platforms
278 *
279 * Core and Atom CPU models have different way to get P State limits. This
280 * structure is used to store those callbacks.
281 */
282struct pstate_funcs {
283 int (*get_max)(int cpu);
284 int (*get_max_physical)(int cpu);
285 int (*get_min)(int cpu);
286 int (*get_turbo)(int cpu);
287 int (*get_scaling)(void);
288 int (*get_cpu_scaling)(int cpu);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
292};
293
294static struct pstate_funcs pstate_funcs __read_mostly;
295
296static bool hwp_active __ro_after_init;
297static int hwp_mode_bdw __ro_after_init;
298static bool per_cpu_limits __ro_after_init;
299static bool hwp_forced __ro_after_init;
300static bool hwp_boost __read_mostly;
301static bool hwp_is_hybrid;
302
303static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305#define HYBRID_SCALING_FACTOR 78741
306#define HYBRID_SCALING_FACTOR_MTL 80000
307#define HYBRID_SCALING_FACTOR_LNL 86957
308
309static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
310
311static inline int core_get_scaling(void)
312{
313 return 100000;
314}
315
316#ifdef CONFIG_ACPI
317static bool acpi_ppc;
318#endif
319
320static struct global_params global;
321
322static DEFINE_MUTEX(intel_pstate_driver_lock);
323static DEFINE_MUTEX(intel_pstate_limits_lock);
324
325#ifdef CONFIG_ACPI
326
327static bool intel_pstate_acpi_pm_profile_server(void)
328{
329 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
330 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
331 return true;
332
333 return false;
334}
335
336static bool intel_pstate_get_ppc_enable_status(void)
337{
338 if (intel_pstate_acpi_pm_profile_server())
339 return true;
340
341 return acpi_ppc;
342}
343
344#ifdef CONFIG_ACPI_CPPC_LIB
345
346/* The work item is needed to avoid CPU hotplug locking issues */
347static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
348{
349 sched_set_itmt_support();
350}
351
352static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
353
354#define CPPC_MAX_PERF U8_MAX
355
356static void intel_pstate_set_itmt_prio(int cpu)
357{
358 struct cppc_perf_caps cppc_perf;
359 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
360 int ret;
361
362 ret = cppc_get_perf_caps(cpu, &cppc_perf);
363 /*
364 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
365 *
366 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
367 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
368 * Fall back to MSR_HWP_CAPABILITIES then too.
369 */
370 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
371 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
372
373 /*
374 * The priorities can be set regardless of whether or not
375 * sched_set_itmt_support(true) has been called and it is valid to
376 * update them at any time after it has been called.
377 */
378 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
379
380 if (max_highest_perf <= min_highest_perf) {
381 if (cppc_perf.highest_perf > max_highest_perf)
382 max_highest_perf = cppc_perf.highest_perf;
383
384 if (cppc_perf.highest_perf < min_highest_perf)
385 min_highest_perf = cppc_perf.highest_perf;
386
387 if (max_highest_perf > min_highest_perf) {
388 /*
389 * This code can be run during CPU online under the
390 * CPU hotplug locks, so sched_set_itmt_support()
391 * cannot be called from here. Queue up a work item
392 * to invoke it.
393 */
394 schedule_work(&sched_itmt_work);
395 }
396 }
397}
398
399static int intel_pstate_get_cppc_guaranteed(int cpu)
400{
401 struct cppc_perf_caps cppc_perf;
402 int ret;
403
404 ret = cppc_get_perf_caps(cpu, &cppc_perf);
405 if (ret)
406 return ret;
407
408 if (cppc_perf.guaranteed_perf)
409 return cppc_perf.guaranteed_perf;
410
411 return cppc_perf.nominal_perf;
412}
413
414static int intel_pstate_cppc_get_scaling(int cpu)
415{
416 struct cppc_perf_caps cppc_perf;
417 int ret;
418
419 ret = cppc_get_perf_caps(cpu, &cppc_perf);
420
421 /*
422 * If the nominal frequency and the nominal performance are not
423 * zero and the ratio between them is not 100, return the hybrid
424 * scaling factor.
425 */
426 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
427 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
428 return hybrid_scaling_factor;
429
430 return core_get_scaling();
431}
432
433#else /* CONFIG_ACPI_CPPC_LIB */
434static inline void intel_pstate_set_itmt_prio(int cpu)
435{
436}
437#endif /* CONFIG_ACPI_CPPC_LIB */
438
439static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
440{
441 struct cpudata *cpu;
442 int ret;
443 int i;
444
445 if (hwp_active) {
446 intel_pstate_set_itmt_prio(policy->cpu);
447 return;
448 }
449
450 if (!intel_pstate_get_ppc_enable_status())
451 return;
452
453 cpu = all_cpu_data[policy->cpu];
454
455 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
456 policy->cpu);
457 if (ret)
458 return;
459
460 /*
461 * Check if the control value in _PSS is for PERF_CTL MSR, which should
462 * guarantee that the states returned by it map to the states in our
463 * list directly.
464 */
465 if (cpu->acpi_perf_data.control_register.space_id !=
466 ACPI_ADR_SPACE_FIXED_HARDWARE)
467 goto err;
468
469 /*
470 * If there is only one entry _PSS, simply ignore _PSS and continue as
471 * usual without taking _PSS into account
472 */
473 if (cpu->acpi_perf_data.state_count < 2)
474 goto err;
475
476 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
477 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
478 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
479 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
480 (u32) cpu->acpi_perf_data.states[i].core_frequency,
481 (u32) cpu->acpi_perf_data.states[i].power,
482 (u32) cpu->acpi_perf_data.states[i].control);
483 }
484
485 cpu->valid_pss_table = true;
486 pr_debug("_PPC limits will be enforced\n");
487
488 return;
489
490 err:
491 cpu->valid_pss_table = false;
492 acpi_processor_unregister_performance(policy->cpu);
493}
494
495static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
496{
497 struct cpudata *cpu;
498
499 cpu = all_cpu_data[policy->cpu];
500 if (!cpu->valid_pss_table)
501 return;
502
503 acpi_processor_unregister_performance(policy->cpu);
504}
505#else /* CONFIG_ACPI */
506static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
507{
508}
509
510static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
511{
512}
513
514static inline bool intel_pstate_acpi_pm_profile_server(void)
515{
516 return false;
517}
518#endif /* CONFIG_ACPI */
519
520#ifndef CONFIG_ACPI_CPPC_LIB
521static inline int intel_pstate_get_cppc_guaranteed(int cpu)
522{
523 return -ENOTSUPP;
524}
525
526static int intel_pstate_cppc_get_scaling(int cpu)
527{
528 return core_get_scaling();
529}
530#endif /* CONFIG_ACPI_CPPC_LIB */
531
532static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
533 unsigned int relation)
534{
535 if (freq == cpu->pstate.turbo_freq)
536 return cpu->pstate.turbo_pstate;
537
538 if (freq == cpu->pstate.max_freq)
539 return cpu->pstate.max_pstate;
540
541 switch (relation) {
542 case CPUFREQ_RELATION_H:
543 return freq / cpu->pstate.scaling;
544 case CPUFREQ_RELATION_C:
545 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
546 }
547
548 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
549}
550
551static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
552{
553 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
554}
555
556/**
557 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
558 * @cpu: Target CPU.
559 *
560 * On hybrid processors, HWP may expose more performance levels than there are
561 * P-states accessible through the PERF_CTL interface. If that happens, the
562 * scaling factor between HWP performance levels and CPU frequency will be less
563 * than the scaling factor between P-state values and CPU frequency.
564 *
565 * In that case, adjust the CPU parameters used in computations accordingly.
566 */
567static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
568{
569 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
570 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
571 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
572 int scaling = cpu->pstate.scaling;
573 int freq;
574
575 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
576 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
577 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
578 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
579 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
580 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
581
582 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
583 perf_ctl_scaling);
584 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
585 perf_ctl_scaling);
586
587 freq = perf_ctl_max_phys * perf_ctl_scaling;
588 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
589
590 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
591 cpu->pstate.min_freq = freq;
592 /*
593 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
594 * the effective range of HWP performance levels.
595 */
596 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
597}
598
599static bool turbo_is_disabled(void)
600{
601 u64 misc_en;
602
603 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
604
605 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
606}
607
608static int min_perf_pct_min(void)
609{
610 struct cpudata *cpu = all_cpu_data[0];
611 int turbo_pstate = cpu->pstate.turbo_pstate;
612
613 return turbo_pstate ?
614 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
615}
616
617static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
618{
619 u64 epb;
620 int ret;
621
622 if (!boot_cpu_has(X86_FEATURE_EPB))
623 return -ENXIO;
624
625 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
626 if (ret)
627 return (s16)ret;
628
629 return (s16)(epb & 0x0f);
630}
631
632static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
633{
634 s16 epp;
635
636 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
637 /*
638 * When hwp_req_data is 0, means that caller didn't read
639 * MSR_HWP_REQUEST, so need to read and get EPP.
640 */
641 if (!hwp_req_data) {
642 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
643 &hwp_req_data);
644 if (epp)
645 return epp;
646 }
647 epp = (hwp_req_data >> 24) & 0xff;
648 } else {
649 /* When there is no EPP present, HWP uses EPB settings */
650 epp = intel_pstate_get_epb(cpu_data);
651 }
652
653 return epp;
654}
655
656static int intel_pstate_set_epb(int cpu, s16 pref)
657{
658 u64 epb;
659 int ret;
660
661 if (!boot_cpu_has(X86_FEATURE_EPB))
662 return -ENXIO;
663
664 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
665 if (ret)
666 return ret;
667
668 epb = (epb & ~0x0f) | pref;
669 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
670
671 return 0;
672}
673
674/*
675 * EPP/EPB display strings corresponding to EPP index in the
676 * energy_perf_strings[]
677 * index String
678 *-------------------------------------
679 * 0 default
680 * 1 performance
681 * 2 balance_performance
682 * 3 balance_power
683 * 4 power
684 */
685
686enum energy_perf_value_index {
687 EPP_INDEX_DEFAULT = 0,
688 EPP_INDEX_PERFORMANCE,
689 EPP_INDEX_BALANCE_PERFORMANCE,
690 EPP_INDEX_BALANCE_POWERSAVE,
691 EPP_INDEX_POWERSAVE,
692};
693
694static const char * const energy_perf_strings[] = {
695 [EPP_INDEX_DEFAULT] = "default",
696 [EPP_INDEX_PERFORMANCE] = "performance",
697 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
698 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
699 [EPP_INDEX_POWERSAVE] = "power",
700 NULL
701};
702static unsigned int epp_values[] = {
703 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
704 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
705 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
706 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
707 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
708};
709
710static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
711{
712 s16 epp;
713 int index = -EINVAL;
714
715 *raw_epp = 0;
716 epp = intel_pstate_get_epp(cpu_data, 0);
717 if (epp < 0)
718 return epp;
719
720 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
721 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
722 return EPP_INDEX_PERFORMANCE;
723 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
724 return EPP_INDEX_BALANCE_PERFORMANCE;
725 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
726 return EPP_INDEX_BALANCE_POWERSAVE;
727 if (epp == epp_values[EPP_INDEX_POWERSAVE])
728 return EPP_INDEX_POWERSAVE;
729 *raw_epp = epp;
730 return 0;
731 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
732 /*
733 * Range:
734 * 0x00-0x03 : Performance
735 * 0x04-0x07 : Balance performance
736 * 0x08-0x0B : Balance power
737 * 0x0C-0x0F : Power
738 * The EPB is a 4 bit value, but our ranges restrict the
739 * value which can be set. Here only using top two bits
740 * effectively.
741 */
742 index = (epp >> 2) + 1;
743 }
744
745 return index;
746}
747
748static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
749{
750 int ret;
751
752 /*
753 * Use the cached HWP Request MSR value, because in the active mode the
754 * register itself may be updated by intel_pstate_hwp_boost_up() or
755 * intel_pstate_hwp_boost_down() at any time.
756 */
757 u64 value = READ_ONCE(cpu->hwp_req_cached);
758
759 value &= ~GENMASK_ULL(31, 24);
760 value |= (u64)epp << 24;
761 /*
762 * The only other updater of hwp_req_cached in the active mode,
763 * intel_pstate_hwp_set(), is called under the same lock as this
764 * function, so it cannot run in parallel with the update below.
765 */
766 WRITE_ONCE(cpu->hwp_req_cached, value);
767 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
768 if (!ret)
769 cpu->epp_cached = epp;
770
771 return ret;
772}
773
774static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
775 int pref_index, bool use_raw,
776 u32 raw_epp)
777{
778 int epp = -EINVAL;
779 int ret;
780
781 if (!pref_index)
782 epp = cpu_data->epp_default;
783
784 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
785 if (use_raw)
786 epp = raw_epp;
787 else if (epp == -EINVAL)
788 epp = epp_values[pref_index];
789
790 /*
791 * To avoid confusion, refuse to set EPP to any values different
792 * from 0 (performance) if the current policy is "performance",
793 * because those values would be overridden.
794 */
795 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
796 return -EBUSY;
797
798 ret = intel_pstate_set_epp(cpu_data, epp);
799 } else {
800 if (epp == -EINVAL)
801 epp = (pref_index - 1) << 2;
802 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
803 }
804
805 return ret;
806}
807
808static ssize_t show_energy_performance_available_preferences(
809 struct cpufreq_policy *policy, char *buf)
810{
811 int i = 0;
812 int ret = 0;
813
814 while (energy_perf_strings[i] != NULL)
815 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
816
817 ret += sprintf(&buf[ret], "\n");
818
819 return ret;
820}
821
822cpufreq_freq_attr_ro(energy_performance_available_preferences);
823
824static struct cpufreq_driver intel_pstate;
825
826static ssize_t store_energy_performance_preference(
827 struct cpufreq_policy *policy, const char *buf, size_t count)
828{
829 struct cpudata *cpu = all_cpu_data[policy->cpu];
830 char str_preference[21];
831 bool raw = false;
832 ssize_t ret;
833 u32 epp = 0;
834
835 ret = sscanf(buf, "%20s", str_preference);
836 if (ret != 1)
837 return -EINVAL;
838
839 ret = match_string(energy_perf_strings, -1, str_preference);
840 if (ret < 0) {
841 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
842 return ret;
843
844 ret = kstrtouint(buf, 10, &epp);
845 if (ret)
846 return ret;
847
848 if (epp > 255)
849 return -EINVAL;
850
851 raw = true;
852 }
853
854 /*
855 * This function runs with the policy R/W semaphore held, which
856 * guarantees that the driver pointer will not change while it is
857 * running.
858 */
859 if (!intel_pstate_driver)
860 return -EAGAIN;
861
862 mutex_lock(&intel_pstate_limits_lock);
863
864 if (intel_pstate_driver == &intel_pstate) {
865 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
866 } else {
867 /*
868 * In the passive mode the governor needs to be stopped on the
869 * target CPU before the EPP update and restarted after it,
870 * which is super-heavy-weight, so make sure it is worth doing
871 * upfront.
872 */
873 if (!raw)
874 epp = ret ? epp_values[ret] : cpu->epp_default;
875
876 if (cpu->epp_cached != epp) {
877 int err;
878
879 cpufreq_stop_governor(policy);
880 ret = intel_pstate_set_epp(cpu, epp);
881 err = cpufreq_start_governor(policy);
882 if (!ret)
883 ret = err;
884 } else {
885 ret = 0;
886 }
887 }
888
889 mutex_unlock(&intel_pstate_limits_lock);
890
891 return ret ?: count;
892}
893
894static ssize_t show_energy_performance_preference(
895 struct cpufreq_policy *policy, char *buf)
896{
897 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
898 int preference, raw_epp;
899
900 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
901 if (preference < 0)
902 return preference;
903
904 if (raw_epp)
905 return sprintf(buf, "%d\n", raw_epp);
906 else
907 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
908}
909
910cpufreq_freq_attr_rw(energy_performance_preference);
911
912static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
913{
914 struct cpudata *cpu = all_cpu_data[policy->cpu];
915 int ratio, freq;
916
917 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
918 if (ratio <= 0) {
919 u64 cap;
920
921 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
922 ratio = HWP_GUARANTEED_PERF(cap);
923 }
924
925 freq = ratio * cpu->pstate.scaling;
926 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
927 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
928
929 return sprintf(buf, "%d\n", freq);
930}
931
932cpufreq_freq_attr_ro(base_frequency);
933
934static struct freq_attr *hwp_cpufreq_attrs[] = {
935 &energy_performance_preference,
936 &energy_performance_available_preferences,
937 &base_frequency,
938 NULL,
939};
940
941static struct cpudata *hybrid_max_perf_cpu __read_mostly;
942/*
943 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata,
944 * and the x86 arch scale-invariance information from concurrent updates.
945 */
946static DEFINE_MUTEX(hybrid_capacity_lock);
947
948static void hybrid_set_cpu_capacity(struct cpudata *cpu)
949{
950 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf,
951 hybrid_max_perf_cpu->capacity_perf,
952 cpu->capacity_perf,
953 cpu->pstate.max_pstate_physical);
954
955 pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu,
956 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf,
957 cpu->pstate.max_pstate_physical);
958}
959
960static void hybrid_clear_cpu_capacity(unsigned int cpunum)
961{
962 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1);
963}
964
965static void hybrid_get_capacity_perf(struct cpudata *cpu)
966{
967 if (READ_ONCE(global.no_turbo)) {
968 cpu->capacity_perf = cpu->pstate.max_pstate_physical;
969 return;
970 }
971
972 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
973}
974
975static void hybrid_set_capacity_of_cpus(void)
976{
977 int cpunum;
978
979 for_each_online_cpu(cpunum) {
980 struct cpudata *cpu = all_cpu_data[cpunum];
981
982 if (cpu)
983 hybrid_set_cpu_capacity(cpu);
984 }
985}
986
987static void hybrid_update_cpu_capacity_scaling(void)
988{
989 struct cpudata *max_perf_cpu = NULL;
990 unsigned int max_cap_perf = 0;
991 int cpunum;
992
993 for_each_online_cpu(cpunum) {
994 struct cpudata *cpu = all_cpu_data[cpunum];
995
996 if (!cpu)
997 continue;
998
999 /*
1000 * During initialization, CPU performance at full capacity needs
1001 * to be determined.
1002 */
1003 if (!hybrid_max_perf_cpu)
1004 hybrid_get_capacity_perf(cpu);
1005
1006 /*
1007 * If hybrid_max_perf_cpu is not NULL at this point, it is
1008 * being replaced, so don't take it into account when looking
1009 * for the new one.
1010 */
1011 if (cpu == hybrid_max_perf_cpu)
1012 continue;
1013
1014 if (cpu->capacity_perf > max_cap_perf) {
1015 max_cap_perf = cpu->capacity_perf;
1016 max_perf_cpu = cpu;
1017 }
1018 }
1019
1020 if (max_perf_cpu) {
1021 hybrid_max_perf_cpu = max_perf_cpu;
1022 hybrid_set_capacity_of_cpus();
1023 } else {
1024 pr_info("Found no CPUs with nonzero maximum performance\n");
1025 /* Revert to the flat CPU capacity structure. */
1026 for_each_online_cpu(cpunum)
1027 hybrid_clear_cpu_capacity(cpunum);
1028 }
1029}
1030
1031static void __hybrid_refresh_cpu_capacity_scaling(void)
1032{
1033 hybrid_max_perf_cpu = NULL;
1034 hybrid_update_cpu_capacity_scaling();
1035}
1036
1037static void hybrid_refresh_cpu_capacity_scaling(void)
1038{
1039 guard(mutex)(&hybrid_capacity_lock);
1040
1041 __hybrid_refresh_cpu_capacity_scaling();
1042}
1043
1044static void hybrid_init_cpu_capacity_scaling(bool refresh)
1045{
1046 /*
1047 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity
1048 * scaling has been enabled already and the driver is just changing the
1049 * operation mode.
1050 */
1051 if (refresh) {
1052 hybrid_refresh_cpu_capacity_scaling();
1053 return;
1054 }
1055
1056 /*
1057 * On hybrid systems, use asym capacity instead of ITMT, but because
1058 * the capacity of SMT threads is not deterministic even approximately,
1059 * do not do that when SMT is in use.
1060 */
1061 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) {
1062 hybrid_refresh_cpu_capacity_scaling();
1063 /*
1064 * Disabling ITMT causes sched domains to be rebuilt to disable asym
1065 * packing and enable asym capacity.
1066 */
1067 sched_clear_itmt_support();
1068 }
1069}
1070
1071static bool hybrid_clear_max_perf_cpu(void)
1072{
1073 bool ret;
1074
1075 guard(mutex)(&hybrid_capacity_lock);
1076
1077 ret = !!hybrid_max_perf_cpu;
1078 hybrid_max_perf_cpu = NULL;
1079
1080 return ret;
1081}
1082
1083static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
1084{
1085 u64 cap;
1086
1087 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
1088 WRITE_ONCE(cpu->hwp_cap_cached, cap);
1089 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
1090 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
1091}
1092
1093static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
1094{
1095 int scaling = cpu->pstate.scaling;
1096
1097 __intel_pstate_get_hwp_cap(cpu);
1098
1099 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
1100 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
1101 if (scaling != cpu->pstate.perf_ctl_scaling) {
1102 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
1103
1104 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
1105 perf_ctl_scaling);
1106 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
1107 perf_ctl_scaling);
1108 }
1109}
1110
1111static void hybrid_update_capacity(struct cpudata *cpu)
1112{
1113 unsigned int max_cap_perf;
1114
1115 mutex_lock(&hybrid_capacity_lock);
1116
1117 if (!hybrid_max_perf_cpu)
1118 goto unlock;
1119
1120 /*
1121 * The maximum performance of the CPU may have changed, but assume
1122 * that the performance of the other CPUs has not changed.
1123 */
1124 max_cap_perf = hybrid_max_perf_cpu->capacity_perf;
1125
1126 intel_pstate_get_hwp_cap(cpu);
1127
1128 hybrid_get_capacity_perf(cpu);
1129 /* Should hybrid_max_perf_cpu be replaced by this CPU? */
1130 if (cpu->capacity_perf > max_cap_perf) {
1131 hybrid_max_perf_cpu = cpu;
1132 hybrid_set_capacity_of_cpus();
1133 goto unlock;
1134 }
1135
1136 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */
1137 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) {
1138 hybrid_update_cpu_capacity_scaling();
1139 goto unlock;
1140 }
1141
1142 hybrid_set_cpu_capacity(cpu);
1143
1144unlock:
1145 mutex_unlock(&hybrid_capacity_lock);
1146}
1147
1148static void intel_pstate_hwp_set(unsigned int cpu)
1149{
1150 struct cpudata *cpu_data = all_cpu_data[cpu];
1151 int max, min;
1152 u64 value;
1153 s16 epp;
1154
1155 max = cpu_data->max_perf_ratio;
1156 min = cpu_data->min_perf_ratio;
1157
1158 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
1159 min = max;
1160
1161 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
1162
1163 value &= ~HWP_MIN_PERF(~0L);
1164 value |= HWP_MIN_PERF(min);
1165
1166 value &= ~HWP_MAX_PERF(~0L);
1167 value |= HWP_MAX_PERF(max);
1168
1169 if (cpu_data->epp_policy == cpu_data->policy)
1170 goto skip_epp;
1171
1172 cpu_data->epp_policy = cpu_data->policy;
1173
1174 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
1175 epp = intel_pstate_get_epp(cpu_data, value);
1176 cpu_data->epp_powersave = epp;
1177 /* If EPP read was failed, then don't try to write */
1178 if (epp < 0)
1179 goto skip_epp;
1180
1181 epp = 0;
1182 } else {
1183 /* skip setting EPP, when saved value is invalid */
1184 if (cpu_data->epp_powersave < 0)
1185 goto skip_epp;
1186
1187 /*
1188 * No need to restore EPP when it is not zero. This
1189 * means:
1190 * - Policy is not changed
1191 * - user has manually changed
1192 * - Error reading EPB
1193 */
1194 epp = intel_pstate_get_epp(cpu_data, value);
1195 if (epp)
1196 goto skip_epp;
1197
1198 epp = cpu_data->epp_powersave;
1199 }
1200 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1201 value &= ~GENMASK_ULL(31, 24);
1202 value |= (u64)epp << 24;
1203 } else {
1204 intel_pstate_set_epb(cpu, epp);
1205 }
1206skip_epp:
1207 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1208 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1209}
1210
1211static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1212
1213static void intel_pstate_hwp_offline(struct cpudata *cpu)
1214{
1215 u64 value = READ_ONCE(cpu->hwp_req_cached);
1216 int min_perf;
1217
1218 intel_pstate_disable_hwp_interrupt(cpu);
1219
1220 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1221 /*
1222 * In case the EPP has been set to "performance" by the
1223 * active mode "performance" scaling algorithm, replace that
1224 * temporary value with the cached EPP one.
1225 */
1226 value &= ~GENMASK_ULL(31, 24);
1227 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1228 /*
1229 * However, make sure that EPP will be set to "performance" when
1230 * the CPU is brought back online again and the "performance"
1231 * scaling algorithm is still in effect.
1232 */
1233 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1234 }
1235
1236 /*
1237 * Clear the desired perf field in the cached HWP request value to
1238 * prevent nonzero desired values from being leaked into the active
1239 * mode.
1240 */
1241 value &= ~HWP_DESIRED_PERF(~0L);
1242 WRITE_ONCE(cpu->hwp_req_cached, value);
1243
1244 value &= ~GENMASK_ULL(31, 0);
1245 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1246
1247 /* Set hwp_max = hwp_min */
1248 value |= HWP_MAX_PERF(min_perf);
1249 value |= HWP_MIN_PERF(min_perf);
1250
1251 /* Set EPP to min */
1252 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1253 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1254
1255 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1256
1257 mutex_lock(&hybrid_capacity_lock);
1258
1259 if (!hybrid_max_perf_cpu) {
1260 mutex_unlock(&hybrid_capacity_lock);
1261
1262 return;
1263 }
1264
1265 if (hybrid_max_perf_cpu == cpu)
1266 hybrid_update_cpu_capacity_scaling();
1267
1268 mutex_unlock(&hybrid_capacity_lock);
1269
1270 /* Reset the capacity of the CPU going offline to the initial value. */
1271 hybrid_clear_cpu_capacity(cpu->cpu);
1272}
1273
1274#define POWER_CTL_EE_ENABLE 1
1275#define POWER_CTL_EE_DISABLE 2
1276
1277static int power_ctl_ee_state;
1278
1279static void set_power_ctl_ee_state(bool input)
1280{
1281 u64 power_ctl;
1282
1283 mutex_lock(&intel_pstate_driver_lock);
1284 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1285 if (input) {
1286 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1287 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1288 } else {
1289 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1290 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1291 }
1292 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1293 mutex_unlock(&intel_pstate_driver_lock);
1294}
1295
1296static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1297
1298static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1299{
1300 intel_pstate_hwp_enable(cpu);
1301 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1302}
1303
1304static int intel_pstate_suspend(struct cpufreq_policy *policy)
1305{
1306 struct cpudata *cpu = all_cpu_data[policy->cpu];
1307
1308 pr_debug("CPU %d suspending\n", cpu->cpu);
1309
1310 cpu->suspended = true;
1311
1312 /* disable HWP interrupt and cancel any pending work */
1313 intel_pstate_disable_hwp_interrupt(cpu);
1314
1315 return 0;
1316}
1317
1318static int intel_pstate_resume(struct cpufreq_policy *policy)
1319{
1320 struct cpudata *cpu = all_cpu_data[policy->cpu];
1321
1322 pr_debug("CPU %d resuming\n", cpu->cpu);
1323
1324 /* Only restore if the system default is changed */
1325 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1326 set_power_ctl_ee_state(true);
1327 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1328 set_power_ctl_ee_state(false);
1329
1330 if (cpu->suspended && hwp_active) {
1331 mutex_lock(&intel_pstate_limits_lock);
1332
1333 /* Re-enable HWP, because "online" has not done that. */
1334 intel_pstate_hwp_reenable(cpu);
1335
1336 mutex_unlock(&intel_pstate_limits_lock);
1337 }
1338
1339 cpu->suspended = false;
1340
1341 return 0;
1342}
1343
1344static void intel_pstate_update_policies(void)
1345{
1346 int cpu;
1347
1348 for_each_possible_cpu(cpu)
1349 cpufreq_update_policy(cpu);
1350}
1351
1352static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1353 struct cpufreq_policy *policy)
1354{
1355 if (hwp_active)
1356 intel_pstate_get_hwp_cap(cpudata);
1357
1358 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
1359 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1360
1361 refresh_frequency_limits(policy);
1362}
1363
1364static void intel_pstate_update_limits(unsigned int cpu)
1365{
1366 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1367 struct cpudata *cpudata;
1368
1369 if (!policy)
1370 return;
1371
1372 cpudata = all_cpu_data[cpu];
1373
1374 __intel_pstate_update_max_freq(cpudata, policy);
1375
1376 /* Prevent the driver from being unregistered now. */
1377 mutex_lock(&intel_pstate_driver_lock);
1378
1379 cpufreq_cpu_release(policy);
1380
1381 hybrid_update_capacity(cpudata);
1382
1383 mutex_unlock(&intel_pstate_driver_lock);
1384}
1385
1386static void intel_pstate_update_limits_for_all(void)
1387{
1388 int cpu;
1389
1390 for_each_possible_cpu(cpu) {
1391 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1392
1393 if (!policy)
1394 continue;
1395
1396 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1397
1398 cpufreq_cpu_release(policy);
1399 }
1400
1401 mutex_lock(&hybrid_capacity_lock);
1402
1403 if (hybrid_max_perf_cpu)
1404 __hybrid_refresh_cpu_capacity_scaling();
1405
1406 mutex_unlock(&hybrid_capacity_lock);
1407}
1408
1409/************************** sysfs begin ************************/
1410#define show_one(file_name, object) \
1411 static ssize_t show_##file_name \
1412 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1413 { \
1414 return sprintf(buf, "%u\n", global.object); \
1415 }
1416
1417static ssize_t intel_pstate_show_status(char *buf);
1418static int intel_pstate_update_status(const char *buf, size_t size);
1419
1420static ssize_t show_status(struct kobject *kobj,
1421 struct kobj_attribute *attr, char *buf)
1422{
1423 ssize_t ret;
1424
1425 mutex_lock(&intel_pstate_driver_lock);
1426 ret = intel_pstate_show_status(buf);
1427 mutex_unlock(&intel_pstate_driver_lock);
1428
1429 return ret;
1430}
1431
1432static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1433 const char *buf, size_t count)
1434{
1435 char *p = memchr(buf, '\n', count);
1436 int ret;
1437
1438 mutex_lock(&intel_pstate_driver_lock);
1439 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1440 mutex_unlock(&intel_pstate_driver_lock);
1441
1442 return ret < 0 ? ret : count;
1443}
1444
1445static ssize_t show_turbo_pct(struct kobject *kobj,
1446 struct kobj_attribute *attr, char *buf)
1447{
1448 struct cpudata *cpu;
1449 int total, no_turbo, turbo_pct;
1450 uint32_t turbo_fp;
1451
1452 mutex_lock(&intel_pstate_driver_lock);
1453
1454 if (!intel_pstate_driver) {
1455 mutex_unlock(&intel_pstate_driver_lock);
1456 return -EAGAIN;
1457 }
1458
1459 cpu = all_cpu_data[0];
1460
1461 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1462 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1463 turbo_fp = div_fp(no_turbo, total);
1464 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1465
1466 mutex_unlock(&intel_pstate_driver_lock);
1467
1468 return sprintf(buf, "%u\n", turbo_pct);
1469}
1470
1471static ssize_t show_num_pstates(struct kobject *kobj,
1472 struct kobj_attribute *attr, char *buf)
1473{
1474 struct cpudata *cpu;
1475 int total;
1476
1477 mutex_lock(&intel_pstate_driver_lock);
1478
1479 if (!intel_pstate_driver) {
1480 mutex_unlock(&intel_pstate_driver_lock);
1481 return -EAGAIN;
1482 }
1483
1484 cpu = all_cpu_data[0];
1485 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1486
1487 mutex_unlock(&intel_pstate_driver_lock);
1488
1489 return sprintf(buf, "%u\n", total);
1490}
1491
1492static ssize_t show_no_turbo(struct kobject *kobj,
1493 struct kobj_attribute *attr, char *buf)
1494{
1495 ssize_t ret;
1496
1497 mutex_lock(&intel_pstate_driver_lock);
1498
1499 if (!intel_pstate_driver) {
1500 mutex_unlock(&intel_pstate_driver_lock);
1501 return -EAGAIN;
1502 }
1503
1504 ret = sprintf(buf, "%u\n", global.no_turbo);
1505
1506 mutex_unlock(&intel_pstate_driver_lock);
1507
1508 return ret;
1509}
1510
1511static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1512 const char *buf, size_t count)
1513{
1514 unsigned int input;
1515 bool no_turbo;
1516
1517 if (sscanf(buf, "%u", &input) != 1)
1518 return -EINVAL;
1519
1520 mutex_lock(&intel_pstate_driver_lock);
1521
1522 if (!intel_pstate_driver) {
1523 count = -EAGAIN;
1524 goto unlock_driver;
1525 }
1526
1527 no_turbo = !!clamp_t(int, input, 0, 1);
1528
1529 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled());
1530 if (global.turbo_disabled && !no_turbo) {
1531 pr_notice("Turbo disabled by BIOS or unavailable on processor\n");
1532 count = -EPERM;
1533 if (global.no_turbo)
1534 goto unlock_driver;
1535 else
1536 no_turbo = 1;
1537 }
1538
1539 if (no_turbo == global.no_turbo) {
1540 goto unlock_driver;
1541 }
1542
1543 WRITE_ONCE(global.no_turbo, no_turbo);
1544
1545 mutex_lock(&intel_pstate_limits_lock);
1546
1547 if (no_turbo) {
1548 struct cpudata *cpu = all_cpu_data[0];
1549 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1550
1551 /* Squash the global minimum into the permitted range. */
1552 if (global.min_perf_pct > pct)
1553 global.min_perf_pct = pct;
1554 }
1555
1556 mutex_unlock(&intel_pstate_limits_lock);
1557
1558 intel_pstate_update_limits_for_all();
1559 arch_set_max_freq_ratio(no_turbo);
1560
1561unlock_driver:
1562 mutex_unlock(&intel_pstate_driver_lock);
1563
1564 return count;
1565}
1566
1567static void update_qos_request(enum freq_qos_req_type type)
1568{
1569 struct freq_qos_request *req;
1570 struct cpufreq_policy *policy;
1571 int i;
1572
1573 for_each_possible_cpu(i) {
1574 struct cpudata *cpu = all_cpu_data[i];
1575 unsigned int freq, perf_pct;
1576
1577 policy = cpufreq_cpu_get(i);
1578 if (!policy)
1579 continue;
1580
1581 req = policy->driver_data;
1582 cpufreq_cpu_put(policy);
1583
1584 if (!req)
1585 continue;
1586
1587 if (hwp_active)
1588 intel_pstate_get_hwp_cap(cpu);
1589
1590 if (type == FREQ_QOS_MIN) {
1591 perf_pct = global.min_perf_pct;
1592 } else {
1593 req++;
1594 perf_pct = global.max_perf_pct;
1595 }
1596
1597 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1598
1599 if (freq_qos_update_request(req, freq) < 0)
1600 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1601 }
1602}
1603
1604static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1605 const char *buf, size_t count)
1606{
1607 unsigned int input;
1608 int ret;
1609
1610 ret = sscanf(buf, "%u", &input);
1611 if (ret != 1)
1612 return -EINVAL;
1613
1614 mutex_lock(&intel_pstate_driver_lock);
1615
1616 if (!intel_pstate_driver) {
1617 mutex_unlock(&intel_pstate_driver_lock);
1618 return -EAGAIN;
1619 }
1620
1621 mutex_lock(&intel_pstate_limits_lock);
1622
1623 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1624
1625 mutex_unlock(&intel_pstate_limits_lock);
1626
1627 if (intel_pstate_driver == &intel_pstate)
1628 intel_pstate_update_policies();
1629 else
1630 update_qos_request(FREQ_QOS_MAX);
1631
1632 mutex_unlock(&intel_pstate_driver_lock);
1633
1634 return count;
1635}
1636
1637static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1638 const char *buf, size_t count)
1639{
1640 unsigned int input;
1641 int ret;
1642
1643 ret = sscanf(buf, "%u", &input);
1644 if (ret != 1)
1645 return -EINVAL;
1646
1647 mutex_lock(&intel_pstate_driver_lock);
1648
1649 if (!intel_pstate_driver) {
1650 mutex_unlock(&intel_pstate_driver_lock);
1651 return -EAGAIN;
1652 }
1653
1654 mutex_lock(&intel_pstate_limits_lock);
1655
1656 global.min_perf_pct = clamp_t(int, input,
1657 min_perf_pct_min(), global.max_perf_pct);
1658
1659 mutex_unlock(&intel_pstate_limits_lock);
1660
1661 if (intel_pstate_driver == &intel_pstate)
1662 intel_pstate_update_policies();
1663 else
1664 update_qos_request(FREQ_QOS_MIN);
1665
1666 mutex_unlock(&intel_pstate_driver_lock);
1667
1668 return count;
1669}
1670
1671static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1672 struct kobj_attribute *attr, char *buf)
1673{
1674 return sprintf(buf, "%u\n", hwp_boost);
1675}
1676
1677static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1678 struct kobj_attribute *b,
1679 const char *buf, size_t count)
1680{
1681 unsigned int input;
1682 int ret;
1683
1684 ret = kstrtouint(buf, 10, &input);
1685 if (ret)
1686 return ret;
1687
1688 mutex_lock(&intel_pstate_driver_lock);
1689 hwp_boost = !!input;
1690 intel_pstate_update_policies();
1691 mutex_unlock(&intel_pstate_driver_lock);
1692
1693 return count;
1694}
1695
1696static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1697 char *buf)
1698{
1699 u64 power_ctl;
1700 int enable;
1701
1702 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1703 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1704 return sprintf(buf, "%d\n", !enable);
1705}
1706
1707static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1708 const char *buf, size_t count)
1709{
1710 bool input;
1711 int ret;
1712
1713 ret = kstrtobool(buf, &input);
1714 if (ret)
1715 return ret;
1716
1717 set_power_ctl_ee_state(input);
1718
1719 return count;
1720}
1721
1722show_one(max_perf_pct, max_perf_pct);
1723show_one(min_perf_pct, min_perf_pct);
1724
1725define_one_global_rw(status);
1726define_one_global_rw(no_turbo);
1727define_one_global_rw(max_perf_pct);
1728define_one_global_rw(min_perf_pct);
1729define_one_global_ro(turbo_pct);
1730define_one_global_ro(num_pstates);
1731define_one_global_rw(hwp_dynamic_boost);
1732define_one_global_rw(energy_efficiency);
1733
1734static struct attribute *intel_pstate_attributes[] = {
1735 &status.attr,
1736 &no_turbo.attr,
1737 NULL
1738};
1739
1740static const struct attribute_group intel_pstate_attr_group = {
1741 .attrs = intel_pstate_attributes,
1742};
1743
1744static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1745
1746static struct kobject *intel_pstate_kobject;
1747
1748static void __init intel_pstate_sysfs_expose_params(void)
1749{
1750 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1751 int rc;
1752
1753 if (dev_root) {
1754 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1755 put_device(dev_root);
1756 }
1757 if (WARN_ON(!intel_pstate_kobject))
1758 return;
1759
1760 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1761 if (WARN_ON(rc))
1762 return;
1763
1764 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1765 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1766 WARN_ON(rc);
1767
1768 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1769 WARN_ON(rc);
1770 }
1771
1772 /*
1773 * If per cpu limits are enforced there are no global limits, so
1774 * return without creating max/min_perf_pct attributes
1775 */
1776 if (per_cpu_limits)
1777 return;
1778
1779 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1780 WARN_ON(rc);
1781
1782 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1783 WARN_ON(rc);
1784
1785 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1786 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1787 WARN_ON(rc);
1788 }
1789}
1790
1791static void __init intel_pstate_sysfs_remove(void)
1792{
1793 if (!intel_pstate_kobject)
1794 return;
1795
1796 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1797
1798 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1799 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1800 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1801 }
1802
1803 if (!per_cpu_limits) {
1804 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1805 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1806
1807 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1808 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1809 }
1810
1811 kobject_put(intel_pstate_kobject);
1812}
1813
1814static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1815{
1816 int rc;
1817
1818 if (!hwp_active)
1819 return;
1820
1821 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1822 WARN_ON_ONCE(rc);
1823}
1824
1825static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1826{
1827 if (!hwp_active)
1828 return;
1829
1830 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1831}
1832
1833/************************** sysfs end ************************/
1834
1835static void intel_pstate_notify_work(struct work_struct *work)
1836{
1837 struct cpudata *cpudata =
1838 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1839 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1840
1841 if (policy) {
1842 __intel_pstate_update_max_freq(cpudata, policy);
1843
1844 cpufreq_cpu_release(policy);
1845
1846 /*
1847 * The driver will not be unregistered while this function is
1848 * running, so update the capacity without acquiring the driver
1849 * lock.
1850 */
1851 hybrid_update_capacity(cpudata);
1852 }
1853
1854 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1855}
1856
1857static DEFINE_RAW_SPINLOCK(hwp_notify_lock);
1858static cpumask_t hwp_intr_enable_mask;
1859
1860#define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0)
1861#define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3)
1862
1863void notify_hwp_interrupt(void)
1864{
1865 unsigned int this_cpu = smp_processor_id();
1866 u64 value, status_mask;
1867 unsigned long flags;
1868
1869 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1870 return;
1871
1872 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
1873 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1874 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
1875
1876 rdmsrl_safe(MSR_HWP_STATUS, &value);
1877 if (!(value & status_mask))
1878 return;
1879
1880 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1881
1882 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1883 goto ack_intr;
1884
1885 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work,
1886 msecs_to_jiffies(10));
1887
1888 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1889
1890 return;
1891
1892ack_intr:
1893 wrmsrl_safe(MSR_HWP_STATUS, 0);
1894 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1895}
1896
1897static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1898{
1899 bool cancel_work;
1900
1901 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1902 return;
1903
1904 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1905 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1906
1907 raw_spin_lock_irq(&hwp_notify_lock);
1908 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1909 raw_spin_unlock_irq(&hwp_notify_lock);
1910
1911 if (cancel_work)
1912 cancel_delayed_work_sync(&cpudata->hwp_notify_work);
1913}
1914
1915#define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
1916#define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2)
1917
1918static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1919{
1920 /* Enable HWP notification interrupt for performance change */
1921 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1922 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
1923
1924 raw_spin_lock_irq(&hwp_notify_lock);
1925 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1926 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1927 raw_spin_unlock_irq(&hwp_notify_lock);
1928
1929 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1930 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
1931
1932 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1933 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
1934 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1935 }
1936}
1937
1938static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1939{
1940 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1941
1942 /*
1943 * If the EPP is set by firmware, which means that firmware enabled HWP
1944 * - Is equal or less than 0x80 (default balance_perf EPP)
1945 * - But less performance oriented than performance EPP
1946 * then use this as new balance_perf EPP.
1947 */
1948 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1949 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1950 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1951 return;
1952 }
1953
1954 /*
1955 * If this CPU gen doesn't call for change in balance_perf
1956 * EPP return.
1957 */
1958 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1959 return;
1960
1961 /*
1962 * Use hard coded value per gen to update the balance_perf
1963 * and default EPP.
1964 */
1965 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1966 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1967}
1968
1969static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1970{
1971 /* First disable HWP notification interrupt till we activate again */
1972 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1973 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1974
1975 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1976
1977 intel_pstate_enable_hwp_interrupt(cpudata);
1978
1979 if (cpudata->epp_default >= 0)
1980 return;
1981
1982 intel_pstate_update_epp_defaults(cpudata);
1983}
1984
1985static int atom_get_min_pstate(int not_used)
1986{
1987 u64 value;
1988
1989 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1990 return (value >> 8) & 0x7F;
1991}
1992
1993static int atom_get_max_pstate(int not_used)
1994{
1995 u64 value;
1996
1997 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1998 return (value >> 16) & 0x7F;
1999}
2000
2001static int atom_get_turbo_pstate(int not_used)
2002{
2003 u64 value;
2004
2005 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
2006 return value & 0x7F;
2007}
2008
2009static u64 atom_get_val(struct cpudata *cpudata, int pstate)
2010{
2011 u64 val;
2012 int32_t vid_fp;
2013 u32 vid;
2014
2015 val = (u64)pstate << 8;
2016 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2017 val |= (u64)1 << 32;
2018
2019 vid_fp = cpudata->vid.min + mul_fp(
2020 int_tofp(pstate - cpudata->pstate.min_pstate),
2021 cpudata->vid.ratio);
2022
2023 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
2024 vid = ceiling_fp(vid_fp);
2025
2026 if (pstate > cpudata->pstate.max_pstate)
2027 vid = cpudata->vid.turbo;
2028
2029 return val | vid;
2030}
2031
2032static int silvermont_get_scaling(void)
2033{
2034 u64 value;
2035 int i;
2036 /* Defined in Table 35-6 from SDM (Sept 2015) */
2037 static int silvermont_freq_table[] = {
2038 83300, 100000, 133300, 116700, 80000};
2039
2040 rdmsrl(MSR_FSB_FREQ, value);
2041 i = value & 0x7;
2042 WARN_ON(i > 4);
2043
2044 return silvermont_freq_table[i];
2045}
2046
2047static int airmont_get_scaling(void)
2048{
2049 u64 value;
2050 int i;
2051 /* Defined in Table 35-10 from SDM (Sept 2015) */
2052 static int airmont_freq_table[] = {
2053 83300, 100000, 133300, 116700, 80000,
2054 93300, 90000, 88900, 87500};
2055
2056 rdmsrl(MSR_FSB_FREQ, value);
2057 i = value & 0xF;
2058 WARN_ON(i > 8);
2059
2060 return airmont_freq_table[i];
2061}
2062
2063static void atom_get_vid(struct cpudata *cpudata)
2064{
2065 u64 value;
2066
2067 rdmsrl(MSR_ATOM_CORE_VIDS, value);
2068 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
2069 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
2070 cpudata->vid.ratio = div_fp(
2071 cpudata->vid.max - cpudata->vid.min,
2072 int_tofp(cpudata->pstate.max_pstate -
2073 cpudata->pstate.min_pstate));
2074
2075 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
2076 cpudata->vid.turbo = value & 0x7f;
2077}
2078
2079static int core_get_min_pstate(int cpu)
2080{
2081 u64 value;
2082
2083 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2084 return (value >> 40) & 0xFF;
2085}
2086
2087static int core_get_max_pstate_physical(int cpu)
2088{
2089 u64 value;
2090
2091 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2092 return (value >> 8) & 0xFF;
2093}
2094
2095static int core_get_tdp_ratio(int cpu, u64 plat_info)
2096{
2097 /* Check how many TDP levels present */
2098 if (plat_info & 0x600000000) {
2099 u64 tdp_ctrl;
2100 u64 tdp_ratio;
2101 int tdp_msr;
2102 int err;
2103
2104 /* Get the TDP level (0, 1, 2) to get ratios */
2105 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
2106 if (err)
2107 return err;
2108
2109 /* TDP MSR are continuous starting at 0x648 */
2110 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
2111 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
2112 if (err)
2113 return err;
2114
2115 /* For level 1 and 2, bits[23:16] contain the ratio */
2116 if (tdp_ctrl & 0x03)
2117 tdp_ratio >>= 16;
2118
2119 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
2120 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
2121
2122 return (int)tdp_ratio;
2123 }
2124
2125 return -ENXIO;
2126}
2127
2128static int core_get_max_pstate(int cpu)
2129{
2130 u64 tar;
2131 u64 plat_info;
2132 int max_pstate;
2133 int tdp_ratio;
2134 int err;
2135
2136 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
2137 max_pstate = (plat_info >> 8) & 0xFF;
2138
2139 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
2140 if (tdp_ratio <= 0)
2141 return max_pstate;
2142
2143 if (hwp_active) {
2144 /* Turbo activation ratio is not used on HWP platforms */
2145 return tdp_ratio;
2146 }
2147
2148 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
2149 if (!err) {
2150 int tar_levels;
2151
2152 /* Do some sanity checking for safety */
2153 tar_levels = tar & 0xff;
2154 if (tdp_ratio - 1 == tar_levels) {
2155 max_pstate = tar_levels;
2156 pr_debug("max_pstate=TAC %x\n", max_pstate);
2157 }
2158 }
2159
2160 return max_pstate;
2161}
2162
2163static int core_get_turbo_pstate(int cpu)
2164{
2165 u64 value;
2166 int nont, ret;
2167
2168 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2169 nont = core_get_max_pstate(cpu);
2170 ret = (value) & 255;
2171 if (ret <= nont)
2172 ret = nont;
2173 return ret;
2174}
2175
2176static u64 core_get_val(struct cpudata *cpudata, int pstate)
2177{
2178 u64 val;
2179
2180 val = (u64)pstate << 8;
2181 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2182 val |= (u64)1 << 32;
2183
2184 return val;
2185}
2186
2187static int knl_get_aperf_mperf_shift(void)
2188{
2189 return 10;
2190}
2191
2192static int knl_get_turbo_pstate(int cpu)
2193{
2194 u64 value;
2195 int nont, ret;
2196
2197 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2198 nont = core_get_max_pstate(cpu);
2199 ret = (((value) >> 8) & 0xFF);
2200 if (ret <= nont)
2201 ret = nont;
2202 return ret;
2203}
2204
2205static void hybrid_get_type(void *data)
2206{
2207 u8 *cpu_type = data;
2208
2209 *cpu_type = get_this_hybrid_cpu_type();
2210}
2211
2212static int hwp_get_cpu_scaling(int cpu)
2213{
2214 u8 cpu_type = 0;
2215
2216 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
2217 /* P-cores have a smaller perf level-to-freqency scaling factor. */
2218 if (cpu_type == 0x40)
2219 return hybrid_scaling_factor;
2220
2221 /* Use default core scaling for E-cores */
2222 if (cpu_type == 0x20)
2223 return core_get_scaling();
2224
2225 /*
2226 * If reached here, this system is either non-hybrid (like Tiger
2227 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2228 * no E cores (in which case CPUID for hybrid support is 0).
2229 *
2230 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2231 * so the default core scaling will be used for them.
2232 */
2233 return intel_pstate_cppc_get_scaling(cpu);
2234}
2235
2236static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2237{
2238 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2239 cpu->pstate.current_pstate = pstate;
2240 /*
2241 * Generally, there is no guarantee that this code will always run on
2242 * the CPU being updated, so force the register update to run on the
2243 * right CPU.
2244 */
2245 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2246 pstate_funcs.get_val(cpu, pstate));
2247}
2248
2249static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2250{
2251 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2252}
2253
2254static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2255{
2256 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2257 int perf_ctl_scaling = pstate_funcs.get_scaling();
2258
2259 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2260 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2261 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2262
2263 if (hwp_active && !hwp_mode_bdw) {
2264 __intel_pstate_get_hwp_cap(cpu);
2265
2266 if (pstate_funcs.get_cpu_scaling) {
2267 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2268 if (cpu->pstate.scaling != perf_ctl_scaling) {
2269 intel_pstate_hybrid_hwp_adjust(cpu);
2270 hwp_is_hybrid = true;
2271 }
2272 } else {
2273 cpu->pstate.scaling = perf_ctl_scaling;
2274 }
2275 /*
2276 * If the CPU is going online for the first time and it was
2277 * offline initially, asym capacity scaling needs to be updated.
2278 */
2279 hybrid_update_capacity(cpu);
2280 } else {
2281 cpu->pstate.scaling = perf_ctl_scaling;
2282 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2283 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2284 }
2285
2286 if (cpu->pstate.scaling == perf_ctl_scaling) {
2287 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2288 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2289 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2290 }
2291
2292 if (pstate_funcs.get_aperf_mperf_shift)
2293 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2294
2295 if (pstate_funcs.get_vid)
2296 pstate_funcs.get_vid(cpu);
2297
2298 intel_pstate_set_min_pstate(cpu);
2299}
2300
2301/*
2302 * Long hold time will keep high perf limits for long time,
2303 * which negatively impacts perf/watt for some workloads,
2304 * like specpower. 3ms is based on experiements on some
2305 * workoads.
2306 */
2307static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2308
2309static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2310{
2311 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2312 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2313 u32 max_limit = (hwp_req & 0xff00) >> 8;
2314 u32 min_limit = (hwp_req & 0xff);
2315 u32 boost_level1;
2316
2317 /*
2318 * Cases to consider (User changes via sysfs or boot time):
2319 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2320 * No boost, return.
2321 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2322 * Should result in one level boost only for P0.
2323 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2324 * Should result in two level boost:
2325 * (min + p1)/2 and P1.
2326 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2327 * Should result in three level boost:
2328 * (min + p1)/2, P1 and P0.
2329 */
2330
2331 /* If max and min are equal or already at max, nothing to boost */
2332 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2333 return;
2334
2335 if (!cpu->hwp_boost_min)
2336 cpu->hwp_boost_min = min_limit;
2337
2338 /* level at half way mark between min and guranteed */
2339 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2340
2341 if (cpu->hwp_boost_min < boost_level1)
2342 cpu->hwp_boost_min = boost_level1;
2343 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2344 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2345 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2346 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2347 cpu->hwp_boost_min = max_limit;
2348 else
2349 return;
2350
2351 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2352 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2353 cpu->last_update = cpu->sample.time;
2354}
2355
2356static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2357{
2358 if (cpu->hwp_boost_min) {
2359 bool expired;
2360
2361 /* Check if we are idle for hold time to boost down */
2362 expired = time_after64(cpu->sample.time, cpu->last_update +
2363 hwp_boost_hold_time_ns);
2364 if (expired) {
2365 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2366 cpu->hwp_boost_min = 0;
2367 }
2368 }
2369 cpu->last_update = cpu->sample.time;
2370}
2371
2372static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2373 u64 time)
2374{
2375 cpu->sample.time = time;
2376
2377 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2378 bool do_io = false;
2379
2380 cpu->sched_flags = 0;
2381 /*
2382 * Set iowait_boost flag and update time. Since IO WAIT flag
2383 * is set all the time, we can't just conclude that there is
2384 * some IO bound activity is scheduled on this CPU with just
2385 * one occurrence. If we receive at least two in two
2386 * consecutive ticks, then we treat as boost candidate.
2387 */
2388 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2389 do_io = true;
2390
2391 cpu->last_io_update = time;
2392
2393 if (do_io)
2394 intel_pstate_hwp_boost_up(cpu);
2395
2396 } else {
2397 intel_pstate_hwp_boost_down(cpu);
2398 }
2399}
2400
2401static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2402 u64 time, unsigned int flags)
2403{
2404 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2405
2406 cpu->sched_flags |= flags;
2407
2408 if (smp_processor_id() == cpu->cpu)
2409 intel_pstate_update_util_hwp_local(cpu, time);
2410}
2411
2412static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2413{
2414 struct sample *sample = &cpu->sample;
2415
2416 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2417}
2418
2419static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2420{
2421 u64 aperf, mperf;
2422 unsigned long flags;
2423 u64 tsc;
2424
2425 local_irq_save(flags);
2426 rdmsrl(MSR_IA32_APERF, aperf);
2427 rdmsrl(MSR_IA32_MPERF, mperf);
2428 tsc = rdtsc();
2429 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2430 local_irq_restore(flags);
2431 return false;
2432 }
2433 local_irq_restore(flags);
2434
2435 cpu->last_sample_time = cpu->sample.time;
2436 cpu->sample.time = time;
2437 cpu->sample.aperf = aperf;
2438 cpu->sample.mperf = mperf;
2439 cpu->sample.tsc = tsc;
2440 cpu->sample.aperf -= cpu->prev_aperf;
2441 cpu->sample.mperf -= cpu->prev_mperf;
2442 cpu->sample.tsc -= cpu->prev_tsc;
2443
2444 cpu->prev_aperf = aperf;
2445 cpu->prev_mperf = mperf;
2446 cpu->prev_tsc = tsc;
2447 /*
2448 * First time this function is invoked in a given cycle, all of the
2449 * previous sample data fields are equal to zero or stale and they must
2450 * be populated with meaningful numbers for things to work, so assume
2451 * that sample.time will always be reset before setting the utilization
2452 * update hook and make the caller skip the sample then.
2453 */
2454 if (cpu->last_sample_time) {
2455 intel_pstate_calc_avg_perf(cpu);
2456 return true;
2457 }
2458 return false;
2459}
2460
2461static inline int32_t get_avg_frequency(struct cpudata *cpu)
2462{
2463 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2464}
2465
2466static inline int32_t get_avg_pstate(struct cpudata *cpu)
2467{
2468 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2469 cpu->sample.core_avg_perf);
2470}
2471
2472static inline int32_t get_target_pstate(struct cpudata *cpu)
2473{
2474 struct sample *sample = &cpu->sample;
2475 int32_t busy_frac;
2476 int target, avg_pstate;
2477
2478 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2479 sample->tsc);
2480
2481 if (busy_frac < cpu->iowait_boost)
2482 busy_frac = cpu->iowait_boost;
2483
2484 sample->busy_scaled = busy_frac * 100;
2485
2486 target = READ_ONCE(global.no_turbo) ?
2487 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2488 target += target >> 2;
2489 target = mul_fp(target, busy_frac);
2490 if (target < cpu->pstate.min_pstate)
2491 target = cpu->pstate.min_pstate;
2492
2493 /*
2494 * If the average P-state during the previous cycle was higher than the
2495 * current target, add 50% of the difference to the target to reduce
2496 * possible performance oscillations and offset possible performance
2497 * loss related to moving the workload from one CPU to another within
2498 * a package/module.
2499 */
2500 avg_pstate = get_avg_pstate(cpu);
2501 if (avg_pstate > target)
2502 target += (avg_pstate - target) >> 1;
2503
2504 return target;
2505}
2506
2507static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2508{
2509 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2510 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2511
2512 return clamp_t(int, pstate, min_pstate, max_pstate);
2513}
2514
2515static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2516{
2517 if (pstate == cpu->pstate.current_pstate)
2518 return;
2519
2520 cpu->pstate.current_pstate = pstate;
2521 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2522}
2523
2524static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2525{
2526 int from = cpu->pstate.current_pstate;
2527 struct sample *sample;
2528 int target_pstate;
2529
2530 target_pstate = get_target_pstate(cpu);
2531 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2532 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2533 intel_pstate_update_pstate(cpu, target_pstate);
2534
2535 sample = &cpu->sample;
2536 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2537 fp_toint(sample->busy_scaled),
2538 from,
2539 cpu->pstate.current_pstate,
2540 sample->mperf,
2541 sample->aperf,
2542 sample->tsc,
2543 get_avg_frequency(cpu),
2544 fp_toint(cpu->iowait_boost * 100));
2545}
2546
2547static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2548 unsigned int flags)
2549{
2550 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2551 u64 delta_ns;
2552
2553 /* Don't allow remote callbacks */
2554 if (smp_processor_id() != cpu->cpu)
2555 return;
2556
2557 delta_ns = time - cpu->last_update;
2558 if (flags & SCHED_CPUFREQ_IOWAIT) {
2559 /* Start over if the CPU may have been idle. */
2560 if (delta_ns > TICK_NSEC) {
2561 cpu->iowait_boost = ONE_EIGHTH_FP;
2562 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2563 cpu->iowait_boost <<= 1;
2564 if (cpu->iowait_boost > int_tofp(1))
2565 cpu->iowait_boost = int_tofp(1);
2566 } else {
2567 cpu->iowait_boost = ONE_EIGHTH_FP;
2568 }
2569 } else if (cpu->iowait_boost) {
2570 /* Clear iowait_boost if the CPU may have been idle. */
2571 if (delta_ns > TICK_NSEC)
2572 cpu->iowait_boost = 0;
2573 else
2574 cpu->iowait_boost >>= 1;
2575 }
2576 cpu->last_update = time;
2577 delta_ns = time - cpu->sample.time;
2578 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2579 return;
2580
2581 if (intel_pstate_sample(cpu, time))
2582 intel_pstate_adjust_pstate(cpu);
2583}
2584
2585static struct pstate_funcs core_funcs = {
2586 .get_max = core_get_max_pstate,
2587 .get_max_physical = core_get_max_pstate_physical,
2588 .get_min = core_get_min_pstate,
2589 .get_turbo = core_get_turbo_pstate,
2590 .get_scaling = core_get_scaling,
2591 .get_val = core_get_val,
2592};
2593
2594static const struct pstate_funcs silvermont_funcs = {
2595 .get_max = atom_get_max_pstate,
2596 .get_max_physical = atom_get_max_pstate,
2597 .get_min = atom_get_min_pstate,
2598 .get_turbo = atom_get_turbo_pstate,
2599 .get_val = atom_get_val,
2600 .get_scaling = silvermont_get_scaling,
2601 .get_vid = atom_get_vid,
2602};
2603
2604static const struct pstate_funcs airmont_funcs = {
2605 .get_max = atom_get_max_pstate,
2606 .get_max_physical = atom_get_max_pstate,
2607 .get_min = atom_get_min_pstate,
2608 .get_turbo = atom_get_turbo_pstate,
2609 .get_val = atom_get_val,
2610 .get_scaling = airmont_get_scaling,
2611 .get_vid = atom_get_vid,
2612};
2613
2614static const struct pstate_funcs knl_funcs = {
2615 .get_max = core_get_max_pstate,
2616 .get_max_physical = core_get_max_pstate_physical,
2617 .get_min = core_get_min_pstate,
2618 .get_turbo = knl_get_turbo_pstate,
2619 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2620 .get_scaling = core_get_scaling,
2621 .get_val = core_get_val,
2622};
2623
2624#define X86_MATCH(vfm, policy) \
2625 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy)
2626
2627static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2628 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs),
2629 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs),
2630 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs),
2631 X86_MATCH(INTEL_IVYBRIDGE, core_funcs),
2632 X86_MATCH(INTEL_HASWELL, core_funcs),
2633 X86_MATCH(INTEL_BROADWELL, core_funcs),
2634 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs),
2635 X86_MATCH(INTEL_HASWELL_X, core_funcs),
2636 X86_MATCH(INTEL_HASWELL_L, core_funcs),
2637 X86_MATCH(INTEL_HASWELL_G, core_funcs),
2638 X86_MATCH(INTEL_BROADWELL_G, core_funcs),
2639 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs),
2640 X86_MATCH(INTEL_SKYLAKE_L, core_funcs),
2641 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2642 X86_MATCH(INTEL_SKYLAKE, core_funcs),
2643 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2644 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs),
2645 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs),
2646 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs),
2647 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs),
2648 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2649 X86_MATCH(INTEL_COMETLAKE, core_funcs),
2650 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2651 X86_MATCH(INTEL_TIGERLAKE, core_funcs),
2652 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2653 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2654 {}
2655};
2656MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2657
2658#ifdef CONFIG_ACPI
2659static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2660 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2661 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2662 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2663 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2664 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2665 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2666 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs),
2667 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs),
2668 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs),
2669 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs),
2670 {}
2671};
2672#endif
2673
2674static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2675 X86_MATCH(INTEL_KABYLAKE, core_funcs),
2676 {}
2677};
2678
2679static int intel_pstate_init_cpu(unsigned int cpunum)
2680{
2681 struct cpudata *cpu;
2682
2683 cpu = all_cpu_data[cpunum];
2684
2685 if (!cpu) {
2686 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2687 if (!cpu)
2688 return -ENOMEM;
2689
2690 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2691
2692 cpu->cpu = cpunum;
2693
2694 cpu->epp_default = -EINVAL;
2695
2696 if (hwp_active) {
2697 intel_pstate_hwp_enable(cpu);
2698
2699 if (intel_pstate_acpi_pm_profile_server())
2700 hwp_boost = true;
2701 }
2702 } else if (hwp_active) {
2703 /*
2704 * Re-enable HWP in case this happens after a resume from ACPI
2705 * S3 if the CPU was offline during the whole system/resume
2706 * cycle.
2707 */
2708 intel_pstate_hwp_reenable(cpu);
2709 }
2710
2711 cpu->epp_powersave = -EINVAL;
2712 cpu->epp_policy = 0;
2713
2714 intel_pstate_get_cpu_pstates(cpu);
2715
2716 pr_debug("controlling: cpu %d\n", cpunum);
2717
2718 return 0;
2719}
2720
2721static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2722{
2723 struct cpudata *cpu = all_cpu_data[cpu_num];
2724
2725 if (hwp_active && !hwp_boost)
2726 return;
2727
2728 if (cpu->update_util_set)
2729 return;
2730
2731 /* Prevent intel_pstate_update_util() from using stale data. */
2732 cpu->sample.time = 0;
2733 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2734 (hwp_active ?
2735 intel_pstate_update_util_hwp :
2736 intel_pstate_update_util));
2737 cpu->update_util_set = true;
2738}
2739
2740static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2741{
2742 struct cpudata *cpu_data = all_cpu_data[cpu];
2743
2744 if (!cpu_data->update_util_set)
2745 return;
2746
2747 cpufreq_remove_update_util_hook(cpu);
2748 cpu_data->update_util_set = false;
2749 synchronize_rcu();
2750}
2751
2752static int intel_pstate_get_max_freq(struct cpudata *cpu)
2753{
2754 return READ_ONCE(global.no_turbo) ?
2755 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2756}
2757
2758static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2759 unsigned int policy_min,
2760 unsigned int policy_max)
2761{
2762 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2763 int32_t max_policy_perf, min_policy_perf;
2764
2765 max_policy_perf = policy_max / perf_ctl_scaling;
2766 if (policy_max == policy_min) {
2767 min_policy_perf = max_policy_perf;
2768 } else {
2769 min_policy_perf = policy_min / perf_ctl_scaling;
2770 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2771 0, max_policy_perf);
2772 }
2773
2774 /*
2775 * HWP needs some special consideration, because HWP_REQUEST uses
2776 * abstract values to represent performance rather than pure ratios.
2777 */
2778 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2779 int freq;
2780
2781 freq = max_policy_perf * perf_ctl_scaling;
2782 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2783 freq = min_policy_perf * perf_ctl_scaling;
2784 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2785 }
2786
2787 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2788 cpu->cpu, min_policy_perf, max_policy_perf);
2789
2790 /* Normalize user input to [min_perf, max_perf] */
2791 if (per_cpu_limits) {
2792 cpu->min_perf_ratio = min_policy_perf;
2793 cpu->max_perf_ratio = max_policy_perf;
2794 } else {
2795 int turbo_max = cpu->pstate.turbo_pstate;
2796 int32_t global_min, global_max;
2797
2798 /* Global limits are in percent of the maximum turbo P-state. */
2799 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2800 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2801 global_min = clamp_t(int32_t, global_min, 0, global_max);
2802
2803 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2804 global_min, global_max);
2805
2806 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2807 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2808 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2809 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2810
2811 /* Make sure min_perf <= max_perf */
2812 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2813 cpu->max_perf_ratio);
2814
2815 }
2816 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2817 cpu->max_perf_ratio,
2818 cpu->min_perf_ratio);
2819}
2820
2821static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2822{
2823 struct cpudata *cpu;
2824
2825 if (!policy->cpuinfo.max_freq)
2826 return -ENODEV;
2827
2828 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2829 policy->cpuinfo.max_freq, policy->max);
2830
2831 cpu = all_cpu_data[policy->cpu];
2832 cpu->policy = policy->policy;
2833
2834 mutex_lock(&intel_pstate_limits_lock);
2835
2836 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2837
2838 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2839 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2840
2841 /*
2842 * NOHZ_FULL CPUs need this as the governor callback may not
2843 * be invoked on them.
2844 */
2845 intel_pstate_clear_update_util_hook(policy->cpu);
2846 intel_pstate_set_pstate(cpu, pstate);
2847 } else {
2848 intel_pstate_set_update_util_hook(policy->cpu);
2849 }
2850
2851 if (hwp_active) {
2852 /*
2853 * When hwp_boost was active before and dynamically it
2854 * was turned off, in that case we need to clear the
2855 * update util hook.
2856 */
2857 if (!hwp_boost)
2858 intel_pstate_clear_update_util_hook(policy->cpu);
2859 intel_pstate_hwp_set(policy->cpu);
2860 }
2861 /*
2862 * policy->cur is never updated with the intel_pstate driver, but it
2863 * is used as a stale frequency value. So, keep it within limits.
2864 */
2865 policy->cur = policy->min;
2866
2867 mutex_unlock(&intel_pstate_limits_lock);
2868
2869 return 0;
2870}
2871
2872static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2873 struct cpufreq_policy_data *policy)
2874{
2875 if (!hwp_active &&
2876 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2877 policy->max < policy->cpuinfo.max_freq &&
2878 policy->max > cpu->pstate.max_freq) {
2879 pr_debug("policy->max > max non turbo frequency\n");
2880 policy->max = policy->cpuinfo.max_freq;
2881 }
2882}
2883
2884static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2885 struct cpufreq_policy_data *policy)
2886{
2887 int max_freq;
2888
2889 if (hwp_active) {
2890 intel_pstate_get_hwp_cap(cpu);
2891 max_freq = READ_ONCE(global.no_turbo) ?
2892 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2893 } else {
2894 max_freq = intel_pstate_get_max_freq(cpu);
2895 }
2896 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2897
2898 intel_pstate_adjust_policy_max(cpu, policy);
2899}
2900
2901static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2902{
2903 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2904
2905 return 0;
2906}
2907
2908static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2909{
2910 struct cpudata *cpu = all_cpu_data[policy->cpu];
2911
2912 pr_debug("CPU %d going offline\n", cpu->cpu);
2913
2914 if (cpu->suspended)
2915 return 0;
2916
2917 /*
2918 * If the CPU is an SMT thread and it goes offline with the performance
2919 * settings different from the minimum, it will prevent its sibling
2920 * from getting to lower performance levels, so force the minimum
2921 * performance on CPU offline to prevent that from happening.
2922 */
2923 if (hwp_active)
2924 intel_pstate_hwp_offline(cpu);
2925 else
2926 intel_pstate_set_min_pstate(cpu);
2927
2928 intel_pstate_exit_perf_limits(policy);
2929
2930 return 0;
2931}
2932
2933static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2934{
2935 struct cpudata *cpu = all_cpu_data[policy->cpu];
2936
2937 pr_debug("CPU %d going online\n", cpu->cpu);
2938
2939 intel_pstate_init_acpi_perf_limits(policy);
2940
2941 if (hwp_active) {
2942 /*
2943 * Re-enable HWP and clear the "suspended" flag to let "resume"
2944 * know that it need not do that.
2945 */
2946 intel_pstate_hwp_reenable(cpu);
2947 cpu->suspended = false;
2948
2949 hybrid_update_capacity(cpu);
2950 }
2951
2952 return 0;
2953}
2954
2955static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2956{
2957 intel_pstate_clear_update_util_hook(policy->cpu);
2958
2959 return intel_cpufreq_cpu_offline(policy);
2960}
2961
2962static void intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2963{
2964 pr_debug("CPU %d exiting\n", policy->cpu);
2965
2966 policy->fast_switch_possible = false;
2967}
2968
2969static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2970{
2971 struct cpudata *cpu;
2972 int rc;
2973
2974 rc = intel_pstate_init_cpu(policy->cpu);
2975 if (rc)
2976 return rc;
2977
2978 cpu = all_cpu_data[policy->cpu];
2979
2980 cpu->max_perf_ratio = 0xFF;
2981 cpu->min_perf_ratio = 0;
2982
2983 /* cpuinfo and default policy values */
2984 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2985 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
2986 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2987
2988 policy->min = policy->cpuinfo.min_freq;
2989 policy->max = policy->cpuinfo.max_freq;
2990
2991 intel_pstate_init_acpi_perf_limits(policy);
2992
2993 policy->fast_switch_possible = true;
2994
2995 return 0;
2996}
2997
2998static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2999{
3000 int ret = __intel_pstate_cpu_init(policy);
3001
3002 if (ret)
3003 return ret;
3004
3005 /*
3006 * Set the policy to powersave to provide a valid fallback value in case
3007 * the default cpufreq governor is neither powersave nor performance.
3008 */
3009 policy->policy = CPUFREQ_POLICY_POWERSAVE;
3010
3011 if (hwp_active) {
3012 struct cpudata *cpu = all_cpu_data[policy->cpu];
3013
3014 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
3015 }
3016
3017 return 0;
3018}
3019
3020static struct cpufreq_driver intel_pstate = {
3021 .flags = CPUFREQ_CONST_LOOPS,
3022 .verify = intel_pstate_verify_policy,
3023 .setpolicy = intel_pstate_set_policy,
3024 .suspend = intel_pstate_suspend,
3025 .resume = intel_pstate_resume,
3026 .init = intel_pstate_cpu_init,
3027 .exit = intel_pstate_cpu_exit,
3028 .offline = intel_pstate_cpu_offline,
3029 .online = intel_pstate_cpu_online,
3030 .update_limits = intel_pstate_update_limits,
3031 .name = "intel_pstate",
3032};
3033
3034static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
3035{
3036 struct cpudata *cpu = all_cpu_data[policy->cpu];
3037
3038 intel_pstate_verify_cpu_policy(cpu, policy);
3039 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
3040
3041 return 0;
3042}
3043
3044/* Use of trace in passive mode:
3045 *
3046 * In passive mode the trace core_busy field (also known as the
3047 * performance field, and lablelled as such on the graphs; also known as
3048 * core_avg_perf) is not needed and so is re-assigned to indicate if the
3049 * driver call was via the normal or fast switch path. Various graphs
3050 * output from the intel_pstate_tracer.py utility that include core_busy
3051 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
3052 * so we use 10 to indicate the normal path through the driver, and
3053 * 90 to indicate the fast switch path through the driver.
3054 * The scaled_busy field is not used, and is set to 0.
3055 */
3056
3057#define INTEL_PSTATE_TRACE_TARGET 10
3058#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
3059
3060static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
3061{
3062 struct sample *sample;
3063
3064 if (!trace_pstate_sample_enabled())
3065 return;
3066
3067 if (!intel_pstate_sample(cpu, ktime_get()))
3068 return;
3069
3070 sample = &cpu->sample;
3071 trace_pstate_sample(trace_type,
3072 0,
3073 old_pstate,
3074 cpu->pstate.current_pstate,
3075 sample->mperf,
3076 sample->aperf,
3077 sample->tsc,
3078 get_avg_frequency(cpu),
3079 fp_toint(cpu->iowait_boost * 100));
3080}
3081
3082static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
3083 u32 desired, bool fast_switch)
3084{
3085 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
3086
3087 value &= ~HWP_MIN_PERF(~0L);
3088 value |= HWP_MIN_PERF(min);
3089
3090 value &= ~HWP_MAX_PERF(~0L);
3091 value |= HWP_MAX_PERF(max);
3092
3093 value &= ~HWP_DESIRED_PERF(~0L);
3094 value |= HWP_DESIRED_PERF(desired);
3095
3096 if (value == prev)
3097 return;
3098
3099 WRITE_ONCE(cpu->hwp_req_cached, value);
3100 if (fast_switch)
3101 wrmsrl(MSR_HWP_REQUEST, value);
3102 else
3103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3104}
3105
3106static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
3107 u32 target_pstate, bool fast_switch)
3108{
3109 if (fast_switch)
3110 wrmsrl(MSR_IA32_PERF_CTL,
3111 pstate_funcs.get_val(cpu, target_pstate));
3112 else
3113 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
3114 pstate_funcs.get_val(cpu, target_pstate));
3115}
3116
3117static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
3118 int target_pstate, bool fast_switch)
3119{
3120 struct cpudata *cpu = all_cpu_data[policy->cpu];
3121 int old_pstate = cpu->pstate.current_pstate;
3122
3123 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
3124 if (hwp_active) {
3125 int max_pstate = policy->strict_target ?
3126 target_pstate : cpu->max_perf_ratio;
3127
3128 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
3129 fast_switch);
3130 } else if (target_pstate != old_pstate) {
3131 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
3132 }
3133
3134 cpu->pstate.current_pstate = target_pstate;
3135
3136 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
3137 INTEL_PSTATE_TRACE_TARGET, old_pstate);
3138
3139 return target_pstate;
3140}
3141
3142static int intel_cpufreq_target(struct cpufreq_policy *policy,
3143 unsigned int target_freq,
3144 unsigned int relation)
3145{
3146 struct cpudata *cpu = all_cpu_data[policy->cpu];
3147 struct cpufreq_freqs freqs;
3148 int target_pstate;
3149
3150 freqs.old = policy->cur;
3151 freqs.new = target_freq;
3152
3153 cpufreq_freq_transition_begin(policy, &freqs);
3154
3155 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
3156 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
3157
3158 freqs.new = target_pstate * cpu->pstate.scaling;
3159
3160 cpufreq_freq_transition_end(policy, &freqs, false);
3161
3162 return 0;
3163}
3164
3165static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
3166 unsigned int target_freq)
3167{
3168 struct cpudata *cpu = all_cpu_data[policy->cpu];
3169 int target_pstate;
3170
3171 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
3172
3173 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
3174
3175 return target_pstate * cpu->pstate.scaling;
3176}
3177
3178static void intel_cpufreq_adjust_perf(unsigned int cpunum,
3179 unsigned long min_perf,
3180 unsigned long target_perf,
3181 unsigned long capacity)
3182{
3183 struct cpudata *cpu = all_cpu_data[cpunum];
3184 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
3185 int old_pstate = cpu->pstate.current_pstate;
3186 int cap_pstate, min_pstate, max_pstate, target_pstate;
3187
3188 cap_pstate = READ_ONCE(global.no_turbo) ?
3189 HWP_GUARANTEED_PERF(hwp_cap) :
3190 HWP_HIGHEST_PERF(hwp_cap);
3191
3192 /* Optimization: Avoid unnecessary divisions. */
3193
3194 target_pstate = cap_pstate;
3195 if (target_perf < capacity)
3196 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
3197
3198 min_pstate = cap_pstate;
3199 if (min_perf < capacity)
3200 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
3201
3202 if (min_pstate < cpu->pstate.min_pstate)
3203 min_pstate = cpu->pstate.min_pstate;
3204
3205 if (min_pstate < cpu->min_perf_ratio)
3206 min_pstate = cpu->min_perf_ratio;
3207
3208 if (min_pstate > cpu->max_perf_ratio)
3209 min_pstate = cpu->max_perf_ratio;
3210
3211 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
3212 if (max_pstate < min_pstate)
3213 max_pstate = min_pstate;
3214
3215 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
3216
3217 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3218
3219 cpu->pstate.current_pstate = target_pstate;
3220 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3221}
3222
3223static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3224{
3225 struct freq_qos_request *req;
3226 struct cpudata *cpu;
3227 struct device *dev;
3228 int ret, freq;
3229
3230 dev = get_cpu_device(policy->cpu);
3231 if (!dev)
3232 return -ENODEV;
3233
3234 ret = __intel_pstate_cpu_init(policy);
3235 if (ret)
3236 return ret;
3237
3238 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3239 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3240 policy->cur = policy->cpuinfo.min_freq;
3241
3242 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3243 if (!req) {
3244 ret = -ENOMEM;
3245 goto pstate_exit;
3246 }
3247
3248 cpu = all_cpu_data[policy->cpu];
3249
3250 if (hwp_active) {
3251 u64 value;
3252
3253 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3254
3255 intel_pstate_get_hwp_cap(cpu);
3256
3257 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3258 WRITE_ONCE(cpu->hwp_req_cached, value);
3259
3260 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3261 } else {
3262 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3263 }
3264
3265 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3266
3267 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3268 freq);
3269 if (ret < 0) {
3270 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3271 goto free_req;
3272 }
3273
3274 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3275
3276 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3277 freq);
3278 if (ret < 0) {
3279 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3280 goto remove_min_req;
3281 }
3282
3283 policy->driver_data = req;
3284
3285 return 0;
3286
3287remove_min_req:
3288 freq_qos_remove_request(req);
3289free_req:
3290 kfree(req);
3291pstate_exit:
3292 intel_pstate_exit_perf_limits(policy);
3293
3294 return ret;
3295}
3296
3297static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3298{
3299 struct freq_qos_request *req;
3300
3301 req = policy->driver_data;
3302
3303 freq_qos_remove_request(req + 1);
3304 freq_qos_remove_request(req);
3305 kfree(req);
3306
3307 intel_pstate_cpu_exit(policy);
3308}
3309
3310static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3311{
3312 intel_pstate_suspend(policy);
3313
3314 if (hwp_active) {
3315 struct cpudata *cpu = all_cpu_data[policy->cpu];
3316 u64 value = READ_ONCE(cpu->hwp_req_cached);
3317
3318 /*
3319 * Clear the desired perf field in MSR_HWP_REQUEST in case
3320 * intel_cpufreq_adjust_perf() is in use and the last value
3321 * written by it may not be suitable.
3322 */
3323 value &= ~HWP_DESIRED_PERF(~0L);
3324 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3325 WRITE_ONCE(cpu->hwp_req_cached, value);
3326 }
3327
3328 return 0;
3329}
3330
3331static struct cpufreq_driver intel_cpufreq = {
3332 .flags = CPUFREQ_CONST_LOOPS,
3333 .verify = intel_cpufreq_verify_policy,
3334 .target = intel_cpufreq_target,
3335 .fast_switch = intel_cpufreq_fast_switch,
3336 .init = intel_cpufreq_cpu_init,
3337 .exit = intel_cpufreq_cpu_exit,
3338 .offline = intel_cpufreq_cpu_offline,
3339 .online = intel_pstate_cpu_online,
3340 .suspend = intel_cpufreq_suspend,
3341 .resume = intel_pstate_resume,
3342 .update_limits = intel_pstate_update_limits,
3343 .name = "intel_cpufreq",
3344};
3345
3346static struct cpufreq_driver *default_driver;
3347
3348static void intel_pstate_driver_cleanup(void)
3349{
3350 unsigned int cpu;
3351
3352 cpus_read_lock();
3353 for_each_online_cpu(cpu) {
3354 if (all_cpu_data[cpu]) {
3355 if (intel_pstate_driver == &intel_pstate)
3356 intel_pstate_clear_update_util_hook(cpu);
3357
3358 kfree(all_cpu_data[cpu]);
3359 WRITE_ONCE(all_cpu_data[cpu], NULL);
3360 }
3361 }
3362 cpus_read_unlock();
3363
3364 intel_pstate_driver = NULL;
3365}
3366
3367static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3368{
3369 bool refresh_cpu_cap_scaling;
3370 int ret;
3371
3372 if (driver == &intel_pstate)
3373 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3374
3375 memset(&global, 0, sizeof(global));
3376 global.max_perf_pct = 100;
3377 global.turbo_disabled = turbo_is_disabled();
3378 global.no_turbo = global.turbo_disabled;
3379
3380 arch_set_max_freq_ratio(global.turbo_disabled);
3381
3382 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu();
3383
3384 intel_pstate_driver = driver;
3385 ret = cpufreq_register_driver(intel_pstate_driver);
3386 if (ret) {
3387 intel_pstate_driver_cleanup();
3388 return ret;
3389 }
3390
3391 global.min_perf_pct = min_perf_pct_min();
3392
3393 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling);
3394
3395 return 0;
3396}
3397
3398static ssize_t intel_pstate_show_status(char *buf)
3399{
3400 if (!intel_pstate_driver)
3401 return sprintf(buf, "off\n");
3402
3403 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3404 "active" : "passive");
3405}
3406
3407static int intel_pstate_update_status(const char *buf, size_t size)
3408{
3409 if (size == 3 && !strncmp(buf, "off", size)) {
3410 if (!intel_pstate_driver)
3411 return -EINVAL;
3412
3413 if (hwp_active)
3414 return -EBUSY;
3415
3416 cpufreq_unregister_driver(intel_pstate_driver);
3417 intel_pstate_driver_cleanup();
3418 return 0;
3419 }
3420
3421 if (size == 6 && !strncmp(buf, "active", size)) {
3422 if (intel_pstate_driver) {
3423 if (intel_pstate_driver == &intel_pstate)
3424 return 0;
3425
3426 cpufreq_unregister_driver(intel_pstate_driver);
3427 }
3428
3429 return intel_pstate_register_driver(&intel_pstate);
3430 }
3431
3432 if (size == 7 && !strncmp(buf, "passive", size)) {
3433 if (intel_pstate_driver) {
3434 if (intel_pstate_driver == &intel_cpufreq)
3435 return 0;
3436
3437 cpufreq_unregister_driver(intel_pstate_driver);
3438 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3439 }
3440
3441 return intel_pstate_register_driver(&intel_cpufreq);
3442 }
3443
3444 return -EINVAL;
3445}
3446
3447static int no_load __initdata;
3448static int no_hwp __initdata;
3449static int hwp_only __initdata;
3450static unsigned int force_load __initdata;
3451
3452static int __init intel_pstate_msrs_not_valid(void)
3453{
3454 if (!pstate_funcs.get_max(0) ||
3455 !pstate_funcs.get_min(0) ||
3456 !pstate_funcs.get_turbo(0))
3457 return -ENODEV;
3458
3459 return 0;
3460}
3461
3462static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3463{
3464 pstate_funcs.get_max = funcs->get_max;
3465 pstate_funcs.get_max_physical = funcs->get_max_physical;
3466 pstate_funcs.get_min = funcs->get_min;
3467 pstate_funcs.get_turbo = funcs->get_turbo;
3468 pstate_funcs.get_scaling = funcs->get_scaling;
3469 pstate_funcs.get_val = funcs->get_val;
3470 pstate_funcs.get_vid = funcs->get_vid;
3471 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3472}
3473
3474#ifdef CONFIG_ACPI
3475
3476static bool __init intel_pstate_no_acpi_pss(void)
3477{
3478 int i;
3479
3480 for_each_possible_cpu(i) {
3481 acpi_status status;
3482 union acpi_object *pss;
3483 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3484 struct acpi_processor *pr = per_cpu(processors, i);
3485
3486 if (!pr)
3487 continue;
3488
3489 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3490 if (ACPI_FAILURE(status))
3491 continue;
3492
3493 pss = buffer.pointer;
3494 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3495 kfree(pss);
3496 return false;
3497 }
3498
3499 kfree(pss);
3500 }
3501
3502 pr_debug("ACPI _PSS not found\n");
3503 return true;
3504}
3505
3506static bool __init intel_pstate_no_acpi_pcch(void)
3507{
3508 acpi_status status;
3509 acpi_handle handle;
3510
3511 status = acpi_get_handle(NULL, "\\_SB", &handle);
3512 if (ACPI_FAILURE(status))
3513 goto not_found;
3514
3515 if (acpi_has_method(handle, "PCCH"))
3516 return false;
3517
3518not_found:
3519 pr_debug("ACPI PCCH not found\n");
3520 return true;
3521}
3522
3523static bool __init intel_pstate_has_acpi_ppc(void)
3524{
3525 int i;
3526
3527 for_each_possible_cpu(i) {
3528 struct acpi_processor *pr = per_cpu(processors, i);
3529
3530 if (!pr)
3531 continue;
3532 if (acpi_has_method(pr->handle, "_PPC"))
3533 return true;
3534 }
3535 pr_debug("ACPI _PPC not found\n");
3536 return false;
3537}
3538
3539enum {
3540 PSS,
3541 PPC,
3542};
3543
3544/* Hardware vendor-specific info that has its own power management modes */
3545static struct acpi_platform_list plat_info[] __initdata = {
3546 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3547 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3548 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3549 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3550 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3551 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3552 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3553 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3554 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3555 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3556 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3557 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3558 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3559 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3560 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3561 { } /* End */
3562};
3563
3564#define BITMASK_OOB (BIT(8) | BIT(18))
3565
3566static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3567{
3568 const struct x86_cpu_id *id;
3569 u64 misc_pwr;
3570 int idx;
3571
3572 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3573 if (id) {
3574 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3575 if (misc_pwr & BITMASK_OOB) {
3576 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3577 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3578 return true;
3579 }
3580 }
3581
3582 idx = acpi_match_platform_list(plat_info);
3583 if (idx < 0)
3584 return false;
3585
3586 switch (plat_info[idx].data) {
3587 case PSS:
3588 if (!intel_pstate_no_acpi_pss())
3589 return false;
3590
3591 return intel_pstate_no_acpi_pcch();
3592 case PPC:
3593 return intel_pstate_has_acpi_ppc() && !force_load;
3594 }
3595
3596 return false;
3597}
3598
3599static void intel_pstate_request_control_from_smm(void)
3600{
3601 /*
3602 * It may be unsafe to request P-states control from SMM if _PPC support
3603 * has not been enabled.
3604 */
3605 if (acpi_ppc)
3606 acpi_processor_pstate_control();
3607}
3608#else /* CONFIG_ACPI not enabled */
3609static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3610static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3611static inline void intel_pstate_request_control_from_smm(void) {}
3612#endif /* CONFIG_ACPI */
3613
3614#define INTEL_PSTATE_HWP_BROADWELL 0x01
3615
3616#define X86_MATCH_HWP(vfm, hwp_mode) \
3617 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode)
3618
3619static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3620 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3621 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3622 X86_MATCH_HWP(INTEL_ANY, 0),
3623 {}
3624};
3625
3626static bool intel_pstate_hwp_is_enabled(void)
3627{
3628 u64 value;
3629
3630 rdmsrl(MSR_PM_ENABLE, value);
3631 return !!(value & 0x1);
3632}
3633
3634#define POWERSAVE_MASK GENMASK(7, 0)
3635#define BALANCE_POWER_MASK GENMASK(15, 8)
3636#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3637#define PERFORMANCE_MASK GENMASK(31, 24)
3638
3639#define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3640 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3641 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3642 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3643 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3644
3645#define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3646 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3647 balance_perf, HWP_EPP_PERFORMANCE))
3648
3649static const struct x86_cpu_id intel_epp_default[] = {
3650 /*
3651 * Set EPP value as 102, this is the max suggested EPP
3652 * which can result in one core turbo frequency for
3653 * AlderLake Mobile CPUs.
3654 */
3655 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3656 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3657 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3658 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3659 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3660 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3661 179, 64, 16)),
3662 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3663 179, 64, 16)),
3664 {}
3665};
3666
3667static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3668 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3669 X86_MATCH_VFM(INTEL_ARROWLAKE, HYBRID_SCALING_FACTOR_MTL),
3670 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL),
3671 {}
3672};
3673
3674static int __init intel_pstate_init(void)
3675{
3676 static struct cpudata **_all_cpu_data;
3677 const struct x86_cpu_id *id;
3678 int rc;
3679
3680 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3681 return -ENODEV;
3682
3683 id = x86_match_cpu(hwp_support_ids);
3684 if (id) {
3685 hwp_forced = intel_pstate_hwp_is_enabled();
3686
3687 if (hwp_forced)
3688 pr_info("HWP enabled by BIOS\n");
3689 else if (no_load)
3690 return -ENODEV;
3691
3692 copy_cpu_funcs(&core_funcs);
3693 /*
3694 * Avoid enabling HWP for processors without EPP support,
3695 * because that means incomplete HWP implementation which is a
3696 * corner case and supporting it is generally problematic.
3697 *
3698 * If HWP is enabled already, though, there is no choice but to
3699 * deal with it.
3700 */
3701 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3702 hwp_active = true;
3703 hwp_mode_bdw = id->driver_data;
3704 intel_pstate.attr = hwp_cpufreq_attrs;
3705 intel_cpufreq.attr = hwp_cpufreq_attrs;
3706 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3707 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3708 if (!default_driver)
3709 default_driver = &intel_pstate;
3710
3711 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3712
3713 goto hwp_cpu_matched;
3714 }
3715 pr_info("HWP not enabled\n");
3716 } else {
3717 if (no_load)
3718 return -ENODEV;
3719
3720 id = x86_match_cpu(intel_pstate_cpu_ids);
3721 if (!id) {
3722 pr_info("CPU model not supported\n");
3723 return -ENODEV;
3724 }
3725
3726 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3727 }
3728
3729 if (intel_pstate_msrs_not_valid()) {
3730 pr_info("Invalid MSRs\n");
3731 return -ENODEV;
3732 }
3733 /* Without HWP start in the passive mode. */
3734 if (!default_driver)
3735 default_driver = &intel_cpufreq;
3736
3737hwp_cpu_matched:
3738 /*
3739 * The Intel pstate driver will be ignored if the platform
3740 * firmware has its own power management modes.
3741 */
3742 if (intel_pstate_platform_pwr_mgmt_exists()) {
3743 pr_info("P-states controlled by the platform\n");
3744 return -ENODEV;
3745 }
3746
3747 if (!hwp_active && hwp_only)
3748 return -ENOTSUPP;
3749
3750 pr_info("Intel P-state driver initializing\n");
3751
3752 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3753 if (!_all_cpu_data)
3754 return -ENOMEM;
3755
3756 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3757
3758 intel_pstate_request_control_from_smm();
3759
3760 intel_pstate_sysfs_expose_params();
3761
3762 if (hwp_active) {
3763 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3764 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3765
3766 if (id) {
3767 epp_values[EPP_INDEX_POWERSAVE] =
3768 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3769 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3770 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3771 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3772 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3773 epp_values[EPP_INDEX_PERFORMANCE] =
3774 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3775 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3776 epp_values[EPP_INDEX_POWERSAVE],
3777 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3778 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3779 epp_values[EPP_INDEX_PERFORMANCE]);
3780 }
3781
3782 if (hybrid_id) {
3783 hybrid_scaling_factor = hybrid_id->driver_data;
3784 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3785 }
3786
3787 }
3788
3789 mutex_lock(&intel_pstate_driver_lock);
3790 rc = intel_pstate_register_driver(default_driver);
3791 mutex_unlock(&intel_pstate_driver_lock);
3792 if (rc) {
3793 intel_pstate_sysfs_remove();
3794 return rc;
3795 }
3796
3797 if (hwp_active) {
3798 const struct x86_cpu_id *id;
3799
3800 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3801 if (id) {
3802 set_power_ctl_ee_state(false);
3803 pr_info("Disabling energy efficiency optimization\n");
3804 }
3805
3806 pr_info("HWP enabled\n");
3807 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3808 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3809 }
3810
3811 return 0;
3812}
3813device_initcall(intel_pstate_init);
3814
3815static int __init intel_pstate_setup(char *str)
3816{
3817 if (!str)
3818 return -EINVAL;
3819
3820 if (!strcmp(str, "disable"))
3821 no_load = 1;
3822 else if (!strcmp(str, "active"))
3823 default_driver = &intel_pstate;
3824 else if (!strcmp(str, "passive"))
3825 default_driver = &intel_cpufreq;
3826
3827 if (!strcmp(str, "no_hwp"))
3828 no_hwp = 1;
3829
3830 if (!strcmp(str, "force"))
3831 force_load = 1;
3832 if (!strcmp(str, "hwp_only"))
3833 hwp_only = 1;
3834 if (!strcmp(str, "per_cpu_perf_limits"))
3835 per_cpu_limits = true;
3836
3837#ifdef CONFIG_ACPI
3838 if (!strcmp(str, "support_acpi_ppc"))
3839 acpi_ppc = true;
3840#endif
3841
3842 return 0;
3843}
3844early_param("intel_pstate", intel_pstate_setup);
3845
3846MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3847MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/kernel_stat.h>
13#include <linux/module.h>
14#include <linux/ktime.h>
15#include <linux/hrtimer.h>
16#include <linux/tick.h>
17#include <linux/slab.h>
18#include <linux/sched/cpufreq.h>
19#include <linux/list.h>
20#include <linux/cpu.h>
21#include <linux/cpufreq.h>
22#include <linux/sysfs.h>
23#include <linux/types.h>
24#include <linux/fs.h>
25#include <linux/acpi.h>
26#include <linux/vmalloc.h>
27#include <linux/pm_qos.h>
28#include <linux/bitfield.h>
29#include <trace/events/power.h>
30
31#include <asm/cpu.h>
32#include <asm/div64.h>
33#include <asm/msr.h>
34#include <asm/cpu_device_id.h>
35#include <asm/cpufeature.h>
36#include <asm/intel-family.h>
37#include "../drivers/thermal/intel/thermal_interrupt.h"
38
39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40
41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42#define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
43#define INTEL_CPUFREQ_TRANSITION_DELAY 500
44
45#ifdef CONFIG_ACPI
46#include <acpi/processor.h>
47#include <acpi/cppc_acpi.h>
48#endif
49
50#define FRAC_BITS 8
51#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
52#define fp_toint(X) ((X) >> FRAC_BITS)
53
54#define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
55
56#define EXT_BITS 6
57#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
58#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
59#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60
61static inline int32_t mul_fp(int32_t x, int32_t y)
62{
63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
64}
65
66static inline int32_t div_fp(s64 x, s64 y)
67{
68 return div64_s64((int64_t)x << FRAC_BITS, y);
69}
70
71static inline int ceiling_fp(int32_t x)
72{
73 int mask, ret;
74
75 ret = fp_toint(x);
76 mask = (1 << FRAC_BITS) - 1;
77 if (x & mask)
78 ret += 1;
79 return ret;
80}
81
82static inline u64 mul_ext_fp(u64 x, u64 y)
83{
84 return (x * y) >> EXT_FRAC_BITS;
85}
86
87static inline u64 div_ext_fp(u64 x, u64 y)
88{
89 return div64_u64(x << EXT_FRAC_BITS, y);
90}
91
92/**
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
104 * current sample
105 * @time: Current time from scheduler
106 *
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
109 */
110struct sample {
111 int32_t core_avg_perf;
112 int32_t busy_scaled;
113 u64 aperf;
114 u64 mperf;
115 u64 tsc;
116 u64 time;
117};
118
119/**
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
128 * @scaling: Scaling factor between performance and frequency
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @min_freq: @min_pstate frequency in cpufreq units
131 * @max_freq: @max_pstate frequency in cpufreq units
132 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 *
134 * Stores the per cpu model P state limits and current P state.
135 */
136struct pstate_data {
137 int current_pstate;
138 int min_pstate;
139 int max_pstate;
140 int max_pstate_physical;
141 int perf_ctl_scaling;
142 int scaling;
143 int turbo_pstate;
144 unsigned int min_freq;
145 unsigned int max_freq;
146 unsigned int turbo_freq;
147};
148
149/**
150 * struct vid_data - Stores voltage information data
151 * @min: VID data for this platform corresponding to
152 * the lowest P state
153 * @max: VID data corresponding to the highest P State.
154 * @turbo: VID data for turbo P state
155 * @ratio: Ratio of (vid max - vid min) /
156 * (max P state - Min P State)
157 *
158 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
159 * This data is used in Atom platforms, where in addition to target P state,
160 * the voltage data needs to be specified to select next P State.
161 */
162struct vid_data {
163 int min;
164 int max;
165 int turbo;
166 int32_t ratio;
167};
168
169/**
170 * struct global_params - Global parameters, mostly tunable via sysfs.
171 * @no_turbo: Whether or not to use turbo P-states.
172 * @turbo_disabled: Whether or not turbo P-states are available at all,
173 * based on the MSR_IA32_MISC_ENABLE value and whether or
174 * not the maximum reported turbo P-state is different from
175 * the maximum reported non-turbo one.
176 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
177 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * P-state capacity.
179 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
180 * P-state capacity.
181 */
182struct global_params {
183 bool no_turbo;
184 bool turbo_disabled;
185 bool turbo_disabled_mf;
186 int max_perf_pct;
187 int min_perf_pct;
188};
189
190/**
191 * struct cpudata - Per CPU instance data storage
192 * @cpu: CPU number for this instance data
193 * @policy: CPUFreq policy value
194 * @update_util: CPUFreq utility callback information
195 * @update_util_set: CPUFreq utility callback is set
196 * @iowait_boost: iowait-related boost fraction
197 * @last_update: Time of the last update.
198 * @pstate: Stores P state limits for this CPU
199 * @vid: Stores VID limits for this CPU
200 * @last_sample_time: Last Sample time
201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
202 * @prev_aperf: Last APERF value read from APERF MSR
203 * @prev_mperf: Last MPERF value read from MPERF MSR
204 * @prev_tsc: Last timestamp counter (TSC) value
205 * @sample: Storage for storing last Sample data
206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
208 * @acpi_perf_data: Stores ACPI perf information read from _PSS
209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
210 * @epp_powersave: Last saved HWP energy performance preference
211 * (EPP) or energy performance bias (EPB),
212 * when policy switched to performance
213 * @epp_policy: Last saved policy used to set EPP/EPB
214 * @epp_default: Power on default HWP energy performance
215 * preference/bias
216 * @epp_cached Cached HWP energy-performance preference value
217 * @hwp_req_cached: Cached value of the last HWP Request MSR
218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
219 * @last_io_update: Last time when IO wake flag was set
220 * @sched_flags: Store scheduler flags for possible cross CPU update
221 * @hwp_boost_min: Last HWP boosted min performance
222 * @suspended: Whether or not the driver has been suspended.
223 * @hwp_notify_work: workqueue for HWP notifications.
224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
227struct cpudata {
228 int cpu;
229
230 unsigned int policy;
231 struct update_util_data update_util;
232 bool update_util_set;
233
234 struct pstate_data pstate;
235 struct vid_data vid;
236
237 u64 last_update;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
240 u64 prev_aperf;
241 u64 prev_mperf;
242 u64 prev_tsc;
243 struct sample sample;
244 int32_t min_perf_ratio;
245 int32_t max_perf_ratio;
246#ifdef CONFIG_ACPI
247 struct acpi_processor_performance acpi_perf_data;
248 bool valid_pss_table;
249#endif
250 unsigned int iowait_boost;
251 s16 epp_powersave;
252 s16 epp_policy;
253 s16 epp_default;
254 s16 epp_cached;
255 u64 hwp_req_cached;
256 u64 hwp_cap_cached;
257 u64 last_io_update;
258 unsigned int sched_flags;
259 u32 hwp_boost_min;
260 bool suspended;
261 struct delayed_work hwp_notify_work;
262};
263
264static struct cpudata **all_cpu_data;
265
266/**
267 * struct pstate_funcs - Per CPU model specific callbacks
268 * @get_max: Callback to get maximum non turbo effective P state
269 * @get_max_physical: Callback to get maximum non turbo physical P state
270 * @get_min: Callback to get minimum P state
271 * @get_turbo: Callback to get turbo P state
272 * @get_scaling: Callback to get frequency scaling factor
273 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
274 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
275 * @get_val: Callback to convert P state to actual MSR write value
276 * @get_vid: Callback to get VID data for Atom platforms
277 *
278 * Core and Atom CPU models have different way to get P State limits. This
279 * structure is used to store those callbacks.
280 */
281struct pstate_funcs {
282 int (*get_max)(int cpu);
283 int (*get_max_physical)(int cpu);
284 int (*get_min)(int cpu);
285 int (*get_turbo)(int cpu);
286 int (*get_scaling)(void);
287 int (*get_cpu_scaling)(int cpu);
288 int (*get_aperf_mperf_shift)(void);
289 u64 (*get_val)(struct cpudata*, int pstate);
290 void (*get_vid)(struct cpudata *);
291};
292
293static struct pstate_funcs pstate_funcs __read_mostly;
294
295static int hwp_active __read_mostly;
296static int hwp_mode_bdw __read_mostly;
297static bool per_cpu_limits __read_mostly;
298static bool hwp_boost __read_mostly;
299static bool hwp_forced __read_mostly;
300
301static struct cpufreq_driver *intel_pstate_driver __read_mostly;
302
303#define HYBRID_SCALING_FACTOR 78741
304#define HYBRID_SCALING_FACTOR_MTL 80000
305
306static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;
307
308static inline int core_get_scaling(void)
309{
310 return 100000;
311}
312
313#ifdef CONFIG_ACPI
314static bool acpi_ppc;
315#endif
316
317static struct global_params global;
318
319static DEFINE_MUTEX(intel_pstate_driver_lock);
320static DEFINE_MUTEX(intel_pstate_limits_lock);
321
322#ifdef CONFIG_ACPI
323
324static bool intel_pstate_acpi_pm_profile_server(void)
325{
326 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
327 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
328 return true;
329
330 return false;
331}
332
333static bool intel_pstate_get_ppc_enable_status(void)
334{
335 if (intel_pstate_acpi_pm_profile_server())
336 return true;
337
338 return acpi_ppc;
339}
340
341#ifdef CONFIG_ACPI_CPPC_LIB
342
343/* The work item is needed to avoid CPU hotplug locking issues */
344static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
345{
346 sched_set_itmt_support();
347}
348
349static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
350
351#define CPPC_MAX_PERF U8_MAX
352
353static void intel_pstate_set_itmt_prio(int cpu)
354{
355 struct cppc_perf_caps cppc_perf;
356 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
357 int ret;
358
359 ret = cppc_get_perf_caps(cpu, &cppc_perf);
360 if (ret)
361 return;
362
363 /*
364 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
365 * In this case we can't use CPPC.highest_perf to enable ITMT.
366 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
367 */
368 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
369 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
370
371 /*
372 * The priorities can be set regardless of whether or not
373 * sched_set_itmt_support(true) has been called and it is valid to
374 * update them at any time after it has been called.
375 */
376 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
377
378 if (max_highest_perf <= min_highest_perf) {
379 if (cppc_perf.highest_perf > max_highest_perf)
380 max_highest_perf = cppc_perf.highest_perf;
381
382 if (cppc_perf.highest_perf < min_highest_perf)
383 min_highest_perf = cppc_perf.highest_perf;
384
385 if (max_highest_perf > min_highest_perf) {
386 /*
387 * This code can be run during CPU online under the
388 * CPU hotplug locks, so sched_set_itmt_support()
389 * cannot be called from here. Queue up a work item
390 * to invoke it.
391 */
392 schedule_work(&sched_itmt_work);
393 }
394 }
395}
396
397static int intel_pstate_get_cppc_guaranteed(int cpu)
398{
399 struct cppc_perf_caps cppc_perf;
400 int ret;
401
402 ret = cppc_get_perf_caps(cpu, &cppc_perf);
403 if (ret)
404 return ret;
405
406 if (cppc_perf.guaranteed_perf)
407 return cppc_perf.guaranteed_perf;
408
409 return cppc_perf.nominal_perf;
410}
411
412static int intel_pstate_cppc_get_scaling(int cpu)
413{
414 struct cppc_perf_caps cppc_perf;
415 int ret;
416
417 ret = cppc_get_perf_caps(cpu, &cppc_perf);
418
419 /*
420 * If the nominal frequency and the nominal performance are not
421 * zero and the ratio between them is not 100, return the hybrid
422 * scaling factor.
423 */
424 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
425 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
426 return hybrid_scaling_factor;
427
428 return core_get_scaling();
429}
430
431#else /* CONFIG_ACPI_CPPC_LIB */
432static inline void intel_pstate_set_itmt_prio(int cpu)
433{
434}
435#endif /* CONFIG_ACPI_CPPC_LIB */
436
437static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
438{
439 struct cpudata *cpu;
440 int ret;
441 int i;
442
443 if (hwp_active) {
444 intel_pstate_set_itmt_prio(policy->cpu);
445 return;
446 }
447
448 if (!intel_pstate_get_ppc_enable_status())
449 return;
450
451 cpu = all_cpu_data[policy->cpu];
452
453 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
454 policy->cpu);
455 if (ret)
456 return;
457
458 /*
459 * Check if the control value in _PSS is for PERF_CTL MSR, which should
460 * guarantee that the states returned by it map to the states in our
461 * list directly.
462 */
463 if (cpu->acpi_perf_data.control_register.space_id !=
464 ACPI_ADR_SPACE_FIXED_HARDWARE)
465 goto err;
466
467 /*
468 * If there is only one entry _PSS, simply ignore _PSS and continue as
469 * usual without taking _PSS into account
470 */
471 if (cpu->acpi_perf_data.state_count < 2)
472 goto err;
473
474 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
475 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
476 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
477 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
478 (u32) cpu->acpi_perf_data.states[i].core_frequency,
479 (u32) cpu->acpi_perf_data.states[i].power,
480 (u32) cpu->acpi_perf_data.states[i].control);
481 }
482
483 cpu->valid_pss_table = true;
484 pr_debug("_PPC limits will be enforced\n");
485
486 return;
487
488 err:
489 cpu->valid_pss_table = false;
490 acpi_processor_unregister_performance(policy->cpu);
491}
492
493static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
494{
495 struct cpudata *cpu;
496
497 cpu = all_cpu_data[policy->cpu];
498 if (!cpu->valid_pss_table)
499 return;
500
501 acpi_processor_unregister_performance(policy->cpu);
502}
503#else /* CONFIG_ACPI */
504static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
505{
506}
507
508static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
509{
510}
511
512static inline bool intel_pstate_acpi_pm_profile_server(void)
513{
514 return false;
515}
516#endif /* CONFIG_ACPI */
517
518#ifndef CONFIG_ACPI_CPPC_LIB
519static inline int intel_pstate_get_cppc_guaranteed(int cpu)
520{
521 return -ENOTSUPP;
522}
523
524static int intel_pstate_cppc_get_scaling(int cpu)
525{
526 return core_get_scaling();
527}
528#endif /* CONFIG_ACPI_CPPC_LIB */
529
530static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
531 unsigned int relation)
532{
533 if (freq == cpu->pstate.turbo_freq)
534 return cpu->pstate.turbo_pstate;
535
536 if (freq == cpu->pstate.max_freq)
537 return cpu->pstate.max_pstate;
538
539 switch (relation) {
540 case CPUFREQ_RELATION_H:
541 return freq / cpu->pstate.scaling;
542 case CPUFREQ_RELATION_C:
543 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
544 }
545
546 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
547}
548
549static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
550{
551 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
552}
553
554/**
555 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
556 * @cpu: Target CPU.
557 *
558 * On hybrid processors, HWP may expose more performance levels than there are
559 * P-states accessible through the PERF_CTL interface. If that happens, the
560 * scaling factor between HWP performance levels and CPU frequency will be less
561 * than the scaling factor between P-state values and CPU frequency.
562 *
563 * In that case, adjust the CPU parameters used in computations accordingly.
564 */
565static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
566{
567 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
568 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
569 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
570 int scaling = cpu->pstate.scaling;
571 int freq;
572
573 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
574 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
575 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
576 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
577 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
578 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
579
580 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
581 perf_ctl_scaling);
582 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
583 perf_ctl_scaling);
584
585 freq = perf_ctl_max_phys * perf_ctl_scaling;
586 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
587
588 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
589 cpu->pstate.min_freq = freq;
590 /*
591 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
592 * the effective range of HWP performance levels.
593 */
594 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
595}
596
597static inline void update_turbo_state(void)
598{
599 u64 misc_en;
600
601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
602 global.turbo_disabled = misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
603}
604
605static int min_perf_pct_min(void)
606{
607 struct cpudata *cpu = all_cpu_data[0];
608 int turbo_pstate = cpu->pstate.turbo_pstate;
609
610 return turbo_pstate ?
611 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
612}
613
614static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
615{
616 u64 epb;
617 int ret;
618
619 if (!boot_cpu_has(X86_FEATURE_EPB))
620 return -ENXIO;
621
622 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
623 if (ret)
624 return (s16)ret;
625
626 return (s16)(epb & 0x0f);
627}
628
629static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
630{
631 s16 epp;
632
633 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
634 /*
635 * When hwp_req_data is 0, means that caller didn't read
636 * MSR_HWP_REQUEST, so need to read and get EPP.
637 */
638 if (!hwp_req_data) {
639 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
640 &hwp_req_data);
641 if (epp)
642 return epp;
643 }
644 epp = (hwp_req_data >> 24) & 0xff;
645 } else {
646 /* When there is no EPP present, HWP uses EPB settings */
647 epp = intel_pstate_get_epb(cpu_data);
648 }
649
650 return epp;
651}
652
653static int intel_pstate_set_epb(int cpu, s16 pref)
654{
655 u64 epb;
656 int ret;
657
658 if (!boot_cpu_has(X86_FEATURE_EPB))
659 return -ENXIO;
660
661 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
662 if (ret)
663 return ret;
664
665 epb = (epb & ~0x0f) | pref;
666 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
667
668 return 0;
669}
670
671/*
672 * EPP/EPB display strings corresponding to EPP index in the
673 * energy_perf_strings[]
674 * index String
675 *-------------------------------------
676 * 0 default
677 * 1 performance
678 * 2 balance_performance
679 * 3 balance_power
680 * 4 power
681 */
682
683enum energy_perf_value_index {
684 EPP_INDEX_DEFAULT = 0,
685 EPP_INDEX_PERFORMANCE,
686 EPP_INDEX_BALANCE_PERFORMANCE,
687 EPP_INDEX_BALANCE_POWERSAVE,
688 EPP_INDEX_POWERSAVE,
689};
690
691static const char * const energy_perf_strings[] = {
692 [EPP_INDEX_DEFAULT] = "default",
693 [EPP_INDEX_PERFORMANCE] = "performance",
694 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
695 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
696 [EPP_INDEX_POWERSAVE] = "power",
697 NULL
698};
699static unsigned int epp_values[] = {
700 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
701 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
702 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
703 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
704 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
705};
706
707static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
708{
709 s16 epp;
710 int index = -EINVAL;
711
712 *raw_epp = 0;
713 epp = intel_pstate_get_epp(cpu_data, 0);
714 if (epp < 0)
715 return epp;
716
717 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
718 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
719 return EPP_INDEX_PERFORMANCE;
720 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
721 return EPP_INDEX_BALANCE_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
723 return EPP_INDEX_BALANCE_POWERSAVE;
724 if (epp == epp_values[EPP_INDEX_POWERSAVE])
725 return EPP_INDEX_POWERSAVE;
726 *raw_epp = epp;
727 return 0;
728 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
729 /*
730 * Range:
731 * 0x00-0x03 : Performance
732 * 0x04-0x07 : Balance performance
733 * 0x08-0x0B : Balance power
734 * 0x0C-0x0F : Power
735 * The EPB is a 4 bit value, but our ranges restrict the
736 * value which can be set. Here only using top two bits
737 * effectively.
738 */
739 index = (epp >> 2) + 1;
740 }
741
742 return index;
743}
744
745static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
746{
747 int ret;
748
749 /*
750 * Use the cached HWP Request MSR value, because in the active mode the
751 * register itself may be updated by intel_pstate_hwp_boost_up() or
752 * intel_pstate_hwp_boost_down() at any time.
753 */
754 u64 value = READ_ONCE(cpu->hwp_req_cached);
755
756 value &= ~GENMASK_ULL(31, 24);
757 value |= (u64)epp << 24;
758 /*
759 * The only other updater of hwp_req_cached in the active mode,
760 * intel_pstate_hwp_set(), is called under the same lock as this
761 * function, so it cannot run in parallel with the update below.
762 */
763 WRITE_ONCE(cpu->hwp_req_cached, value);
764 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
765 if (!ret)
766 cpu->epp_cached = epp;
767
768 return ret;
769}
770
771static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
772 int pref_index, bool use_raw,
773 u32 raw_epp)
774{
775 int epp = -EINVAL;
776 int ret;
777
778 if (!pref_index)
779 epp = cpu_data->epp_default;
780
781 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
782 if (use_raw)
783 epp = raw_epp;
784 else if (epp == -EINVAL)
785 epp = epp_values[pref_index];
786
787 /*
788 * To avoid confusion, refuse to set EPP to any values different
789 * from 0 (performance) if the current policy is "performance",
790 * because those values would be overridden.
791 */
792 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
793 return -EBUSY;
794
795 ret = intel_pstate_set_epp(cpu_data, epp);
796 } else {
797 if (epp == -EINVAL)
798 epp = (pref_index - 1) << 2;
799 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
800 }
801
802 return ret;
803}
804
805static ssize_t show_energy_performance_available_preferences(
806 struct cpufreq_policy *policy, char *buf)
807{
808 int i = 0;
809 int ret = 0;
810
811 while (energy_perf_strings[i] != NULL)
812 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
813
814 ret += sprintf(&buf[ret], "\n");
815
816 return ret;
817}
818
819cpufreq_freq_attr_ro(energy_performance_available_preferences);
820
821static struct cpufreq_driver intel_pstate;
822
823static ssize_t store_energy_performance_preference(
824 struct cpufreq_policy *policy, const char *buf, size_t count)
825{
826 struct cpudata *cpu = all_cpu_data[policy->cpu];
827 char str_preference[21];
828 bool raw = false;
829 ssize_t ret;
830 u32 epp = 0;
831
832 ret = sscanf(buf, "%20s", str_preference);
833 if (ret != 1)
834 return -EINVAL;
835
836 ret = match_string(energy_perf_strings, -1, str_preference);
837 if (ret < 0) {
838 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
839 return ret;
840
841 ret = kstrtouint(buf, 10, &epp);
842 if (ret)
843 return ret;
844
845 if (epp > 255)
846 return -EINVAL;
847
848 raw = true;
849 }
850
851 /*
852 * This function runs with the policy R/W semaphore held, which
853 * guarantees that the driver pointer will not change while it is
854 * running.
855 */
856 if (!intel_pstate_driver)
857 return -EAGAIN;
858
859 mutex_lock(&intel_pstate_limits_lock);
860
861 if (intel_pstate_driver == &intel_pstate) {
862 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
863 } else {
864 /*
865 * In the passive mode the governor needs to be stopped on the
866 * target CPU before the EPP update and restarted after it,
867 * which is super-heavy-weight, so make sure it is worth doing
868 * upfront.
869 */
870 if (!raw)
871 epp = ret ? epp_values[ret] : cpu->epp_default;
872
873 if (cpu->epp_cached != epp) {
874 int err;
875
876 cpufreq_stop_governor(policy);
877 ret = intel_pstate_set_epp(cpu, epp);
878 err = cpufreq_start_governor(policy);
879 if (!ret)
880 ret = err;
881 } else {
882 ret = 0;
883 }
884 }
885
886 mutex_unlock(&intel_pstate_limits_lock);
887
888 return ret ?: count;
889}
890
891static ssize_t show_energy_performance_preference(
892 struct cpufreq_policy *policy, char *buf)
893{
894 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
895 int preference, raw_epp;
896
897 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
898 if (preference < 0)
899 return preference;
900
901 if (raw_epp)
902 return sprintf(buf, "%d\n", raw_epp);
903 else
904 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
905}
906
907cpufreq_freq_attr_rw(energy_performance_preference);
908
909static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
910{
911 struct cpudata *cpu = all_cpu_data[policy->cpu];
912 int ratio, freq;
913
914 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
915 if (ratio <= 0) {
916 u64 cap;
917
918 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
919 ratio = HWP_GUARANTEED_PERF(cap);
920 }
921
922 freq = ratio * cpu->pstate.scaling;
923 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
924 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
925
926 return sprintf(buf, "%d\n", freq);
927}
928
929cpufreq_freq_attr_ro(base_frequency);
930
931static struct freq_attr *hwp_cpufreq_attrs[] = {
932 &energy_performance_preference,
933 &energy_performance_available_preferences,
934 &base_frequency,
935 NULL,
936};
937
938static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
939{
940 u64 cap;
941
942 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
943 WRITE_ONCE(cpu->hwp_cap_cached, cap);
944 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
945 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
946}
947
948static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
949{
950 int scaling = cpu->pstate.scaling;
951
952 __intel_pstate_get_hwp_cap(cpu);
953
954 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
955 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
956 if (scaling != cpu->pstate.perf_ctl_scaling) {
957 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
958
959 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
960 perf_ctl_scaling);
961 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
962 perf_ctl_scaling);
963 }
964}
965
966static void intel_pstate_hwp_set(unsigned int cpu)
967{
968 struct cpudata *cpu_data = all_cpu_data[cpu];
969 int max, min;
970 u64 value;
971 s16 epp;
972
973 max = cpu_data->max_perf_ratio;
974 min = cpu_data->min_perf_ratio;
975
976 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
977 min = max;
978
979 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
980
981 value &= ~HWP_MIN_PERF(~0L);
982 value |= HWP_MIN_PERF(min);
983
984 value &= ~HWP_MAX_PERF(~0L);
985 value |= HWP_MAX_PERF(max);
986
987 if (cpu_data->epp_policy == cpu_data->policy)
988 goto skip_epp;
989
990 cpu_data->epp_policy = cpu_data->policy;
991
992 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
993 epp = intel_pstate_get_epp(cpu_data, value);
994 cpu_data->epp_powersave = epp;
995 /* If EPP read was failed, then don't try to write */
996 if (epp < 0)
997 goto skip_epp;
998
999 epp = 0;
1000 } else {
1001 /* skip setting EPP, when saved value is invalid */
1002 if (cpu_data->epp_powersave < 0)
1003 goto skip_epp;
1004
1005 /*
1006 * No need to restore EPP when it is not zero. This
1007 * means:
1008 * - Policy is not changed
1009 * - user has manually changed
1010 * - Error reading EPB
1011 */
1012 epp = intel_pstate_get_epp(cpu_data, value);
1013 if (epp)
1014 goto skip_epp;
1015
1016 epp = cpu_data->epp_powersave;
1017 }
1018 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1019 value &= ~GENMASK_ULL(31, 24);
1020 value |= (u64)epp << 24;
1021 } else {
1022 intel_pstate_set_epb(cpu, epp);
1023 }
1024skip_epp:
1025 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1026 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1027}
1028
1029static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1030
1031static void intel_pstate_hwp_offline(struct cpudata *cpu)
1032{
1033 u64 value = READ_ONCE(cpu->hwp_req_cached);
1034 int min_perf;
1035
1036 intel_pstate_disable_hwp_interrupt(cpu);
1037
1038 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1039 /*
1040 * In case the EPP has been set to "performance" by the
1041 * active mode "performance" scaling algorithm, replace that
1042 * temporary value with the cached EPP one.
1043 */
1044 value &= ~GENMASK_ULL(31, 24);
1045 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1046 /*
1047 * However, make sure that EPP will be set to "performance" when
1048 * the CPU is brought back online again and the "performance"
1049 * scaling algorithm is still in effect.
1050 */
1051 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1052 }
1053
1054 /*
1055 * Clear the desired perf field in the cached HWP request value to
1056 * prevent nonzero desired values from being leaked into the active
1057 * mode.
1058 */
1059 value &= ~HWP_DESIRED_PERF(~0L);
1060 WRITE_ONCE(cpu->hwp_req_cached, value);
1061
1062 value &= ~GENMASK_ULL(31, 0);
1063 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1064
1065 /* Set hwp_max = hwp_min */
1066 value |= HWP_MAX_PERF(min_perf);
1067 value |= HWP_MIN_PERF(min_perf);
1068
1069 /* Set EPP to min */
1070 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1071 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1072
1073 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1074}
1075
1076#define POWER_CTL_EE_ENABLE 1
1077#define POWER_CTL_EE_DISABLE 2
1078
1079static int power_ctl_ee_state;
1080
1081static void set_power_ctl_ee_state(bool input)
1082{
1083 u64 power_ctl;
1084
1085 mutex_lock(&intel_pstate_driver_lock);
1086 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1087 if (input) {
1088 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1089 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1090 } else {
1091 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1092 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1093 }
1094 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1095 mutex_unlock(&intel_pstate_driver_lock);
1096}
1097
1098static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1099
1100static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1101{
1102 intel_pstate_hwp_enable(cpu);
1103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1104}
1105
1106static int intel_pstate_suspend(struct cpufreq_policy *policy)
1107{
1108 struct cpudata *cpu = all_cpu_data[policy->cpu];
1109
1110 pr_debug("CPU %d suspending\n", cpu->cpu);
1111
1112 cpu->suspended = true;
1113
1114 /* disable HWP interrupt and cancel any pending work */
1115 intel_pstate_disable_hwp_interrupt(cpu);
1116
1117 return 0;
1118}
1119
1120static int intel_pstate_resume(struct cpufreq_policy *policy)
1121{
1122 struct cpudata *cpu = all_cpu_data[policy->cpu];
1123
1124 pr_debug("CPU %d resuming\n", cpu->cpu);
1125
1126 /* Only restore if the system default is changed */
1127 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1128 set_power_ctl_ee_state(true);
1129 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1130 set_power_ctl_ee_state(false);
1131
1132 if (cpu->suspended && hwp_active) {
1133 mutex_lock(&intel_pstate_limits_lock);
1134
1135 /* Re-enable HWP, because "online" has not done that. */
1136 intel_pstate_hwp_reenable(cpu);
1137
1138 mutex_unlock(&intel_pstate_limits_lock);
1139 }
1140
1141 cpu->suspended = false;
1142
1143 return 0;
1144}
1145
1146static void intel_pstate_update_policies(void)
1147{
1148 int cpu;
1149
1150 for_each_possible_cpu(cpu)
1151 cpufreq_update_policy(cpu);
1152}
1153
1154static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1155 struct cpufreq_policy *policy)
1156{
1157 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1158 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1159 refresh_frequency_limits(policy);
1160}
1161
1162static void intel_pstate_update_max_freq(unsigned int cpu)
1163{
1164 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1165
1166 if (!policy)
1167 return;
1168
1169 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1170
1171 cpufreq_cpu_release(policy);
1172}
1173
1174static void intel_pstate_update_limits(unsigned int cpu)
1175{
1176 mutex_lock(&intel_pstate_driver_lock);
1177
1178 update_turbo_state();
1179 /*
1180 * If turbo has been turned on or off globally, policy limits for
1181 * all CPUs need to be updated to reflect that.
1182 */
1183 if (global.turbo_disabled_mf != global.turbo_disabled) {
1184 global.turbo_disabled_mf = global.turbo_disabled;
1185 arch_set_max_freq_ratio(global.turbo_disabled);
1186 for_each_possible_cpu(cpu)
1187 intel_pstate_update_max_freq(cpu);
1188 } else {
1189 cpufreq_update_policy(cpu);
1190 }
1191
1192 mutex_unlock(&intel_pstate_driver_lock);
1193}
1194
1195/************************** sysfs begin ************************/
1196#define show_one(file_name, object) \
1197 static ssize_t show_##file_name \
1198 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1199 { \
1200 return sprintf(buf, "%u\n", global.object); \
1201 }
1202
1203static ssize_t intel_pstate_show_status(char *buf);
1204static int intel_pstate_update_status(const char *buf, size_t size);
1205
1206static ssize_t show_status(struct kobject *kobj,
1207 struct kobj_attribute *attr, char *buf)
1208{
1209 ssize_t ret;
1210
1211 mutex_lock(&intel_pstate_driver_lock);
1212 ret = intel_pstate_show_status(buf);
1213 mutex_unlock(&intel_pstate_driver_lock);
1214
1215 return ret;
1216}
1217
1218static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1219 const char *buf, size_t count)
1220{
1221 char *p = memchr(buf, '\n', count);
1222 int ret;
1223
1224 mutex_lock(&intel_pstate_driver_lock);
1225 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1226 mutex_unlock(&intel_pstate_driver_lock);
1227
1228 return ret < 0 ? ret : count;
1229}
1230
1231static ssize_t show_turbo_pct(struct kobject *kobj,
1232 struct kobj_attribute *attr, char *buf)
1233{
1234 struct cpudata *cpu;
1235 int total, no_turbo, turbo_pct;
1236 uint32_t turbo_fp;
1237
1238 mutex_lock(&intel_pstate_driver_lock);
1239
1240 if (!intel_pstate_driver) {
1241 mutex_unlock(&intel_pstate_driver_lock);
1242 return -EAGAIN;
1243 }
1244
1245 cpu = all_cpu_data[0];
1246
1247 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1248 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1249 turbo_fp = div_fp(no_turbo, total);
1250 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1251
1252 mutex_unlock(&intel_pstate_driver_lock);
1253
1254 return sprintf(buf, "%u\n", turbo_pct);
1255}
1256
1257static ssize_t show_num_pstates(struct kobject *kobj,
1258 struct kobj_attribute *attr, char *buf)
1259{
1260 struct cpudata *cpu;
1261 int total;
1262
1263 mutex_lock(&intel_pstate_driver_lock);
1264
1265 if (!intel_pstate_driver) {
1266 mutex_unlock(&intel_pstate_driver_lock);
1267 return -EAGAIN;
1268 }
1269
1270 cpu = all_cpu_data[0];
1271 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1272
1273 mutex_unlock(&intel_pstate_driver_lock);
1274
1275 return sprintf(buf, "%u\n", total);
1276}
1277
1278static ssize_t show_no_turbo(struct kobject *kobj,
1279 struct kobj_attribute *attr, char *buf)
1280{
1281 ssize_t ret;
1282
1283 mutex_lock(&intel_pstate_driver_lock);
1284
1285 if (!intel_pstate_driver) {
1286 mutex_unlock(&intel_pstate_driver_lock);
1287 return -EAGAIN;
1288 }
1289
1290 update_turbo_state();
1291 if (global.turbo_disabled)
1292 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1293 else
1294 ret = sprintf(buf, "%u\n", global.no_turbo);
1295
1296 mutex_unlock(&intel_pstate_driver_lock);
1297
1298 return ret;
1299}
1300
1301static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1302 const char *buf, size_t count)
1303{
1304 unsigned int input;
1305 int ret;
1306
1307 ret = sscanf(buf, "%u", &input);
1308 if (ret != 1)
1309 return -EINVAL;
1310
1311 mutex_lock(&intel_pstate_driver_lock);
1312
1313 if (!intel_pstate_driver) {
1314 mutex_unlock(&intel_pstate_driver_lock);
1315 return -EAGAIN;
1316 }
1317
1318 mutex_lock(&intel_pstate_limits_lock);
1319
1320 update_turbo_state();
1321 if (global.turbo_disabled) {
1322 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1323 mutex_unlock(&intel_pstate_limits_lock);
1324 mutex_unlock(&intel_pstate_driver_lock);
1325 return -EPERM;
1326 }
1327
1328 global.no_turbo = clamp_t(int, input, 0, 1);
1329
1330 if (global.no_turbo) {
1331 struct cpudata *cpu = all_cpu_data[0];
1332 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1333
1334 /* Squash the global minimum into the permitted range. */
1335 if (global.min_perf_pct > pct)
1336 global.min_perf_pct = pct;
1337 }
1338
1339 mutex_unlock(&intel_pstate_limits_lock);
1340
1341 intel_pstate_update_policies();
1342 arch_set_max_freq_ratio(global.no_turbo);
1343
1344 mutex_unlock(&intel_pstate_driver_lock);
1345
1346 return count;
1347}
1348
1349static void update_qos_request(enum freq_qos_req_type type)
1350{
1351 struct freq_qos_request *req;
1352 struct cpufreq_policy *policy;
1353 int i;
1354
1355 for_each_possible_cpu(i) {
1356 struct cpudata *cpu = all_cpu_data[i];
1357 unsigned int freq, perf_pct;
1358
1359 policy = cpufreq_cpu_get(i);
1360 if (!policy)
1361 continue;
1362
1363 req = policy->driver_data;
1364 cpufreq_cpu_put(policy);
1365
1366 if (!req)
1367 continue;
1368
1369 if (hwp_active)
1370 intel_pstate_get_hwp_cap(cpu);
1371
1372 if (type == FREQ_QOS_MIN) {
1373 perf_pct = global.min_perf_pct;
1374 } else {
1375 req++;
1376 perf_pct = global.max_perf_pct;
1377 }
1378
1379 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1380
1381 if (freq_qos_update_request(req, freq) < 0)
1382 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1383 }
1384}
1385
1386static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1387 const char *buf, size_t count)
1388{
1389 unsigned int input;
1390 int ret;
1391
1392 ret = sscanf(buf, "%u", &input);
1393 if (ret != 1)
1394 return -EINVAL;
1395
1396 mutex_lock(&intel_pstate_driver_lock);
1397
1398 if (!intel_pstate_driver) {
1399 mutex_unlock(&intel_pstate_driver_lock);
1400 return -EAGAIN;
1401 }
1402
1403 mutex_lock(&intel_pstate_limits_lock);
1404
1405 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1406
1407 mutex_unlock(&intel_pstate_limits_lock);
1408
1409 if (intel_pstate_driver == &intel_pstate)
1410 intel_pstate_update_policies();
1411 else
1412 update_qos_request(FREQ_QOS_MAX);
1413
1414 mutex_unlock(&intel_pstate_driver_lock);
1415
1416 return count;
1417}
1418
1419static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1420 const char *buf, size_t count)
1421{
1422 unsigned int input;
1423 int ret;
1424
1425 ret = sscanf(buf, "%u", &input);
1426 if (ret != 1)
1427 return -EINVAL;
1428
1429 mutex_lock(&intel_pstate_driver_lock);
1430
1431 if (!intel_pstate_driver) {
1432 mutex_unlock(&intel_pstate_driver_lock);
1433 return -EAGAIN;
1434 }
1435
1436 mutex_lock(&intel_pstate_limits_lock);
1437
1438 global.min_perf_pct = clamp_t(int, input,
1439 min_perf_pct_min(), global.max_perf_pct);
1440
1441 mutex_unlock(&intel_pstate_limits_lock);
1442
1443 if (intel_pstate_driver == &intel_pstate)
1444 intel_pstate_update_policies();
1445 else
1446 update_qos_request(FREQ_QOS_MIN);
1447
1448 mutex_unlock(&intel_pstate_driver_lock);
1449
1450 return count;
1451}
1452
1453static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1454 struct kobj_attribute *attr, char *buf)
1455{
1456 return sprintf(buf, "%u\n", hwp_boost);
1457}
1458
1459static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1460 struct kobj_attribute *b,
1461 const char *buf, size_t count)
1462{
1463 unsigned int input;
1464 int ret;
1465
1466 ret = kstrtouint(buf, 10, &input);
1467 if (ret)
1468 return ret;
1469
1470 mutex_lock(&intel_pstate_driver_lock);
1471 hwp_boost = !!input;
1472 intel_pstate_update_policies();
1473 mutex_unlock(&intel_pstate_driver_lock);
1474
1475 return count;
1476}
1477
1478static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1479 char *buf)
1480{
1481 u64 power_ctl;
1482 int enable;
1483
1484 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1485 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1486 return sprintf(buf, "%d\n", !enable);
1487}
1488
1489static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1490 const char *buf, size_t count)
1491{
1492 bool input;
1493 int ret;
1494
1495 ret = kstrtobool(buf, &input);
1496 if (ret)
1497 return ret;
1498
1499 set_power_ctl_ee_state(input);
1500
1501 return count;
1502}
1503
1504show_one(max_perf_pct, max_perf_pct);
1505show_one(min_perf_pct, min_perf_pct);
1506
1507define_one_global_rw(status);
1508define_one_global_rw(no_turbo);
1509define_one_global_rw(max_perf_pct);
1510define_one_global_rw(min_perf_pct);
1511define_one_global_ro(turbo_pct);
1512define_one_global_ro(num_pstates);
1513define_one_global_rw(hwp_dynamic_boost);
1514define_one_global_rw(energy_efficiency);
1515
1516static struct attribute *intel_pstate_attributes[] = {
1517 &status.attr,
1518 &no_turbo.attr,
1519 NULL
1520};
1521
1522static const struct attribute_group intel_pstate_attr_group = {
1523 .attrs = intel_pstate_attributes,
1524};
1525
1526static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1527
1528static struct kobject *intel_pstate_kobject;
1529
1530static void __init intel_pstate_sysfs_expose_params(void)
1531{
1532 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1533 int rc;
1534
1535 if (dev_root) {
1536 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1537 put_device(dev_root);
1538 }
1539 if (WARN_ON(!intel_pstate_kobject))
1540 return;
1541
1542 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1543 if (WARN_ON(rc))
1544 return;
1545
1546 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1547 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1548 WARN_ON(rc);
1549
1550 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1551 WARN_ON(rc);
1552 }
1553
1554 /*
1555 * If per cpu limits are enforced there are no global limits, so
1556 * return without creating max/min_perf_pct attributes
1557 */
1558 if (per_cpu_limits)
1559 return;
1560
1561 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1562 WARN_ON(rc);
1563
1564 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1565 WARN_ON(rc);
1566
1567 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1568 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1569 WARN_ON(rc);
1570 }
1571}
1572
1573static void __init intel_pstate_sysfs_remove(void)
1574{
1575 if (!intel_pstate_kobject)
1576 return;
1577
1578 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1579
1580 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1581 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1582 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1583 }
1584
1585 if (!per_cpu_limits) {
1586 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1587 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1588
1589 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1590 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1591 }
1592
1593 kobject_put(intel_pstate_kobject);
1594}
1595
1596static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1597{
1598 int rc;
1599
1600 if (!hwp_active)
1601 return;
1602
1603 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1604 WARN_ON_ONCE(rc);
1605}
1606
1607static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1608{
1609 if (!hwp_active)
1610 return;
1611
1612 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1613}
1614
1615/************************** sysfs end ************************/
1616
1617static void intel_pstate_notify_work(struct work_struct *work)
1618{
1619 struct cpudata *cpudata =
1620 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1621 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1622
1623 if (policy) {
1624 intel_pstate_get_hwp_cap(cpudata);
1625 __intel_pstate_update_max_freq(cpudata, policy);
1626
1627 cpufreq_cpu_release(policy);
1628 }
1629
1630 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1631}
1632
1633static DEFINE_SPINLOCK(hwp_notify_lock);
1634static cpumask_t hwp_intr_enable_mask;
1635
1636void notify_hwp_interrupt(void)
1637{
1638 unsigned int this_cpu = smp_processor_id();
1639 struct cpudata *cpudata;
1640 unsigned long flags;
1641 u64 value;
1642
1643 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1644 return;
1645
1646 rdmsrl_safe(MSR_HWP_STATUS, &value);
1647 if (!(value & 0x01))
1648 return;
1649
1650 spin_lock_irqsave(&hwp_notify_lock, flags);
1651
1652 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1653 goto ack_intr;
1654
1655 /*
1656 * Currently we never free all_cpu_data. And we can't reach here
1657 * without this allocated. But for safety for future changes, added
1658 * check.
1659 */
1660 if (unlikely(!READ_ONCE(all_cpu_data)))
1661 goto ack_intr;
1662
1663 /*
1664 * The free is done during cleanup, when cpufreq registry is failed.
1665 * We wouldn't be here if it fails on init or switch status. But for
1666 * future changes, added check.
1667 */
1668 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1669 if (unlikely(!cpudata))
1670 goto ack_intr;
1671
1672 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1673
1674 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1675
1676 return;
1677
1678ack_intr:
1679 wrmsrl_safe(MSR_HWP_STATUS, 0);
1680 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1681}
1682
1683static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1684{
1685 unsigned long flags;
1686
1687 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1688 return;
1689
1690 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1691 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1692
1693 spin_lock_irqsave(&hwp_notify_lock, flags);
1694 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1695 cancel_delayed_work(&cpudata->hwp_notify_work);
1696 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1697}
1698
1699static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1700{
1701 /* Enable HWP notification interrupt for guaranteed performance change */
1702 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1703 unsigned long flags;
1704
1705 spin_lock_irqsave(&hwp_notify_lock, flags);
1706 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1707 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1708 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1709
1710 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1711 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1712 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1713 }
1714}
1715
1716static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1717{
1718 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1719
1720 /*
1721 * If the EPP is set by firmware, which means that firmware enabled HWP
1722 * - Is equal or less than 0x80 (default balance_perf EPP)
1723 * - But less performance oriented than performance EPP
1724 * then use this as new balance_perf EPP.
1725 */
1726 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1727 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1728 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1729 return;
1730 }
1731
1732 /*
1733 * If this CPU gen doesn't call for change in balance_perf
1734 * EPP return.
1735 */
1736 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1737 return;
1738
1739 /*
1740 * Use hard coded value per gen to update the balance_perf
1741 * and default EPP.
1742 */
1743 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1744 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1745}
1746
1747static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1748{
1749 /* First disable HWP notification interrupt till we activate again */
1750 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1751 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1752
1753 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1754
1755 intel_pstate_enable_hwp_interrupt(cpudata);
1756
1757 if (cpudata->epp_default >= 0)
1758 return;
1759
1760 intel_pstate_update_epp_defaults(cpudata);
1761}
1762
1763static int atom_get_min_pstate(int not_used)
1764{
1765 u64 value;
1766
1767 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1768 return (value >> 8) & 0x7F;
1769}
1770
1771static int atom_get_max_pstate(int not_used)
1772{
1773 u64 value;
1774
1775 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1776 return (value >> 16) & 0x7F;
1777}
1778
1779static int atom_get_turbo_pstate(int not_used)
1780{
1781 u64 value;
1782
1783 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1784 return value & 0x7F;
1785}
1786
1787static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1788{
1789 u64 val;
1790 int32_t vid_fp;
1791 u32 vid;
1792
1793 val = (u64)pstate << 8;
1794 if (global.no_turbo && !global.turbo_disabled)
1795 val |= (u64)1 << 32;
1796
1797 vid_fp = cpudata->vid.min + mul_fp(
1798 int_tofp(pstate - cpudata->pstate.min_pstate),
1799 cpudata->vid.ratio);
1800
1801 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1802 vid = ceiling_fp(vid_fp);
1803
1804 if (pstate > cpudata->pstate.max_pstate)
1805 vid = cpudata->vid.turbo;
1806
1807 return val | vid;
1808}
1809
1810static int silvermont_get_scaling(void)
1811{
1812 u64 value;
1813 int i;
1814 /* Defined in Table 35-6 from SDM (Sept 2015) */
1815 static int silvermont_freq_table[] = {
1816 83300, 100000, 133300, 116700, 80000};
1817
1818 rdmsrl(MSR_FSB_FREQ, value);
1819 i = value & 0x7;
1820 WARN_ON(i > 4);
1821
1822 return silvermont_freq_table[i];
1823}
1824
1825static int airmont_get_scaling(void)
1826{
1827 u64 value;
1828 int i;
1829 /* Defined in Table 35-10 from SDM (Sept 2015) */
1830 static int airmont_freq_table[] = {
1831 83300, 100000, 133300, 116700, 80000,
1832 93300, 90000, 88900, 87500};
1833
1834 rdmsrl(MSR_FSB_FREQ, value);
1835 i = value & 0xF;
1836 WARN_ON(i > 8);
1837
1838 return airmont_freq_table[i];
1839}
1840
1841static void atom_get_vid(struct cpudata *cpudata)
1842{
1843 u64 value;
1844
1845 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1846 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1847 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1848 cpudata->vid.ratio = div_fp(
1849 cpudata->vid.max - cpudata->vid.min,
1850 int_tofp(cpudata->pstate.max_pstate -
1851 cpudata->pstate.min_pstate));
1852
1853 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1854 cpudata->vid.turbo = value & 0x7f;
1855}
1856
1857static int core_get_min_pstate(int cpu)
1858{
1859 u64 value;
1860
1861 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1862 return (value >> 40) & 0xFF;
1863}
1864
1865static int core_get_max_pstate_physical(int cpu)
1866{
1867 u64 value;
1868
1869 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1870 return (value >> 8) & 0xFF;
1871}
1872
1873static int core_get_tdp_ratio(int cpu, u64 plat_info)
1874{
1875 /* Check how many TDP levels present */
1876 if (plat_info & 0x600000000) {
1877 u64 tdp_ctrl;
1878 u64 tdp_ratio;
1879 int tdp_msr;
1880 int err;
1881
1882 /* Get the TDP level (0, 1, 2) to get ratios */
1883 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1884 if (err)
1885 return err;
1886
1887 /* TDP MSR are continuous starting at 0x648 */
1888 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1889 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1890 if (err)
1891 return err;
1892
1893 /* For level 1 and 2, bits[23:16] contain the ratio */
1894 if (tdp_ctrl & 0x03)
1895 tdp_ratio >>= 16;
1896
1897 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1898 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1899
1900 return (int)tdp_ratio;
1901 }
1902
1903 return -ENXIO;
1904}
1905
1906static int core_get_max_pstate(int cpu)
1907{
1908 u64 tar;
1909 u64 plat_info;
1910 int max_pstate;
1911 int tdp_ratio;
1912 int err;
1913
1914 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1915 max_pstate = (plat_info >> 8) & 0xFF;
1916
1917 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1918 if (tdp_ratio <= 0)
1919 return max_pstate;
1920
1921 if (hwp_active) {
1922 /* Turbo activation ratio is not used on HWP platforms */
1923 return tdp_ratio;
1924 }
1925
1926 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1927 if (!err) {
1928 int tar_levels;
1929
1930 /* Do some sanity checking for safety */
1931 tar_levels = tar & 0xff;
1932 if (tdp_ratio - 1 == tar_levels) {
1933 max_pstate = tar_levels;
1934 pr_debug("max_pstate=TAC %x\n", max_pstate);
1935 }
1936 }
1937
1938 return max_pstate;
1939}
1940
1941static int core_get_turbo_pstate(int cpu)
1942{
1943 u64 value;
1944 int nont, ret;
1945
1946 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1947 nont = core_get_max_pstate(cpu);
1948 ret = (value) & 255;
1949 if (ret <= nont)
1950 ret = nont;
1951 return ret;
1952}
1953
1954static u64 core_get_val(struct cpudata *cpudata, int pstate)
1955{
1956 u64 val;
1957
1958 val = (u64)pstate << 8;
1959 if (global.no_turbo && !global.turbo_disabled)
1960 val |= (u64)1 << 32;
1961
1962 return val;
1963}
1964
1965static int knl_get_aperf_mperf_shift(void)
1966{
1967 return 10;
1968}
1969
1970static int knl_get_turbo_pstate(int cpu)
1971{
1972 u64 value;
1973 int nont, ret;
1974
1975 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1976 nont = core_get_max_pstate(cpu);
1977 ret = (((value) >> 8) & 0xFF);
1978 if (ret <= nont)
1979 ret = nont;
1980 return ret;
1981}
1982
1983static void hybrid_get_type(void *data)
1984{
1985 u8 *cpu_type = data;
1986
1987 *cpu_type = get_this_hybrid_cpu_type();
1988}
1989
1990static int hwp_get_cpu_scaling(int cpu)
1991{
1992 u8 cpu_type = 0;
1993
1994 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1995 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1996 if (cpu_type == 0x40)
1997 return hybrid_scaling_factor;
1998
1999 /* Use default core scaling for E-cores */
2000 if (cpu_type == 0x20)
2001 return core_get_scaling();
2002
2003 /*
2004 * If reached here, this system is either non-hybrid (like Tiger
2005 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2006 * no E cores (in which case CPUID for hybrid support is 0).
2007 *
2008 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2009 * so the default core scaling will be used for them.
2010 */
2011 return intel_pstate_cppc_get_scaling(cpu);
2012}
2013
2014static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2015{
2016 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2017 cpu->pstate.current_pstate = pstate;
2018 /*
2019 * Generally, there is no guarantee that this code will always run on
2020 * the CPU being updated, so force the register update to run on the
2021 * right CPU.
2022 */
2023 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2024 pstate_funcs.get_val(cpu, pstate));
2025}
2026
2027static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2028{
2029 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2030}
2031
2032static void intel_pstate_max_within_limits(struct cpudata *cpu)
2033{
2034 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2035
2036 update_turbo_state();
2037 intel_pstate_set_pstate(cpu, pstate);
2038}
2039
2040static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2041{
2042 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2043 int perf_ctl_scaling = pstate_funcs.get_scaling();
2044
2045 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2046 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2047 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2048
2049 if (hwp_active && !hwp_mode_bdw) {
2050 __intel_pstate_get_hwp_cap(cpu);
2051
2052 if (pstate_funcs.get_cpu_scaling) {
2053 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2054 if (cpu->pstate.scaling != perf_ctl_scaling)
2055 intel_pstate_hybrid_hwp_adjust(cpu);
2056 } else {
2057 cpu->pstate.scaling = perf_ctl_scaling;
2058 }
2059 } else {
2060 cpu->pstate.scaling = perf_ctl_scaling;
2061 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2062 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2063 }
2064
2065 if (cpu->pstate.scaling == perf_ctl_scaling) {
2066 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2067 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2068 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2069 }
2070
2071 if (pstate_funcs.get_aperf_mperf_shift)
2072 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2073
2074 if (pstate_funcs.get_vid)
2075 pstate_funcs.get_vid(cpu);
2076
2077 intel_pstate_set_min_pstate(cpu);
2078}
2079
2080/*
2081 * Long hold time will keep high perf limits for long time,
2082 * which negatively impacts perf/watt for some workloads,
2083 * like specpower. 3ms is based on experiements on some
2084 * workoads.
2085 */
2086static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2087
2088static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2089{
2090 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2091 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2092 u32 max_limit = (hwp_req & 0xff00) >> 8;
2093 u32 min_limit = (hwp_req & 0xff);
2094 u32 boost_level1;
2095
2096 /*
2097 * Cases to consider (User changes via sysfs or boot time):
2098 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2099 * No boost, return.
2100 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2101 * Should result in one level boost only for P0.
2102 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2103 * Should result in two level boost:
2104 * (min + p1)/2 and P1.
2105 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2106 * Should result in three level boost:
2107 * (min + p1)/2, P1 and P0.
2108 */
2109
2110 /* If max and min are equal or already at max, nothing to boost */
2111 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2112 return;
2113
2114 if (!cpu->hwp_boost_min)
2115 cpu->hwp_boost_min = min_limit;
2116
2117 /* level at half way mark between min and guranteed */
2118 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2119
2120 if (cpu->hwp_boost_min < boost_level1)
2121 cpu->hwp_boost_min = boost_level1;
2122 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2123 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2124 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2125 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2126 cpu->hwp_boost_min = max_limit;
2127 else
2128 return;
2129
2130 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2131 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2132 cpu->last_update = cpu->sample.time;
2133}
2134
2135static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2136{
2137 if (cpu->hwp_boost_min) {
2138 bool expired;
2139
2140 /* Check if we are idle for hold time to boost down */
2141 expired = time_after64(cpu->sample.time, cpu->last_update +
2142 hwp_boost_hold_time_ns);
2143 if (expired) {
2144 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2145 cpu->hwp_boost_min = 0;
2146 }
2147 }
2148 cpu->last_update = cpu->sample.time;
2149}
2150
2151static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2152 u64 time)
2153{
2154 cpu->sample.time = time;
2155
2156 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2157 bool do_io = false;
2158
2159 cpu->sched_flags = 0;
2160 /*
2161 * Set iowait_boost flag and update time. Since IO WAIT flag
2162 * is set all the time, we can't just conclude that there is
2163 * some IO bound activity is scheduled on this CPU with just
2164 * one occurrence. If we receive at least two in two
2165 * consecutive ticks, then we treat as boost candidate.
2166 */
2167 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2168 do_io = true;
2169
2170 cpu->last_io_update = time;
2171
2172 if (do_io)
2173 intel_pstate_hwp_boost_up(cpu);
2174
2175 } else {
2176 intel_pstate_hwp_boost_down(cpu);
2177 }
2178}
2179
2180static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2181 u64 time, unsigned int flags)
2182{
2183 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2184
2185 cpu->sched_flags |= flags;
2186
2187 if (smp_processor_id() == cpu->cpu)
2188 intel_pstate_update_util_hwp_local(cpu, time);
2189}
2190
2191static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2192{
2193 struct sample *sample = &cpu->sample;
2194
2195 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2196}
2197
2198static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2199{
2200 u64 aperf, mperf;
2201 unsigned long flags;
2202 u64 tsc;
2203
2204 local_irq_save(flags);
2205 rdmsrl(MSR_IA32_APERF, aperf);
2206 rdmsrl(MSR_IA32_MPERF, mperf);
2207 tsc = rdtsc();
2208 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2209 local_irq_restore(flags);
2210 return false;
2211 }
2212 local_irq_restore(flags);
2213
2214 cpu->last_sample_time = cpu->sample.time;
2215 cpu->sample.time = time;
2216 cpu->sample.aperf = aperf;
2217 cpu->sample.mperf = mperf;
2218 cpu->sample.tsc = tsc;
2219 cpu->sample.aperf -= cpu->prev_aperf;
2220 cpu->sample.mperf -= cpu->prev_mperf;
2221 cpu->sample.tsc -= cpu->prev_tsc;
2222
2223 cpu->prev_aperf = aperf;
2224 cpu->prev_mperf = mperf;
2225 cpu->prev_tsc = tsc;
2226 /*
2227 * First time this function is invoked in a given cycle, all of the
2228 * previous sample data fields are equal to zero or stale and they must
2229 * be populated with meaningful numbers for things to work, so assume
2230 * that sample.time will always be reset before setting the utilization
2231 * update hook and make the caller skip the sample then.
2232 */
2233 if (cpu->last_sample_time) {
2234 intel_pstate_calc_avg_perf(cpu);
2235 return true;
2236 }
2237 return false;
2238}
2239
2240static inline int32_t get_avg_frequency(struct cpudata *cpu)
2241{
2242 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2243}
2244
2245static inline int32_t get_avg_pstate(struct cpudata *cpu)
2246{
2247 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2248 cpu->sample.core_avg_perf);
2249}
2250
2251static inline int32_t get_target_pstate(struct cpudata *cpu)
2252{
2253 struct sample *sample = &cpu->sample;
2254 int32_t busy_frac;
2255 int target, avg_pstate;
2256
2257 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2258 sample->tsc);
2259
2260 if (busy_frac < cpu->iowait_boost)
2261 busy_frac = cpu->iowait_boost;
2262
2263 sample->busy_scaled = busy_frac * 100;
2264
2265 target = global.no_turbo || global.turbo_disabled ?
2266 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2267 target += target >> 2;
2268 target = mul_fp(target, busy_frac);
2269 if (target < cpu->pstate.min_pstate)
2270 target = cpu->pstate.min_pstate;
2271
2272 /*
2273 * If the average P-state during the previous cycle was higher than the
2274 * current target, add 50% of the difference to the target to reduce
2275 * possible performance oscillations and offset possible performance
2276 * loss related to moving the workload from one CPU to another within
2277 * a package/module.
2278 */
2279 avg_pstate = get_avg_pstate(cpu);
2280 if (avg_pstate > target)
2281 target += (avg_pstate - target) >> 1;
2282
2283 return target;
2284}
2285
2286static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2287{
2288 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2289 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2290
2291 return clamp_t(int, pstate, min_pstate, max_pstate);
2292}
2293
2294static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2295{
2296 if (pstate == cpu->pstate.current_pstate)
2297 return;
2298
2299 cpu->pstate.current_pstate = pstate;
2300 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2301}
2302
2303static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2304{
2305 int from = cpu->pstate.current_pstate;
2306 struct sample *sample;
2307 int target_pstate;
2308
2309 update_turbo_state();
2310
2311 target_pstate = get_target_pstate(cpu);
2312 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2313 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2314 intel_pstate_update_pstate(cpu, target_pstate);
2315
2316 sample = &cpu->sample;
2317 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2318 fp_toint(sample->busy_scaled),
2319 from,
2320 cpu->pstate.current_pstate,
2321 sample->mperf,
2322 sample->aperf,
2323 sample->tsc,
2324 get_avg_frequency(cpu),
2325 fp_toint(cpu->iowait_boost * 100));
2326}
2327
2328static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2329 unsigned int flags)
2330{
2331 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2332 u64 delta_ns;
2333
2334 /* Don't allow remote callbacks */
2335 if (smp_processor_id() != cpu->cpu)
2336 return;
2337
2338 delta_ns = time - cpu->last_update;
2339 if (flags & SCHED_CPUFREQ_IOWAIT) {
2340 /* Start over if the CPU may have been idle. */
2341 if (delta_ns > TICK_NSEC) {
2342 cpu->iowait_boost = ONE_EIGHTH_FP;
2343 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2344 cpu->iowait_boost <<= 1;
2345 if (cpu->iowait_boost > int_tofp(1))
2346 cpu->iowait_boost = int_tofp(1);
2347 } else {
2348 cpu->iowait_boost = ONE_EIGHTH_FP;
2349 }
2350 } else if (cpu->iowait_boost) {
2351 /* Clear iowait_boost if the CPU may have been idle. */
2352 if (delta_ns > TICK_NSEC)
2353 cpu->iowait_boost = 0;
2354 else
2355 cpu->iowait_boost >>= 1;
2356 }
2357 cpu->last_update = time;
2358 delta_ns = time - cpu->sample.time;
2359 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2360 return;
2361
2362 if (intel_pstate_sample(cpu, time))
2363 intel_pstate_adjust_pstate(cpu);
2364}
2365
2366static struct pstate_funcs core_funcs = {
2367 .get_max = core_get_max_pstate,
2368 .get_max_physical = core_get_max_pstate_physical,
2369 .get_min = core_get_min_pstate,
2370 .get_turbo = core_get_turbo_pstate,
2371 .get_scaling = core_get_scaling,
2372 .get_val = core_get_val,
2373};
2374
2375static const struct pstate_funcs silvermont_funcs = {
2376 .get_max = atom_get_max_pstate,
2377 .get_max_physical = atom_get_max_pstate,
2378 .get_min = atom_get_min_pstate,
2379 .get_turbo = atom_get_turbo_pstate,
2380 .get_val = atom_get_val,
2381 .get_scaling = silvermont_get_scaling,
2382 .get_vid = atom_get_vid,
2383};
2384
2385static const struct pstate_funcs airmont_funcs = {
2386 .get_max = atom_get_max_pstate,
2387 .get_max_physical = atom_get_max_pstate,
2388 .get_min = atom_get_min_pstate,
2389 .get_turbo = atom_get_turbo_pstate,
2390 .get_val = atom_get_val,
2391 .get_scaling = airmont_get_scaling,
2392 .get_vid = atom_get_vid,
2393};
2394
2395static const struct pstate_funcs knl_funcs = {
2396 .get_max = core_get_max_pstate,
2397 .get_max_physical = core_get_max_pstate_physical,
2398 .get_min = core_get_min_pstate,
2399 .get_turbo = knl_get_turbo_pstate,
2400 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2401 .get_scaling = core_get_scaling,
2402 .get_val = core_get_val,
2403};
2404
2405#define X86_MATCH(model, policy) \
2406 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2407 X86_FEATURE_APERFMPERF, &policy)
2408
2409static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2410 X86_MATCH(SANDYBRIDGE, core_funcs),
2411 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2412 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2413 X86_MATCH(IVYBRIDGE, core_funcs),
2414 X86_MATCH(HASWELL, core_funcs),
2415 X86_MATCH(BROADWELL, core_funcs),
2416 X86_MATCH(IVYBRIDGE_X, core_funcs),
2417 X86_MATCH(HASWELL_X, core_funcs),
2418 X86_MATCH(HASWELL_L, core_funcs),
2419 X86_MATCH(HASWELL_G, core_funcs),
2420 X86_MATCH(BROADWELL_G, core_funcs),
2421 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2422 X86_MATCH(SKYLAKE_L, core_funcs),
2423 X86_MATCH(BROADWELL_X, core_funcs),
2424 X86_MATCH(SKYLAKE, core_funcs),
2425 X86_MATCH(BROADWELL_D, core_funcs),
2426 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2427 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2428 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2429 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2430 X86_MATCH(SKYLAKE_X, core_funcs),
2431 X86_MATCH(COMETLAKE, core_funcs),
2432 X86_MATCH(ICELAKE_X, core_funcs),
2433 X86_MATCH(TIGERLAKE, core_funcs),
2434 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2435 X86_MATCH(EMERALDRAPIDS_X, core_funcs),
2436 {}
2437};
2438MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2439
2440static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2441 X86_MATCH(BROADWELL_D, core_funcs),
2442 X86_MATCH(BROADWELL_X, core_funcs),
2443 X86_MATCH(SKYLAKE_X, core_funcs),
2444 X86_MATCH(ICELAKE_X, core_funcs),
2445 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2446 {}
2447};
2448
2449static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2450 X86_MATCH(KABYLAKE, core_funcs),
2451 {}
2452};
2453
2454static int intel_pstate_init_cpu(unsigned int cpunum)
2455{
2456 struct cpudata *cpu;
2457
2458 cpu = all_cpu_data[cpunum];
2459
2460 if (!cpu) {
2461 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2462 if (!cpu)
2463 return -ENOMEM;
2464
2465 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2466
2467 cpu->cpu = cpunum;
2468
2469 cpu->epp_default = -EINVAL;
2470
2471 if (hwp_active) {
2472 intel_pstate_hwp_enable(cpu);
2473
2474 if (intel_pstate_acpi_pm_profile_server())
2475 hwp_boost = true;
2476 }
2477 } else if (hwp_active) {
2478 /*
2479 * Re-enable HWP in case this happens after a resume from ACPI
2480 * S3 if the CPU was offline during the whole system/resume
2481 * cycle.
2482 */
2483 intel_pstate_hwp_reenable(cpu);
2484 }
2485
2486 cpu->epp_powersave = -EINVAL;
2487 cpu->epp_policy = 0;
2488
2489 intel_pstate_get_cpu_pstates(cpu);
2490
2491 pr_debug("controlling: cpu %d\n", cpunum);
2492
2493 return 0;
2494}
2495
2496static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2497{
2498 struct cpudata *cpu = all_cpu_data[cpu_num];
2499
2500 if (hwp_active && !hwp_boost)
2501 return;
2502
2503 if (cpu->update_util_set)
2504 return;
2505
2506 /* Prevent intel_pstate_update_util() from using stale data. */
2507 cpu->sample.time = 0;
2508 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2509 (hwp_active ?
2510 intel_pstate_update_util_hwp :
2511 intel_pstate_update_util));
2512 cpu->update_util_set = true;
2513}
2514
2515static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2516{
2517 struct cpudata *cpu_data = all_cpu_data[cpu];
2518
2519 if (!cpu_data->update_util_set)
2520 return;
2521
2522 cpufreq_remove_update_util_hook(cpu);
2523 cpu_data->update_util_set = false;
2524 synchronize_rcu();
2525}
2526
2527static int intel_pstate_get_max_freq(struct cpudata *cpu)
2528{
2529 return global.turbo_disabled || global.no_turbo ?
2530 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2531}
2532
2533static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2534 unsigned int policy_min,
2535 unsigned int policy_max)
2536{
2537 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2538 int32_t max_policy_perf, min_policy_perf;
2539
2540 max_policy_perf = policy_max / perf_ctl_scaling;
2541 if (policy_max == policy_min) {
2542 min_policy_perf = max_policy_perf;
2543 } else {
2544 min_policy_perf = policy_min / perf_ctl_scaling;
2545 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2546 0, max_policy_perf);
2547 }
2548
2549 /*
2550 * HWP needs some special consideration, because HWP_REQUEST uses
2551 * abstract values to represent performance rather than pure ratios.
2552 */
2553 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2554 int freq;
2555
2556 freq = max_policy_perf * perf_ctl_scaling;
2557 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2558 freq = min_policy_perf * perf_ctl_scaling;
2559 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2560 }
2561
2562 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2563 cpu->cpu, min_policy_perf, max_policy_perf);
2564
2565 /* Normalize user input to [min_perf, max_perf] */
2566 if (per_cpu_limits) {
2567 cpu->min_perf_ratio = min_policy_perf;
2568 cpu->max_perf_ratio = max_policy_perf;
2569 } else {
2570 int turbo_max = cpu->pstate.turbo_pstate;
2571 int32_t global_min, global_max;
2572
2573 /* Global limits are in percent of the maximum turbo P-state. */
2574 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2575 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2576 global_min = clamp_t(int32_t, global_min, 0, global_max);
2577
2578 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2579 global_min, global_max);
2580
2581 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2582 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2583 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2584 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2585
2586 /* Make sure min_perf <= max_perf */
2587 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2588 cpu->max_perf_ratio);
2589
2590 }
2591 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2592 cpu->max_perf_ratio,
2593 cpu->min_perf_ratio);
2594}
2595
2596static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2597{
2598 struct cpudata *cpu;
2599
2600 if (!policy->cpuinfo.max_freq)
2601 return -ENODEV;
2602
2603 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2604 policy->cpuinfo.max_freq, policy->max);
2605
2606 cpu = all_cpu_data[policy->cpu];
2607 cpu->policy = policy->policy;
2608
2609 mutex_lock(&intel_pstate_limits_lock);
2610
2611 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2612
2613 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2614 /*
2615 * NOHZ_FULL CPUs need this as the governor callback may not
2616 * be invoked on them.
2617 */
2618 intel_pstate_clear_update_util_hook(policy->cpu);
2619 intel_pstate_max_within_limits(cpu);
2620 } else {
2621 intel_pstate_set_update_util_hook(policy->cpu);
2622 }
2623
2624 if (hwp_active) {
2625 /*
2626 * When hwp_boost was active before and dynamically it
2627 * was turned off, in that case we need to clear the
2628 * update util hook.
2629 */
2630 if (!hwp_boost)
2631 intel_pstate_clear_update_util_hook(policy->cpu);
2632 intel_pstate_hwp_set(policy->cpu);
2633 }
2634 /*
2635 * policy->cur is never updated with the intel_pstate driver, but it
2636 * is used as a stale frequency value. So, keep it within limits.
2637 */
2638 policy->cur = policy->min;
2639
2640 mutex_unlock(&intel_pstate_limits_lock);
2641
2642 return 0;
2643}
2644
2645static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2646 struct cpufreq_policy_data *policy)
2647{
2648 if (!hwp_active &&
2649 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2650 policy->max < policy->cpuinfo.max_freq &&
2651 policy->max > cpu->pstate.max_freq) {
2652 pr_debug("policy->max > max non turbo frequency\n");
2653 policy->max = policy->cpuinfo.max_freq;
2654 }
2655}
2656
2657static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2658 struct cpufreq_policy_data *policy)
2659{
2660 int max_freq;
2661
2662 update_turbo_state();
2663 if (hwp_active) {
2664 intel_pstate_get_hwp_cap(cpu);
2665 max_freq = global.no_turbo || global.turbo_disabled ?
2666 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2667 } else {
2668 max_freq = intel_pstate_get_max_freq(cpu);
2669 }
2670 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2671
2672 intel_pstate_adjust_policy_max(cpu, policy);
2673}
2674
2675static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2676{
2677 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2678
2679 return 0;
2680}
2681
2682static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2683{
2684 struct cpudata *cpu = all_cpu_data[policy->cpu];
2685
2686 pr_debug("CPU %d going offline\n", cpu->cpu);
2687
2688 if (cpu->suspended)
2689 return 0;
2690
2691 /*
2692 * If the CPU is an SMT thread and it goes offline with the performance
2693 * settings different from the minimum, it will prevent its sibling
2694 * from getting to lower performance levels, so force the minimum
2695 * performance on CPU offline to prevent that from happening.
2696 */
2697 if (hwp_active)
2698 intel_pstate_hwp_offline(cpu);
2699 else
2700 intel_pstate_set_min_pstate(cpu);
2701
2702 intel_pstate_exit_perf_limits(policy);
2703
2704 return 0;
2705}
2706
2707static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2708{
2709 struct cpudata *cpu = all_cpu_data[policy->cpu];
2710
2711 pr_debug("CPU %d going online\n", cpu->cpu);
2712
2713 intel_pstate_init_acpi_perf_limits(policy);
2714
2715 if (hwp_active) {
2716 /*
2717 * Re-enable HWP and clear the "suspended" flag to let "resume"
2718 * know that it need not do that.
2719 */
2720 intel_pstate_hwp_reenable(cpu);
2721 cpu->suspended = false;
2722 }
2723
2724 return 0;
2725}
2726
2727static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2728{
2729 intel_pstate_clear_update_util_hook(policy->cpu);
2730
2731 return intel_cpufreq_cpu_offline(policy);
2732}
2733
2734static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2735{
2736 pr_debug("CPU %d exiting\n", policy->cpu);
2737
2738 policy->fast_switch_possible = false;
2739
2740 return 0;
2741}
2742
2743static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2744{
2745 struct cpudata *cpu;
2746 int rc;
2747
2748 rc = intel_pstate_init_cpu(policy->cpu);
2749 if (rc)
2750 return rc;
2751
2752 cpu = all_cpu_data[policy->cpu];
2753
2754 cpu->max_perf_ratio = 0xFF;
2755 cpu->min_perf_ratio = 0;
2756
2757 /* cpuinfo and default policy values */
2758 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2759 update_turbo_state();
2760 global.turbo_disabled_mf = global.turbo_disabled;
2761 policy->cpuinfo.max_freq = global.turbo_disabled ?
2762 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2763
2764 policy->min = policy->cpuinfo.min_freq;
2765 policy->max = policy->cpuinfo.max_freq;
2766
2767 intel_pstate_init_acpi_perf_limits(policy);
2768
2769 policy->fast_switch_possible = true;
2770
2771 return 0;
2772}
2773
2774static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2775{
2776 int ret = __intel_pstate_cpu_init(policy);
2777
2778 if (ret)
2779 return ret;
2780
2781 /*
2782 * Set the policy to powersave to provide a valid fallback value in case
2783 * the default cpufreq governor is neither powersave nor performance.
2784 */
2785 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2786
2787 if (hwp_active) {
2788 struct cpudata *cpu = all_cpu_data[policy->cpu];
2789
2790 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2791 }
2792
2793 return 0;
2794}
2795
2796static struct cpufreq_driver intel_pstate = {
2797 .flags = CPUFREQ_CONST_LOOPS,
2798 .verify = intel_pstate_verify_policy,
2799 .setpolicy = intel_pstate_set_policy,
2800 .suspend = intel_pstate_suspend,
2801 .resume = intel_pstate_resume,
2802 .init = intel_pstate_cpu_init,
2803 .exit = intel_pstate_cpu_exit,
2804 .offline = intel_pstate_cpu_offline,
2805 .online = intel_pstate_cpu_online,
2806 .update_limits = intel_pstate_update_limits,
2807 .name = "intel_pstate",
2808};
2809
2810static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2811{
2812 struct cpudata *cpu = all_cpu_data[policy->cpu];
2813
2814 intel_pstate_verify_cpu_policy(cpu, policy);
2815 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2816
2817 return 0;
2818}
2819
2820/* Use of trace in passive mode:
2821 *
2822 * In passive mode the trace core_busy field (also known as the
2823 * performance field, and lablelled as such on the graphs; also known as
2824 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2825 * driver call was via the normal or fast switch path. Various graphs
2826 * output from the intel_pstate_tracer.py utility that include core_busy
2827 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2828 * so we use 10 to indicate the normal path through the driver, and
2829 * 90 to indicate the fast switch path through the driver.
2830 * The scaled_busy field is not used, and is set to 0.
2831 */
2832
2833#define INTEL_PSTATE_TRACE_TARGET 10
2834#define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2835
2836static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2837{
2838 struct sample *sample;
2839
2840 if (!trace_pstate_sample_enabled())
2841 return;
2842
2843 if (!intel_pstate_sample(cpu, ktime_get()))
2844 return;
2845
2846 sample = &cpu->sample;
2847 trace_pstate_sample(trace_type,
2848 0,
2849 old_pstate,
2850 cpu->pstate.current_pstate,
2851 sample->mperf,
2852 sample->aperf,
2853 sample->tsc,
2854 get_avg_frequency(cpu),
2855 fp_toint(cpu->iowait_boost * 100));
2856}
2857
2858static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2859 u32 desired, bool fast_switch)
2860{
2861 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2862
2863 value &= ~HWP_MIN_PERF(~0L);
2864 value |= HWP_MIN_PERF(min);
2865
2866 value &= ~HWP_MAX_PERF(~0L);
2867 value |= HWP_MAX_PERF(max);
2868
2869 value &= ~HWP_DESIRED_PERF(~0L);
2870 value |= HWP_DESIRED_PERF(desired);
2871
2872 if (value == prev)
2873 return;
2874
2875 WRITE_ONCE(cpu->hwp_req_cached, value);
2876 if (fast_switch)
2877 wrmsrl(MSR_HWP_REQUEST, value);
2878 else
2879 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2880}
2881
2882static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2883 u32 target_pstate, bool fast_switch)
2884{
2885 if (fast_switch)
2886 wrmsrl(MSR_IA32_PERF_CTL,
2887 pstate_funcs.get_val(cpu, target_pstate));
2888 else
2889 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2890 pstate_funcs.get_val(cpu, target_pstate));
2891}
2892
2893static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2894 int target_pstate, bool fast_switch)
2895{
2896 struct cpudata *cpu = all_cpu_data[policy->cpu];
2897 int old_pstate = cpu->pstate.current_pstate;
2898
2899 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2900 if (hwp_active) {
2901 int max_pstate = policy->strict_target ?
2902 target_pstate : cpu->max_perf_ratio;
2903
2904 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2905 fast_switch);
2906 } else if (target_pstate != old_pstate) {
2907 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2908 }
2909
2910 cpu->pstate.current_pstate = target_pstate;
2911
2912 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2913 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2914
2915 return target_pstate;
2916}
2917
2918static int intel_cpufreq_target(struct cpufreq_policy *policy,
2919 unsigned int target_freq,
2920 unsigned int relation)
2921{
2922 struct cpudata *cpu = all_cpu_data[policy->cpu];
2923 struct cpufreq_freqs freqs;
2924 int target_pstate;
2925
2926 update_turbo_state();
2927
2928 freqs.old = policy->cur;
2929 freqs.new = target_freq;
2930
2931 cpufreq_freq_transition_begin(policy, &freqs);
2932
2933 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2934 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2935
2936 freqs.new = target_pstate * cpu->pstate.scaling;
2937
2938 cpufreq_freq_transition_end(policy, &freqs, false);
2939
2940 return 0;
2941}
2942
2943static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2944 unsigned int target_freq)
2945{
2946 struct cpudata *cpu = all_cpu_data[policy->cpu];
2947 int target_pstate;
2948
2949 update_turbo_state();
2950
2951 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2952
2953 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2954
2955 return target_pstate * cpu->pstate.scaling;
2956}
2957
2958static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2959 unsigned long min_perf,
2960 unsigned long target_perf,
2961 unsigned long capacity)
2962{
2963 struct cpudata *cpu = all_cpu_data[cpunum];
2964 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2965 int old_pstate = cpu->pstate.current_pstate;
2966 int cap_pstate, min_pstate, max_pstate, target_pstate;
2967
2968 update_turbo_state();
2969 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2970 HWP_HIGHEST_PERF(hwp_cap);
2971
2972 /* Optimization: Avoid unnecessary divisions. */
2973
2974 target_pstate = cap_pstate;
2975 if (target_perf < capacity)
2976 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2977
2978 min_pstate = cap_pstate;
2979 if (min_perf < capacity)
2980 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2981
2982 if (min_pstate < cpu->pstate.min_pstate)
2983 min_pstate = cpu->pstate.min_pstate;
2984
2985 if (min_pstate < cpu->min_perf_ratio)
2986 min_pstate = cpu->min_perf_ratio;
2987
2988 if (min_pstate > cpu->max_perf_ratio)
2989 min_pstate = cpu->max_perf_ratio;
2990
2991 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2992 if (max_pstate < min_pstate)
2993 max_pstate = min_pstate;
2994
2995 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2996
2997 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2998
2999 cpu->pstate.current_pstate = target_pstate;
3000 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3001}
3002
3003static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3004{
3005 struct freq_qos_request *req;
3006 struct cpudata *cpu;
3007 struct device *dev;
3008 int ret, freq;
3009
3010 dev = get_cpu_device(policy->cpu);
3011 if (!dev)
3012 return -ENODEV;
3013
3014 ret = __intel_pstate_cpu_init(policy);
3015 if (ret)
3016 return ret;
3017
3018 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3019 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3020 policy->cur = policy->cpuinfo.min_freq;
3021
3022 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3023 if (!req) {
3024 ret = -ENOMEM;
3025 goto pstate_exit;
3026 }
3027
3028 cpu = all_cpu_data[policy->cpu];
3029
3030 if (hwp_active) {
3031 u64 value;
3032
3033 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3034
3035 intel_pstate_get_hwp_cap(cpu);
3036
3037 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3038 WRITE_ONCE(cpu->hwp_req_cached, value);
3039
3040 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3041 } else {
3042 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3043 }
3044
3045 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3046
3047 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3048 freq);
3049 if (ret < 0) {
3050 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3051 goto free_req;
3052 }
3053
3054 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3055
3056 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3057 freq);
3058 if (ret < 0) {
3059 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3060 goto remove_min_req;
3061 }
3062
3063 policy->driver_data = req;
3064
3065 return 0;
3066
3067remove_min_req:
3068 freq_qos_remove_request(req);
3069free_req:
3070 kfree(req);
3071pstate_exit:
3072 intel_pstate_exit_perf_limits(policy);
3073
3074 return ret;
3075}
3076
3077static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3078{
3079 struct freq_qos_request *req;
3080
3081 req = policy->driver_data;
3082
3083 freq_qos_remove_request(req + 1);
3084 freq_qos_remove_request(req);
3085 kfree(req);
3086
3087 return intel_pstate_cpu_exit(policy);
3088}
3089
3090static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3091{
3092 intel_pstate_suspend(policy);
3093
3094 if (hwp_active) {
3095 struct cpudata *cpu = all_cpu_data[policy->cpu];
3096 u64 value = READ_ONCE(cpu->hwp_req_cached);
3097
3098 /*
3099 * Clear the desired perf field in MSR_HWP_REQUEST in case
3100 * intel_cpufreq_adjust_perf() is in use and the last value
3101 * written by it may not be suitable.
3102 */
3103 value &= ~HWP_DESIRED_PERF(~0L);
3104 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3105 WRITE_ONCE(cpu->hwp_req_cached, value);
3106 }
3107
3108 return 0;
3109}
3110
3111static struct cpufreq_driver intel_cpufreq = {
3112 .flags = CPUFREQ_CONST_LOOPS,
3113 .verify = intel_cpufreq_verify_policy,
3114 .target = intel_cpufreq_target,
3115 .fast_switch = intel_cpufreq_fast_switch,
3116 .init = intel_cpufreq_cpu_init,
3117 .exit = intel_cpufreq_cpu_exit,
3118 .offline = intel_cpufreq_cpu_offline,
3119 .online = intel_pstate_cpu_online,
3120 .suspend = intel_cpufreq_suspend,
3121 .resume = intel_pstate_resume,
3122 .update_limits = intel_pstate_update_limits,
3123 .name = "intel_cpufreq",
3124};
3125
3126static struct cpufreq_driver *default_driver;
3127
3128static void intel_pstate_driver_cleanup(void)
3129{
3130 unsigned int cpu;
3131
3132 cpus_read_lock();
3133 for_each_online_cpu(cpu) {
3134 if (all_cpu_data[cpu]) {
3135 if (intel_pstate_driver == &intel_pstate)
3136 intel_pstate_clear_update_util_hook(cpu);
3137
3138 spin_lock(&hwp_notify_lock);
3139 kfree(all_cpu_data[cpu]);
3140 WRITE_ONCE(all_cpu_data[cpu], NULL);
3141 spin_unlock(&hwp_notify_lock);
3142 }
3143 }
3144 cpus_read_unlock();
3145
3146 intel_pstate_driver = NULL;
3147}
3148
3149static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3150{
3151 int ret;
3152
3153 if (driver == &intel_pstate)
3154 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3155
3156 memset(&global, 0, sizeof(global));
3157 global.max_perf_pct = 100;
3158
3159 intel_pstate_driver = driver;
3160 ret = cpufreq_register_driver(intel_pstate_driver);
3161 if (ret) {
3162 intel_pstate_driver_cleanup();
3163 return ret;
3164 }
3165
3166 global.min_perf_pct = min_perf_pct_min();
3167
3168 return 0;
3169}
3170
3171static ssize_t intel_pstate_show_status(char *buf)
3172{
3173 if (!intel_pstate_driver)
3174 return sprintf(buf, "off\n");
3175
3176 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3177 "active" : "passive");
3178}
3179
3180static int intel_pstate_update_status(const char *buf, size_t size)
3181{
3182 if (size == 3 && !strncmp(buf, "off", size)) {
3183 if (!intel_pstate_driver)
3184 return -EINVAL;
3185
3186 if (hwp_active)
3187 return -EBUSY;
3188
3189 cpufreq_unregister_driver(intel_pstate_driver);
3190 intel_pstate_driver_cleanup();
3191 return 0;
3192 }
3193
3194 if (size == 6 && !strncmp(buf, "active", size)) {
3195 if (intel_pstate_driver) {
3196 if (intel_pstate_driver == &intel_pstate)
3197 return 0;
3198
3199 cpufreq_unregister_driver(intel_pstate_driver);
3200 }
3201
3202 return intel_pstate_register_driver(&intel_pstate);
3203 }
3204
3205 if (size == 7 && !strncmp(buf, "passive", size)) {
3206 if (intel_pstate_driver) {
3207 if (intel_pstate_driver == &intel_cpufreq)
3208 return 0;
3209
3210 cpufreq_unregister_driver(intel_pstate_driver);
3211 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3212 }
3213
3214 return intel_pstate_register_driver(&intel_cpufreq);
3215 }
3216
3217 return -EINVAL;
3218}
3219
3220static int no_load __initdata;
3221static int no_hwp __initdata;
3222static int hwp_only __initdata;
3223static unsigned int force_load __initdata;
3224
3225static int __init intel_pstate_msrs_not_valid(void)
3226{
3227 if (!pstate_funcs.get_max(0) ||
3228 !pstate_funcs.get_min(0) ||
3229 !pstate_funcs.get_turbo(0))
3230 return -ENODEV;
3231
3232 return 0;
3233}
3234
3235static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3236{
3237 pstate_funcs.get_max = funcs->get_max;
3238 pstate_funcs.get_max_physical = funcs->get_max_physical;
3239 pstate_funcs.get_min = funcs->get_min;
3240 pstate_funcs.get_turbo = funcs->get_turbo;
3241 pstate_funcs.get_scaling = funcs->get_scaling;
3242 pstate_funcs.get_val = funcs->get_val;
3243 pstate_funcs.get_vid = funcs->get_vid;
3244 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3245}
3246
3247#ifdef CONFIG_ACPI
3248
3249static bool __init intel_pstate_no_acpi_pss(void)
3250{
3251 int i;
3252
3253 for_each_possible_cpu(i) {
3254 acpi_status status;
3255 union acpi_object *pss;
3256 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3257 struct acpi_processor *pr = per_cpu(processors, i);
3258
3259 if (!pr)
3260 continue;
3261
3262 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3263 if (ACPI_FAILURE(status))
3264 continue;
3265
3266 pss = buffer.pointer;
3267 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3268 kfree(pss);
3269 return false;
3270 }
3271
3272 kfree(pss);
3273 }
3274
3275 pr_debug("ACPI _PSS not found\n");
3276 return true;
3277}
3278
3279static bool __init intel_pstate_no_acpi_pcch(void)
3280{
3281 acpi_status status;
3282 acpi_handle handle;
3283
3284 status = acpi_get_handle(NULL, "\\_SB", &handle);
3285 if (ACPI_FAILURE(status))
3286 goto not_found;
3287
3288 if (acpi_has_method(handle, "PCCH"))
3289 return false;
3290
3291not_found:
3292 pr_debug("ACPI PCCH not found\n");
3293 return true;
3294}
3295
3296static bool __init intel_pstate_has_acpi_ppc(void)
3297{
3298 int i;
3299
3300 for_each_possible_cpu(i) {
3301 struct acpi_processor *pr = per_cpu(processors, i);
3302
3303 if (!pr)
3304 continue;
3305 if (acpi_has_method(pr->handle, "_PPC"))
3306 return true;
3307 }
3308 pr_debug("ACPI _PPC not found\n");
3309 return false;
3310}
3311
3312enum {
3313 PSS,
3314 PPC,
3315};
3316
3317/* Hardware vendor-specific info that has its own power management modes */
3318static struct acpi_platform_list plat_info[] __initdata = {
3319 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3320 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3334 { } /* End */
3335};
3336
3337#define BITMASK_OOB (BIT(8) | BIT(18))
3338
3339static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3340{
3341 const struct x86_cpu_id *id;
3342 u64 misc_pwr;
3343 int idx;
3344
3345 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3346 if (id) {
3347 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3348 if (misc_pwr & BITMASK_OOB) {
3349 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3350 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3351 return true;
3352 }
3353 }
3354
3355 idx = acpi_match_platform_list(plat_info);
3356 if (idx < 0)
3357 return false;
3358
3359 switch (plat_info[idx].data) {
3360 case PSS:
3361 if (!intel_pstate_no_acpi_pss())
3362 return false;
3363
3364 return intel_pstate_no_acpi_pcch();
3365 case PPC:
3366 return intel_pstate_has_acpi_ppc() && !force_load;
3367 }
3368
3369 return false;
3370}
3371
3372static void intel_pstate_request_control_from_smm(void)
3373{
3374 /*
3375 * It may be unsafe to request P-states control from SMM if _PPC support
3376 * has not been enabled.
3377 */
3378 if (acpi_ppc)
3379 acpi_processor_pstate_control();
3380}
3381#else /* CONFIG_ACPI not enabled */
3382static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3383static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3384static inline void intel_pstate_request_control_from_smm(void) {}
3385#endif /* CONFIG_ACPI */
3386
3387#define INTEL_PSTATE_HWP_BROADWELL 0x01
3388
3389#define X86_MATCH_HWP(model, hwp_mode) \
3390 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3391 X86_FEATURE_HWP, hwp_mode)
3392
3393static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3394 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3395 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3396 X86_MATCH_HWP(ANY, 0),
3397 {}
3398};
3399
3400static bool intel_pstate_hwp_is_enabled(void)
3401{
3402 u64 value;
3403
3404 rdmsrl(MSR_PM_ENABLE, value);
3405 return !!(value & 0x1);
3406}
3407
3408#define POWERSAVE_MASK GENMASK(7, 0)
3409#define BALANCE_POWER_MASK GENMASK(15, 8)
3410#define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3411#define PERFORMANCE_MASK GENMASK(31, 24)
3412
3413#define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3414 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3415 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3416 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3417 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3418
3419#define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3420 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3421 balance_perf, HWP_EPP_PERFORMANCE))
3422
3423static const struct x86_cpu_id intel_epp_default[] = {
3424 /*
3425 * Set EPP value as 102, this is the max suggested EPP
3426 * which can result in one core turbo frequency for
3427 * AlderLake Mobile CPUs.
3428 */
3429 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3430 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3431 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3432 HWP_EPP_BALANCE_POWERSAVE, 115, 16)),
3433 {}
3434};
3435
3436static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3437 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3438 {}
3439};
3440
3441static int __init intel_pstate_init(void)
3442{
3443 static struct cpudata **_all_cpu_data;
3444 const struct x86_cpu_id *id;
3445 int rc;
3446
3447 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3448 return -ENODEV;
3449
3450 id = x86_match_cpu(hwp_support_ids);
3451 if (id) {
3452 hwp_forced = intel_pstate_hwp_is_enabled();
3453
3454 if (hwp_forced)
3455 pr_info("HWP enabled by BIOS\n");
3456 else if (no_load)
3457 return -ENODEV;
3458
3459 copy_cpu_funcs(&core_funcs);
3460 /*
3461 * Avoid enabling HWP for processors without EPP support,
3462 * because that means incomplete HWP implementation which is a
3463 * corner case and supporting it is generally problematic.
3464 *
3465 * If HWP is enabled already, though, there is no choice but to
3466 * deal with it.
3467 */
3468 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3469 WRITE_ONCE(hwp_active, 1);
3470 hwp_mode_bdw = id->driver_data;
3471 intel_pstate.attr = hwp_cpufreq_attrs;
3472 intel_cpufreq.attr = hwp_cpufreq_attrs;
3473 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3474 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3475 if (!default_driver)
3476 default_driver = &intel_pstate;
3477
3478 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3479
3480 goto hwp_cpu_matched;
3481 }
3482 pr_info("HWP not enabled\n");
3483 } else {
3484 if (no_load)
3485 return -ENODEV;
3486
3487 id = x86_match_cpu(intel_pstate_cpu_ids);
3488 if (!id) {
3489 pr_info("CPU model not supported\n");
3490 return -ENODEV;
3491 }
3492
3493 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3494 }
3495
3496 if (intel_pstate_msrs_not_valid()) {
3497 pr_info("Invalid MSRs\n");
3498 return -ENODEV;
3499 }
3500 /* Without HWP start in the passive mode. */
3501 if (!default_driver)
3502 default_driver = &intel_cpufreq;
3503
3504hwp_cpu_matched:
3505 /*
3506 * The Intel pstate driver will be ignored if the platform
3507 * firmware has its own power management modes.
3508 */
3509 if (intel_pstate_platform_pwr_mgmt_exists()) {
3510 pr_info("P-states controlled by the platform\n");
3511 return -ENODEV;
3512 }
3513
3514 if (!hwp_active && hwp_only)
3515 return -ENOTSUPP;
3516
3517 pr_info("Intel P-state driver initializing\n");
3518
3519 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3520 if (!_all_cpu_data)
3521 return -ENOMEM;
3522
3523 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3524
3525 intel_pstate_request_control_from_smm();
3526
3527 intel_pstate_sysfs_expose_params();
3528
3529 if (hwp_active) {
3530 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3531 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3532
3533 if (id) {
3534 epp_values[EPP_INDEX_POWERSAVE] =
3535 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3536 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3537 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3538 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3539 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3540 epp_values[EPP_INDEX_PERFORMANCE] =
3541 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3542 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3543 epp_values[EPP_INDEX_POWERSAVE],
3544 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3545 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3546 epp_values[EPP_INDEX_PERFORMANCE]);
3547 }
3548
3549 if (hybrid_id) {
3550 hybrid_scaling_factor = hybrid_id->driver_data;
3551 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3552 }
3553
3554 }
3555
3556 mutex_lock(&intel_pstate_driver_lock);
3557 rc = intel_pstate_register_driver(default_driver);
3558 mutex_unlock(&intel_pstate_driver_lock);
3559 if (rc) {
3560 intel_pstate_sysfs_remove();
3561 return rc;
3562 }
3563
3564 if (hwp_active) {
3565 const struct x86_cpu_id *id;
3566
3567 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3568 if (id) {
3569 set_power_ctl_ee_state(false);
3570 pr_info("Disabling energy efficiency optimization\n");
3571 }
3572
3573 pr_info("HWP enabled\n");
3574 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3575 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3576 }
3577
3578 return 0;
3579}
3580device_initcall(intel_pstate_init);
3581
3582static int __init intel_pstate_setup(char *str)
3583{
3584 if (!str)
3585 return -EINVAL;
3586
3587 if (!strcmp(str, "disable"))
3588 no_load = 1;
3589 else if (!strcmp(str, "active"))
3590 default_driver = &intel_pstate;
3591 else if (!strcmp(str, "passive"))
3592 default_driver = &intel_cpufreq;
3593
3594 if (!strcmp(str, "no_hwp"))
3595 no_hwp = 1;
3596
3597 if (!strcmp(str, "force"))
3598 force_load = 1;
3599 if (!strcmp(str, "hwp_only"))
3600 hwp_only = 1;
3601 if (!strcmp(str, "per_cpu_perf_limits"))
3602 per_cpu_limits = true;
3603
3604#ifdef CONFIG_ACPI
3605 if (!strcmp(str, "support_acpi_ppc"))
3606 acpi_ppc = true;
3607#endif
3608
3609 return 0;
3610}
3611early_param("intel_pstate", intel_pstate_setup);
3612
3613MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3614MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");