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1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/bitfield.h>
32#include <linux/byteorder/generic.h>
33#include <linux/cec.h>
34#include <linux/hdmi.h>
35#include <linux/i2c.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/seq_buf.h>
40#include <linux/slab.h>
41#include <linux/vga_switcheroo.h>
42
43#include <drm/drm_drv.h>
44#include <drm/drm_edid.h>
45#include <drm/drm_eld.h>
46#include <drm/drm_encoder.h>
47#include <drm/drm_print.h>
48
49#include "drm_crtc_internal.h"
50#include "drm_displayid_internal.h"
51#include "drm_internal.h"
52
53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
95/* Cap the DSC target bitrate to 15bpp */
96#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
97
98#define MICROSOFT_IEEE_OUI 0xca125c
99
100struct detailed_mode_closure {
101 struct drm_connector *connector;
102 const struct drm_edid *drm_edid;
103 bool preferred;
104 int modes;
105};
106
107struct drm_edid_match_closure {
108 const struct drm_edid_ident *ident;
109 bool matched;
110};
111
112#define LEVEL_DMT 0
113#define LEVEL_GTF 1
114#define LEVEL_GTF2 2
115#define LEVEL_CVT 3
116
117#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
118{ \
119 .ident = { \
120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
121 vend_chr_2, product_id), \
122 }, \
123 .quirks = _quirks \
124}
125
126static const struct edid_quirk {
127 const struct drm_edid_ident ident;
128 u32 quirks;
129} edid_quirk_list[] = {
130 /* Acer AL1706 */
131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
132 /* Acer F51 */
133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
134
135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
137
138 /* BenQ GW2765 */
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
140
141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
143
144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
146
147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
149
150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
152
153 /* Belinea 10 15 55 */
154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
156
157 /* Envision Peripherals, Inc. EN-7100e */
158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
159 /* Envision EN2028 */
160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
161
162 /* Funai Electronics PM36B */
163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
164 EDID_QUIRK_DETAILED_IN_CM),
165
166 /* LG 27GP950 */
167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
168
169 /* LG 27GN950 */
170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
171
172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
174
175 /* LG Philips LCD LP154W01-A5 */
176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
178
179 /* Samsung SyncMaster 205BW. Note: irony */
180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
181 /* Samsung SyncMaster 22[5-6]BW */
182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
184
185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
187
188 /* ViewSonic VA2026w */
189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
190
191 /* Medion MD 30217 PG */
192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
193
194 /* Lenovo G50 */
195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
196
197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
199
200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
202
203 /* Valve Index Headset */
204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
221
222 /* HTC Vive and Vive Pro VR Headsets */
223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
225
226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
231
232 /* Windows Mixed Reality Headsets */
233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
239
240 /* Sony PlayStation VR Headset */
241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
242
243 /* Sensics VR Headsets */
244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
245
246 /* OSVR HDK and HDK2 VR Headsets */
247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
249};
250
251/*
252 * Autogenerated from the DMT spec.
253 * This table is copied from xfree86/modes/xf86EdidModes.c.
254 */
255static const struct drm_display_mode drm_dmt_modes[] = {
256 /* 0x01 - 640x350@85Hz */
257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 350, 382, 385, 445, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x02 - 640x400@85Hz */
261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
262 736, 832, 0, 400, 401, 404, 445, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x03 - 720x400@85Hz */
265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
266 828, 936, 0, 400, 401, 404, 446, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x04 - 640x480@60Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
270 752, 800, 0, 480, 490, 492, 525, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x05 - 640x480@72Hz */
273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
274 704, 832, 0, 480, 489, 492, 520, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x06 - 640x480@75Hz */
277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
278 720, 840, 0, 480, 481, 484, 500, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 0x07 - 640x480@85Hz */
281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
282 752, 832, 0, 480, 481, 484, 509, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x08 - 800x600@56Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
286 896, 1024, 0, 600, 601, 603, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x09 - 800x600@60Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
290 968, 1056, 0, 600, 601, 605, 628, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0a - 800x600@72Hz */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
294 976, 1040, 0, 600, 637, 643, 666, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x0b - 800x600@75Hz */
297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
298 896, 1056, 0, 600, 601, 604, 625, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0c - 800x600@85Hz */
301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
302 896, 1048, 0, 600, 601, 604, 631, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 0x0d - 800x600@120Hz RB */
305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
306 880, 960, 0, 600, 603, 607, 636, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 0x0e - 848x480@60Hz */
309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
310 976, 1088, 0, 480, 486, 494, 517, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x0f - 1024x768@43Hz, interlace */
313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
314 1208, 1264, 0, 768, 768, 776, 817, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
316 DRM_MODE_FLAG_INTERLACE) },
317 /* 0x10 - 1024x768@60Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x11 - 1024x768@70Hz */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
323 1184, 1328, 0, 768, 771, 777, 806, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x12 - 1024x768@75Hz */
326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
327 1136, 1312, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x13 - 1024x768@85Hz */
330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
331 1168, 1376, 0, 768, 769, 772, 808, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x14 - 1024x768@120Hz RB */
334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
335 1104, 1184, 0, 768, 771, 775, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x15 - 1152x864@75Hz */
338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
339 1344, 1600, 0, 864, 865, 868, 900, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x55 - 1280x720@60Hz */
342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
343 1430, 1650, 0, 720, 725, 730, 750, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x16 - 1280x768@60Hz RB */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 790, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x17 - 1280x768@60Hz */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
351 1472, 1664, 0, 768, 771, 778, 798, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x18 - 1280x768@75Hz */
354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
355 1488, 1696, 0, 768, 771, 778, 805, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x19 - 1280x768@85Hz */
358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
359 1496, 1712, 0, 768, 771, 778, 809, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1a - 1280x768@120Hz RB */
362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
363 1360, 1440, 0, 768, 771, 778, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x1b - 1280x800@60Hz RB */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 823, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x1c - 1280x800@60Hz */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
371 1480, 1680, 0, 800, 803, 809, 831, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x1d - 1280x800@75Hz */
374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
375 1488, 1696, 0, 800, 803, 809, 838, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x1e - 1280x800@85Hz */
378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
379 1496, 1712, 0, 800, 803, 809, 843, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x1f - 1280x800@120Hz RB */
382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
383 1360, 1440, 0, 800, 803, 809, 847, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x20 - 1280x960@60Hz */
386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
387 1488, 1800, 0, 960, 961, 964, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x21 - 1280x960@85Hz */
390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
391 1504, 1728, 0, 960, 961, 964, 1011, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x22 - 1280x960@120Hz RB */
394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
395 1360, 1440, 0, 960, 963, 967, 1017, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x23 - 1280x1024@60Hz */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x24 - 1280x1024@75Hz */
402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x25 - 1280x1024@85Hz */
406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x26 - 1280x1024@120Hz RB */
410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x27 - 1360x768@60Hz */
414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
415 1536, 1792, 0, 768, 771, 777, 795, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x28 - 1360x768@120Hz RB */
418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
419 1440, 1520, 0, 768, 771, 776, 813, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x51 - 1366x768@60Hz */
422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
423 1579, 1792, 0, 768, 771, 774, 798, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x56 - 1366x768@60Hz */
426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
427 1436, 1500, 0, 768, 769, 772, 800, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x29 - 1400x1050@60Hz RB */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x2a - 1400x1050@60Hz */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x2b - 1400x1050@75Hz */
438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x2c - 1400x1050@85Hz */
442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x2d - 1400x1050@120Hz RB */
446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 0x2e - 1440x900@60Hz RB */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 926, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x2f - 1440x900@60Hz */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
455 1672, 1904, 0, 900, 903, 909, 934, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x30 - 1440x900@75Hz */
458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
459 1688, 1936, 0, 900, 903, 909, 942, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x31 - 1440x900@85Hz */
462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
463 1696, 1952, 0, 900, 903, 909, 948, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x32 - 1440x900@120Hz RB */
466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
467 1520, 1600, 0, 900, 903, 909, 953, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x53 - 1600x900@60Hz */
470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
471 1704, 1800, 0, 900, 901, 904, 1000, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x33 - 1600x1200@60Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x34 - 1600x1200@65Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x35 - 1600x1200@70Hz */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x36 - 1600x1200@75Hz */
486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x37 - 1600x1200@85Hz */
490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x38 - 1600x1200@120Hz RB */
494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x39 - 1680x1050@60Hz RB */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x3a - 1680x1050@60Hz */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x3b - 1680x1050@75Hz */
506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3c - 1680x1050@85Hz */
510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x3d - 1680x1050@120Hz RB */
514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x3e - 1792x1344@60Hz */
518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x3f - 1792x1344@75Hz */
522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x40 - 1792x1344@120Hz RB */
526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x41 - 1856x1392@60Hz */
530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 0x42 - 1856x1392@75Hz */
534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x43 - 1856x1392@120Hz RB */
538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
541 /* 0x52 - 1920x1080@60Hz */
542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x44 - 1920x1200@60Hz RB */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x45 - 1920x1200@60Hz */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 0x46 - 1920x1200@75Hz */
554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x47 - 1920x1200@85Hz */
558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x48 - 1920x1200@120Hz RB */
562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x49 - 1920x1440@60Hz */
566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4a - 1920x1440@75Hz */
570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 0x4b - 1920x1440@120Hz RB */
574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 /* 0x54 - 2048x1152@60Hz */
578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4c - 2560x1600@60Hz RB */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585 /* 0x4d - 2560x1600@60Hz */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 /* 0x4e - 2560x1600@75Hz */
590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
593 /* 0x4f - 2560x1600@85Hz */
594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
597 /* 0x50 - 2560x1600@120Hz RB */
598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 /* 0x57 - 4096x2160@60Hz RB */
602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
605 /* 0x58 - 4096x2160@59.94Hz RB */
606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
609};
610
611/*
612 * These more or less come from the DMT spec. The 720x400 modes are
613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
616 * mode.
617 *
618 * The DMT modes have been fact-checked; the rest are mild guesses.
619 */
620static const struct drm_display_mode edid_est_modes[] = {
621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
622 968, 1056, 0, 600, 601, 605, 628, 0,
623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
625 896, 1024, 0, 600, 601, 603, 625, 0,
626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
628 720, 840, 0, 480, 481, 484, 500, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
631 704, 832, 0, 480, 489, 492, 520, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
634 768, 864, 0, 480, 483, 486, 525, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
637 752, 800, 0, 480, 490, 492, 525, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
640 846, 900, 0, 400, 421, 423, 449, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
643 846, 900, 0, 400, 412, 414, 449, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
649 1136, 1312, 0, 768, 769, 772, 800, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
652 1184, 1328, 0, 768, 771, 777, 806, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
655 1184, 1344, 0, 768, 771, 777, 806, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
658 1208, 1264, 0, 768, 768, 776, 817, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
661 928, 1152, 0, 624, 625, 628, 667, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
664 896, 1056, 0, 600, 601, 604, 625, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
667 976, 1040, 0, 600, 637, 643, 666, 0,
668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
670 1344, 1600, 0, 864, 865, 868, 900, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
672};
673
674struct minimode {
675 short w;
676 short h;
677 short r;
678 short rb;
679};
680
681static const struct minimode est3_modes[] = {
682 /* byte 6 */
683 { 640, 350, 85, 0 },
684 { 640, 400, 85, 0 },
685 { 720, 400, 85, 0 },
686 { 640, 480, 85, 0 },
687 { 848, 480, 60, 0 },
688 { 800, 600, 85, 0 },
689 { 1024, 768, 85, 0 },
690 { 1152, 864, 75, 0 },
691 /* byte 7 */
692 { 1280, 768, 60, 1 },
693 { 1280, 768, 60, 0 },
694 { 1280, 768, 75, 0 },
695 { 1280, 768, 85, 0 },
696 { 1280, 960, 60, 0 },
697 { 1280, 960, 85, 0 },
698 { 1280, 1024, 60, 0 },
699 { 1280, 1024, 85, 0 },
700 /* byte 8 */
701 { 1360, 768, 60, 0 },
702 { 1440, 900, 60, 1 },
703 { 1440, 900, 60, 0 },
704 { 1440, 900, 75, 0 },
705 { 1440, 900, 85, 0 },
706 { 1400, 1050, 60, 1 },
707 { 1400, 1050, 60, 0 },
708 { 1400, 1050, 75, 0 },
709 /* byte 9 */
710 { 1400, 1050, 85, 0 },
711 { 1680, 1050, 60, 1 },
712 { 1680, 1050, 60, 0 },
713 { 1680, 1050, 75, 0 },
714 { 1680, 1050, 85, 0 },
715 { 1600, 1200, 60, 0 },
716 { 1600, 1200, 65, 0 },
717 { 1600, 1200, 70, 0 },
718 /* byte 10 */
719 { 1600, 1200, 75, 0 },
720 { 1600, 1200, 85, 0 },
721 { 1792, 1344, 60, 0 },
722 { 1792, 1344, 75, 0 },
723 { 1856, 1392, 60, 0 },
724 { 1856, 1392, 75, 0 },
725 { 1920, 1200, 60, 1 },
726 { 1920, 1200, 60, 0 },
727 /* byte 11 */
728 { 1920, 1200, 75, 0 },
729 { 1920, 1200, 85, 0 },
730 { 1920, 1440, 60, 0 },
731 { 1920, 1440, 75, 0 },
732};
733
734static const struct minimode extra_modes[] = {
735 { 1024, 576, 60, 0 },
736 { 1366, 768, 60, 0 },
737 { 1600, 900, 60, 0 },
738 { 1680, 945, 60, 0 },
739 { 1920, 1080, 60, 0 },
740 { 2048, 1152, 60, 0 },
741 { 2048, 1536, 60, 0 },
742};
743
744/*
745 * From CEA/CTA-861 spec.
746 *
747 * Do not access directly, instead always use cea_mode_for_vic().
748 */
749static const struct drm_display_mode edid_cea_modes_1[] = {
750 /* 1 - 640x480@60Hz 4:3 */
751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752 752, 800, 0, 480, 490, 492, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
755 /* 2 - 720x480@60Hz 4:3 */
756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
757 798, 858, 0, 480, 489, 495, 525, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
760 /* 3 - 720x480@60Hz 16:9 */
761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
762 798, 858, 0, 480, 489, 495, 525, 0,
763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 4 - 1280x720@60Hz 16:9 */
766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
767 1430, 1650, 0, 720, 725, 730, 750, 0,
768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 5 - 1920x1080i@60Hz 16:9 */
771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
774 DRM_MODE_FLAG_INTERLACE),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 6 - 720(1440)x480i@60Hz 4:3 */
777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 7 - 720(1440)x480i@60Hz 16:9 */
783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 8 - 720(1440)x240@60Hz 4:3 */
789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
790 801, 858, 0, 240, 244, 247, 262, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_DBLCLK),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 9 - 720(1440)x240@60Hz 16:9 */
795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
796 801, 858, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_DBLCLK),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 10 - 2880x480i@60Hz 4:3 */
801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 480, 488, 494, 525, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
804 DRM_MODE_FLAG_INTERLACE),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 11 - 2880x480i@60Hz 16:9 */
807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 480, 488, 494, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
810 DRM_MODE_FLAG_INTERLACE),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 12 - 2880x240@60Hz 4:3 */
813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
814 3204, 3432, 0, 240, 244, 247, 262, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 13 - 2880x240@60Hz 16:9 */
818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819 3204, 3432, 0, 240, 244, 247, 262, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 14 - 1440x480@60Hz 4:3 */
823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
824 1596, 1716, 0, 480, 489, 495, 525, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 15 - 1440x480@60Hz 16:9 */
828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
829 1596, 1716, 0, 480, 489, 495, 525, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 16 - 1920x1080@60Hz 16:9 */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 17 - 720x576@50Hz 4:3 */
838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
839 796, 864, 0, 576, 581, 586, 625, 0,
840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
842 /* 18 - 720x576@50Hz 16:9 */
843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
844 796, 864, 0, 576, 581, 586, 625, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 19 - 1280x720@50Hz 16:9 */
848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
849 1760, 1980, 0, 720, 725, 730, 750, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 20 - 1920x1080i@50Hz 16:9 */
853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
856 DRM_MODE_FLAG_INTERLACE),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 21 - 720(1440)x576i@50Hz 4:3 */
859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 22 - 720(1440)x576i@50Hz 16:9 */
865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 23 - 720(1440)x288@50Hz 4:3 */
871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
872 795, 864, 0, 288, 290, 293, 312, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_DBLCLK),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 24 - 720(1440)x288@50Hz 16:9 */
877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
878 795, 864, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_DBLCLK),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 25 - 2880x576i@50Hz 4:3 */
883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
886 DRM_MODE_FLAG_INTERLACE),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 26 - 2880x576i@50Hz 16:9 */
889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
892 DRM_MODE_FLAG_INTERLACE),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 27 - 2880x288@50Hz 4:3 */
895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
896 3180, 3456, 0, 288, 290, 293, 312, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899 /* 28 - 2880x288@50Hz 16:9 */
900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901 3180, 3456, 0, 288, 290, 293, 312, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 29 - 1440x576@50Hz 4:3 */
905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
906 1592, 1728, 0, 576, 581, 586, 625, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 30 - 1440x576@50Hz 16:9 */
910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
911 1592, 1728, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 31 - 1920x1080@50Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 32 - 1920x1080@24Hz 16:9 */
920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 33 - 1920x1080@25Hz 16:9 */
925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 34 - 1920x1080@30Hz 16:9 */
930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 35 - 2880x480@60Hz 4:3 */
935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
936 3192, 3432, 0, 480, 489, 495, 525, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 36 - 2880x480@60Hz 16:9 */
940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
941 3192, 3432, 0, 480, 489, 495, 525, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 37 - 2880x576@50Hz 4:3 */
945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
946 3184, 3456, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 38 - 2880x576@50Hz 16:9 */
950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
951 3184, 3456, 0, 576, 581, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 39 - 1920x1080i@50Hz 16:9 */
955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
958 DRM_MODE_FLAG_INTERLACE),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 40 - 1920x1080i@100Hz 16:9 */
961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
964 DRM_MODE_FLAG_INTERLACE),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 41 - 1280x720@100Hz 16:9 */
967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
968 1760, 1980, 0, 720, 725, 730, 750, 0,
969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971 /* 42 - 720x576@100Hz 4:3 */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 43 - 720x576@100Hz 16:9 */
977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 44 - 720(1440)x576i@100Hz 4:3 */
982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
983 795, 864, 0, 576, 580, 586, 625, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987 /* 45 - 720(1440)x576i@100Hz 16:9 */
988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
989 795, 864, 0, 576, 580, 586, 625, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 46 - 1920x1080i@120Hz 16:9 */
994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
997 DRM_MODE_FLAG_INTERLACE),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 47 - 1280x720@120Hz 16:9 */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1001 1430, 1650, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 48 - 720x480@120Hz 4:3 */
1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 49 - 720x480@120Hz 16:9 */
1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 50 - 720(1440)x480i@120Hz 4:3 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 51 - 720(1440)x480i@120Hz 16:9 */
1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 52 - 720x576@200Hz 4:3 */
1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1028 796, 864, 0, 576, 581, 586, 625, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 53 - 720x576@200Hz 16:9 */
1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1033 796, 864, 0, 576, 581, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 54 - 720(1440)x576i@200Hz 4:3 */
1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1038 795, 864, 0, 576, 580, 586, 625, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 55 - 720(1440)x576i@200Hz 16:9 */
1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1044 795, 864, 0, 576, 580, 586, 625, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 56 - 720x480@240Hz 4:3 */
1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1050 798, 858, 0, 480, 489, 495, 525, 0,
1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 57 - 720x480@240Hz 16:9 */
1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1055 798, 858, 0, 480, 489, 495, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 58 - 720(1440)x480i@240Hz 4:3 */
1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1060 801, 858, 0, 480, 488, 494, 525, 0,
1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1064 /* 59 - 720(1440)x480i@240Hz 16:9 */
1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1066 801, 858, 0, 480, 488, 494, 525, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 60 - 1280x720@24Hz 16:9 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 61 - 1280x720@25Hz 16:9 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1077 3740, 3960, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 62 - 1280x720@30Hz 16:9 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1085 /* 63 - 1920x1080@120Hz 16:9 */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1090 /* 64 - 1920x1080@100Hz 16:9 */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1095 /* 65 - 1280x720@24Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1097 3080, 3300, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 66 - 1280x720@25Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1102 3740, 3960, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 67 - 1280x720@30Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 68 - 1280x720@50Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1112 1760, 1980, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 69 - 1280x720@60Hz 64:27 */
1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1117 1430, 1650, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 70 - 1280x720@100Hz 64:27 */
1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1122 1760, 1980, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 71 - 1280x720@120Hz 64:27 */
1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1127 1430, 1650, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 72 - 1920x1080@24Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 73 - 1920x1080@25Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 74 - 1920x1080@30Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 75 - 1920x1080@50Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 76 - 1920x1080@60Hz 64:27 */
1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 77 - 1920x1080@100Hz 64:27 */
1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 78 - 1920x1080@120Hz 64:27 */
1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 79 - 1680x720@24Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1167 3080, 3300, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 80 - 1680x720@25Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1172 2948, 3168, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 81 - 1680x720@30Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1177 2420, 2640, 0, 720, 725, 730, 750, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 82 - 1680x720@50Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1182 1980, 2200, 0, 720, 725, 730, 750, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 83 - 1680x720@60Hz 64:27 */
1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1187 1980, 2200, 0, 720, 725, 730, 750, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 84 - 1680x720@100Hz 64:27 */
1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1192 1780, 2000, 0, 720, 725, 730, 825, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 85 - 1680x720@120Hz 64:27 */
1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1197 1780, 2000, 0, 720, 725, 730, 825, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 86 - 2560x1080@24Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 87 - 2560x1080@25Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 88 - 2560x1080@30Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 89 - 2560x1080@50Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 90 - 2560x1080@60Hz 64:27 */
1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1225 /* 91 - 2560x1080@100Hz 64:27 */
1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 92 - 2560x1080@120Hz 64:27 */
1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 93 - 3840x2160@24Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 94 - 3840x2160@25Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 95 - 3840x2160@30Hz 16:9 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1250 /* 96 - 3840x2160@50Hz 16:9 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1255 /* 97 - 3840x2160@60Hz 16:9 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1260 /* 98 - 4096x2160@24Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 99 - 4096x2160@25Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 100 - 4096x2160@30Hz 256:135 */
1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1275 /* 101 - 4096x2160@50Hz 256:135 */
1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1280 /* 102 - 4096x2160@60Hz 256:135 */
1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1285 /* 103 - 3840x2160@24Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 104 - 3840x2160@25Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 105 - 3840x2160@30Hz 64:27 */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1300 /* 106 - 3840x2160@50Hz 64:27 */
1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 107 - 3840x2160@60Hz 64:27 */
1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 108 - 1280x720@48Hz 16:9 */
1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1312 2280, 2500, 0, 720, 725, 730, 750, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 109 - 1280x720@48Hz 64:27 */
1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1317 2280, 2500, 0, 720, 725, 730, 750, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 110 - 1680x720@48Hz 64:27 */
1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1322 2530, 2750, 0, 720, 725, 730, 750, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 111 - 1920x1080@48Hz 16:9 */
1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 112 - 1920x1080@48Hz 64:27 */
1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1335 /* 113 - 2560x1080@48Hz 64:27 */
1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 114 - 3840x2160@48Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 115 - 4096x2160@48Hz 256:135 */
1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1350 /* 116 - 3840x2160@48Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 117 - 3840x2160@100Hz 16:9 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1360 /* 118 - 3840x2160@120Hz 16:9 */
1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1365 /* 119 - 3840x2160@100Hz 64:27 */
1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 120 - 3840x2160@120Hz 64:27 */
1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 121 - 5120x2160@24Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 122 - 5120x2160@25Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 123 - 5120x2160@30Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 124 - 5120x2160@48Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 /* 125 - 5120x2160@50Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 126 - 5120x2160@60Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 127 - 5120x2160@100Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1410};
1411
1412/*
1413 * From CEA/CTA-861 spec.
1414 *
1415 * Do not access directly, instead always use cea_mode_for_vic().
1416 */
1417static const struct drm_display_mode edid_cea_modes_193[] = {
1418 /* 193 - 5120x2160@120Hz 64:27 */
1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1423 /* 194 - 7680x4320@24Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 195 - 7680x4320@25Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 196 - 7680x4320@30Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 197 - 7680x4320@48Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 198 - 7680x4320@50Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 199 - 7680x4320@60Hz 16:9 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1453 /* 200 - 7680x4320@100Hz 16:9 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1458 /* 201 - 7680x4320@120Hz 16:9 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1463 /* 202 - 7680x4320@24Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 203 - 7680x4320@25Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 204 - 7680x4320@30Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 205 - 7680x4320@48Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 206 - 7680x4320@50Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 207 - 7680x4320@60Hz 64:27 */
1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 208 - 7680x4320@100Hz 64:27 */
1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 209 - 7680x4320@120Hz 64:27 */
1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 210 - 10240x4320@24Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 211 - 10240x4320@25Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 212 - 10240x4320@30Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 213 - 10240x4320@48Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 214 - 10240x4320@50Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 215 - 10240x4320@60Hz 64:27 */
1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1533 /* 216 - 10240x4320@100Hz 64:27 */
1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1538 /* 217 - 10240x4320@120Hz 64:27 */
1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1543 /* 218 - 4096x2160@100Hz 256:135 */
1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1548 /* 219 - 4096x2160@120Hz 256:135 */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1553};
1554
1555/*
1556 * HDMI 1.4 4k modes. Index using the VIC.
1557 */
1558static const struct drm_display_mode edid_4k_modes[] = {
1559 /* 0 - dummy, VICs start at 1 */
1560 { },
1561 /* 1 - 3840x2160@30Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 4016, 4104, 4400, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 2 - 3840x2160@25Hz */
1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 3840, 4896, 4984, 5280, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1573 /* 3 - 3840x2160@24Hz */
1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1575 3840, 5116, 5204, 5500, 0,
1576 2160, 2168, 2178, 2250, 0,
1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1579 /* 4 - 4096x2160@24Hz (SMPTE) */
1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1581 4096, 5116, 5204, 5500, 0,
1582 2160, 2168, 2178, 2250, 0,
1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1585};
1586
1587/*** DDC fetch and block validation ***/
1588
1589/*
1590 * The opaque EDID type, internal to drm_edid.c.
1591 */
1592struct drm_edid {
1593 /* Size allocated for edid */
1594 size_t size;
1595 const struct edid *edid;
1596};
1597
1598static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1599
1600static int edid_hfeeodb_block_count(const struct edid *edid)
1601{
1602 int eeodb = edid_hfeeodb_extension_block_count(edid);
1603
1604 return eeodb ? eeodb + 1 : 0;
1605}
1606
1607static int edid_extension_block_count(const struct edid *edid)
1608{
1609 return edid->extensions;
1610}
1611
1612static int edid_block_count(const struct edid *edid)
1613{
1614 return edid_extension_block_count(edid) + 1;
1615}
1616
1617static int edid_size_by_blocks(int num_blocks)
1618{
1619 return num_blocks * EDID_LENGTH;
1620}
1621
1622static int edid_size(const struct edid *edid)
1623{
1624 return edid_size_by_blocks(edid_block_count(edid));
1625}
1626
1627static const void *edid_block_data(const struct edid *edid, int index)
1628{
1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1630
1631 return edid + index;
1632}
1633
1634static const void *edid_extension_block_data(const struct edid *edid, int index)
1635{
1636 return edid_block_data(edid, index + 1);
1637}
1638
1639/* EDID block count indicated in EDID, may exceed allocated size */
1640static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1641{
1642 int num_blocks;
1643
1644 /* Starting point */
1645 num_blocks = edid_block_count(drm_edid->edid);
1646
1647 /* HF-EEODB override */
1648 if (drm_edid->size >= edid_size_by_blocks(2)) {
1649 int eeodb;
1650
1651 /*
1652 * Note: HF-EEODB may specify a smaller extension count than the
1653 * regular one. Unlike in buffer allocation, here we can use it.
1654 */
1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1656 if (eeodb)
1657 num_blocks = eeodb;
1658 }
1659
1660 return num_blocks;
1661}
1662
1663/* EDID block count, limited by allocated size */
1664static int drm_edid_block_count(const struct drm_edid *drm_edid)
1665{
1666 /* Limit by allocated size */
1667 return min(__drm_edid_block_count(drm_edid),
1668 (int)drm_edid->size / EDID_LENGTH);
1669}
1670
1671/* EDID extension block count, limited by allocated size */
1672static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1673{
1674 return drm_edid_block_count(drm_edid) - 1;
1675}
1676
1677static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1678{
1679 return edid_block_data(drm_edid->edid, index);
1680}
1681
1682static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1683 int index)
1684{
1685 return edid_extension_block_data(drm_edid->edid, index);
1686}
1687
1688/*
1689 * Initializer helper for legacy interfaces, where we have no choice but to
1690 * trust edid size. Not for general purpose use.
1691 */
1692static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1693 const struct edid *edid)
1694{
1695 if (!edid)
1696 return NULL;
1697
1698 memset(drm_edid, 0, sizeof(*drm_edid));
1699
1700 drm_edid->edid = edid;
1701 drm_edid->size = edid_size(edid);
1702
1703 return drm_edid;
1704}
1705
1706/*
1707 * EDID base and extension block iterator.
1708 *
1709 * struct drm_edid_iter iter;
1710 * const u8 *block;
1711 *
1712 * drm_edid_iter_begin(drm_edid, &iter);
1713 * drm_edid_iter_for_each(block, &iter) {
1714 * // do stuff with block
1715 * }
1716 * drm_edid_iter_end(&iter);
1717 */
1718struct drm_edid_iter {
1719 const struct drm_edid *drm_edid;
1720
1721 /* Current block index. */
1722 int index;
1723};
1724
1725static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1726 struct drm_edid_iter *iter)
1727{
1728 memset(iter, 0, sizeof(*iter));
1729
1730 iter->drm_edid = drm_edid;
1731}
1732
1733static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1734{
1735 const void *block = NULL;
1736
1737 if (!iter->drm_edid)
1738 return NULL;
1739
1740 if (iter->index < drm_edid_block_count(iter->drm_edid))
1741 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1742
1743 return block;
1744}
1745
1746#define drm_edid_iter_for_each(__block, __iter) \
1747 while (((__block) = __drm_edid_iter_next(__iter)))
1748
1749static void drm_edid_iter_end(struct drm_edid_iter *iter)
1750{
1751 memset(iter, 0, sizeof(*iter));
1752}
1753
1754static const u8 edid_header[] = {
1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1756};
1757
1758static void edid_header_fix(void *edid)
1759{
1760 memcpy(edid, edid_header, sizeof(edid_header));
1761}
1762
1763/**
1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1765 * @_edid: pointer to raw base EDID block
1766 *
1767 * Sanity check the header of the base EDID block.
1768 *
1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1770 */
1771int drm_edid_header_is_valid(const void *_edid)
1772{
1773 const struct edid *edid = _edid;
1774 int i, score = 0;
1775
1776 for (i = 0; i < sizeof(edid_header); i++) {
1777 if (edid->header[i] == edid_header[i])
1778 score++;
1779 }
1780
1781 return score;
1782}
1783EXPORT_SYMBOL(drm_edid_header_is_valid);
1784
1785static int edid_fixup __read_mostly = 6;
1786module_param_named(edid_fixup, edid_fixup, int, 0400);
1787MODULE_PARM_DESC(edid_fixup,
1788 "Minimum number of valid EDID header bytes (0-8, default 6)");
1789
1790static int edid_block_compute_checksum(const void *_block)
1791{
1792 const u8 *block = _block;
1793 int i;
1794 u8 csum = 0, crc = 0;
1795
1796 for (i = 0; i < EDID_LENGTH - 1; i++)
1797 csum += block[i];
1798
1799 crc = 0x100 - csum;
1800
1801 return crc;
1802}
1803
1804static int edid_block_get_checksum(const void *_block)
1805{
1806 const struct edid *block = _block;
1807
1808 return block->checksum;
1809}
1810
1811static int edid_block_tag(const void *_block)
1812{
1813 const u8 *block = _block;
1814
1815 return block[0];
1816}
1817
1818static bool edid_block_is_zero(const void *edid)
1819{
1820 return mem_is_zero(edid, EDID_LENGTH);
1821}
1822
1823static bool drm_edid_eq(const struct drm_edid *drm_edid,
1824 const void *raw_edid, size_t raw_edid_size)
1825{
1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1827 bool edid2_present = raw_edid && raw_edid_size;
1828
1829 if (edid1_present != edid2_present)
1830 return false;
1831
1832 if (edid1_present) {
1833 if (drm_edid->size != raw_edid_size)
1834 return false;
1835
1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
1837 return false;
1838 }
1839
1840 return true;
1841}
1842
1843enum edid_block_status {
1844 EDID_BLOCK_OK = 0,
1845 EDID_BLOCK_READ_FAIL,
1846 EDID_BLOCK_NULL,
1847 EDID_BLOCK_ZERO,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1852 EDID_BLOCK_VERSION,
1853};
1854
1855static enum edid_block_status edid_block_check(const void *_block,
1856 bool is_base_block)
1857{
1858 const struct edid *block = _block;
1859
1860 if (!block)
1861 return EDID_BLOCK_NULL;
1862
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1865
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1869 else
1870 return EDID_BLOCK_HEADER_CORRUPT;
1871 }
1872
1873 if (score < 8)
1874 return EDID_BLOCK_HEADER_REPAIR;
1875 }
1876
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1880 else
1881 return EDID_BLOCK_CHECKSUM;
1882 }
1883
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1887 }
1888
1889 return EDID_BLOCK_OK;
1890}
1891
1892static bool edid_block_status_valid(enum edid_block_status status, int tag)
1893{
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1897}
1898
1899static bool edid_block_valid(const void *block, bool base)
1900{
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1903}
1904
1905static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1907 int block_num)
1908{
1909 switch (status) {
1910 case EDID_BLOCK_OK:
1911 break;
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1914 break;
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1917 break;
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1920 break;
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1923 break;
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1926 break;
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1929 break;
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1935 } else {
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1939 }
1940 break;
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1943 block->version);
1944 break;
1945 default:
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1947 block_num, status);
1948 break;
1949 }
1950}
1951
1952static void edid_block_dump(const char *level, const void *block, int block_num)
1953{
1954 enum edid_block_status status;
1955 char prefix[20];
1956
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1962 else
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1964
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1967}
1968
1969/*
1970 * Validate a base or extension EDID block and optionally dump bad blocks to
1971 * the console.
1972 */
1973static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
1974 bool *edid_corrupt)
1975{
1976 struct edid *block = _block;
1977 enum edid_block_status status;
1978 bool is_base_block = block_num == 0;
1979 bool valid;
1980
1981 if (WARN_ON(!block))
1982 return false;
1983
1984 status = edid_block_check(block, is_base_block);
1985 if (status == EDID_BLOCK_HEADER_REPAIR) {
1986 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1987 edid_header_fix(block);
1988
1989 /* Retry with fixed header, update status if that worked. */
1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_OK)
1992 status = EDID_BLOCK_HEADER_FIXED;
1993 }
1994
1995 if (edid_corrupt) {
1996 /*
1997 * Unknown major version isn't corrupt but we can't use it. Only
1998 * the base block can reset edid_corrupt to false.
1999 */
2000 if (is_base_block &&
2001 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2002 *edid_corrupt = false;
2003 else if (status != EDID_BLOCK_OK)
2004 *edid_corrupt = true;
2005 }
2006
2007 edid_block_status_print(status, block, block_num);
2008
2009 /* Determine whether we can use this block with this status. */
2010 valid = edid_block_status_valid(status, edid_block_tag(block));
2011
2012 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2013 pr_notice("Raw EDID:\n");
2014 edid_block_dump(KERN_NOTICE, block, block_num);
2015 }
2016
2017 return valid;
2018}
2019
2020/**
2021 * drm_edid_is_valid - sanity check EDID data
2022 * @edid: EDID data
2023 *
2024 * Sanity-check an entire EDID record (including extensions)
2025 *
2026 * Return: True if the EDID data is valid, false otherwise.
2027 */
2028bool drm_edid_is_valid(struct edid *edid)
2029{
2030 int i;
2031
2032 if (!edid)
2033 return false;
2034
2035 for (i = 0; i < edid_block_count(edid); i++) {
2036 void *block = (void *)edid_block_data(edid, i);
2037
2038 if (!drm_edid_block_valid(block, i, true, NULL))
2039 return false;
2040 }
2041
2042 return true;
2043}
2044EXPORT_SYMBOL(drm_edid_is_valid);
2045
2046/**
2047 * drm_edid_valid - sanity check EDID data
2048 * @drm_edid: EDID data
2049 *
2050 * Sanity check an EDID. Cross check block count against allocated size and
2051 * checksum the blocks.
2052 *
2053 * Return: True if the EDID data is valid, false otherwise.
2054 */
2055bool drm_edid_valid(const struct drm_edid *drm_edid)
2056{
2057 int i;
2058
2059 if (!drm_edid)
2060 return false;
2061
2062 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2063 return false;
2064
2065 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2066 const void *block = drm_edid_block_data(drm_edid, i);
2067
2068 if (!edid_block_valid(block, i == 0))
2069 return false;
2070 }
2071
2072 return true;
2073}
2074EXPORT_SYMBOL(drm_edid_valid);
2075
2076static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2077 size_t *alloc_size)
2078{
2079 struct edid *new;
2080 int i, valid_blocks = 0;
2081
2082 /*
2083 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2084 * back to regular extension count here. We don't want to start
2085 * modifying the HF-EEODB extension too.
2086 */
2087 for (i = 0; i < edid_block_count(edid); i++) {
2088 const void *src_block = edid_block_data(edid, i);
2089
2090 if (edid_block_valid(src_block, i == 0)) {
2091 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2092
2093 memmove(dst_block, src_block, EDID_LENGTH);
2094 valid_blocks++;
2095 }
2096 }
2097
2098 /* We already trusted the base block to be valid here... */
2099 if (WARN_ON(!valid_blocks)) {
2100 kfree(edid);
2101 return NULL;
2102 }
2103
2104 edid->extensions = valid_blocks - 1;
2105 edid->checksum = edid_block_compute_checksum(edid);
2106
2107 *alloc_size = edid_size_by_blocks(valid_blocks);
2108
2109 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2110 if (!new)
2111 kfree(edid);
2112
2113 return new;
2114}
2115
2116#define DDC_SEGMENT_ADDR 0x30
2117/**
2118 * drm_do_probe_ddc_edid() - get EDID information via I2C
2119 * @data: I2C device adapter
2120 * @buf: EDID data buffer to be filled
2121 * @block: 128 byte EDID block to start fetching from
2122 * @len: EDID data buffer length to fetch
2123 *
2124 * Try to fetch EDID information by calling I2C driver functions.
2125 *
2126 * Return: 0 on success or -1 on failure.
2127 */
2128static int
2129drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2130{
2131 struct i2c_adapter *adapter = data;
2132 unsigned char start = block * EDID_LENGTH;
2133 unsigned char segment = block >> 1;
2134 unsigned char xfers = segment ? 3 : 2;
2135 int ret, retries = 5;
2136
2137 /*
2138 * The core I2C driver will automatically retry the transfer if the
2139 * adapter reports EAGAIN. However, we find that bit-banging transfers
2140 * are susceptible to errors under a heavily loaded machine and
2141 * generate spurious NAKs and timeouts. Retrying the transfer
2142 * of the individual block a few times seems to overcome this.
2143 */
2144 do {
2145 struct i2c_msg msgs[] = {
2146 {
2147 .addr = DDC_SEGMENT_ADDR,
2148 .flags = 0,
2149 .len = 1,
2150 .buf = &segment,
2151 }, {
2152 .addr = DDC_ADDR,
2153 .flags = 0,
2154 .len = 1,
2155 .buf = &start,
2156 }, {
2157 .addr = DDC_ADDR,
2158 .flags = I2C_M_RD,
2159 .len = len,
2160 .buf = buf,
2161 }
2162 };
2163
2164 /*
2165 * Avoid sending the segment addr to not upset non-compliant
2166 * DDC monitors.
2167 */
2168 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2169
2170 if (ret == -ENXIO) {
2171 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2172 adapter->name);
2173 break;
2174 }
2175 } while (ret != xfers && --retries);
2176
2177 return ret == xfers ? 0 : -1;
2178}
2179
2180static void connector_bad_edid(struct drm_connector *connector,
2181 const struct edid *edid, int num_blocks)
2182{
2183 int i;
2184 u8 last_block;
2185
2186 /*
2187 * 0x7e in the EDID is the number of extension blocks. The EDID
2188 * is 1 (base block) + num_ext_blocks big. That means we can think
2189 * of 0x7e in the EDID of the _index_ of the last block in the
2190 * combined chunk of memory.
2191 */
2192 last_block = edid->extensions;
2193
2194 /* Calculate real checksum for the last edid extension block data */
2195 if (last_block < num_blocks)
2196 connector->real_edid_checksum =
2197 edid_block_compute_checksum(edid + last_block);
2198
2199 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2200 return;
2201
2202 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2203 connector->base.id, connector->name);
2204 for (i = 0; i < num_blocks; i++)
2205 edid_block_dump(KERN_DEBUG, edid + i, i);
2206}
2207
2208/* Get override or firmware EDID */
2209static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2210{
2211 const struct drm_edid *override = NULL;
2212
2213 mutex_lock(&connector->edid_override_mutex);
2214
2215 if (connector->edid_override)
2216 override = drm_edid_dup(connector->edid_override);
2217
2218 mutex_unlock(&connector->edid_override_mutex);
2219
2220 if (!override)
2221 override = drm_edid_load_firmware(connector);
2222
2223 return IS_ERR(override) ? NULL : override;
2224}
2225
2226/* For debugfs edid_override implementation */
2227int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2228{
2229 const struct drm_edid *drm_edid;
2230
2231 mutex_lock(&connector->edid_override_mutex);
2232
2233 drm_edid = connector->edid_override;
2234 if (drm_edid)
2235 seq_write(m, drm_edid->edid, drm_edid->size);
2236
2237 mutex_unlock(&connector->edid_override_mutex);
2238
2239 return 0;
2240}
2241
2242/* For debugfs edid_override implementation */
2243int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2244 size_t size)
2245{
2246 const struct drm_edid *drm_edid;
2247
2248 drm_edid = drm_edid_alloc(edid, size);
2249 if (!drm_edid_valid(drm_edid)) {
2250 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2251 connector->base.id, connector->name);
2252 drm_edid_free(drm_edid);
2253 return -EINVAL;
2254 }
2255
2256 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2257 connector->base.id, connector->name);
2258
2259 mutex_lock(&connector->edid_override_mutex);
2260
2261 drm_edid_free(connector->edid_override);
2262 connector->edid_override = drm_edid;
2263
2264 mutex_unlock(&connector->edid_override_mutex);
2265
2266 return 0;
2267}
2268
2269/* For debugfs edid_override implementation */
2270int drm_edid_override_reset(struct drm_connector *connector)
2271{
2272 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2273 connector->base.id, connector->name);
2274
2275 mutex_lock(&connector->edid_override_mutex);
2276
2277 drm_edid_free(connector->edid_override);
2278 connector->edid_override = NULL;
2279
2280 mutex_unlock(&connector->edid_override_mutex);
2281
2282 return 0;
2283}
2284
2285/**
2286 * drm_edid_override_connector_update - add modes from override/firmware EDID
2287 * @connector: connector we're probing
2288 *
2289 * Add modes from the override/firmware EDID, if available. Only to be used from
2290 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2291 * failed during drm_get_edid() and caused the override/firmware EDID to be
2292 * skipped.
2293 *
2294 * Return: The number of modes added or 0 if we couldn't find any.
2295 */
2296int drm_edid_override_connector_update(struct drm_connector *connector)
2297{
2298 const struct drm_edid *override;
2299 int num_modes = 0;
2300
2301 override = drm_edid_override_get(connector);
2302 if (override) {
2303 if (drm_edid_connector_update(connector, override) == 0)
2304 num_modes = drm_edid_connector_add_modes(connector);
2305
2306 drm_edid_free(override);
2307
2308 drm_dbg_kms(connector->dev,
2309 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2310 connector->base.id, connector->name, num_modes);
2311 }
2312
2313 return num_modes;
2314}
2315EXPORT_SYMBOL(drm_edid_override_connector_update);
2316
2317typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2318
2319static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2320 read_block_fn read_block,
2321 void *context)
2322{
2323 enum edid_block_status status;
2324 bool is_base_block = block_num == 0;
2325 int try;
2326
2327 for (try = 0; try < 4; try++) {
2328 if (read_block(context, block, block_num, EDID_LENGTH))
2329 return EDID_BLOCK_READ_FAIL;
2330
2331 status = edid_block_check(block, is_base_block);
2332 if (status == EDID_BLOCK_HEADER_REPAIR) {
2333 edid_header_fix(block);
2334
2335 /* Retry with fixed header, update status if that worked. */
2336 status = edid_block_check(block, is_base_block);
2337 if (status == EDID_BLOCK_OK)
2338 status = EDID_BLOCK_HEADER_FIXED;
2339 }
2340
2341 if (edid_block_status_valid(status, edid_block_tag(block)))
2342 break;
2343
2344 /* Fail early for unrepairable base block all zeros. */
2345 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2346 break;
2347 }
2348
2349 return status;
2350}
2351
2352static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2353 read_block_fn read_block, void *context,
2354 size_t *size)
2355{
2356 enum edid_block_status status;
2357 int i, num_blocks, invalid_blocks = 0;
2358 const struct drm_edid *override;
2359 struct edid *edid, *new;
2360 size_t alloc_size = EDID_LENGTH;
2361
2362 override = drm_edid_override_get(connector);
2363 if (override) {
2364 alloc_size = override->size;
2365 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2366 drm_edid_free(override);
2367 if (!edid)
2368 return NULL;
2369 goto ok;
2370 }
2371
2372 edid = kmalloc(alloc_size, GFP_KERNEL);
2373 if (!edid)
2374 return NULL;
2375
2376 status = edid_block_read(edid, 0, read_block, context);
2377
2378 edid_block_status_print(status, edid, 0);
2379
2380 if (status == EDID_BLOCK_READ_FAIL)
2381 goto fail;
2382
2383 /* FIXME: Clarify what a corrupt EDID actually means. */
2384 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2385 connector->edid_corrupt = false;
2386 else
2387 connector->edid_corrupt = true;
2388
2389 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2390 if (status == EDID_BLOCK_ZERO)
2391 connector->null_edid_counter++;
2392
2393 connector_bad_edid(connector, edid, 1);
2394 goto fail;
2395 }
2396
2397 if (!edid_extension_block_count(edid))
2398 goto ok;
2399
2400 alloc_size = edid_size(edid);
2401 new = krealloc(edid, alloc_size, GFP_KERNEL);
2402 if (!new)
2403 goto fail;
2404 edid = new;
2405
2406 num_blocks = edid_block_count(edid);
2407 for (i = 1; i < num_blocks; i++) {
2408 void *block = (void *)edid_block_data(edid, i);
2409
2410 status = edid_block_read(block, i, read_block, context);
2411
2412 edid_block_status_print(status, block, i);
2413
2414 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2415 if (status == EDID_BLOCK_READ_FAIL)
2416 goto fail;
2417 invalid_blocks++;
2418 } else if (i == 1) {
2419 /*
2420 * If the first EDID extension is a CTA extension, and
2421 * the first Data Block is HF-EEODB, override the
2422 * extension block count.
2423 *
2424 * Note: HF-EEODB could specify a smaller extension
2425 * count too, but we can't risk allocating a smaller
2426 * amount.
2427 */
2428 int eeodb = edid_hfeeodb_block_count(edid);
2429
2430 if (eeodb > num_blocks) {
2431 num_blocks = eeodb;
2432 alloc_size = edid_size_by_blocks(num_blocks);
2433 new = krealloc(edid, alloc_size, GFP_KERNEL);
2434 if (!new)
2435 goto fail;
2436 edid = new;
2437 }
2438 }
2439 }
2440
2441 if (invalid_blocks) {
2442 connector_bad_edid(connector, edid, num_blocks);
2443
2444 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2445 }
2446
2447ok:
2448 if (size)
2449 *size = alloc_size;
2450
2451 return edid;
2452
2453fail:
2454 kfree(edid);
2455 return NULL;
2456}
2457
2458/**
2459 * drm_edid_raw - Get a pointer to the raw EDID data.
2460 * @drm_edid: drm_edid container
2461 *
2462 * Get a pointer to the raw EDID data.
2463 *
2464 * This is for transition only. Avoid using this like the plague.
2465 *
2466 * Return: Pointer to raw EDID data.
2467 */
2468const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2469{
2470 if (!drm_edid || !drm_edid->size)
2471 return NULL;
2472
2473 /*
2474 * Do not return pointers where relying on EDID extension count would
2475 * lead to buffer overflow.
2476 */
2477 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2478 return NULL;
2479
2480 return drm_edid->edid;
2481}
2482EXPORT_SYMBOL(drm_edid_raw);
2483
2484/* Allocate struct drm_edid container *without* duplicating the edid data */
2485static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2486{
2487 struct drm_edid *drm_edid;
2488
2489 if (!edid || !size || size < EDID_LENGTH)
2490 return NULL;
2491
2492 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2493 if (drm_edid) {
2494 drm_edid->edid = edid;
2495 drm_edid->size = size;
2496 }
2497
2498 return drm_edid;
2499}
2500
2501/**
2502 * drm_edid_alloc - Allocate a new drm_edid container
2503 * @edid: Pointer to raw EDID data
2504 * @size: Size of memory allocated for EDID
2505 *
2506 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2507 * the actual size that has been allocated for the data. There is no validation
2508 * of the raw EDID data against the size, but at least the EDID base block must
2509 * fit in the buffer.
2510 *
2511 * The returned pointer must be freed using drm_edid_free().
2512 *
2513 * Return: drm_edid container, or NULL on errors
2514 */
2515const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2516{
2517 const struct drm_edid *drm_edid;
2518
2519 if (!edid || !size || size < EDID_LENGTH)
2520 return NULL;
2521
2522 edid = kmemdup(edid, size, GFP_KERNEL);
2523 if (!edid)
2524 return NULL;
2525
2526 drm_edid = _drm_edid_alloc(edid, size);
2527 if (!drm_edid)
2528 kfree(edid);
2529
2530 return drm_edid;
2531}
2532EXPORT_SYMBOL(drm_edid_alloc);
2533
2534/**
2535 * drm_edid_dup - Duplicate a drm_edid container
2536 * @drm_edid: EDID to duplicate
2537 *
2538 * The returned pointer must be freed using drm_edid_free().
2539 *
2540 * Returns: drm_edid container copy, or NULL on errors
2541 */
2542const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2543{
2544 if (!drm_edid)
2545 return NULL;
2546
2547 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2548}
2549EXPORT_SYMBOL(drm_edid_dup);
2550
2551/**
2552 * drm_edid_free - Free the drm_edid container
2553 * @drm_edid: EDID to free
2554 */
2555void drm_edid_free(const struct drm_edid *drm_edid)
2556{
2557 if (!drm_edid)
2558 return;
2559
2560 kfree(drm_edid->edid);
2561 kfree(drm_edid);
2562}
2563EXPORT_SYMBOL(drm_edid_free);
2564
2565/**
2566 * drm_probe_ddc() - probe DDC presence
2567 * @adapter: I2C adapter to probe
2568 *
2569 * Return: True on success, false on failure.
2570 */
2571bool
2572drm_probe_ddc(struct i2c_adapter *adapter)
2573{
2574 unsigned char out;
2575
2576 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2577}
2578EXPORT_SYMBOL(drm_probe_ddc);
2579
2580/**
2581 * drm_get_edid - get EDID data, if available
2582 * @connector: connector we're probing
2583 * @adapter: I2C adapter to use for DDC
2584 *
2585 * Poke the given I2C channel to grab EDID data if possible. If found,
2586 * attach it to the connector.
2587 *
2588 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2589 */
2590struct edid *drm_get_edid(struct drm_connector *connector,
2591 struct i2c_adapter *adapter)
2592{
2593 struct edid *edid;
2594
2595 if (connector->force == DRM_FORCE_OFF)
2596 return NULL;
2597
2598 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2599 return NULL;
2600
2601 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2602 drm_connector_update_edid_property(connector, edid);
2603 return edid;
2604}
2605EXPORT_SYMBOL(drm_get_edid);
2606
2607/**
2608 * drm_edid_read_custom - Read EDID data using given EDID block read function
2609 * @connector: Connector to use
2610 * @read_block: EDID block read function
2611 * @context: Private data passed to the block read function
2612 *
2613 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2614 * exposes a different interface to read EDID blocks this function can be used
2615 * to get EDID data using a custom block read function.
2616 *
2617 * As in the general case the DDC bus is accessible by the kernel at the I2C
2618 * level, drivers must make all reasonable efforts to expose it as an I2C
2619 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2620 * this function.
2621 *
2622 * The EDID may be overridden using debugfs override_edid or firmware EDID
2623 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2624 * order. Having either of them bypasses actual EDID reads.
2625 *
2626 * The returned pointer must be freed using drm_edid_free().
2627 *
2628 * Return: Pointer to EDID, or NULL if probe/read failed.
2629 */
2630const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2631 read_block_fn read_block,
2632 void *context)
2633{
2634 const struct drm_edid *drm_edid;
2635 struct edid *edid;
2636 size_t size = 0;
2637
2638 edid = _drm_do_get_edid(connector, read_block, context, &size);
2639 if (!edid)
2640 return NULL;
2641
2642 /* Sanity check for now */
2643 drm_WARN_ON(connector->dev, !size);
2644
2645 drm_edid = _drm_edid_alloc(edid, size);
2646 if (!drm_edid)
2647 kfree(edid);
2648
2649 return drm_edid;
2650}
2651EXPORT_SYMBOL(drm_edid_read_custom);
2652
2653/**
2654 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2655 * @connector: Connector to use
2656 * @adapter: I2C adapter to use for DDC
2657 *
2658 * Read EDID using the given I2C adapter.
2659 *
2660 * The EDID may be overridden using debugfs override_edid or firmware EDID
2661 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2662 * order. Having either of them bypasses actual EDID reads.
2663 *
2664 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2665 * using drm_edid_read() instead of this function.
2666 *
2667 * The returned pointer must be freed using drm_edid_free().
2668 *
2669 * Return: Pointer to EDID, or NULL if probe/read failed.
2670 */
2671const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2672 struct i2c_adapter *adapter)
2673{
2674 const struct drm_edid *drm_edid;
2675
2676 if (connector->force == DRM_FORCE_OFF)
2677 return NULL;
2678
2679 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2680 return NULL;
2681
2682 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2683
2684 /* Note: Do *not* call connector updates here. */
2685
2686 return drm_edid;
2687}
2688EXPORT_SYMBOL(drm_edid_read_ddc);
2689
2690/**
2691 * drm_edid_read - Read EDID data using connector's I2C adapter
2692 * @connector: Connector to use
2693 *
2694 * Read EDID using the connector's I2C adapter.
2695 *
2696 * The EDID may be overridden using debugfs override_edid or firmware EDID
2697 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2698 * order. Having either of them bypasses actual EDID reads.
2699 *
2700 * The returned pointer must be freed using drm_edid_free().
2701 *
2702 * Return: Pointer to EDID, or NULL if probe/read failed.
2703 */
2704const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2705{
2706 if (drm_WARN_ON(connector->dev, !connector->ddc))
2707 return NULL;
2708
2709 return drm_edid_read_ddc(connector, connector->ddc);
2710}
2711EXPORT_SYMBOL(drm_edid_read);
2712
2713/**
2714 * drm_edid_get_product_id - Get the vendor and product identification
2715 * @drm_edid: EDID
2716 * @id: Where to place the product id
2717 */
2718void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2719 struct drm_edid_product_id *id)
2720{
2721 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2722 memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2723 else
2724 memset(id, 0, sizeof(*id));
2725}
2726EXPORT_SYMBOL(drm_edid_get_product_id);
2727
2728static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2729{
2730 int week = id->week_of_manufacture;
2731 int year = id->year_of_manufacture + 1990;
2732
2733 if (week == 0xff)
2734 seq_buf_printf(s, "model year: %d", year);
2735 else if (!week)
2736 seq_buf_printf(s, "year of manufacture: %d", year);
2737 else
2738 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2739}
2740
2741/**
2742 * drm_edid_print_product_id - Print decoded product id to printer
2743 * @p: drm printer
2744 * @id: EDID product id
2745 * @raw: If true, also print the raw hex
2746 *
2747 * See VESA E-EDID 1.4 section 3.4.
2748 */
2749void drm_edid_print_product_id(struct drm_printer *p,
2750 const struct drm_edid_product_id *id, bool raw)
2751{
2752 DECLARE_SEQ_BUF(date, 40);
2753 char vend[4];
2754
2755 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2756
2757 decode_date(&date, id);
2758
2759 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2760 vend, le16_to_cpu(id->product_code),
2761 le32_to_cpu(id->serial_number), seq_buf_str(&date));
2762
2763 if (raw)
2764 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2765
2766 WARN_ON(seq_buf_has_overflowed(&date));
2767}
2768EXPORT_SYMBOL(drm_edid_print_product_id);
2769
2770/**
2771 * drm_edid_get_panel_id - Get a panel's ID from EDID
2772 * @drm_edid: EDID that contains panel ID.
2773 *
2774 * This function uses the first block of the EDID of a panel and (assuming
2775 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2776 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2777 * supposed to be different for each different modem of panel.
2778 *
2779 * Return: A 32-bit ID that should be different for each make/model of panel.
2780 * See the functions drm_edid_encode_panel_id() and
2781 * drm_edid_decode_panel_id() for some details on the structure of this
2782 * ID. Return 0 if the EDID size is less than a base block.
2783 */
2784u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
2785{
2786 const struct edid *edid = drm_edid->edid;
2787
2788 if (drm_edid->size < EDID_LENGTH)
2789 return 0;
2790
2791 /*
2792 * We represent the ID as a 32-bit number so it can easily be compared
2793 * with "==".
2794 *
2795 * NOTE that we deal with endianness differently for the top half
2796 * of this ID than for the bottom half. The bottom half (the product
2797 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2798 * that's how everyone seems to interpret it. The top half (the mfg_id)
2799 * gets stored as big endian because that makes
2800 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2801 * to write (it's easier to extract the ASCII). It doesn't really
2802 * matter, though, as long as the number here is unique.
2803 */
2804 return (u32)edid->mfg_id[0] << 24 |
2805 (u32)edid->mfg_id[1] << 16 |
2806 (u32)EDID_PRODUCT_ID(edid);
2807}
2808EXPORT_SYMBOL(drm_edid_get_panel_id);
2809
2810/**
2811 * drm_edid_read_base_block - Get a panel's EDID base block
2812 * @adapter: I2C adapter to use for DDC
2813 *
2814 * This function returns the drm_edid containing the first block of the EDID of
2815 * a panel.
2816 *
2817 * This function is intended to be used during early probing on devices where
2818 * more than one panel might be present. Because of its intended use it must
2819 * assume that the EDID of the panel is correct, at least as far as the base
2820 * block is concerned (in other words, we don't process any overrides here).
2821 *
2822 * Caller should call drm_edid_free() after use.
2823 *
2824 * NOTE: it's expected that this function and drm_do_get_edid() will both
2825 * be read the EDID, but there is no caching between them. Since we're only
2826 * reading the first block, hopefully this extra overhead won't be too big.
2827 *
2828 * WARNING: Only use this function when the connector is unknown. For example,
2829 * during the early probe of panel. The EDID read from the function is temporary
2830 * and should be replaced by the full EDID returned from other drm_edid_read.
2831 *
2832 * Return: Pointer to allocated EDID base block, or NULL on any failure.
2833 */
2834const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
2835{
2836 enum edid_block_status status;
2837 void *base_block;
2838
2839 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2840 if (!base_block)
2841 return NULL;
2842
2843 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2844
2845 edid_block_status_print(status, base_block, 0);
2846
2847 if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
2848 edid_block_dump(KERN_NOTICE, base_block, 0);
2849 kfree(base_block);
2850 return NULL;
2851 }
2852
2853 return _drm_edid_alloc(base_block, EDID_LENGTH);
2854}
2855EXPORT_SYMBOL(drm_edid_read_base_block);
2856
2857/**
2858 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2859 * @connector: connector we're probing
2860 * @adapter: I2C adapter to use for DDC
2861 *
2862 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2863 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2864 * switch DDC to the GPU which is retrieving EDID.
2865 *
2866 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2867 */
2868struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2869 struct i2c_adapter *adapter)
2870{
2871 struct drm_device *dev = connector->dev;
2872 struct pci_dev *pdev = to_pci_dev(dev->dev);
2873 struct edid *edid;
2874
2875 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2876 return NULL;
2877
2878 vga_switcheroo_lock_ddc(pdev);
2879 edid = drm_get_edid(connector, adapter);
2880 vga_switcheroo_unlock_ddc(pdev);
2881
2882 return edid;
2883}
2884EXPORT_SYMBOL(drm_get_edid_switcheroo);
2885
2886/**
2887 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2888 * @connector: connector we're probing
2889 * @adapter: I2C adapter to use for DDC
2890 *
2891 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2892 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2893 * temporarily switch DDC to the GPU which is retrieving EDID.
2894 *
2895 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2896 */
2897const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2898 struct i2c_adapter *adapter)
2899{
2900 struct drm_device *dev = connector->dev;
2901 struct pci_dev *pdev = to_pci_dev(dev->dev);
2902 const struct drm_edid *drm_edid;
2903
2904 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2905 return NULL;
2906
2907 vga_switcheroo_lock_ddc(pdev);
2908 drm_edid = drm_edid_read_ddc(connector, adapter);
2909 vga_switcheroo_unlock_ddc(pdev);
2910
2911 return drm_edid;
2912}
2913EXPORT_SYMBOL(drm_edid_read_switcheroo);
2914
2915/**
2916 * drm_edid_duplicate - duplicate an EDID and the extensions
2917 * @edid: EDID to duplicate
2918 *
2919 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2920 */
2921struct edid *drm_edid_duplicate(const struct edid *edid)
2922{
2923 if (!edid)
2924 return NULL;
2925
2926 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2927}
2928EXPORT_SYMBOL(drm_edid_duplicate);
2929
2930/*** EDID parsing ***/
2931
2932/**
2933 * edid_get_quirks - return quirk flags for a given EDID
2934 * @drm_edid: EDID to process
2935 *
2936 * This tells subsequent routines what fixes they need to apply.
2937 *
2938 * Return: A u32 represents the quirks to apply.
2939 */
2940static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2941{
2942 const struct edid_quirk *quirk;
2943 int i;
2944
2945 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2946 quirk = &edid_quirk_list[i];
2947 if (drm_edid_match(drm_edid, &quirk->ident))
2948 return quirk->quirks;
2949 }
2950
2951 return 0;
2952}
2953
2954#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2955#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2956
2957/*
2958 * Walk the mode list for connector, clearing the preferred status on existing
2959 * modes and setting it anew for the right mode ala quirks.
2960 */
2961static void edid_fixup_preferred(struct drm_connector *connector)
2962{
2963 const struct drm_display_info *info = &connector->display_info;
2964 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2965 int target_refresh = 0;
2966 int cur_vrefresh, preferred_vrefresh;
2967
2968 if (list_empty(&connector->probed_modes))
2969 return;
2970
2971 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2972 target_refresh = 60;
2973 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2974 target_refresh = 75;
2975
2976 preferred_mode = list_first_entry(&connector->probed_modes,
2977 struct drm_display_mode, head);
2978
2979 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2980 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2981
2982 if (cur_mode == preferred_mode)
2983 continue;
2984
2985 /* Largest mode is preferred */
2986 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2987 preferred_mode = cur_mode;
2988
2989 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2990 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2991 /* At a given size, try to get closest to target refresh */
2992 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2993 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2994 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2995 preferred_mode = cur_mode;
2996 }
2997 }
2998
2999 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3000}
3001
3002static bool
3003mode_is_rb(const struct drm_display_mode *mode)
3004{
3005 return (mode->htotal - mode->hdisplay == 160) &&
3006 (mode->hsync_end - mode->hdisplay == 80) &&
3007 (mode->hsync_end - mode->hsync_start == 32) &&
3008 (mode->vsync_start - mode->vdisplay == 3);
3009}
3010
3011/*
3012 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3013 * @dev: Device to duplicate against
3014 * @hsize: Mode width
3015 * @vsize: Mode height
3016 * @fresh: Mode refresh rate
3017 * @rb: Mode reduced-blanking-ness
3018 *
3019 * Walk the DMT mode list looking for a match for the given parameters.
3020 *
3021 * Return: A newly allocated copy of the mode, or NULL if not found.
3022 */
3023struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3024 int hsize, int vsize, int fresh,
3025 bool rb)
3026{
3027 int i;
3028
3029 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3030 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3031
3032 if (hsize != ptr->hdisplay)
3033 continue;
3034 if (vsize != ptr->vdisplay)
3035 continue;
3036 if (fresh != drm_mode_vrefresh(ptr))
3037 continue;
3038 if (rb != mode_is_rb(ptr))
3039 continue;
3040
3041 return drm_mode_duplicate(dev, ptr);
3042 }
3043
3044 return NULL;
3045}
3046EXPORT_SYMBOL(drm_mode_find_dmt);
3047
3048static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3049{
3050 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3052 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3053
3054 return descriptor->pixel_clock == 0 &&
3055 descriptor->data.other_data.pad1 == 0 &&
3056 descriptor->data.other_data.type == type;
3057}
3058
3059static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3060{
3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3062
3063 return descriptor->pixel_clock != 0;
3064}
3065
3066typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3067
3068static void
3069cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3070{
3071 int i, n;
3072 u8 d = ext[0x02];
3073 const u8 *det_base = ext + d;
3074
3075 if (d < 4 || d > 127)
3076 return;
3077
3078 n = (127 - d) / 18;
3079 for (i = 0; i < n; i++)
3080 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3081}
3082
3083static void
3084vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3085{
3086 unsigned int i, n = min((int)ext[0x02], 6);
3087 const u8 *det_base = ext + 5;
3088
3089 if (ext[0x01] != 1)
3090 return; /* unknown version */
3091
3092 for (i = 0; i < n; i++)
3093 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3094}
3095
3096static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3097 detailed_cb *cb, void *closure)
3098{
3099 struct drm_edid_iter edid_iter;
3100 const u8 *ext;
3101 int i;
3102
3103 if (!drm_edid)
3104 return;
3105
3106 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3107 cb(&drm_edid->edid->detailed_timings[i], closure);
3108
3109 drm_edid_iter_begin(drm_edid, &edid_iter);
3110 drm_edid_iter_for_each(ext, &edid_iter) {
3111 switch (*ext) {
3112 case CEA_EXT:
3113 cea_for_each_detailed_block(ext, cb, closure);
3114 break;
3115 case VTB_EXT:
3116 vtb_for_each_detailed_block(ext, cb, closure);
3117 break;
3118 default:
3119 break;
3120 }
3121 }
3122 drm_edid_iter_end(&edid_iter);
3123}
3124
3125static void
3126is_rb(const struct detailed_timing *descriptor, void *data)
3127{
3128 bool *res = data;
3129
3130 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3131 return;
3132
3133 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3134 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3135
3136 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3137 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3138 *res = true;
3139}
3140
3141/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3142static bool
3143drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3144{
3145 if (drm_edid->edid->revision >= 4) {
3146 bool ret = false;
3147
3148 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3149 return ret;
3150 }
3151
3152 return drm_edid_is_digital(drm_edid);
3153}
3154
3155static void
3156find_gtf2(const struct detailed_timing *descriptor, void *data)
3157{
3158 const struct detailed_timing **res = data;
3159
3160 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3161 return;
3162
3163 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3164
3165 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3166 *res = descriptor;
3167}
3168
3169/* Secondary GTF curve kicks in above some break frequency */
3170static int
3171drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3172{
3173 const struct detailed_timing *descriptor = NULL;
3174
3175 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3176
3177 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3178
3179 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3180}
3181
3182static int
3183drm_gtf2_2c(const struct drm_edid *drm_edid)
3184{
3185 const struct detailed_timing *descriptor = NULL;
3186
3187 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3188
3189 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3190
3191 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3192}
3193
3194static int
3195drm_gtf2_m(const struct drm_edid *drm_edid)
3196{
3197 const struct detailed_timing *descriptor = NULL;
3198
3199 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3200
3201 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3202
3203 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3204}
3205
3206static int
3207drm_gtf2_k(const struct drm_edid *drm_edid)
3208{
3209 const struct detailed_timing *descriptor = NULL;
3210
3211 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3212
3213 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3214
3215 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3216}
3217
3218static int
3219drm_gtf2_2j(const struct drm_edid *drm_edid)
3220{
3221 const struct detailed_timing *descriptor = NULL;
3222
3223 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3224
3225 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3226
3227 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3228}
3229
3230static void
3231get_timing_level(const struct detailed_timing *descriptor, void *data)
3232{
3233 int *res = data;
3234
3235 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3236 return;
3237
3238 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3239
3240 switch (descriptor->data.other_data.data.range.flags) {
3241 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3242 *res = LEVEL_GTF;
3243 break;
3244 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3245 *res = LEVEL_GTF2;
3246 break;
3247 case DRM_EDID_CVT_SUPPORT_FLAG:
3248 *res = LEVEL_CVT;
3249 break;
3250 default:
3251 break;
3252 }
3253}
3254
3255/* Get standard timing level (CVT/GTF/DMT). */
3256static int standard_timing_level(const struct drm_edid *drm_edid)
3257{
3258 const struct edid *edid = drm_edid->edid;
3259
3260 if (edid->revision >= 4) {
3261 /*
3262 * If the range descriptor doesn't
3263 * indicate otherwise default to CVT
3264 */
3265 int ret = LEVEL_CVT;
3266
3267 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3268
3269 return ret;
3270 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3271 return LEVEL_GTF2;
3272 } else if (edid->revision >= 2) {
3273 return LEVEL_GTF;
3274 } else {
3275 return LEVEL_DMT;
3276 }
3277}
3278
3279/*
3280 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3281 * monitors fill with ascii space (0x20) instead.
3282 */
3283static int
3284bad_std_timing(u8 a, u8 b)
3285{
3286 return (a == 0x00 && b == 0x00) ||
3287 (a == 0x01 && b == 0x01) ||
3288 (a == 0x20 && b == 0x20);
3289}
3290
3291static int drm_mode_hsync(const struct drm_display_mode *mode)
3292{
3293 if (mode->htotal <= 0)
3294 return 0;
3295
3296 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3297}
3298
3299static struct drm_display_mode *
3300drm_gtf2_mode(struct drm_device *dev,
3301 const struct drm_edid *drm_edid,
3302 int hsize, int vsize, int vrefresh_rate)
3303{
3304 struct drm_display_mode *mode;
3305
3306 /*
3307 * This is potentially wrong if there's ever a monitor with
3308 * more than one ranges section, each claiming a different
3309 * secondary GTF curve. Please don't do that.
3310 */
3311 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3312 if (!mode)
3313 return NULL;
3314
3315 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3316 drm_mode_destroy(dev, mode);
3317 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3318 vrefresh_rate, 0, 0,
3319 drm_gtf2_m(drm_edid),
3320 drm_gtf2_2c(drm_edid),
3321 drm_gtf2_k(drm_edid),
3322 drm_gtf2_2j(drm_edid));
3323 }
3324
3325 return mode;
3326}
3327
3328/*
3329 * Take the standard timing params (in this case width, aspect, and refresh)
3330 * and convert them into a real mode using CVT/GTF/DMT.
3331 */
3332static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3333 const struct drm_edid *drm_edid,
3334 const struct std_timing *t)
3335{
3336 struct drm_device *dev = connector->dev;
3337 struct drm_display_mode *m, *mode = NULL;
3338 int hsize, vsize;
3339 int vrefresh_rate;
3340 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3341 >> EDID_TIMING_ASPECT_SHIFT;
3342 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3343 >> EDID_TIMING_VFREQ_SHIFT;
3344 int timing_level = standard_timing_level(drm_edid);
3345
3346 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3347 return NULL;
3348
3349 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3350 hsize = t->hsize * 8 + 248;
3351 /* vrefresh_rate = vfreq + 60 */
3352 vrefresh_rate = vfreq + 60;
3353 /* the vdisplay is calculated based on the aspect ratio */
3354 if (aspect_ratio == 0) {
3355 if (drm_edid->edid->revision < 3)
3356 vsize = hsize;
3357 else
3358 vsize = (hsize * 10) / 16;
3359 } else if (aspect_ratio == 1)
3360 vsize = (hsize * 3) / 4;
3361 else if (aspect_ratio == 2)
3362 vsize = (hsize * 4) / 5;
3363 else
3364 vsize = (hsize * 9) / 16;
3365
3366 /* HDTV hack, part 1 */
3367 if (vrefresh_rate == 60 &&
3368 ((hsize == 1360 && vsize == 765) ||
3369 (hsize == 1368 && vsize == 769))) {
3370 hsize = 1366;
3371 vsize = 768;
3372 }
3373
3374 /*
3375 * If this connector already has a mode for this size and refresh
3376 * rate (because it came from detailed or CVT info), use that
3377 * instead. This way we don't have to guess at interlace or
3378 * reduced blanking.
3379 */
3380 list_for_each_entry(m, &connector->probed_modes, head)
3381 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3382 drm_mode_vrefresh(m) == vrefresh_rate)
3383 return NULL;
3384
3385 /* HDTV hack, part 2 */
3386 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3387 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3388 false);
3389 if (!mode)
3390 return NULL;
3391 mode->hdisplay = 1366;
3392 mode->hsync_start = mode->hsync_start - 1;
3393 mode->hsync_end = mode->hsync_end - 1;
3394 return mode;
3395 }
3396
3397 /* check whether it can be found in default mode table */
3398 if (drm_monitor_supports_rb(drm_edid)) {
3399 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3400 true);
3401 if (mode)
3402 return mode;
3403 }
3404 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3405 if (mode)
3406 return mode;
3407
3408 /* okay, generate it */
3409 switch (timing_level) {
3410 case LEVEL_DMT:
3411 break;
3412 case LEVEL_GTF:
3413 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3414 break;
3415 case LEVEL_GTF2:
3416 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3417 break;
3418 case LEVEL_CVT:
3419 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3420 false);
3421 break;
3422 }
3423 return mode;
3424}
3425
3426/*
3427 * EDID is delightfully ambiguous about how interlaced modes are to be
3428 * encoded. Our internal representation is of frame height, but some
3429 * HDTV detailed timings are encoded as field height.
3430 *
3431 * The format list here is from CEA, in frame size. Technically we
3432 * should be checking refresh rate too. Whatever.
3433 */
3434static void
3435drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3436 const struct detailed_pixel_timing *pt)
3437{
3438 int i;
3439 static const struct {
3440 int w, h;
3441 } cea_interlaced[] = {
3442 { 1920, 1080 },
3443 { 720, 480 },
3444 { 1440, 480 },
3445 { 2880, 480 },
3446 { 720, 576 },
3447 { 1440, 576 },
3448 { 2880, 576 },
3449 };
3450
3451 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3452 return;
3453
3454 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3455 if ((mode->hdisplay == cea_interlaced[i].w) &&
3456 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3457 mode->vdisplay *= 2;
3458 mode->vsync_start *= 2;
3459 mode->vsync_end *= 2;
3460 mode->vtotal *= 2;
3461 mode->vtotal |= 1;
3462 }
3463 }
3464
3465 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3466}
3467
3468/*
3469 * Create a new mode from an EDID detailed timing section. An EDID detailed
3470 * timing block contains enough info for us to create and return a new struct
3471 * drm_display_mode.
3472 */
3473static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3474 const struct drm_edid *drm_edid,
3475 const struct detailed_timing *timing)
3476{
3477 const struct drm_display_info *info = &connector->display_info;
3478 struct drm_device *dev = connector->dev;
3479 struct drm_display_mode *mode;
3480 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3481 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3482 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3483 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3484 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3485 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3486 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3487 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3488 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3489
3490 /* ignore tiny modes */
3491 if (hactive < 64 || vactive < 64)
3492 return NULL;
3493
3494 if (pt->misc & DRM_EDID_PT_STEREO) {
3495 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3496 connector->base.id, connector->name);
3497 return NULL;
3498 }
3499 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3500 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3501 connector->base.id, connector->name);
3502 }
3503
3504 /* it is incorrect if hsync/vsync width is zero */
3505 if (!hsync_pulse_width || !vsync_pulse_width) {
3506 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3507 connector->base.id, connector->name);
3508 return NULL;
3509 }
3510
3511 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3512 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3513 if (!mode)
3514 return NULL;
3515
3516 goto set_size;
3517 }
3518
3519 mode = drm_mode_create(dev);
3520 if (!mode)
3521 return NULL;
3522
3523 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3524 mode->clock = 1088 * 10;
3525 else
3526 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3527
3528 mode->hdisplay = hactive;
3529 mode->hsync_start = mode->hdisplay + hsync_offset;
3530 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3531 mode->htotal = mode->hdisplay + hblank;
3532
3533 mode->vdisplay = vactive;
3534 mode->vsync_start = mode->vdisplay + vsync_offset;
3535 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3536 mode->vtotal = mode->vdisplay + vblank;
3537
3538 /* Some EDIDs have bogus h/vsync_end values */
3539 if (mode->hsync_end > mode->htotal) {
3540 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3541 connector->base.id, connector->name,
3542 mode->hsync_end, mode->htotal);
3543 mode->hsync_end = mode->htotal;
3544 }
3545 if (mode->vsync_end > mode->vtotal) {
3546 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3547 connector->base.id, connector->name,
3548 mode->vsync_end, mode->vtotal);
3549 mode->vsync_end = mode->vtotal;
3550 }
3551
3552 drm_mode_do_interlace_quirk(mode, pt);
3553
3554 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3555 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3556 } else {
3557 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3558 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3559 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3560 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3561 }
3562
3563set_size:
3564 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3565 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3566
3567 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3568 mode->width_mm *= 10;
3569 mode->height_mm *= 10;
3570 }
3571
3572 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3573 mode->width_mm = drm_edid->edid->width_cm * 10;
3574 mode->height_mm = drm_edid->edid->height_cm * 10;
3575 }
3576
3577 mode->type = DRM_MODE_TYPE_DRIVER;
3578 drm_mode_set_name(mode);
3579
3580 return mode;
3581}
3582
3583static bool
3584mode_in_hsync_range(const struct drm_display_mode *mode,
3585 const struct edid *edid, const u8 *t)
3586{
3587 int hsync, hmin, hmax;
3588
3589 hmin = t[7];
3590 if (edid->revision >= 4)
3591 hmin += ((t[4] & 0x04) ? 255 : 0);
3592 hmax = t[8];
3593 if (edid->revision >= 4)
3594 hmax += ((t[4] & 0x08) ? 255 : 0);
3595 hsync = drm_mode_hsync(mode);
3596
3597 return (hsync <= hmax && hsync >= hmin);
3598}
3599
3600static bool
3601mode_in_vsync_range(const struct drm_display_mode *mode,
3602 const struct edid *edid, const u8 *t)
3603{
3604 int vsync, vmin, vmax;
3605
3606 vmin = t[5];
3607 if (edid->revision >= 4)
3608 vmin += ((t[4] & 0x01) ? 255 : 0);
3609 vmax = t[6];
3610 if (edid->revision >= 4)
3611 vmax += ((t[4] & 0x02) ? 255 : 0);
3612 vsync = drm_mode_vrefresh(mode);
3613
3614 return (vsync <= vmax && vsync >= vmin);
3615}
3616
3617static u32
3618range_pixel_clock(const struct edid *edid, const u8 *t)
3619{
3620 /* unspecified */
3621 if (t[9] == 0 || t[9] == 255)
3622 return 0;
3623
3624 /* 1.4 with CVT support gives us real precision, yay */
3625 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3626 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3627
3628 /* 1.3 is pathetic, so fuzz up a bit */
3629 return t[9] * 10000 + 5001;
3630}
3631
3632static bool mode_in_range(const struct drm_display_mode *mode,
3633 const struct drm_edid *drm_edid,
3634 const struct detailed_timing *timing)
3635{
3636 const struct edid *edid = drm_edid->edid;
3637 u32 max_clock;
3638 const u8 *t = (const u8 *)timing;
3639
3640 if (!mode_in_hsync_range(mode, edid, t))
3641 return false;
3642
3643 if (!mode_in_vsync_range(mode, edid, t))
3644 return false;
3645
3646 max_clock = range_pixel_clock(edid, t);
3647 if (max_clock)
3648 if (mode->clock > max_clock)
3649 return false;
3650
3651 /* 1.4 max horizontal check */
3652 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3653 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3654 return false;
3655
3656 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3657 return false;
3658
3659 return true;
3660}
3661
3662static bool valid_inferred_mode(const struct drm_connector *connector,
3663 const struct drm_display_mode *mode)
3664{
3665 const struct drm_display_mode *m;
3666 bool ok = false;
3667
3668 list_for_each_entry(m, &connector->probed_modes, head) {
3669 if (mode->hdisplay == m->hdisplay &&
3670 mode->vdisplay == m->vdisplay &&
3671 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3672 return false; /* duplicated */
3673 if (mode->hdisplay <= m->hdisplay &&
3674 mode->vdisplay <= m->vdisplay)
3675 ok = true;
3676 }
3677 return ok;
3678}
3679
3680static int drm_dmt_modes_for_range(struct drm_connector *connector,
3681 const struct drm_edid *drm_edid,
3682 const struct detailed_timing *timing)
3683{
3684 int i, modes = 0;
3685 struct drm_display_mode *newmode;
3686 struct drm_device *dev = connector->dev;
3687
3688 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3689 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3690 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3691 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3692 if (newmode) {
3693 drm_mode_probed_add(connector, newmode);
3694 modes++;
3695 }
3696 }
3697 }
3698
3699 return modes;
3700}
3701
3702/* fix up 1366x768 mode from 1368x768;
3703 * GFT/CVT can't express 1366 width which isn't dividable by 8
3704 */
3705void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3706{
3707 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3708 mode->hdisplay = 1366;
3709 mode->hsync_start--;
3710 mode->hsync_end--;
3711 drm_mode_set_name(mode);
3712 }
3713}
3714
3715static int drm_gtf_modes_for_range(struct drm_connector *connector,
3716 const struct drm_edid *drm_edid,
3717 const struct detailed_timing *timing)
3718{
3719 int i, modes = 0;
3720 struct drm_display_mode *newmode;
3721 struct drm_device *dev = connector->dev;
3722
3723 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3724 const struct minimode *m = &extra_modes[i];
3725
3726 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3727 if (!newmode)
3728 return modes;
3729
3730 drm_mode_fixup_1366x768(newmode);
3731 if (!mode_in_range(newmode, drm_edid, timing) ||
3732 !valid_inferred_mode(connector, newmode)) {
3733 drm_mode_destroy(dev, newmode);
3734 continue;
3735 }
3736
3737 drm_mode_probed_add(connector, newmode);
3738 modes++;
3739 }
3740
3741 return modes;
3742}
3743
3744static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3745 const struct drm_edid *drm_edid,
3746 const struct detailed_timing *timing)
3747{
3748 int i, modes = 0;
3749 struct drm_display_mode *newmode;
3750 struct drm_device *dev = connector->dev;
3751
3752 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3753 const struct minimode *m = &extra_modes[i];
3754
3755 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3756 if (!newmode)
3757 return modes;
3758
3759 drm_mode_fixup_1366x768(newmode);
3760 if (!mode_in_range(newmode, drm_edid, timing) ||
3761 !valid_inferred_mode(connector, newmode)) {
3762 drm_mode_destroy(dev, newmode);
3763 continue;
3764 }
3765
3766 drm_mode_probed_add(connector, newmode);
3767 modes++;
3768 }
3769
3770 return modes;
3771}
3772
3773static int drm_cvt_modes_for_range(struct drm_connector *connector,
3774 const struct drm_edid *drm_edid,
3775 const struct detailed_timing *timing)
3776{
3777 int i, modes = 0;
3778 struct drm_display_mode *newmode;
3779 struct drm_device *dev = connector->dev;
3780 bool rb = drm_monitor_supports_rb(drm_edid);
3781
3782 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3783 const struct minimode *m = &extra_modes[i];
3784
3785 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3786 if (!newmode)
3787 return modes;
3788
3789 drm_mode_fixup_1366x768(newmode);
3790 if (!mode_in_range(newmode, drm_edid, timing) ||
3791 !valid_inferred_mode(connector, newmode)) {
3792 drm_mode_destroy(dev, newmode);
3793 continue;
3794 }
3795
3796 drm_mode_probed_add(connector, newmode);
3797 modes++;
3798 }
3799
3800 return modes;
3801}
3802
3803static void
3804do_inferred_modes(const struct detailed_timing *timing, void *c)
3805{
3806 struct detailed_mode_closure *closure = c;
3807 const struct detailed_non_pixel *data = &timing->data.other_data;
3808 const struct detailed_data_monitor_range *range = &data->data.range;
3809
3810 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3811 return;
3812
3813 closure->modes += drm_dmt_modes_for_range(closure->connector,
3814 closure->drm_edid,
3815 timing);
3816
3817 if (closure->drm_edid->edid->revision < 2)
3818 return; /* GTF not defined yet */
3819
3820 switch (range->flags) {
3821 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3822 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3823 closure->drm_edid,
3824 timing);
3825 break;
3826 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3827 closure->modes += drm_gtf_modes_for_range(closure->connector,
3828 closure->drm_edid,
3829 timing);
3830 break;
3831 case DRM_EDID_CVT_SUPPORT_FLAG:
3832 if (closure->drm_edid->edid->revision < 4)
3833 break;
3834
3835 closure->modes += drm_cvt_modes_for_range(closure->connector,
3836 closure->drm_edid,
3837 timing);
3838 break;
3839 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3840 default:
3841 break;
3842 }
3843}
3844
3845static int add_inferred_modes(struct drm_connector *connector,
3846 const struct drm_edid *drm_edid)
3847{
3848 struct detailed_mode_closure closure = {
3849 .connector = connector,
3850 .drm_edid = drm_edid,
3851 };
3852
3853 if (drm_edid->edid->revision >= 1)
3854 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3855
3856 return closure.modes;
3857}
3858
3859static int
3860drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3861{
3862 int i, j, m, modes = 0;
3863 struct drm_display_mode *mode;
3864 const u8 *est = ((const u8 *)timing) + 6;
3865
3866 for (i = 0; i < 6; i++) {
3867 for (j = 7; j >= 0; j--) {
3868 m = (i * 8) + (7 - j);
3869 if (m >= ARRAY_SIZE(est3_modes))
3870 break;
3871 if (est[i] & (1 << j)) {
3872 mode = drm_mode_find_dmt(connector->dev,
3873 est3_modes[m].w,
3874 est3_modes[m].h,
3875 est3_modes[m].r,
3876 est3_modes[m].rb);
3877 if (mode) {
3878 drm_mode_probed_add(connector, mode);
3879 modes++;
3880 }
3881 }
3882 }
3883 }
3884
3885 return modes;
3886}
3887
3888static void
3889do_established_modes(const struct detailed_timing *timing, void *c)
3890{
3891 struct detailed_mode_closure *closure = c;
3892
3893 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3894 return;
3895
3896 closure->modes += drm_est3_modes(closure->connector, timing);
3897}
3898
3899/*
3900 * Get established modes from EDID and add them. Each EDID block contains a
3901 * bitmap of the supported "established modes" list (defined above). Tease them
3902 * out and add them to the global modes list.
3903 */
3904static int add_established_modes(struct drm_connector *connector,
3905 const struct drm_edid *drm_edid)
3906{
3907 struct drm_device *dev = connector->dev;
3908 const struct edid *edid = drm_edid->edid;
3909 unsigned long est_bits = edid->established_timings.t1 |
3910 (edid->established_timings.t2 << 8) |
3911 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3912 int i, modes = 0;
3913 struct detailed_mode_closure closure = {
3914 .connector = connector,
3915 .drm_edid = drm_edid,
3916 };
3917
3918 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3919 if (est_bits & (1<<i)) {
3920 struct drm_display_mode *newmode;
3921
3922 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3923 if (newmode) {
3924 drm_mode_probed_add(connector, newmode);
3925 modes++;
3926 }
3927 }
3928 }
3929
3930 if (edid->revision >= 1)
3931 drm_for_each_detailed_block(drm_edid, do_established_modes,
3932 &closure);
3933
3934 return modes + closure.modes;
3935}
3936
3937static void
3938do_standard_modes(const struct detailed_timing *timing, void *c)
3939{
3940 struct detailed_mode_closure *closure = c;
3941 const struct detailed_non_pixel *data = &timing->data.other_data;
3942 struct drm_connector *connector = closure->connector;
3943 int i;
3944
3945 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3946 return;
3947
3948 for (i = 0; i < 6; i++) {
3949 const struct std_timing *std = &data->data.timings[i];
3950 struct drm_display_mode *newmode;
3951
3952 newmode = drm_mode_std(connector, closure->drm_edid, std);
3953 if (newmode) {
3954 drm_mode_probed_add(connector, newmode);
3955 closure->modes++;
3956 }
3957 }
3958}
3959
3960/*
3961 * Get standard modes from EDID and add them. Standard modes can be calculated
3962 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3963 * add them to the list.
3964 */
3965static int add_standard_modes(struct drm_connector *connector,
3966 const struct drm_edid *drm_edid)
3967{
3968 int i, modes = 0;
3969 struct detailed_mode_closure closure = {
3970 .connector = connector,
3971 .drm_edid = drm_edid,
3972 };
3973
3974 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3975 struct drm_display_mode *newmode;
3976
3977 newmode = drm_mode_std(connector, drm_edid,
3978 &drm_edid->edid->standard_timings[i]);
3979 if (newmode) {
3980 drm_mode_probed_add(connector, newmode);
3981 modes++;
3982 }
3983 }
3984
3985 if (drm_edid->edid->revision >= 1)
3986 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3987 &closure);
3988
3989 /* XXX should also look for standard codes in VTB blocks */
3990
3991 return modes + closure.modes;
3992}
3993
3994static int drm_cvt_modes(struct drm_connector *connector,
3995 const struct detailed_timing *timing)
3996{
3997 int i, j, modes = 0;
3998 struct drm_display_mode *newmode;
3999 struct drm_device *dev = connector->dev;
4000 const struct cvt_timing *cvt;
4001 static const int rates[] = { 60, 85, 75, 60, 50 };
4002 const u8 empty[3] = { 0, 0, 0 };
4003
4004 for (i = 0; i < 4; i++) {
4005 int width, height;
4006
4007 cvt = &(timing->data.other_data.data.cvt[i]);
4008
4009 if (!memcmp(cvt->code, empty, 3))
4010 continue;
4011
4012 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4013 switch (cvt->code[1] & 0x0c) {
4014 /* default - because compiler doesn't see that we've enumerated all cases */
4015 default:
4016 case 0x00:
4017 width = height * 4 / 3;
4018 break;
4019 case 0x04:
4020 width = height * 16 / 9;
4021 break;
4022 case 0x08:
4023 width = height * 16 / 10;
4024 break;
4025 case 0x0c:
4026 width = height * 15 / 9;
4027 break;
4028 }
4029
4030 for (j = 1; j < 5; j++) {
4031 if (cvt->code[2] & (1 << j)) {
4032 newmode = drm_cvt_mode(dev, width, height,
4033 rates[j], j == 0,
4034 false, false);
4035 if (newmode) {
4036 drm_mode_probed_add(connector, newmode);
4037 modes++;
4038 }
4039 }
4040 }
4041 }
4042
4043 return modes;
4044}
4045
4046static void
4047do_cvt_mode(const struct detailed_timing *timing, void *c)
4048{
4049 struct detailed_mode_closure *closure = c;
4050
4051 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4052 return;
4053
4054 closure->modes += drm_cvt_modes(closure->connector, timing);
4055}
4056
4057static int
4058add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4059{
4060 struct detailed_mode_closure closure = {
4061 .connector = connector,
4062 .drm_edid = drm_edid,
4063 };
4064
4065 if (drm_edid->edid->revision >= 3)
4066 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4067
4068 /* XXX should also look for CVT codes in VTB blocks */
4069
4070 return closure.modes;
4071}
4072
4073static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4074 struct drm_display_mode *mode);
4075
4076static void
4077do_detailed_mode(const struct detailed_timing *timing, void *c)
4078{
4079 struct detailed_mode_closure *closure = c;
4080 struct drm_display_mode *newmode;
4081
4082 if (!is_detailed_timing_descriptor(timing))
4083 return;
4084
4085 newmode = drm_mode_detailed(closure->connector,
4086 closure->drm_edid, timing);
4087 if (!newmode)
4088 return;
4089
4090 if (closure->preferred)
4091 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4092
4093 /*
4094 * Detailed modes are limited to 10kHz pixel clock resolution,
4095 * so fix up anything that looks like CEA/HDMI mode, but the clock
4096 * is just slightly off.
4097 */
4098 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4099
4100 drm_mode_probed_add(closure->connector, newmode);
4101 closure->modes++;
4102 closure->preferred = false;
4103}
4104
4105/*
4106 * add_detailed_modes - Add modes from detailed timings
4107 * @connector: attached connector
4108 * @drm_edid: EDID block to scan
4109 */
4110static int add_detailed_modes(struct drm_connector *connector,
4111 const struct drm_edid *drm_edid)
4112{
4113 struct detailed_mode_closure closure = {
4114 .connector = connector,
4115 .drm_edid = drm_edid,
4116 };
4117
4118 if (drm_edid->edid->revision >= 4)
4119 closure.preferred = true; /* first detailed timing is always preferred */
4120 else
4121 closure.preferred =
4122 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4123
4124 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4125
4126 return closure.modes;
4127}
4128
4129/* CTA-861-H Table 60 - CTA Tag Codes */
4130#define CTA_DB_AUDIO 1
4131#define CTA_DB_VIDEO 2
4132#define CTA_DB_VENDOR 3
4133#define CTA_DB_SPEAKER 4
4134#define CTA_DB_EXTENDED_TAG 7
4135
4136/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4137#define CTA_EXT_DB_VIDEO_CAP 0
4138#define CTA_EXT_DB_VENDOR 1
4139#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4140#define CTA_EXT_DB_420_VIDEO_DATA 14
4141#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4142#define CTA_EXT_DB_HF_EEODB 0x78
4143#define CTA_EXT_DB_HF_SCDB 0x79
4144
4145#define EDID_BASIC_AUDIO (1 << 6)
4146#define EDID_CEA_YCRCB444 (1 << 5)
4147#define EDID_CEA_YCRCB422 (1 << 4)
4148#define EDID_CEA_VCDB_QS (1 << 6)
4149
4150/*
4151 * Search EDID for CEA extension block.
4152 *
4153 * FIXME: Prefer not returning pointers to raw EDID data.
4154 */
4155const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4156 int ext_id, int *ext_index)
4157{
4158 const u8 *edid_ext = NULL;
4159 int i;
4160
4161 /* No EDID or EDID extensions */
4162 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4163 return NULL;
4164
4165 /* Find CEA extension */
4166 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4167 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4168 if (edid_block_tag(edid_ext) == ext_id)
4169 break;
4170 }
4171
4172 if (i >= drm_edid_extension_block_count(drm_edid))
4173 return NULL;
4174
4175 *ext_index = i + 1;
4176
4177 return edid_ext;
4178}
4179
4180/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4181static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4182{
4183 const struct displayid_block *block;
4184 struct displayid_iter iter;
4185 struct drm_edid_iter edid_iter;
4186 const u8 *ext;
4187 bool found = false;
4188
4189 /* Look for a top level CEA extension block */
4190 drm_edid_iter_begin(drm_edid, &edid_iter);
4191 drm_edid_iter_for_each(ext, &edid_iter) {
4192 if (ext[0] == CEA_EXT) {
4193 found = true;
4194 break;
4195 }
4196 }
4197 drm_edid_iter_end(&edid_iter);
4198
4199 if (found)
4200 return true;
4201
4202 /* CEA blocks can also be found embedded in a DisplayID block */
4203 displayid_iter_edid_begin(drm_edid, &iter);
4204 displayid_iter_for_each(block, &iter) {
4205 if (block->tag == DATA_BLOCK_CTA) {
4206 found = true;
4207 break;
4208 }
4209 }
4210 displayid_iter_end(&iter);
4211
4212 return found;
4213}
4214
4215static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4216{
4217 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4218 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4219
4220 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4221 return &edid_cea_modes_1[vic - 1];
4222 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4223 return &edid_cea_modes_193[vic - 193];
4224 return NULL;
4225}
4226
4227static u8 cea_num_vics(void)
4228{
4229 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4230}
4231
4232static u8 cea_next_vic(u8 vic)
4233{
4234 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4235 vic = 193;
4236 return vic;
4237}
4238
4239/*
4240 * Calculate the alternate clock for the CEA mode
4241 * (60Hz vs. 59.94Hz etc.)
4242 */
4243static unsigned int
4244cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4245{
4246 unsigned int clock = cea_mode->clock;
4247
4248 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4249 return clock;
4250
4251 /*
4252 * edid_cea_modes contains the 59.94Hz
4253 * variant for 240 and 480 line modes,
4254 * and the 60Hz variant otherwise.
4255 */
4256 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4257 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4258 else
4259 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4260
4261 return clock;
4262}
4263
4264static bool
4265cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4266{
4267 /*
4268 * For certain VICs the spec allows the vertical
4269 * front porch to vary by one or two lines.
4270 *
4271 * cea_modes[] stores the variant with the shortest
4272 * vertical front porch. We can adjust the mode to
4273 * get the other variants by simply increasing the
4274 * vertical front porch length.
4275 */
4276 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4277 cea_mode_for_vic(9)->vtotal != 262 ||
4278 cea_mode_for_vic(12)->vtotal != 262 ||
4279 cea_mode_for_vic(13)->vtotal != 262 ||
4280 cea_mode_for_vic(23)->vtotal != 312 ||
4281 cea_mode_for_vic(24)->vtotal != 312 ||
4282 cea_mode_for_vic(27)->vtotal != 312 ||
4283 cea_mode_for_vic(28)->vtotal != 312);
4284
4285 if (((vic == 8 || vic == 9 ||
4286 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4287 ((vic == 23 || vic == 24 ||
4288 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4289 mode->vsync_start++;
4290 mode->vsync_end++;
4291 mode->vtotal++;
4292
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
4299static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4300 unsigned int clock_tolerance)
4301{
4302 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4303 u8 vic;
4304
4305 if (!to_match->clock)
4306 return 0;
4307
4308 if (to_match->picture_aspect_ratio)
4309 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4310
4311 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4312 struct drm_display_mode cea_mode;
4313 unsigned int clock1, clock2;
4314
4315 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4316
4317 /* Check both 60Hz and 59.94Hz */
4318 clock1 = cea_mode.clock;
4319 clock2 = cea_mode_alternate_clock(&cea_mode);
4320
4321 if (abs(to_match->clock - clock1) > clock_tolerance &&
4322 abs(to_match->clock - clock2) > clock_tolerance)
4323 continue;
4324
4325 do {
4326 if (drm_mode_match(to_match, &cea_mode, match_flags))
4327 return vic;
4328 } while (cea_mode_alternate_timings(vic, &cea_mode));
4329 }
4330
4331 return 0;
4332}
4333
4334/**
4335 * drm_match_cea_mode - look for a CEA mode matching given mode
4336 * @to_match: display mode
4337 *
4338 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4339 * mode.
4340 */
4341u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4342{
4343 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4344 u8 vic;
4345
4346 if (!to_match->clock)
4347 return 0;
4348
4349 if (to_match->picture_aspect_ratio)
4350 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4351
4352 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4353 struct drm_display_mode cea_mode;
4354 unsigned int clock1, clock2;
4355
4356 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4357
4358 /* Check both 60Hz and 59.94Hz */
4359 clock1 = cea_mode.clock;
4360 clock2 = cea_mode_alternate_clock(&cea_mode);
4361
4362 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4363 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4364 continue;
4365
4366 do {
4367 if (drm_mode_match(to_match, &cea_mode, match_flags))
4368 return vic;
4369 } while (cea_mode_alternate_timings(vic, &cea_mode));
4370 }
4371
4372 return 0;
4373}
4374EXPORT_SYMBOL(drm_match_cea_mode);
4375
4376static bool drm_valid_cea_vic(u8 vic)
4377{
4378 return cea_mode_for_vic(vic) != NULL;
4379}
4380
4381static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4382{
4383 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4384
4385 if (mode)
4386 return mode->picture_aspect_ratio;
4387
4388 return HDMI_PICTURE_ASPECT_NONE;
4389}
4390
4391static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4392{
4393 return edid_4k_modes[video_code].picture_aspect_ratio;
4394}
4395
4396/*
4397 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4398 * specific block).
4399 */
4400static unsigned int
4401hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4402{
4403 return cea_mode_alternate_clock(hdmi_mode);
4404}
4405
4406static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4407 unsigned int clock_tolerance)
4408{
4409 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4410 u8 vic;
4411
4412 if (!to_match->clock)
4413 return 0;
4414
4415 if (to_match->picture_aspect_ratio)
4416 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4417
4418 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4419 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4420 unsigned int clock1, clock2;
4421
4422 /* Make sure to also match alternate clocks */
4423 clock1 = hdmi_mode->clock;
4424 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4425
4426 if (abs(to_match->clock - clock1) > clock_tolerance &&
4427 abs(to_match->clock - clock2) > clock_tolerance)
4428 continue;
4429
4430 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4431 return vic;
4432 }
4433
4434 return 0;
4435}
4436
4437/*
4438 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4439 * @to_match: display mode
4440 *
4441 * An HDMI mode is one defined in the HDMI vendor specific block.
4442 *
4443 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4444 */
4445static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4446{
4447 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4448 u8 vic;
4449
4450 if (!to_match->clock)
4451 return 0;
4452
4453 if (to_match->picture_aspect_ratio)
4454 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4455
4456 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4457 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4458 unsigned int clock1, clock2;
4459
4460 /* Make sure to also match alternate clocks */
4461 clock1 = hdmi_mode->clock;
4462 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4463
4464 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4465 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4466 drm_mode_match(to_match, hdmi_mode, match_flags))
4467 return vic;
4468 }
4469 return 0;
4470}
4471
4472static bool drm_valid_hdmi_vic(u8 vic)
4473{
4474 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4475}
4476
4477static int add_alternate_cea_modes(struct drm_connector *connector,
4478 const struct drm_edid *drm_edid)
4479{
4480 struct drm_device *dev = connector->dev;
4481 struct drm_display_mode *mode, *tmp;
4482 LIST_HEAD(list);
4483 int modes = 0;
4484
4485 /* Don't add CTA modes if the CTA extension block is missing */
4486 if (!drm_edid_has_cta_extension(drm_edid))
4487 return 0;
4488
4489 /*
4490 * Go through all probed modes and create a new mode
4491 * with the alternate clock for certain CEA modes.
4492 */
4493 list_for_each_entry(mode, &connector->probed_modes, head) {
4494 const struct drm_display_mode *cea_mode = NULL;
4495 struct drm_display_mode *newmode;
4496 u8 vic = drm_match_cea_mode(mode);
4497 unsigned int clock1, clock2;
4498
4499 if (drm_valid_cea_vic(vic)) {
4500 cea_mode = cea_mode_for_vic(vic);
4501 clock2 = cea_mode_alternate_clock(cea_mode);
4502 } else {
4503 vic = drm_match_hdmi_mode(mode);
4504 if (drm_valid_hdmi_vic(vic)) {
4505 cea_mode = &edid_4k_modes[vic];
4506 clock2 = hdmi_mode_alternate_clock(cea_mode);
4507 }
4508 }
4509
4510 if (!cea_mode)
4511 continue;
4512
4513 clock1 = cea_mode->clock;
4514
4515 if (clock1 == clock2)
4516 continue;
4517
4518 if (mode->clock != clock1 && mode->clock != clock2)
4519 continue;
4520
4521 newmode = drm_mode_duplicate(dev, cea_mode);
4522 if (!newmode)
4523 continue;
4524
4525 /* Carry over the stereo flags */
4526 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4527
4528 /*
4529 * The current mode could be either variant. Make
4530 * sure to pick the "other" clock for the new mode.
4531 */
4532 if (mode->clock != clock1)
4533 newmode->clock = clock1;
4534 else
4535 newmode->clock = clock2;
4536
4537 list_add_tail(&newmode->head, &list);
4538 }
4539
4540 list_for_each_entry_safe(mode, tmp, &list, head) {
4541 list_del(&mode->head);
4542 drm_mode_probed_add(connector, mode);
4543 modes++;
4544 }
4545
4546 return modes;
4547}
4548
4549static u8 svd_to_vic(u8 svd)
4550{
4551 /* 0-6 bit vic, 7th bit native mode indicator */
4552 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4553 return svd & 127;
4554
4555 return svd;
4556}
4557
4558/*
4559 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4560 * the EDID, or NULL on errors.
4561 */
4562static struct drm_display_mode *
4563drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4564{
4565 const struct drm_display_info *info = &connector->display_info;
4566 struct drm_device *dev = connector->dev;
4567
4568 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4569 return NULL;
4570
4571 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4572}
4573
4574/*
4575 * do_y420vdb_modes - Parse YCBCR 420 only modes
4576 * @connector: connector corresponding to the HDMI sink
4577 * @svds: start of the data block of CEA YCBCR 420 VDB
4578 * @len: length of the CEA YCBCR 420 VDB
4579 *
4580 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4581 * which contains modes which can be supported in YCBCR 420
4582 * output format only.
4583 */
4584static int do_y420vdb_modes(struct drm_connector *connector,
4585 const u8 *svds, u8 svds_len)
4586{
4587 struct drm_device *dev = connector->dev;
4588 int modes = 0, i;
4589
4590 for (i = 0; i < svds_len; i++) {
4591 u8 vic = svd_to_vic(svds[i]);
4592 struct drm_display_mode *newmode;
4593
4594 if (!drm_valid_cea_vic(vic))
4595 continue;
4596
4597 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4598 if (!newmode)
4599 break;
4600 drm_mode_probed_add(connector, newmode);
4601 modes++;
4602 }
4603
4604 return modes;
4605}
4606
4607/**
4608 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4609 * @dev: DRM device
4610 * @video_code: CEA VIC of the mode
4611 *
4612 * Creates a new mode matching the specified CEA VIC.
4613 *
4614 * Returns: A new drm_display_mode on success or NULL on failure
4615 */
4616struct drm_display_mode *
4617drm_display_mode_from_cea_vic(struct drm_device *dev,
4618 u8 video_code)
4619{
4620 const struct drm_display_mode *cea_mode;
4621 struct drm_display_mode *newmode;
4622
4623 cea_mode = cea_mode_for_vic(video_code);
4624 if (!cea_mode)
4625 return NULL;
4626
4627 newmode = drm_mode_duplicate(dev, cea_mode);
4628 if (!newmode)
4629 return NULL;
4630
4631 return newmode;
4632}
4633EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4634
4635/* Add modes based on VICs parsed in parse_cta_vdb() */
4636static int add_cta_vdb_modes(struct drm_connector *connector)
4637{
4638 const struct drm_display_info *info = &connector->display_info;
4639 int i, modes = 0;
4640
4641 if (!info->vics)
4642 return 0;
4643
4644 for (i = 0; i < info->vics_len; i++) {
4645 struct drm_display_mode *mode;
4646
4647 mode = drm_display_mode_from_vic_index(connector, i);
4648 if (mode) {
4649 drm_mode_probed_add(connector, mode);
4650 modes++;
4651 }
4652 }
4653
4654 return modes;
4655}
4656
4657struct stereo_mandatory_mode {
4658 int width, height, vrefresh;
4659 unsigned int flags;
4660};
4661
4662static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4663 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4664 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4665 { 1920, 1080, 50,
4666 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4667 { 1920, 1080, 60,
4668 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4669 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4670 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4671 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4672 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4673};
4674
4675static bool
4676stereo_match_mandatory(const struct drm_display_mode *mode,
4677 const struct stereo_mandatory_mode *stereo_mode)
4678{
4679 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4680
4681 return mode->hdisplay == stereo_mode->width &&
4682 mode->vdisplay == stereo_mode->height &&
4683 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4684 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4685}
4686
4687static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4688{
4689 struct drm_device *dev = connector->dev;
4690 const struct drm_display_mode *mode;
4691 struct list_head stereo_modes;
4692 int modes = 0, i;
4693
4694 INIT_LIST_HEAD(&stereo_modes);
4695
4696 list_for_each_entry(mode, &connector->probed_modes, head) {
4697 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4698 const struct stereo_mandatory_mode *mandatory;
4699 struct drm_display_mode *new_mode;
4700
4701 if (!stereo_match_mandatory(mode,
4702 &stereo_mandatory_modes[i]))
4703 continue;
4704
4705 mandatory = &stereo_mandatory_modes[i];
4706 new_mode = drm_mode_duplicate(dev, mode);
4707 if (!new_mode)
4708 continue;
4709
4710 new_mode->flags |= mandatory->flags;
4711 list_add_tail(&new_mode->head, &stereo_modes);
4712 modes++;
4713 }
4714 }
4715
4716 list_splice_tail(&stereo_modes, &connector->probed_modes);
4717
4718 return modes;
4719}
4720
4721static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4722{
4723 struct drm_device *dev = connector->dev;
4724 struct drm_display_mode *newmode;
4725
4726 if (!drm_valid_hdmi_vic(vic)) {
4727 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4728 connector->base.id, connector->name, vic);
4729 return 0;
4730 }
4731
4732 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4733 if (!newmode)
4734 return 0;
4735
4736 drm_mode_probed_add(connector, newmode);
4737
4738 return 1;
4739}
4740
4741static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4742 int vic_index)
4743{
4744 struct drm_display_mode *newmode;
4745 int modes = 0;
4746
4747 if (structure & (1 << 0)) {
4748 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4749 if (newmode) {
4750 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4751 drm_mode_probed_add(connector, newmode);
4752 modes++;
4753 }
4754 }
4755 if (structure & (1 << 6)) {
4756 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4757 if (newmode) {
4758 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4759 drm_mode_probed_add(connector, newmode);
4760 modes++;
4761 }
4762 }
4763 if (structure & (1 << 8)) {
4764 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4765 if (newmode) {
4766 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4767 drm_mode_probed_add(connector, newmode);
4768 modes++;
4769 }
4770 }
4771
4772 return modes;
4773}
4774
4775static bool hdmi_vsdb_latency_present(const u8 *db)
4776{
4777 return db[8] & BIT(7);
4778}
4779
4780static bool hdmi_vsdb_i_latency_present(const u8 *db)
4781{
4782 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4783}
4784
4785static int hdmi_vsdb_latency_length(const u8 *db)
4786{
4787 if (hdmi_vsdb_i_latency_present(db))
4788 return 4;
4789 else if (hdmi_vsdb_latency_present(db))
4790 return 2;
4791 else
4792 return 0;
4793}
4794
4795/*
4796 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4797 * @connector: connector corresponding to the HDMI sink
4798 * @db: start of the CEA vendor specific block
4799 * @len: length of the CEA block payload, ie. one can access up to db[len]
4800 *
4801 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4802 * also adds the stereo 3d modes when applicable.
4803 */
4804static int
4805do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4806{
4807 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4808 u8 vic_len, hdmi_3d_len = 0;
4809 u16 mask;
4810 u16 structure_all;
4811
4812 if (len < 8)
4813 goto out;
4814
4815 /* no HDMI_Video_Present */
4816 if (!(db[8] & (1 << 5)))
4817 goto out;
4818
4819 offset += hdmi_vsdb_latency_length(db);
4820
4821 /* the declared length is not long enough for the 2 first bytes
4822 * of additional video format capabilities */
4823 if (len < (8 + offset + 2))
4824 goto out;
4825
4826 /* 3D_Present */
4827 offset++;
4828 if (db[8 + offset] & (1 << 7)) {
4829 modes += add_hdmi_mandatory_stereo_modes(connector);
4830
4831 /* 3D_Multi_present */
4832 multi_present = (db[8 + offset] & 0x60) >> 5;
4833 }
4834
4835 offset++;
4836 vic_len = db[8 + offset] >> 5;
4837 hdmi_3d_len = db[8 + offset] & 0x1f;
4838
4839 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4840 u8 vic;
4841
4842 vic = db[9 + offset + i];
4843 modes += add_hdmi_mode(connector, vic);
4844 }
4845 offset += 1 + vic_len;
4846
4847 if (multi_present == 1)
4848 multi_len = 2;
4849 else if (multi_present == 2)
4850 multi_len = 4;
4851 else
4852 multi_len = 0;
4853
4854 if (len < (8 + offset + hdmi_3d_len - 1))
4855 goto out;
4856
4857 if (hdmi_3d_len < multi_len)
4858 goto out;
4859
4860 if (multi_present == 1 || multi_present == 2) {
4861 /* 3D_Structure_ALL */
4862 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4863
4864 /* check if 3D_MASK is present */
4865 if (multi_present == 2)
4866 mask = (db[10 + offset] << 8) | db[11 + offset];
4867 else
4868 mask = 0xffff;
4869
4870 for (i = 0; i < 16; i++) {
4871 if (mask & (1 << i))
4872 modes += add_3d_struct_modes(connector,
4873 structure_all, i);
4874 }
4875 }
4876
4877 offset += multi_len;
4878
4879 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4880 int vic_index;
4881 struct drm_display_mode *newmode = NULL;
4882 unsigned int newflag = 0;
4883 bool detail_present;
4884
4885 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4886
4887 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4888 break;
4889
4890 /* 2D_VIC_order_X */
4891 vic_index = db[8 + offset + i] >> 4;
4892
4893 /* 3D_Structure_X */
4894 switch (db[8 + offset + i] & 0x0f) {
4895 case 0:
4896 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4897 break;
4898 case 6:
4899 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4900 break;
4901 case 8:
4902 /* 3D_Detail_X */
4903 if ((db[9 + offset + i] >> 4) == 1)
4904 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4905 break;
4906 }
4907
4908 if (newflag != 0) {
4909 newmode = drm_display_mode_from_vic_index(connector,
4910 vic_index);
4911
4912 if (newmode) {
4913 newmode->flags |= newflag;
4914 drm_mode_probed_add(connector, newmode);
4915 modes++;
4916 }
4917 }
4918
4919 if (detail_present)
4920 i++;
4921 }
4922
4923out:
4924 return modes;
4925}
4926
4927static int
4928cea_revision(const u8 *cea)
4929{
4930 /*
4931 * FIXME is this correct for the DispID variant?
4932 * The DispID spec doesn't really specify whether
4933 * this is the revision of the CEA extension or
4934 * the DispID CEA data block. And the only value
4935 * given as an example is 0.
4936 */
4937 return cea[1];
4938}
4939
4940/*
4941 * CTA Data Block iterator.
4942 *
4943 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4944 * CTA Data Blocks.
4945 *
4946 * struct cea_db *db:
4947 * struct cea_db_iter iter;
4948 *
4949 * cea_db_iter_edid_begin(edid, &iter);
4950 * cea_db_iter_for_each(db, &iter) {
4951 * // do stuff with db
4952 * }
4953 * cea_db_iter_end(&iter);
4954 */
4955struct cea_db_iter {
4956 struct drm_edid_iter edid_iter;
4957 struct displayid_iter displayid_iter;
4958
4959 /* Current Data Block Collection. */
4960 const u8 *collection;
4961
4962 /* Current Data Block index in current collection. */
4963 int index;
4964
4965 /* End index in current collection. */
4966 int end;
4967};
4968
4969/* CTA-861-H section 7.4 CTA Data BLock Collection */
4970struct cea_db {
4971 u8 tag_length;
4972 u8 data[];
4973} __packed;
4974
4975static int cea_db_tag(const struct cea_db *db)
4976{
4977 return db->tag_length >> 5;
4978}
4979
4980static int cea_db_payload_len(const void *_db)
4981{
4982 /* FIXME: Transition to passing struct cea_db * everywhere. */
4983 const struct cea_db *db = _db;
4984
4985 return db->tag_length & 0x1f;
4986}
4987
4988static const void *cea_db_data(const struct cea_db *db)
4989{
4990 return db->data;
4991}
4992
4993static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4994{
4995 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4996 cea_db_payload_len(db) >= 1 &&
4997 db->data[0] == tag;
4998}
4999
5000static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5001{
5002 const u8 *data = cea_db_data(db);
5003
5004 return cea_db_tag(db) == CTA_DB_VENDOR &&
5005 cea_db_payload_len(db) >= 3 &&
5006 oui(data[2], data[1], data[0]) == vendor_oui;
5007}
5008
5009static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5010 struct cea_db_iter *iter)
5011{
5012 memset(iter, 0, sizeof(*iter));
5013
5014 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5015 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5016}
5017
5018static const struct cea_db *
5019__cea_db_iter_current_block(const struct cea_db_iter *iter)
5020{
5021 const struct cea_db *db;
5022
5023 if (!iter->collection)
5024 return NULL;
5025
5026 db = (const struct cea_db *)&iter->collection[iter->index];
5027
5028 if (iter->index + sizeof(*db) <= iter->end &&
5029 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5030 return db;
5031
5032 return NULL;
5033}
5034
5035/*
5036 * References:
5037 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5038 */
5039static int cea_db_collection_size(const u8 *cta)
5040{
5041 u8 d = cta[2];
5042
5043 if (d < 4 || d > 127)
5044 return 0;
5045
5046 return d - 4;
5047}
5048
5049/*
5050 * References:
5051 * - VESA E-EDID v1.4
5052 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5053 */
5054static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5055{
5056 const u8 *ext;
5057
5058 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5059 int size;
5060
5061 /* Only support CTA Extension revision 3+ */
5062 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5063 continue;
5064
5065 size = cea_db_collection_size(ext);
5066 if (!size)
5067 continue;
5068
5069 iter->index = 4;
5070 iter->end = iter->index + size;
5071
5072 return ext;
5073 }
5074
5075 return NULL;
5076}
5077
5078/*
5079 * References:
5080 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5081 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5082 *
5083 * Note that the above do not specify any connection between DisplayID Data
5084 * Block revision and CTA Extension versions.
5085 */
5086static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5087{
5088 const struct displayid_block *block;
5089
5090 displayid_iter_for_each(block, &iter->displayid_iter) {
5091 if (block->tag != DATA_BLOCK_CTA)
5092 continue;
5093
5094 /*
5095 * The displayid iterator has already verified the block bounds
5096 * in displayid_iter_block().
5097 */
5098 iter->index = sizeof(*block);
5099 iter->end = iter->index + block->num_bytes;
5100
5101 return block;
5102 }
5103
5104 return NULL;
5105}
5106
5107static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5108{
5109 const struct cea_db *db;
5110
5111 if (iter->collection) {
5112 /* Current collection should always be valid. */
5113 db = __cea_db_iter_current_block(iter);
5114 if (WARN_ON(!db)) {
5115 iter->collection = NULL;
5116 return NULL;
5117 }
5118
5119 /* Next block in CTA Data Block Collection */
5120 iter->index += sizeof(*db) + cea_db_payload_len(db);
5121
5122 db = __cea_db_iter_current_block(iter);
5123 if (db)
5124 return db;
5125 }
5126
5127 for (;;) {
5128 /*
5129 * Find the next CTA Data Block Collection. First iterate all
5130 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5131 *
5132 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5133 * Extension, it's recommended that DisplayID extensions are
5134 * exposed after all of the CTA Extensions.
5135 */
5136 iter->collection = __cea_db_iter_edid_next(iter);
5137 if (!iter->collection)
5138 iter->collection = __cea_db_iter_displayid_next(iter);
5139
5140 if (!iter->collection)
5141 return NULL;
5142
5143 db = __cea_db_iter_current_block(iter);
5144 if (db)
5145 return db;
5146 }
5147}
5148
5149#define cea_db_iter_for_each(__db, __iter) \
5150 while (((__db) = __cea_db_iter_next(__iter)))
5151
5152static void cea_db_iter_end(struct cea_db_iter *iter)
5153{
5154 displayid_iter_end(&iter->displayid_iter);
5155 drm_edid_iter_end(&iter->edid_iter);
5156
5157 memset(iter, 0, sizeof(*iter));
5158}
5159
5160static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5161{
5162 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5163 cea_db_payload_len(db) >= 5;
5164}
5165
5166static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5167{
5168 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5169 cea_db_payload_len(db) >= 7;
5170}
5171
5172static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5173{
5174 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5175 cea_db_payload_len(db) >= 2;
5176}
5177
5178static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5179{
5180 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5181 cea_db_payload_len(db) == 21;
5182}
5183
5184static bool cea_db_is_vcdb(const struct cea_db *db)
5185{
5186 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5187 cea_db_payload_len(db) == 2;
5188}
5189
5190static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5191{
5192 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5193 cea_db_payload_len(db) >= 7;
5194}
5195
5196static bool cea_db_is_y420cmdb(const struct cea_db *db)
5197{
5198 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5199}
5200
5201static bool cea_db_is_y420vdb(const struct cea_db *db)
5202{
5203 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5204}
5205
5206static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5207{
5208 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5209 cea_db_payload_len(db) >= 3;
5210}
5211
5212/*
5213 * Get the HF-EEODB override extension block count from EDID.
5214 *
5215 * The passed in EDID may be partially read, as long as it has at least two
5216 * blocks (base block and one extension block) if EDID extension count is > 0.
5217 *
5218 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5219 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5220 * iterators instead.
5221 *
5222 * References:
5223 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5224 */
5225static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5226{
5227 const u8 *cta;
5228
5229 /* No extensions according to base block, no HF-EEODB. */
5230 if (!edid_extension_block_count(edid))
5231 return 0;
5232
5233 /* HF-EEODB is always in the first EDID extension block only */
5234 cta = edid_extension_block_data(edid, 0);
5235 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5236 return 0;
5237
5238 /* Need to have the data block collection, and at least 3 bytes. */
5239 if (cea_db_collection_size(cta) < 3)
5240 return 0;
5241
5242 /*
5243 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5244 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5245 * through 6 of Block 1 of the E-EDID.
5246 */
5247 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5248 return 0;
5249
5250 return cta[4 + 2];
5251}
5252
5253/*
5254 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5255 *
5256 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5257 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5258 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5259 * support YCBCR420 output too.
5260 */
5261static void parse_cta_y420cmdb(struct drm_connector *connector,
5262 const struct cea_db *db, u64 *y420cmdb_map)
5263{
5264 struct drm_display_info *info = &connector->display_info;
5265 int i, map_len = cea_db_payload_len(db) - 1;
5266 const u8 *data = cea_db_data(db) + 1;
5267 u64 map = 0;
5268
5269 if (map_len == 0) {
5270 /* All CEA modes support ycbcr420 sampling also.*/
5271 map = U64_MAX;
5272 goto out;
5273 }
5274
5275 /*
5276 * This map indicates which of the existing CEA block modes
5277 * from VDB can support YCBCR420 output too. So if bit=0 is
5278 * set, first mode from VDB can support YCBCR420 output too.
5279 * We will parse and keep this map, before parsing VDB itself
5280 * to avoid going through the same block again and again.
5281 *
5282 * Spec is not clear about max possible size of this block.
5283 * Clamping max bitmap block size at 8 bytes. Every byte can
5284 * address 8 CEA modes, in this way this map can address
5285 * 8*8 = first 64 SVDs.
5286 */
5287 if (WARN_ON_ONCE(map_len > 8))
5288 map_len = 8;
5289
5290 for (i = 0; i < map_len; i++)
5291 map |= (u64)data[i] << (8 * i);
5292
5293out:
5294 if (map)
5295 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5296
5297 *y420cmdb_map = map;
5298}
5299
5300static int add_cea_modes(struct drm_connector *connector,
5301 const struct drm_edid *drm_edid)
5302{
5303 const struct cea_db *db;
5304 struct cea_db_iter iter;
5305 int modes;
5306
5307 /* CTA VDB block VICs parsed earlier */
5308 modes = add_cta_vdb_modes(connector);
5309
5310 cea_db_iter_edid_begin(drm_edid, &iter);
5311 cea_db_iter_for_each(db, &iter) {
5312 if (cea_db_is_hdmi_vsdb(db)) {
5313 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5314 cea_db_payload_len(db));
5315 } else if (cea_db_is_y420vdb(db)) {
5316 const u8 *vdb420 = cea_db_data(db) + 1;
5317
5318 /* Add 4:2:0(only) modes present in EDID */
5319 modes += do_y420vdb_modes(connector, vdb420,
5320 cea_db_payload_len(db) - 1);
5321 }
5322 }
5323 cea_db_iter_end(&iter);
5324
5325 return modes;
5326}
5327
5328static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5329 struct drm_display_mode *mode)
5330{
5331 const struct drm_display_mode *cea_mode;
5332 int clock1, clock2, clock;
5333 u8 vic;
5334 const char *type;
5335
5336 /*
5337 * allow 5kHz clock difference either way to account for
5338 * the 10kHz clock resolution limit of detailed timings.
5339 */
5340 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5341 if (drm_valid_cea_vic(vic)) {
5342 type = "CEA";
5343 cea_mode = cea_mode_for_vic(vic);
5344 clock1 = cea_mode->clock;
5345 clock2 = cea_mode_alternate_clock(cea_mode);
5346 } else {
5347 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5348 if (drm_valid_hdmi_vic(vic)) {
5349 type = "HDMI";
5350 cea_mode = &edid_4k_modes[vic];
5351 clock1 = cea_mode->clock;
5352 clock2 = hdmi_mode_alternate_clock(cea_mode);
5353 } else {
5354 return;
5355 }
5356 }
5357
5358 /* pick whichever is closest */
5359 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5360 clock = clock1;
5361 else
5362 clock = clock2;
5363
5364 if (mode->clock == clock)
5365 return;
5366
5367 drm_dbg_kms(connector->dev,
5368 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5369 connector->base.id, connector->name,
5370 type, vic, mode->clock, clock);
5371 mode->clock = clock;
5372}
5373
5374static void drm_calculate_luminance_range(struct drm_connector *connector)
5375{
5376 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5377 struct drm_luminance_range_info *luminance_range =
5378 &connector->display_info.luminance_range;
5379 static const u8 pre_computed_values[] = {
5380 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5381 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5382 };
5383 u32 max_avg, min_cll, max, min, q, r;
5384
5385 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5386 return;
5387
5388 max_avg = hdr_metadata->max_fall;
5389 min_cll = hdr_metadata->min_cll;
5390
5391 /*
5392 * From the specification (CTA-861-G), for calculating the maximum
5393 * luminance we need to use:
5394 * Luminance = 50*2**(CV/32)
5395 * Where CV is a one-byte value.
5396 * For calculating this expression we may need float point precision;
5397 * to avoid this complexity level, we take advantage that CV is divided
5398 * by a constant. From the Euclids division algorithm, we know that CV
5399 * can be written as: CV = 32*q + r. Next, we replace CV in the
5400 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5401 * need to pre-compute the value of r/32. For pre-computing the values
5402 * We just used the following Ruby line:
5403 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5404 * The results of the above expressions can be verified at
5405 * pre_computed_values.
5406 */
5407 q = max_avg >> 5;
5408 r = max_avg % 32;
5409 max = (1 << q) * pre_computed_values[r];
5410
5411 /* min luminance: maxLum * (CV/255)^2 / 100 */
5412 q = DIV_ROUND_CLOSEST(min_cll, 255);
5413 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5414
5415 luminance_range->min_luminance = min;
5416 luminance_range->max_luminance = max;
5417}
5418
5419static uint8_t eotf_supported(const u8 *edid_ext)
5420{
5421 return edid_ext[2] &
5422 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5423 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5424 BIT(HDMI_EOTF_SMPTE_ST2084) |
5425 BIT(HDMI_EOTF_BT_2100_HLG));
5426}
5427
5428static uint8_t hdr_metadata_type(const u8 *edid_ext)
5429{
5430 return edid_ext[3] &
5431 BIT(HDMI_STATIC_METADATA_TYPE1);
5432}
5433
5434static void
5435drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5436{
5437 u16 len;
5438
5439 len = cea_db_payload_len(db);
5440
5441 connector->hdr_sink_metadata.hdmi_type1.eotf =
5442 eotf_supported(db);
5443 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5444 hdr_metadata_type(db);
5445
5446 if (len >= 4)
5447 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5448 if (len >= 5)
5449 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5450 if (len >= 6) {
5451 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5452
5453 /* Calculate only when all values are available */
5454 drm_calculate_luminance_range(connector);
5455 }
5456}
5457
5458/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5459static void
5460drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5461{
5462 u8 len = cea_db_payload_len(db);
5463
5464 if (len >= 6 && (db[6] & (1 << 7)))
5465 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5466
5467 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5468 connector->latency_present[0] = true;
5469 connector->video_latency[0] = db[9];
5470 connector->audio_latency[0] = db[10];
5471 }
5472
5473 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5474 connector->latency_present[1] = true;
5475 connector->video_latency[1] = db[11];
5476 connector->audio_latency[1] = db[12];
5477 }
5478
5479 drm_dbg_kms(connector->dev,
5480 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5481 connector->base.id, connector->name,
5482 connector->latency_present[0], connector->latency_present[1],
5483 connector->video_latency[0], connector->video_latency[1],
5484 connector->audio_latency[0], connector->audio_latency[1]);
5485}
5486
5487static void
5488match_identity(const struct detailed_timing *timing, void *data)
5489{
5490 struct drm_edid_match_closure *closure = data;
5491 unsigned int i;
5492 const char *name = closure->ident->name;
5493 unsigned int name_len = strlen(name);
5494 const char *desc = timing->data.other_data.data.str.str;
5495 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5496
5497 if (name_len > desc_len ||
5498 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5499 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5500 return;
5501
5502 if (strncmp(name, desc, name_len))
5503 return;
5504
5505 for (i = name_len; i < desc_len; i++) {
5506 if (desc[i] == '\n')
5507 break;
5508 /* Allow white space before EDID string terminator. */
5509 if (!isspace(desc[i]))
5510 return;
5511 }
5512
5513 closure->matched = true;
5514}
5515
5516/**
5517 * drm_edid_match - match drm_edid with given identity
5518 * @drm_edid: EDID
5519 * @ident: the EDID identity to match with
5520 *
5521 * Check if the EDID matches with the given identity.
5522 *
5523 * Return: True if the given identity matched with EDID, false otherwise.
5524 */
5525bool drm_edid_match(const struct drm_edid *drm_edid,
5526 const struct drm_edid_ident *ident)
5527{
5528 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5529 return false;
5530
5531 /* Match with name only if it's not NULL. */
5532 if (ident->name) {
5533 struct drm_edid_match_closure closure = {
5534 .ident = ident,
5535 .matched = false,
5536 };
5537
5538 drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5539
5540 return closure.matched;
5541 }
5542
5543 return true;
5544}
5545EXPORT_SYMBOL(drm_edid_match);
5546
5547static void
5548monitor_name(const struct detailed_timing *timing, void *data)
5549{
5550 const char **res = data;
5551
5552 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5553 return;
5554
5555 *res = timing->data.other_data.data.str.str;
5556}
5557
5558static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5559{
5560 const char *edid_name = NULL;
5561 int mnl;
5562
5563 if (!drm_edid || !name)
5564 return 0;
5565
5566 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5567 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5568 if (edid_name[mnl] == 0x0a)
5569 break;
5570
5571 name[mnl] = edid_name[mnl];
5572 }
5573
5574 return mnl;
5575}
5576
5577/**
5578 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5579 * @edid: monitor EDID information
5580 * @name: pointer to a character array to hold the name of the monitor
5581 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5582 *
5583 */
5584void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5585{
5586 int name_length = 0;
5587
5588 if (bufsize <= 0)
5589 return;
5590
5591 if (edid) {
5592 char buf[13];
5593 struct drm_edid drm_edid = {
5594 .edid = edid,
5595 .size = edid_size(edid),
5596 };
5597
5598 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5599 memcpy(name, buf, name_length);
5600 }
5601
5602 name[name_length] = '\0';
5603}
5604EXPORT_SYMBOL(drm_edid_get_monitor_name);
5605
5606static void clear_eld(struct drm_connector *connector)
5607{
5608 mutex_lock(&connector->eld_mutex);
5609 memset(connector->eld, 0, sizeof(connector->eld));
5610 mutex_unlock(&connector->eld_mutex);
5611
5612 connector->latency_present[0] = false;
5613 connector->latency_present[1] = false;
5614 connector->video_latency[0] = 0;
5615 connector->audio_latency[0] = 0;
5616 connector->video_latency[1] = 0;
5617 connector->audio_latency[1] = 0;
5618}
5619
5620/*
5621 * Get 3-byte SAD buffer from struct cea_sad.
5622 */
5623void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5624{
5625 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5626 sad[1] = cta_sad->freq;
5627 sad[2] = cta_sad->byte2;
5628}
5629
5630/*
5631 * Set struct cea_sad from 3-byte SAD buffer.
5632 */
5633void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5634{
5635 cta_sad->format = (sad[0] & 0x78) >> 3;
5636 cta_sad->channels = sad[0] & 0x07;
5637 cta_sad->freq = sad[1] & 0x7f;
5638 cta_sad->byte2 = sad[2];
5639}
5640
5641/*
5642 * drm_edid_to_eld - build ELD from EDID
5643 * @connector: connector corresponding to the HDMI/DP sink
5644 * @drm_edid: EDID to parse
5645 *
5646 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5647 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5648 */
5649static void drm_edid_to_eld(struct drm_connector *connector,
5650 const struct drm_edid *drm_edid)
5651{
5652 const struct drm_display_info *info = &connector->display_info;
5653 const struct cea_db *db;
5654 struct cea_db_iter iter;
5655 uint8_t *eld = connector->eld;
5656 int total_sad_count = 0;
5657 int mnl;
5658
5659 if (!drm_edid)
5660 return;
5661
5662 mutex_lock(&connector->eld_mutex);
5663
5664 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5665 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5666 connector->base.id, connector->name,
5667 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5668
5669 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5670 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5671
5672 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5673
5674 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5675 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5676 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5677 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5678
5679 cea_db_iter_edid_begin(drm_edid, &iter);
5680 cea_db_iter_for_each(db, &iter) {
5681 const u8 *data = cea_db_data(db);
5682 int len = cea_db_payload_len(db);
5683 int sad_count;
5684
5685 switch (cea_db_tag(db)) {
5686 case CTA_DB_AUDIO:
5687 /* Audio Data Block, contains SADs */
5688 sad_count = min(len / 3, 15 - total_sad_count);
5689 if (sad_count >= 1)
5690 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5691 data, sad_count * 3);
5692 total_sad_count += sad_count;
5693 break;
5694 case CTA_DB_SPEAKER:
5695 /* Speaker Allocation Data Block */
5696 if (len >= 1)
5697 eld[DRM_ELD_SPEAKER] = data[0];
5698 break;
5699 case CTA_DB_VENDOR:
5700 /* HDMI Vendor-Specific Data Block */
5701 if (cea_db_is_hdmi_vsdb(db))
5702 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5703 break;
5704 default:
5705 break;
5706 }
5707 }
5708 cea_db_iter_end(&iter);
5709
5710 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5711
5712 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5713 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5714 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5715 else
5716 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5717
5718 eld[DRM_ELD_BASELINE_ELD_LEN] =
5719 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5720
5721 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5722 connector->base.id, connector->name,
5723 drm_eld_size(eld), total_sad_count);
5724
5725 mutex_unlock(&connector->eld_mutex);
5726}
5727
5728static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5729 struct cea_sad **psads)
5730{
5731 const struct cea_db *db;
5732 struct cea_db_iter iter;
5733 int count = 0;
5734
5735 cea_db_iter_edid_begin(drm_edid, &iter);
5736 cea_db_iter_for_each(db, &iter) {
5737 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5738 struct cea_sad *sads;
5739 int i;
5740
5741 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5742 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5743 *psads = sads;
5744 if (!sads)
5745 return -ENOMEM;
5746 for (i = 0; i < count; i++)
5747 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5748 break;
5749 }
5750 }
5751 cea_db_iter_end(&iter);
5752
5753 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5754
5755 return count;
5756}
5757
5758/**
5759 * drm_edid_to_sad - extracts SADs from EDID
5760 * @edid: EDID to parse
5761 * @sads: pointer that will be set to the extracted SADs
5762 *
5763 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5764 *
5765 * Note: The returned pointer needs to be freed using kfree().
5766 *
5767 * Return: The number of found SADs or negative number on error.
5768 */
5769int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5770{
5771 struct drm_edid drm_edid;
5772
5773 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5774}
5775EXPORT_SYMBOL(drm_edid_to_sad);
5776
5777static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5778 u8 **sadb)
5779{
5780 const struct cea_db *db;
5781 struct cea_db_iter iter;
5782 int count = 0;
5783
5784 cea_db_iter_edid_begin(drm_edid, &iter);
5785 cea_db_iter_for_each(db, &iter) {
5786 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5787 cea_db_payload_len(db) == 3) {
5788 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5789 GFP_KERNEL);
5790 if (!*sadb)
5791 return -ENOMEM;
5792 count = cea_db_payload_len(db);
5793 break;
5794 }
5795 }
5796 cea_db_iter_end(&iter);
5797
5798 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5799
5800 return count;
5801}
5802
5803/**
5804 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5805 * @edid: EDID to parse
5806 * @sadb: pointer to the speaker block
5807 *
5808 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5809 *
5810 * Note: The returned pointer needs to be freed using kfree().
5811 *
5812 * Return: The number of found Speaker Allocation Blocks or negative number on
5813 * error.
5814 */
5815int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5816{
5817 struct drm_edid drm_edid;
5818
5819 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5820 sadb);
5821}
5822EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5823
5824/**
5825 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5826 * @connector: connector associated with the HDMI/DP sink
5827 * @mode: the display mode
5828 *
5829 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5830 * the sink doesn't support audio or video.
5831 */
5832int drm_av_sync_delay(struct drm_connector *connector,
5833 const struct drm_display_mode *mode)
5834{
5835 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5836 int a, v;
5837
5838 if (!connector->latency_present[0])
5839 return 0;
5840 if (!connector->latency_present[1])
5841 i = 0;
5842
5843 a = connector->audio_latency[i];
5844 v = connector->video_latency[i];
5845
5846 /*
5847 * HDMI/DP sink doesn't support audio or video?
5848 */
5849 if (a == 255 || v == 255)
5850 return 0;
5851
5852 /*
5853 * Convert raw EDID values to millisecond.
5854 * Treat unknown latency as 0ms.
5855 */
5856 if (a)
5857 a = min(2 * (a - 1), 500);
5858 if (v)
5859 v = min(2 * (v - 1), 500);
5860
5861 return max(v - a, 0);
5862}
5863EXPORT_SYMBOL(drm_av_sync_delay);
5864
5865static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5866{
5867 const struct cea_db *db;
5868 struct cea_db_iter iter;
5869 bool hdmi = false;
5870
5871 /*
5872 * Because HDMI identifier is in Vendor Specific Block,
5873 * search it from all data blocks of CEA extension.
5874 */
5875 cea_db_iter_edid_begin(drm_edid, &iter);
5876 cea_db_iter_for_each(db, &iter) {
5877 if (cea_db_is_hdmi_vsdb(db)) {
5878 hdmi = true;
5879 break;
5880 }
5881 }
5882 cea_db_iter_end(&iter);
5883
5884 return hdmi;
5885}
5886
5887/**
5888 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5889 * @edid: monitor EDID information
5890 *
5891 * Parse the CEA extension according to CEA-861-B.
5892 *
5893 * Drivers that have added the modes parsed from EDID to drm_display_info
5894 * should use &drm_display_info.is_hdmi instead of calling this function.
5895 *
5896 * Return: True if the monitor is HDMI, false if not or unknown.
5897 */
5898bool drm_detect_hdmi_monitor(const struct edid *edid)
5899{
5900 struct drm_edid drm_edid;
5901
5902 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5903}
5904EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5905
5906static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5907{
5908 struct drm_edid_iter edid_iter;
5909 const struct cea_db *db;
5910 struct cea_db_iter iter;
5911 const u8 *edid_ext;
5912 bool has_audio = false;
5913
5914 drm_edid_iter_begin(drm_edid, &edid_iter);
5915 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5916 if (edid_ext[0] == CEA_EXT) {
5917 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5918 if (has_audio)
5919 break;
5920 }
5921 }
5922 drm_edid_iter_end(&edid_iter);
5923
5924 if (has_audio) {
5925 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5926 goto end;
5927 }
5928
5929 cea_db_iter_edid_begin(drm_edid, &iter);
5930 cea_db_iter_for_each(db, &iter) {
5931 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5932 const u8 *data = cea_db_data(db);
5933 int i;
5934
5935 for (i = 0; i < cea_db_payload_len(db); i += 3)
5936 DRM_DEBUG_KMS("CEA audio format %d\n",
5937 (data[i] >> 3) & 0xf);
5938 has_audio = true;
5939 break;
5940 }
5941 }
5942 cea_db_iter_end(&iter);
5943
5944end:
5945 return has_audio;
5946}
5947
5948/**
5949 * drm_detect_monitor_audio - check monitor audio capability
5950 * @edid: EDID block to scan
5951 *
5952 * Monitor should have CEA extension block.
5953 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5954 * audio' only. If there is any audio extension block and supported
5955 * audio format, assume at least 'basic audio' support, even if 'basic
5956 * audio' is not defined in EDID.
5957 *
5958 * Return: True if the monitor supports audio, false otherwise.
5959 */
5960bool drm_detect_monitor_audio(const struct edid *edid)
5961{
5962 struct drm_edid drm_edid;
5963
5964 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5965}
5966EXPORT_SYMBOL(drm_detect_monitor_audio);
5967
5968
5969/**
5970 * drm_default_rgb_quant_range - default RGB quantization range
5971 * @mode: display mode
5972 *
5973 * Determine the default RGB quantization range for the mode,
5974 * as specified in CEA-861.
5975 *
5976 * Return: The default RGB quantization range for the mode
5977 */
5978enum hdmi_quantization_range
5979drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5980{
5981 /* All CEA modes other than VIC 1 use limited quantization range. */
5982 return drm_match_cea_mode(mode) > 1 ?
5983 HDMI_QUANTIZATION_RANGE_LIMITED :
5984 HDMI_QUANTIZATION_RANGE_FULL;
5985}
5986EXPORT_SYMBOL(drm_default_rgb_quant_range);
5987
5988/* CTA-861 Video Data Block (CTA VDB) */
5989static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5990{
5991 struct drm_display_info *info = &connector->display_info;
5992 int i, vic_index, len = cea_db_payload_len(db);
5993 const u8 *svds = cea_db_data(db);
5994 u8 *vics;
5995
5996 if (!len)
5997 return;
5998
5999 /* Gracefully handle multiple VDBs, however unlikely that is */
6000 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6001 if (!vics)
6002 return;
6003
6004 vic_index = info->vics_len;
6005 info->vics_len += len;
6006 info->vics = vics;
6007
6008 for (i = 0; i < len; i++) {
6009 u8 vic = svd_to_vic(svds[i]);
6010
6011 if (!drm_valid_cea_vic(vic))
6012 vic = 0;
6013
6014 info->vics[vic_index++] = vic;
6015 }
6016}
6017
6018/*
6019 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6020 *
6021 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6022 * using the VICs themselves.
6023 */
6024static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6025{
6026 struct drm_display_info *info = &connector->display_info;
6027 struct drm_hdmi_info *hdmi = &info->hdmi;
6028 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6029
6030 for (i = 0; i < len; i++) {
6031 u8 vic = info->vics[i];
6032
6033 if (vic && y420cmdb_map & BIT_ULL(i))
6034 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6035 }
6036}
6037
6038static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6039{
6040 const struct drm_display_info *info = &connector->display_info;
6041 int i;
6042
6043 if (!vic || !info->vics)
6044 return false;
6045
6046 for (i = 0; i < info->vics_len; i++) {
6047 if (info->vics[i] == vic)
6048 return true;
6049 }
6050
6051 return false;
6052}
6053
6054/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
6055static void parse_cta_y420vdb(struct drm_connector *connector,
6056 const struct cea_db *db)
6057{
6058 struct drm_display_info *info = &connector->display_info;
6059 struct drm_hdmi_info *hdmi = &info->hdmi;
6060 const u8 *svds = cea_db_data(db) + 1;
6061 int i;
6062
6063 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6064 u8 vic = svd_to_vic(svds[i]);
6065
6066 if (!drm_valid_cea_vic(vic))
6067 continue;
6068
6069 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6070 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6071 }
6072}
6073
6074static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6075{
6076 struct drm_display_info *info = &connector->display_info;
6077
6078 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6079 connector->base.id, connector->name, db[2]);
6080
6081 if (db[2] & EDID_CEA_VCDB_QS)
6082 info->rgb_quant_range_selectable = true;
6083}
6084
6085static
6086void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6087{
6088 switch (max_frl_rate) {
6089 case 1:
6090 *max_lanes = 3;
6091 *max_rate_per_lane = 3;
6092 break;
6093 case 2:
6094 *max_lanes = 3;
6095 *max_rate_per_lane = 6;
6096 break;
6097 case 3:
6098 *max_lanes = 4;
6099 *max_rate_per_lane = 6;
6100 break;
6101 case 4:
6102 *max_lanes = 4;
6103 *max_rate_per_lane = 8;
6104 break;
6105 case 5:
6106 *max_lanes = 4;
6107 *max_rate_per_lane = 10;
6108 break;
6109 case 6:
6110 *max_lanes = 4;
6111 *max_rate_per_lane = 12;
6112 break;
6113 case 0:
6114 default:
6115 *max_lanes = 0;
6116 *max_rate_per_lane = 0;
6117 }
6118}
6119
6120static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6121 const u8 *db)
6122{
6123 u8 dc_mask;
6124 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6125
6126 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6127 hdmi->y420_dc_modes = dc_mask;
6128}
6129
6130static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6131 const u8 *hf_scds)
6132{
6133 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6134
6135 if (!hdmi_dsc->v_1p2)
6136 return;
6137
6138 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6139 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6140
6141 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6142 hdmi_dsc->bpc_supported = 16;
6143 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6144 hdmi_dsc->bpc_supported = 12;
6145 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6146 hdmi_dsc->bpc_supported = 10;
6147 else
6148 /* Supports min 8 BPC if DSC 1.2 is supported*/
6149 hdmi_dsc->bpc_supported = 8;
6150
6151 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6152 u8 dsc_max_slices;
6153 u8 dsc_max_frl_rate;
6154
6155 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6156 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6157 &hdmi_dsc->max_frl_rate_per_lane);
6158
6159 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6160
6161 switch (dsc_max_slices) {
6162 case 1:
6163 hdmi_dsc->max_slices = 1;
6164 hdmi_dsc->clk_per_slice = 340;
6165 break;
6166 case 2:
6167 hdmi_dsc->max_slices = 2;
6168 hdmi_dsc->clk_per_slice = 340;
6169 break;
6170 case 3:
6171 hdmi_dsc->max_slices = 4;
6172 hdmi_dsc->clk_per_slice = 340;
6173 break;
6174 case 4:
6175 hdmi_dsc->max_slices = 8;
6176 hdmi_dsc->clk_per_slice = 340;
6177 break;
6178 case 5:
6179 hdmi_dsc->max_slices = 8;
6180 hdmi_dsc->clk_per_slice = 400;
6181 break;
6182 case 6:
6183 hdmi_dsc->max_slices = 12;
6184 hdmi_dsc->clk_per_slice = 400;
6185 break;
6186 case 7:
6187 hdmi_dsc->max_slices = 16;
6188 hdmi_dsc->clk_per_slice = 400;
6189 break;
6190 case 0:
6191 default:
6192 hdmi_dsc->max_slices = 0;
6193 hdmi_dsc->clk_per_slice = 0;
6194 }
6195 }
6196
6197 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6198 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6199}
6200
6201/* Sink Capability Data Structure */
6202static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6203 const u8 *hf_scds)
6204{
6205 struct drm_display_info *info = &connector->display_info;
6206 struct drm_hdmi_info *hdmi = &info->hdmi;
6207 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6208 int max_tmds_clock = 0;
6209 u8 max_frl_rate = 0;
6210 bool dsc_support = false;
6211
6212 info->has_hdmi_infoframe = true;
6213
6214 if (hf_scds[6] & 0x80) {
6215 hdmi->scdc.supported = true;
6216 if (hf_scds[6] & 0x40)
6217 hdmi->scdc.read_request = true;
6218 }
6219
6220 /*
6221 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6222 * And as per the spec, three factors confirm this:
6223 * * Availability of a HF-VSDB block in EDID (check)
6224 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6225 * * SCDC support available (let's check)
6226 * Lets check it out.
6227 */
6228
6229 if (hf_scds[5]) {
6230 struct drm_scdc *scdc = &hdmi->scdc;
6231
6232 /* max clock is 5000 KHz times block value */
6233 max_tmds_clock = hf_scds[5] * 5000;
6234
6235 if (max_tmds_clock > 340000) {
6236 info->max_tmds_clock = max_tmds_clock;
6237 }
6238
6239 if (scdc->supported) {
6240 scdc->scrambling.supported = true;
6241
6242 /* Few sinks support scrambling for clocks < 340M */
6243 if ((hf_scds[6] & 0x8))
6244 scdc->scrambling.low_rates = true;
6245 }
6246 }
6247
6248 if (hf_scds[7]) {
6249 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6250 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6251 &hdmi->max_frl_rate_per_lane);
6252 }
6253
6254 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6255
6256 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6257 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6258 dsc_support = true;
6259 }
6260
6261 drm_dbg_kms(connector->dev,
6262 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6263 connector->base.id, connector->name,
6264 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6265}
6266
6267static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6268 const u8 *hdmi)
6269{
6270 struct drm_display_info *info = &connector->display_info;
6271 unsigned int dc_bpc = 0;
6272
6273 /* HDMI supports at least 8 bpc */
6274 info->bpc = 8;
6275
6276 if (cea_db_payload_len(hdmi) < 6)
6277 return;
6278
6279 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6280 dc_bpc = 10;
6281 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6282 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6283 connector->base.id, connector->name);
6284 }
6285
6286 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6287 dc_bpc = 12;
6288 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6289 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6290 connector->base.id, connector->name);
6291 }
6292
6293 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6294 dc_bpc = 16;
6295 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6296 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6297 connector->base.id, connector->name);
6298 }
6299
6300 if (dc_bpc == 0) {
6301 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6302 connector->base.id, connector->name);
6303 return;
6304 }
6305
6306 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6307 connector->base.id, connector->name, dc_bpc);
6308 info->bpc = dc_bpc;
6309
6310 /* YCRCB444 is optional according to spec. */
6311 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6312 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6313 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6314 connector->base.id, connector->name);
6315 }
6316
6317 /*
6318 * Spec says that if any deep color mode is supported at all,
6319 * then deep color 36 bit must be supported.
6320 */
6321 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6322 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6323 connector->base.id, connector->name);
6324 }
6325}
6326
6327/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6328static void
6329drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6330{
6331 struct drm_display_info *info = &connector->display_info;
6332 u8 len = cea_db_payload_len(db);
6333
6334 info->is_hdmi = true;
6335
6336 info->source_physical_address = (db[4] << 8) | db[5];
6337
6338 if (len >= 6)
6339 info->dvi_dual = db[6] & 1;
6340 if (len >= 7)
6341 info->max_tmds_clock = db[7] * 5000;
6342
6343 /*
6344 * Try to infer whether the sink supports HDMI infoframes.
6345 *
6346 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6347 * supports infoframes if HDMI_Video_present is set.
6348 */
6349 if (len >= 8 && db[8] & BIT(5))
6350 info->has_hdmi_infoframe = true;
6351
6352 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6353 connector->base.id, connector->name,
6354 info->dvi_dual, info->max_tmds_clock);
6355
6356 drm_parse_hdmi_deep_color_info(connector, db);
6357}
6358
6359/*
6360 * See EDID extension for head-mounted and specialized monitors, specified at:
6361 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6362 */
6363static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6364 const u8 *db)
6365{
6366 struct drm_display_info *info = &connector->display_info;
6367 u8 version = db[4];
6368 bool desktop_usage = db[5] & BIT(6);
6369
6370 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6371 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6372 info->non_desktop = true;
6373
6374 drm_dbg_kms(connector->dev,
6375 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6376 connector->base.id, connector->name, version, db[5]);
6377}
6378
6379static void drm_parse_cea_ext(struct drm_connector *connector,
6380 const struct drm_edid *drm_edid)
6381{
6382 struct drm_display_info *info = &connector->display_info;
6383 struct drm_edid_iter edid_iter;
6384 const struct cea_db *db;
6385 struct cea_db_iter iter;
6386 const u8 *edid_ext;
6387 u64 y420cmdb_map = 0;
6388
6389 drm_edid_iter_begin(drm_edid, &edid_iter);
6390 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6391 if (edid_ext[0] != CEA_EXT)
6392 continue;
6393
6394 if (!info->cea_rev)
6395 info->cea_rev = edid_ext[1];
6396
6397 if (info->cea_rev != edid_ext[1])
6398 drm_dbg_kms(connector->dev,
6399 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6400 connector->base.id, connector->name,
6401 info->cea_rev, edid_ext[1]);
6402
6403 /* The existence of a CTA extension should imply RGB support */
6404 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6405 if (edid_ext[3] & EDID_CEA_YCRCB444)
6406 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6407 if (edid_ext[3] & EDID_CEA_YCRCB422)
6408 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6409 if (edid_ext[3] & EDID_BASIC_AUDIO)
6410 info->has_audio = true;
6411
6412 }
6413 drm_edid_iter_end(&edid_iter);
6414
6415 cea_db_iter_edid_begin(drm_edid, &iter);
6416 cea_db_iter_for_each(db, &iter) {
6417 /* FIXME: convert parsers to use struct cea_db */
6418 const u8 *data = (const u8 *)db;
6419
6420 if (cea_db_is_hdmi_vsdb(db))
6421 drm_parse_hdmi_vsdb_video(connector, data);
6422 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6423 cea_db_is_hdmi_forum_scdb(db))
6424 drm_parse_hdmi_forum_scds(connector, data);
6425 else if (cea_db_is_microsoft_vsdb(db))
6426 drm_parse_microsoft_vsdb(connector, data);
6427 else if (cea_db_is_y420cmdb(db))
6428 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6429 else if (cea_db_is_y420vdb(db))
6430 parse_cta_y420vdb(connector, db);
6431 else if (cea_db_is_vcdb(db))
6432 drm_parse_vcdb(connector, data);
6433 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6434 drm_parse_hdr_metadata_block(connector, data);
6435 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6436 parse_cta_vdb(connector, db);
6437 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6438 info->has_audio = true;
6439 }
6440 cea_db_iter_end(&iter);
6441
6442 if (y420cmdb_map)
6443 update_cta_y420cmdb(connector, y420cmdb_map);
6444}
6445
6446static
6447void get_monitor_range(const struct detailed_timing *timing, void *c)
6448{
6449 struct detailed_mode_closure *closure = c;
6450 struct drm_display_info *info = &closure->connector->display_info;
6451 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6452 const struct detailed_non_pixel *data = &timing->data.other_data;
6453 const struct detailed_data_monitor_range *range = &data->data.range;
6454 const struct edid *edid = closure->drm_edid->edid;
6455
6456 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6457 return;
6458
6459 /*
6460 * These limits are used to determine the VRR refresh
6461 * rate range. Only the "range limits only" variant
6462 * of the range descriptor seems to guarantee that
6463 * any and all timings are accepted by the sink, as
6464 * opposed to just timings conforming to the indicated
6465 * formula (GTF/GTF2/CVT). Thus other variants of the
6466 * range descriptor are not accepted here.
6467 */
6468 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6469 return;
6470
6471 monitor_range->min_vfreq = range->min_vfreq;
6472 monitor_range->max_vfreq = range->max_vfreq;
6473
6474 if (edid->revision >= 4) {
6475 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6476 monitor_range->min_vfreq += 255;
6477 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6478 monitor_range->max_vfreq += 255;
6479 }
6480}
6481
6482static void drm_get_monitor_range(struct drm_connector *connector,
6483 const struct drm_edid *drm_edid)
6484{
6485 const struct drm_display_info *info = &connector->display_info;
6486 struct detailed_mode_closure closure = {
6487 .connector = connector,
6488 .drm_edid = drm_edid,
6489 };
6490
6491 if (drm_edid->edid->revision < 4)
6492 return;
6493
6494 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6495 return;
6496
6497 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6498
6499 drm_dbg_kms(connector->dev,
6500 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6501 connector->base.id, connector->name,
6502 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6503}
6504
6505static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6506 const struct displayid_block *block)
6507{
6508 struct displayid_vesa_vendor_specific_block *vesa =
6509 (struct displayid_vesa_vendor_specific_block *)block;
6510 struct drm_display_info *info = &connector->display_info;
6511
6512 if (block->num_bytes < 3) {
6513 drm_dbg_kms(connector->dev,
6514 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6515 connector->base.id, connector->name, block->num_bytes);
6516 return;
6517 }
6518
6519 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6520 return;
6521
6522 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6523 drm_dbg_kms(connector->dev,
6524 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6525 connector->base.id, connector->name);
6526 return;
6527 }
6528
6529 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6530 default:
6531 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6532 connector->base.id, connector->name);
6533 fallthrough;
6534 case 0:
6535 info->mso_stream_count = 0;
6536 break;
6537 case 1:
6538 info->mso_stream_count = 2; /* 2 or 4 links */
6539 break;
6540 case 2:
6541 info->mso_stream_count = 4; /* 4 links */
6542 break;
6543 }
6544
6545 if (!info->mso_stream_count) {
6546 info->mso_pixel_overlap = 0;
6547 return;
6548 }
6549
6550 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6551 if (info->mso_pixel_overlap > 8) {
6552 drm_dbg_kms(connector->dev,
6553 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6554 connector->base.id, connector->name,
6555 info->mso_pixel_overlap);
6556 info->mso_pixel_overlap = 8;
6557 }
6558
6559 drm_dbg_kms(connector->dev,
6560 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6561 connector->base.id, connector->name,
6562 info->mso_stream_count, info->mso_pixel_overlap);
6563}
6564
6565static void drm_update_mso(struct drm_connector *connector,
6566 const struct drm_edid *drm_edid)
6567{
6568 const struct displayid_block *block;
6569 struct displayid_iter iter;
6570
6571 displayid_iter_edid_begin(drm_edid, &iter);
6572 displayid_iter_for_each(block, &iter) {
6573 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6574 drm_parse_vesa_mso_data(connector, block);
6575 }
6576 displayid_iter_end(&iter);
6577}
6578
6579/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6580 * all of the values which would have been set from EDID
6581 */
6582static void drm_reset_display_info(struct drm_connector *connector)
6583{
6584 struct drm_display_info *info = &connector->display_info;
6585
6586 info->width_mm = 0;
6587 info->height_mm = 0;
6588
6589 info->bpc = 0;
6590 info->color_formats = 0;
6591 info->cea_rev = 0;
6592 info->max_tmds_clock = 0;
6593 info->dvi_dual = false;
6594 info->is_hdmi = false;
6595 info->has_audio = false;
6596 info->has_hdmi_infoframe = false;
6597 info->rgb_quant_range_selectable = false;
6598 memset(&info->hdmi, 0, sizeof(info->hdmi));
6599
6600 info->edid_hdmi_rgb444_dc_modes = 0;
6601 info->edid_hdmi_ycbcr444_dc_modes = 0;
6602
6603 info->non_desktop = 0;
6604 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6605 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6606
6607 info->mso_stream_count = 0;
6608 info->mso_pixel_overlap = 0;
6609 info->max_dsc_bpp = 0;
6610
6611 kfree(info->vics);
6612 info->vics = NULL;
6613 info->vics_len = 0;
6614
6615 info->quirks = 0;
6616
6617 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6618}
6619
6620static void update_displayid_info(struct drm_connector *connector,
6621 const struct drm_edid *drm_edid)
6622{
6623 struct drm_display_info *info = &connector->display_info;
6624 const struct displayid_block *block;
6625 struct displayid_iter iter;
6626
6627 displayid_iter_edid_begin(drm_edid, &iter);
6628 displayid_iter_for_each(block, &iter) {
6629 drm_dbg_kms(connector->dev,
6630 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n",
6631 connector->base.id, connector->name,
6632 displayid_version(&iter),
6633 displayid_primary_use(&iter));
6634 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6635 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6636 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6637 info->non_desktop = true;
6638
6639 /*
6640 * We're only interested in the base section here, no need to
6641 * iterate further.
6642 */
6643 break;
6644 }
6645 displayid_iter_end(&iter);
6646}
6647
6648static void update_display_info(struct drm_connector *connector,
6649 const struct drm_edid *drm_edid)
6650{
6651 struct drm_display_info *info = &connector->display_info;
6652 const struct edid *edid;
6653
6654 drm_reset_display_info(connector);
6655 clear_eld(connector);
6656
6657 if (!drm_edid)
6658 return;
6659
6660 edid = drm_edid->edid;
6661
6662 info->quirks = edid_get_quirks(drm_edid);
6663
6664 info->width_mm = edid->width_cm * 10;
6665 info->height_mm = edid->height_cm * 10;
6666
6667 drm_get_monitor_range(connector, drm_edid);
6668
6669 if (edid->revision < 3)
6670 goto out;
6671
6672 if (!drm_edid_is_digital(drm_edid))
6673 goto out;
6674
6675 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6676 drm_parse_cea_ext(connector, drm_edid);
6677
6678 update_displayid_info(connector, drm_edid);
6679
6680 /*
6681 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6682 *
6683 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6684 * tells us to assume 8 bpc color depth if the EDID doesn't have
6685 * extensions which tell otherwise.
6686 */
6687 if (info->bpc == 0 && edid->revision == 3 &&
6688 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6689 info->bpc = 8;
6690 drm_dbg_kms(connector->dev,
6691 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6692 connector->base.id, connector->name, info->bpc);
6693 }
6694
6695 /* Only defined for 1.4 with digital displays */
6696 if (edid->revision < 4)
6697 goto out;
6698
6699 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6700 case DRM_EDID_DIGITAL_DEPTH_6:
6701 info->bpc = 6;
6702 break;
6703 case DRM_EDID_DIGITAL_DEPTH_8:
6704 info->bpc = 8;
6705 break;
6706 case DRM_EDID_DIGITAL_DEPTH_10:
6707 info->bpc = 10;
6708 break;
6709 case DRM_EDID_DIGITAL_DEPTH_12:
6710 info->bpc = 12;
6711 break;
6712 case DRM_EDID_DIGITAL_DEPTH_14:
6713 info->bpc = 14;
6714 break;
6715 case DRM_EDID_DIGITAL_DEPTH_16:
6716 info->bpc = 16;
6717 break;
6718 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6719 default:
6720 info->bpc = 0;
6721 break;
6722 }
6723
6724 drm_dbg_kms(connector->dev,
6725 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6726 connector->base.id, connector->name, info->bpc);
6727
6728 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6729 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6730 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6731 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6732
6733 drm_update_mso(connector, drm_edid);
6734
6735out:
6736 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6737 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6738 connector->base.id, connector->name,
6739 info->non_desktop ? " (redundant quirk)" : "");
6740 info->non_desktop = true;
6741 }
6742
6743 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6744 info->max_dsc_bpp = 15;
6745
6746 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6747 info->bpc = 6;
6748
6749 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6750 info->bpc = 8;
6751
6752 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6753 info->bpc = 10;
6754
6755 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6756 info->bpc = 12;
6757
6758 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6759 drm_edid_to_eld(connector, drm_edid);
6760}
6761
6762static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6763 struct displayid_detailed_timings_1 *timings,
6764 bool type_7)
6765{
6766 struct drm_display_mode *mode;
6767 unsigned pixel_clock = (timings->pixel_clock[0] |
6768 (timings->pixel_clock[1] << 8) |
6769 (timings->pixel_clock[2] << 16)) + 1;
6770 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6771 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6772 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6773 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6774 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6775 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6776 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6777 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6778 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6779 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6780
6781 mode = drm_mode_create(dev);
6782 if (!mode)
6783 return NULL;
6784
6785 /* resolution is kHz for type VII, and 10 kHz for type I */
6786 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6787 mode->hdisplay = hactive;
6788 mode->hsync_start = mode->hdisplay + hsync;
6789 mode->hsync_end = mode->hsync_start + hsync_width;
6790 mode->htotal = mode->hdisplay + hblank;
6791
6792 mode->vdisplay = vactive;
6793 mode->vsync_start = mode->vdisplay + vsync;
6794 mode->vsync_end = mode->vsync_start + vsync_width;
6795 mode->vtotal = mode->vdisplay + vblank;
6796
6797 mode->flags = 0;
6798 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6799 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6800 mode->type = DRM_MODE_TYPE_DRIVER;
6801
6802 if (timings->flags & 0x80)
6803 mode->type |= DRM_MODE_TYPE_PREFERRED;
6804 drm_mode_set_name(mode);
6805
6806 return mode;
6807}
6808
6809static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6810 const struct displayid_block *block)
6811{
6812 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6813 int i;
6814 int num_timings;
6815 struct drm_display_mode *newmode;
6816 int num_modes = 0;
6817 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6818 /* blocks must be multiple of 20 bytes length */
6819 if (block->num_bytes % 20)
6820 return 0;
6821
6822 num_timings = block->num_bytes / 20;
6823 for (i = 0; i < num_timings; i++) {
6824 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6825
6826 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6827 if (!newmode)
6828 continue;
6829
6830 drm_mode_probed_add(connector, newmode);
6831 num_modes++;
6832 }
6833 return num_modes;
6834}
6835
6836static int add_displayid_detailed_modes(struct drm_connector *connector,
6837 const struct drm_edid *drm_edid)
6838{
6839 const struct displayid_block *block;
6840 struct displayid_iter iter;
6841 int num_modes = 0;
6842
6843 displayid_iter_edid_begin(drm_edid, &iter);
6844 displayid_iter_for_each(block, &iter) {
6845 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6846 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6847 num_modes += add_displayid_detailed_1_modes(connector, block);
6848 }
6849 displayid_iter_end(&iter);
6850
6851 return num_modes;
6852}
6853
6854static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6855 const struct drm_edid *drm_edid)
6856{
6857 const struct drm_display_info *info = &connector->display_info;
6858 int num_modes = 0;
6859
6860 if (!drm_edid)
6861 return 0;
6862
6863 /*
6864 * EDID spec says modes should be preferred in this order:
6865 * - preferred detailed mode
6866 * - other detailed modes from base block
6867 * - detailed modes from extension blocks
6868 * - CVT 3-byte code modes
6869 * - standard timing codes
6870 * - established timing codes
6871 * - modes inferred from GTF or CVT range information
6872 *
6873 * We get this pretty much right.
6874 *
6875 * XXX order for additional mode types in extension blocks?
6876 */
6877 num_modes += add_detailed_modes(connector, drm_edid);
6878 num_modes += add_cvt_modes(connector, drm_edid);
6879 num_modes += add_standard_modes(connector, drm_edid);
6880 num_modes += add_established_modes(connector, drm_edid);
6881 num_modes += add_cea_modes(connector, drm_edid);
6882 num_modes += add_alternate_cea_modes(connector, drm_edid);
6883 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6884 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6885 num_modes += add_inferred_modes(connector, drm_edid);
6886
6887 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6888 edid_fixup_preferred(connector);
6889
6890 return num_modes;
6891}
6892
6893static void _drm_update_tile_info(struct drm_connector *connector,
6894 const struct drm_edid *drm_edid);
6895
6896static int _drm_edid_connector_property_update(struct drm_connector *connector,
6897 const struct drm_edid *drm_edid)
6898{
6899 struct drm_device *dev = connector->dev;
6900 int ret;
6901
6902 if (connector->edid_blob_ptr) {
6903 const void *old_edid = connector->edid_blob_ptr->data;
6904 size_t old_edid_size = connector->edid_blob_ptr->length;
6905
6906 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6907 connector->epoch_counter++;
6908 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6909 connector->base.id, connector->name,
6910 connector->epoch_counter);
6911 }
6912 }
6913
6914 ret = drm_property_replace_global_blob(dev,
6915 &connector->edid_blob_ptr,
6916 drm_edid ? drm_edid->size : 0,
6917 drm_edid ? drm_edid->edid : NULL,
6918 &connector->base,
6919 dev->mode_config.edid_property);
6920 if (ret) {
6921 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6922 connector->base.id, connector->name, ret);
6923 goto out;
6924 }
6925
6926 ret = drm_object_property_set_value(&connector->base,
6927 dev->mode_config.non_desktop_property,
6928 connector->display_info.non_desktop);
6929 if (ret) {
6930 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6931 connector->base.id, connector->name, ret);
6932 goto out;
6933 }
6934
6935 ret = drm_connector_set_tile_property(connector);
6936 if (ret) {
6937 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6938 connector->base.id, connector->name, ret);
6939 goto out;
6940 }
6941
6942out:
6943 return ret;
6944}
6945
6946/* For sysfs edid show implementation */
6947ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
6948 char *buf, loff_t off, size_t count)
6949{
6950 const void *edid;
6951 size_t size;
6952 ssize_t ret = 0;
6953
6954 mutex_lock(&connector->dev->mode_config.mutex);
6955
6956 if (!connector->edid_blob_ptr)
6957 goto unlock;
6958
6959 edid = connector->edid_blob_ptr->data;
6960 size = connector->edid_blob_ptr->length;
6961 if (!edid)
6962 goto unlock;
6963
6964 if (off >= size)
6965 goto unlock;
6966
6967 if (off + count > size)
6968 count = size - off;
6969
6970 memcpy(buf, edid + off, count);
6971
6972 ret = count;
6973unlock:
6974 mutex_unlock(&connector->dev->mode_config.mutex);
6975
6976 return ret;
6977}
6978
6979/**
6980 * drm_edid_connector_update - Update connector information from EDID
6981 * @connector: Connector
6982 * @drm_edid: EDID
6983 *
6984 * Update the connector display info, ELD, HDR metadata, relevant properties,
6985 * etc. from the passed in EDID.
6986 *
6987 * If EDID is NULL, reset the information.
6988 *
6989 * Must be called before calling drm_edid_connector_add_modes().
6990 *
6991 * Return: 0 on success, negative error on errors.
6992 */
6993int drm_edid_connector_update(struct drm_connector *connector,
6994 const struct drm_edid *drm_edid)
6995{
6996 update_display_info(connector, drm_edid);
6997
6998 _drm_update_tile_info(connector, drm_edid);
6999
7000 return _drm_edid_connector_property_update(connector, drm_edid);
7001}
7002EXPORT_SYMBOL(drm_edid_connector_update);
7003
7004/**
7005 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7006 * @connector: Connector
7007 *
7008 * Add the modes from the previously updated EDID property to the connector
7009 * probed modes list.
7010 *
7011 * drm_edid_connector_update() must have been called before this to update the
7012 * EDID property.
7013 *
7014 * Return: The number of modes added, or 0 if we couldn't find any.
7015 */
7016int drm_edid_connector_add_modes(struct drm_connector *connector)
7017{
7018 const struct drm_edid *drm_edid = NULL;
7019 int count;
7020
7021 if (connector->edid_blob_ptr)
7022 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7023 connector->edid_blob_ptr->length);
7024
7025 count = _drm_edid_connector_add_modes(connector, drm_edid);
7026
7027 drm_edid_free(drm_edid);
7028
7029 return count;
7030}
7031EXPORT_SYMBOL(drm_edid_connector_add_modes);
7032
7033/**
7034 * drm_connector_update_edid_property - update the edid property of a connector
7035 * @connector: drm connector
7036 * @edid: new value of the edid property
7037 *
7038 * This function creates a new blob modeset object and assigns its id to the
7039 * connector's edid property.
7040 * Since we also parse tile information from EDID's displayID block, we also
7041 * set the connector's tile property here. See drm_connector_set_tile_property()
7042 * for more details.
7043 *
7044 * This function is deprecated. Use drm_edid_connector_update() instead.
7045 *
7046 * Returns:
7047 * Zero on success, negative errno on failure.
7048 */
7049int drm_connector_update_edid_property(struct drm_connector *connector,
7050 const struct edid *edid)
7051{
7052 struct drm_edid drm_edid;
7053
7054 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
7055}
7056EXPORT_SYMBOL(drm_connector_update_edid_property);
7057
7058/**
7059 * drm_add_edid_modes - add modes from EDID data, if available
7060 * @connector: connector we're probing
7061 * @edid: EDID data
7062 *
7063 * Add the specified modes to the connector's mode list. Also fills out the
7064 * &drm_display_info structure and ELD in @connector with any information which
7065 * can be derived from the edid.
7066 *
7067 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
7068 *
7069 * Return: The number of modes added or 0 if we couldn't find any.
7070 */
7071int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7072{
7073 struct drm_edid _drm_edid;
7074 const struct drm_edid *drm_edid;
7075
7076 if (edid && !drm_edid_is_valid(edid)) {
7077 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7078 connector->base.id, connector->name);
7079 edid = NULL;
7080 }
7081
7082 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7083
7084 update_display_info(connector, drm_edid);
7085
7086 return _drm_edid_connector_add_modes(connector, drm_edid);
7087}
7088EXPORT_SYMBOL(drm_add_edid_modes);
7089
7090/**
7091 * drm_add_modes_noedid - add modes for the connectors without EDID
7092 * @connector: connector we're probing
7093 * @hdisplay: the horizontal display limit
7094 * @vdisplay: the vertical display limit
7095 *
7096 * Add the specified modes to the connector's mode list. Only when the
7097 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7098 *
7099 * Return: The number of modes added or 0 if we couldn't find any.
7100 */
7101int drm_add_modes_noedid(struct drm_connector *connector,
7102 int hdisplay, int vdisplay)
7103{
7104 int i, count, num_modes = 0;
7105 struct drm_display_mode *mode;
7106 struct drm_device *dev = connector->dev;
7107
7108 count = ARRAY_SIZE(drm_dmt_modes);
7109 if (hdisplay < 0)
7110 hdisplay = 0;
7111 if (vdisplay < 0)
7112 vdisplay = 0;
7113
7114 for (i = 0; i < count; i++) {
7115 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
7116
7117 if (hdisplay && vdisplay) {
7118 /*
7119 * Only when two are valid, they will be used to check
7120 * whether the mode should be added to the mode list of
7121 * the connector.
7122 */
7123 if (ptr->hdisplay > hdisplay ||
7124 ptr->vdisplay > vdisplay)
7125 continue;
7126 }
7127 if (drm_mode_vrefresh(ptr) > 61)
7128 continue;
7129 mode = drm_mode_duplicate(dev, ptr);
7130 if (mode) {
7131 drm_mode_probed_add(connector, mode);
7132 num_modes++;
7133 }
7134 }
7135 return num_modes;
7136}
7137EXPORT_SYMBOL(drm_add_modes_noedid);
7138
7139static bool is_hdmi2_sink(const struct drm_connector *connector)
7140{
7141 /*
7142 * FIXME: sil-sii8620 doesn't have a connector around when
7143 * we need one, so we have to be prepared for a NULL connector.
7144 */
7145 if (!connector)
7146 return true;
7147
7148 return connector->display_info.hdmi.scdc.supported ||
7149 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7150}
7151
7152static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7153 const struct drm_display_mode *mode)
7154{
7155 bool has_hdmi_infoframe = connector ?
7156 connector->display_info.has_hdmi_infoframe : false;
7157
7158 if (!has_hdmi_infoframe)
7159 return 0;
7160
7161 /* No HDMI VIC when signalling 3D video format */
7162 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7163 return 0;
7164
7165 return drm_match_hdmi_mode(mode);
7166}
7167
7168static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7169 const struct drm_display_mode *mode)
7170{
7171 /*
7172 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7173 * we should send its VIC in vendor infoframes, else send the
7174 * VIC in AVI infoframes. Lets check if this mode is present in
7175 * HDMI 1.4b 4K modes
7176 */
7177 if (drm_mode_hdmi_vic(connector, mode))
7178 return 0;
7179
7180 return drm_match_cea_mode(mode);
7181}
7182
7183/*
7184 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7185 * conform to HDMI 1.4.
7186 *
7187 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7188 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7189 *
7190 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7191 * version.
7192 */
7193static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7194{
7195 if (!is_hdmi2_sink(connector) && vic > 64 &&
7196 !cta_vdb_has_vic(connector, vic))
7197 return 0;
7198
7199 return vic;
7200}
7201
7202/**
7203 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7204 * data from a DRM display mode
7205 * @frame: HDMI AVI infoframe
7206 * @connector: the connector
7207 * @mode: DRM display mode
7208 *
7209 * Return: 0 on success or a negative error code on failure.
7210 */
7211int
7212drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7213 const struct drm_connector *connector,
7214 const struct drm_display_mode *mode)
7215{
7216 enum hdmi_picture_aspect picture_aspect;
7217 u8 vic, hdmi_vic;
7218
7219 if (!frame || !mode)
7220 return -EINVAL;
7221
7222 hdmi_avi_infoframe_init(frame);
7223
7224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7225 frame->pixel_repeat = 1;
7226
7227 vic = drm_mode_cea_vic(connector, mode);
7228 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7229
7230 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7231
7232 /*
7233 * As some drivers don't support atomic, we can't use connector state.
7234 * So just initialize the frame with default values, just the same way
7235 * as it's done with other properties here.
7236 */
7237 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7238 frame->itc = 0;
7239
7240 /*
7241 * Populate picture aspect ratio from either
7242 * user input (if specified) or from the CEA/HDMI mode lists.
7243 */
7244 picture_aspect = mode->picture_aspect_ratio;
7245 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7246 if (vic)
7247 picture_aspect = drm_get_cea_aspect_ratio(vic);
7248 else if (hdmi_vic)
7249 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7250 }
7251
7252 /*
7253 * The infoframe can't convey anything but none, 4:3
7254 * and 16:9, so if the user has asked for anything else
7255 * we can only satisfy it by specifying the right VIC.
7256 */
7257 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7258 if (vic) {
7259 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7260 return -EINVAL;
7261 } else if (hdmi_vic) {
7262 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7263 return -EINVAL;
7264 } else {
7265 return -EINVAL;
7266 }
7267
7268 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7269 }
7270
7271 frame->video_code = vic_for_avi_infoframe(connector, vic);
7272 frame->picture_aspect = picture_aspect;
7273 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7274 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7275
7276 return 0;
7277}
7278EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7279
7280/**
7281 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7282 * quantization range information
7283 * @frame: HDMI AVI infoframe
7284 * @connector: the connector
7285 * @mode: DRM display mode
7286 * @rgb_quant_range: RGB quantization range (Q)
7287 */
7288void
7289drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7290 const struct drm_connector *connector,
7291 const struct drm_display_mode *mode,
7292 enum hdmi_quantization_range rgb_quant_range)
7293{
7294 const struct drm_display_info *info = &connector->display_info;
7295
7296 /*
7297 * CEA-861:
7298 * "A Source shall not send a non-zero Q value that does not correspond
7299 * to the default RGB Quantization Range for the transmitted Picture
7300 * unless the Sink indicates support for the Q bit in a Video
7301 * Capabilities Data Block."
7302 *
7303 * HDMI 2.0 recommends sending non-zero Q when it does match the
7304 * default RGB quantization range for the mode, even when QS=0.
7305 */
7306 if (info->rgb_quant_range_selectable ||
7307 rgb_quant_range == drm_default_rgb_quant_range(mode))
7308 frame->quantization_range = rgb_quant_range;
7309 else
7310 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7311
7312 /*
7313 * CEA-861-F:
7314 * "When transmitting any RGB colorimetry, the Source should set the
7315 * YQ-field to match the RGB Quantization Range being transmitted
7316 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7317 * set YQ=1) and the Sink shall ignore the YQ-field."
7318 *
7319 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7320 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7321 * good way to tell which version of CEA-861 the sink supports, so
7322 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7323 * on CEA-861-F.
7324 */
7325 if (!is_hdmi2_sink(connector) ||
7326 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7327 frame->ycc_quantization_range =
7328 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7329 else
7330 frame->ycc_quantization_range =
7331 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7332}
7333EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7334
7335static enum hdmi_3d_structure
7336s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7337{
7338 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7339
7340 switch (layout) {
7341 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7342 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7343 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7344 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7345 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7346 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7347 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7348 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7349 case DRM_MODE_FLAG_3D_L_DEPTH:
7350 return HDMI_3D_STRUCTURE_L_DEPTH;
7351 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7352 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7353 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7354 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7355 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7356 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7357 default:
7358 return HDMI_3D_STRUCTURE_INVALID;
7359 }
7360}
7361
7362/**
7363 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7364 * data from a DRM display mode
7365 * @frame: HDMI vendor infoframe
7366 * @connector: the connector
7367 * @mode: DRM display mode
7368 *
7369 * Note that there's is a need to send HDMI vendor infoframes only when using a
7370 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7371 * function will return -EINVAL, error that can be safely ignored.
7372 *
7373 * Return: 0 on success or a negative error code on failure.
7374 */
7375int
7376drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7377 const struct drm_connector *connector,
7378 const struct drm_display_mode *mode)
7379{
7380 /*
7381 * FIXME: sil-sii8620 doesn't have a connector around when
7382 * we need one, so we have to be prepared for a NULL connector.
7383 */
7384 bool has_hdmi_infoframe = connector ?
7385 connector->display_info.has_hdmi_infoframe : false;
7386 int err;
7387
7388 if (!frame || !mode)
7389 return -EINVAL;
7390
7391 if (!has_hdmi_infoframe)
7392 return -EINVAL;
7393
7394 err = hdmi_vendor_infoframe_init(frame);
7395 if (err < 0)
7396 return err;
7397
7398 /*
7399 * Even if it's not absolutely necessary to send the infoframe
7400 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7401 * know that the sink can handle it. This is based on a
7402 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7403 * have trouble realizing that they should switch from 3D to 2D
7404 * mode if the source simply stops sending the infoframe when
7405 * it wants to switch from 3D to 2D.
7406 */
7407 frame->vic = drm_mode_hdmi_vic(connector, mode);
7408 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7409
7410 return 0;
7411}
7412EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7413
7414static void drm_parse_tiled_block(struct drm_connector *connector,
7415 const struct displayid_block *block)
7416{
7417 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7418 u16 w, h;
7419 u8 tile_v_loc, tile_h_loc;
7420 u8 num_v_tile, num_h_tile;
7421 struct drm_tile_group *tg;
7422
7423 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7424 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7425
7426 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7427 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7428 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7429 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7430
7431 connector->has_tile = true;
7432 if (tile->tile_cap & 0x80)
7433 connector->tile_is_single_monitor = true;
7434
7435 connector->num_h_tile = num_h_tile + 1;
7436 connector->num_v_tile = num_v_tile + 1;
7437 connector->tile_h_loc = tile_h_loc;
7438 connector->tile_v_loc = tile_v_loc;
7439 connector->tile_h_size = w + 1;
7440 connector->tile_v_size = h + 1;
7441
7442 drm_dbg_kms(connector->dev,
7443 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7444 connector->base.id, connector->name,
7445 tile->tile_cap,
7446 connector->tile_h_size, connector->tile_v_size,
7447 connector->num_h_tile, connector->num_v_tile,
7448 connector->tile_h_loc, connector->tile_v_loc,
7449 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7450
7451 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7452 if (!tg)
7453 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7454 if (!tg)
7455 return;
7456
7457 if (connector->tile_group != tg) {
7458 /* if we haven't got a pointer,
7459 take the reference, drop ref to old tile group */
7460 if (connector->tile_group)
7461 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7462 connector->tile_group = tg;
7463 } else {
7464 /* if same tile group, then release the ref we just took. */
7465 drm_mode_put_tile_group(connector->dev, tg);
7466 }
7467}
7468
7469static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7470 const struct displayid_block *block)
7471{
7472 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7473 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7474 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7475 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7476}
7477
7478static void _drm_update_tile_info(struct drm_connector *connector,
7479 const struct drm_edid *drm_edid)
7480{
7481 const struct displayid_block *block;
7482 struct displayid_iter iter;
7483
7484 connector->has_tile = false;
7485
7486 displayid_iter_edid_begin(drm_edid, &iter);
7487 displayid_iter_for_each(block, &iter) {
7488 if (displayid_is_tiled_block(&iter, block))
7489 drm_parse_tiled_block(connector, block);
7490 }
7491 displayid_iter_end(&iter);
7492
7493 if (!connector->has_tile && connector->tile_group) {
7494 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7495 connector->tile_group = NULL;
7496 }
7497}
7498
7499/**
7500 * drm_edid_is_digital - is digital?
7501 * @drm_edid: The EDID
7502 *
7503 * Return true if input is digital.
7504 */
7505bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7506{
7507 return drm_edid && drm_edid->edid &&
7508 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7509}
7510EXPORT_SYMBOL(drm_edid_is_digital);
1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/bitfield.h>
32#include <linux/cec.h>
33#include <linux/hdmi.h>
34#include <linux/i2c.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/slab.h>
39#include <linux/vga_switcheroo.h>
40
41#include <drm/drm_displayid.h>
42#include <drm/drm_drv.h>
43#include <drm/drm_edid.h>
44#include <drm/drm_eld.h>
45#include <drm/drm_encoder.h>
46#include <drm/drm_print.h>
47
48#include "drm_crtc_internal.h"
49#include "drm_internal.h"
50
51static int oui(u8 first, u8 second, u8 third)
52{
53 return (first << 16) | (second << 8) | third;
54}
55
56#define EDID_EST_TIMINGS 16
57#define EDID_STD_TIMINGS 8
58#define EDID_DETAILED_TIMINGS 4
59
60/*
61 * EDID blocks out in the wild have a variety of bugs, try to collect
62 * them here (note that userspace may work around broken monitors first,
63 * but fixes should make their way here so that the kernel "just works"
64 * on as many displays as possible).
65 */
66
67/* First detailed mode wrong, use largest 60Hz mode */
68#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
69/* Reported 135MHz pixel clock is too high, needs adjustment */
70#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
71/* Prefer the largest mode at 75 Hz */
72#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
73/* Detail timing is in cm not mm */
74#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
75/* Detailed timing descriptors have bogus size values, so just take the
76 * maximum size and use that.
77 */
78#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
79/* use +hsync +vsync for detailed mode */
80#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
81/* Force reduced-blanking timings for detailed modes */
82#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
83/* Force 8bpc */
84#define EDID_QUIRK_FORCE_8BPC (1 << 8)
85/* Force 12bpc */
86#define EDID_QUIRK_FORCE_12BPC (1 << 9)
87/* Force 6bpc */
88#define EDID_QUIRK_FORCE_6BPC (1 << 10)
89/* Force 10bpc */
90#define EDID_QUIRK_FORCE_10BPC (1 << 11)
91/* Non desktop display (i.e. HMD) */
92#define EDID_QUIRK_NON_DESKTOP (1 << 12)
93/* Cap the DSC target bitrate to 15bpp */
94#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
95
96#define MICROSOFT_IEEE_OUI 0xca125c
97
98struct detailed_mode_closure {
99 struct drm_connector *connector;
100 const struct drm_edid *drm_edid;
101 bool preferred;
102 int modes;
103};
104
105#define LEVEL_DMT 0
106#define LEVEL_GTF 1
107#define LEVEL_GTF2 2
108#define LEVEL_CVT 3
109
110#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
111{ \
112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 product_id), \
114 .quirks = _quirks \
115}
116
117static const struct edid_quirk {
118 u32 panel_id;
119 u32 quirks;
120} edid_quirk_list[] = {
121 /* Acer AL1706 */
122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
123 /* Acer F51 */
124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
125
126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128
129 /* BenQ GW2765 */
130 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
131
132 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
134
135 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
137
138 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
140
141 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
143
144 /* Belinea 10 15 55 */
145 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
146 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
147
148 /* Envision Peripherals, Inc. EN-7100e */
149 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
150 /* Envision EN2028 */
151 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
152
153 /* Funai Electronics PM36B */
154 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
155 EDID_QUIRK_DETAILED_IN_CM),
156
157 /* LG 27GP950 */
158 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
159
160 /* LG 27GN950 */
161 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
162
163 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
164 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
165
166 /* LG Philips LCD LP154W01-A5 */
167 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
168 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
169
170 /* Samsung SyncMaster 205BW. Note: irony */
171 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
172 /* Samsung SyncMaster 22[5-6]BW */
173 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
174 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
175
176 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
177 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
178
179 /* ViewSonic VA2026w */
180 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
181
182 /* Medion MD 30217 PG */
183 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
184
185 /* Lenovo G50 */
186 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
187
188 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
189 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
190
191 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
192 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
193
194 /* Valve Index Headset */
195 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
212
213 /* HTC Vive and Vive Pro VR Headsets */
214 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
216
217 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
218 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
222
223 /* Windows Mixed Reality Headsets */
224 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
227 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
230
231 /* Sony PlayStation VR Headset */
232 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
233
234 /* Sensics VR Headsets */
235 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
236
237 /* OSVR HDK and HDK2 VR Headsets */
238 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
239 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
240};
241
242/*
243 * Autogenerated from the DMT spec.
244 * This table is copied from xfree86/modes/xf86EdidModes.c.
245 */
246static const struct drm_display_mode drm_dmt_modes[] = {
247 /* 0x01 - 640x350@85Hz */
248 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
249 736, 832, 0, 350, 382, 385, 445, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x02 - 640x400@85Hz */
252 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
253 736, 832, 0, 400, 401, 404, 445, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x03 - 720x400@85Hz */
256 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
257 828, 936, 0, 400, 401, 404, 446, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x04 - 640x480@60Hz */
260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
261 752, 800, 0, 480, 490, 492, 525, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x05 - 640x480@72Hz */
264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
265 704, 832, 0, 480, 489, 492, 520, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
267 /* 0x06 - 640x480@75Hz */
268 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
269 720, 840, 0, 480, 481, 484, 500, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x07 - 640x480@85Hz */
272 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
273 752, 832, 0, 480, 481, 484, 509, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x08 - 800x600@56Hz */
276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
277 896, 1024, 0, 600, 601, 603, 625, 0,
278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x09 - 800x600@60Hz */
280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
281 968, 1056, 0, 600, 601, 605, 628, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x0a - 800x600@72Hz */
284 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
285 976, 1040, 0, 600, 637, 643, 666, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x0b - 800x600@75Hz */
288 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
289 896, 1056, 0, 600, 601, 604, 625, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x0c - 800x600@85Hz */
292 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
293 896, 1048, 0, 600, 601, 604, 631, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x0d - 800x600@120Hz RB */
296 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
297 880, 960, 0, 600, 603, 607, 636, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x0e - 848x480@60Hz */
300 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
301 976, 1088, 0, 480, 486, 494, 517, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x0f - 1024x768@43Hz, interlace */
304 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
305 1208, 1264, 0, 768, 768, 776, 817, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
307 DRM_MODE_FLAG_INTERLACE) },
308 /* 0x10 - 1024x768@60Hz */
309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
310 1184, 1344, 0, 768, 771, 777, 806, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
312 /* 0x11 - 1024x768@70Hz */
313 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
314 1184, 1328, 0, 768, 771, 777, 806, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
316 /* 0x12 - 1024x768@75Hz */
317 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
318 1136, 1312, 0, 768, 769, 772, 800, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 0x13 - 1024x768@85Hz */
321 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
322 1168, 1376, 0, 768, 769, 772, 808, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x14 - 1024x768@120Hz RB */
325 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
326 1104, 1184, 0, 768, 771, 775, 813, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 0x15 - 1152x864@75Hz */
329 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
330 1344, 1600, 0, 864, 865, 868, 900, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 0x55 - 1280x720@60Hz */
333 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
334 1430, 1650, 0, 720, 725, 730, 750, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x16 - 1280x768@60Hz RB */
337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
338 1360, 1440, 0, 768, 771, 778, 790, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
340 /* 0x17 - 1280x768@60Hz */
341 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
342 1472, 1664, 0, 768, 771, 778, 798, 0,
343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x18 - 1280x768@75Hz */
345 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
346 1488, 1696, 0, 768, 771, 778, 805, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x19 - 1280x768@85Hz */
349 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
350 1496, 1712, 0, 768, 771, 778, 809, 0,
351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 0x1a - 1280x768@120Hz RB */
353 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
354 1360, 1440, 0, 768, 771, 778, 813, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
356 /* 0x1b - 1280x800@60Hz RB */
357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
358 1360, 1440, 0, 800, 803, 809, 823, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360 /* 0x1c - 1280x800@60Hz */
361 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
362 1480, 1680, 0, 800, 803, 809, 831, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x1d - 1280x800@75Hz */
365 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
366 1488, 1696, 0, 800, 803, 809, 838, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
368 /* 0x1e - 1280x800@85Hz */
369 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
370 1496, 1712, 0, 800, 803, 809, 843, 0,
371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
372 /* 0x1f - 1280x800@120Hz RB */
373 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
374 1360, 1440, 0, 800, 803, 809, 847, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
376 /* 0x20 - 1280x960@60Hz */
377 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
378 1488, 1800, 0, 960, 961, 964, 1000, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 0x21 - 1280x960@85Hz */
381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
382 1504, 1728, 0, 960, 961, 964, 1011, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x22 - 1280x960@120Hz RB */
385 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
386 1360, 1440, 0, 960, 963, 967, 1017, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 0x23 - 1280x1024@60Hz */
389 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
390 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x24 - 1280x1024@75Hz */
393 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
394 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 0x25 - 1280x1024@85Hz */
397 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
398 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400 /* 0x26 - 1280x1024@120Hz RB */
401 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
402 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
404 /* 0x27 - 1360x768@60Hz */
405 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
406 1536, 1792, 0, 768, 771, 777, 795, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 0x28 - 1360x768@120Hz RB */
409 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
410 1440, 1520, 0, 768, 771, 776, 813, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 0x51 - 1366x768@60Hz */
413 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
414 1579, 1792, 0, 768, 771, 774, 798, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
416 /* 0x56 - 1366x768@60Hz */
417 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
418 1436, 1500, 0, 768, 769, 772, 800, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 0x29 - 1400x1050@60Hz RB */
421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
422 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
424 /* 0x2a - 1400x1050@60Hz */
425 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
426 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x2b - 1400x1050@75Hz */
429 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
430 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x2c - 1400x1050@85Hz */
433 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
434 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 0x2d - 1400x1050@120Hz RB */
437 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
438 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
440 /* 0x2e - 1440x900@60Hz RB */
441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
442 1520, 1600, 0, 900, 903, 909, 926, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 0x2f - 1440x900@60Hz */
445 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
446 1672, 1904, 0, 900, 903, 909, 934, 0,
447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
448 /* 0x30 - 1440x900@75Hz */
449 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
450 1688, 1936, 0, 900, 903, 909, 942, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 0x31 - 1440x900@85Hz */
453 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
454 1696, 1952, 0, 900, 903, 909, 948, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 0x32 - 1440x900@120Hz RB */
457 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
458 1520, 1600, 0, 900, 903, 909, 953, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
460 /* 0x53 - 1600x900@60Hz */
461 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
462 1704, 1800, 0, 900, 901, 904, 1000, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
464 /* 0x33 - 1600x1200@60Hz */
465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 0x34 - 1600x1200@65Hz */
469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
470 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 0x35 - 1600x1200@70Hz */
473 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
474 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 0x36 - 1600x1200@75Hz */
477 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
478 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x37 - 1600x1200@85Hz */
481 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
482 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
484 /* 0x38 - 1600x1200@120Hz RB */
485 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
486 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
488 /* 0x39 - 1680x1050@60Hz RB */
489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
490 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 0x3a - 1680x1050@60Hz */
493 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
494 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
496 /* 0x3b - 1680x1050@75Hz */
497 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
498 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x3c - 1680x1050@85Hz */
501 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
502 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 0x3d - 1680x1050@120Hz RB */
505 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
506 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508 /* 0x3e - 1792x1344@60Hz */
509 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
510 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 0x3f - 1792x1344@75Hz */
513 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
514 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516 /* 0x40 - 1792x1344@120Hz RB */
517 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
518 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
520 /* 0x41 - 1856x1392@60Hz */
521 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
522 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
524 /* 0x42 - 1856x1392@75Hz */
525 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
526 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 0x43 - 1856x1392@120Hz RB */
529 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
530 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
532 /* 0x52 - 1920x1080@60Hz */
533 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
534 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
536 /* 0x44 - 1920x1200@60Hz RB */
537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
538 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
540 /* 0x45 - 1920x1200@60Hz */
541 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
542 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 0x46 - 1920x1200@75Hz */
545 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
546 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 0x47 - 1920x1200@85Hz */
549 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
550 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 0x48 - 1920x1200@120Hz RB */
553 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
554 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
556 /* 0x49 - 1920x1440@60Hz */
557 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
558 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 0x4a - 1920x1440@75Hz */
561 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
562 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 0x4b - 1920x1440@120Hz RB */
565 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
566 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
568 /* 0x54 - 2048x1152@60Hz */
569 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
570 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 0x4c - 2560x1600@60Hz RB */
573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
574 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
576 /* 0x4d - 2560x1600@60Hz */
577 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
578 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 0x4e - 2560x1600@75Hz */
581 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
582 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 0x4f - 2560x1600@85Hz */
585 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
586 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
587 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 0x50 - 2560x1600@120Hz RB */
589 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
590 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
592 /* 0x57 - 4096x2160@60Hz RB */
593 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
594 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
596 /* 0x58 - 4096x2160@59.94Hz RB */
597 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
598 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
600};
601
602/*
603 * These more or less come from the DMT spec. The 720x400 modes are
604 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
605 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
606 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
607 * mode.
608 *
609 * The DMT modes have been fact-checked; the rest are mild guesses.
610 */
611static const struct drm_display_mode edid_est_modes[] = {
612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
613 968, 1056, 0, 600, 601, 605, 628, 0,
614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
616 896, 1024, 0, 600, 601, 603, 625, 0,
617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
619 720, 840, 0, 480, 481, 484, 500, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
622 704, 832, 0, 480, 489, 492, 520, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
625 768, 864, 0, 480, 483, 486, 525, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
628 752, 800, 0, 480, 490, 492, 525, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
631 846, 900, 0, 400, 421, 423, 449, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
633 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
634 846, 900, 0, 400, 412, 414, 449, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
636 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
637 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
640 1136, 1312, 0, 768, 769, 772, 800, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
643 1184, 1328, 0, 768, 771, 777, 806, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
645 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
646 1184, 1344, 0, 768, 771, 777, 806, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
648 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
649 1208, 1264, 0, 768, 768, 776, 817, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
651 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
652 928, 1152, 0, 624, 625, 628, 667, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
655 896, 1056, 0, 600, 601, 604, 625, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
657 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
658 976, 1040, 0, 600, 637, 643, 666, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
660 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
661 1344, 1600, 0, 864, 865, 868, 900, 0,
662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
663};
664
665struct minimode {
666 short w;
667 short h;
668 short r;
669 short rb;
670};
671
672static const struct minimode est3_modes[] = {
673 /* byte 6 */
674 { 640, 350, 85, 0 },
675 { 640, 400, 85, 0 },
676 { 720, 400, 85, 0 },
677 { 640, 480, 85, 0 },
678 { 848, 480, 60, 0 },
679 { 800, 600, 85, 0 },
680 { 1024, 768, 85, 0 },
681 { 1152, 864, 75, 0 },
682 /* byte 7 */
683 { 1280, 768, 60, 1 },
684 { 1280, 768, 60, 0 },
685 { 1280, 768, 75, 0 },
686 { 1280, 768, 85, 0 },
687 { 1280, 960, 60, 0 },
688 { 1280, 960, 85, 0 },
689 { 1280, 1024, 60, 0 },
690 { 1280, 1024, 85, 0 },
691 /* byte 8 */
692 { 1360, 768, 60, 0 },
693 { 1440, 900, 60, 1 },
694 { 1440, 900, 60, 0 },
695 { 1440, 900, 75, 0 },
696 { 1440, 900, 85, 0 },
697 { 1400, 1050, 60, 1 },
698 { 1400, 1050, 60, 0 },
699 { 1400, 1050, 75, 0 },
700 /* byte 9 */
701 { 1400, 1050, 85, 0 },
702 { 1680, 1050, 60, 1 },
703 { 1680, 1050, 60, 0 },
704 { 1680, 1050, 75, 0 },
705 { 1680, 1050, 85, 0 },
706 { 1600, 1200, 60, 0 },
707 { 1600, 1200, 65, 0 },
708 { 1600, 1200, 70, 0 },
709 /* byte 10 */
710 { 1600, 1200, 75, 0 },
711 { 1600, 1200, 85, 0 },
712 { 1792, 1344, 60, 0 },
713 { 1792, 1344, 75, 0 },
714 { 1856, 1392, 60, 0 },
715 { 1856, 1392, 75, 0 },
716 { 1920, 1200, 60, 1 },
717 { 1920, 1200, 60, 0 },
718 /* byte 11 */
719 { 1920, 1200, 75, 0 },
720 { 1920, 1200, 85, 0 },
721 { 1920, 1440, 60, 0 },
722 { 1920, 1440, 75, 0 },
723};
724
725static const struct minimode extra_modes[] = {
726 { 1024, 576, 60, 0 },
727 { 1366, 768, 60, 0 },
728 { 1600, 900, 60, 0 },
729 { 1680, 945, 60, 0 },
730 { 1920, 1080, 60, 0 },
731 { 2048, 1152, 60, 0 },
732 { 2048, 1536, 60, 0 },
733};
734
735/*
736 * From CEA/CTA-861 spec.
737 *
738 * Do not access directly, instead always use cea_mode_for_vic().
739 */
740static const struct drm_display_mode edid_cea_modes_1[] = {
741 /* 1 - 640x480@60Hz 4:3 */
742 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
743 752, 800, 0, 480, 490, 492, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 2 - 720x480@60Hz 4:3 */
747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
748 798, 858, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 3 - 720x480@60Hz 16:9 */
752 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
753 798, 858, 0, 480, 489, 495, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 4 - 1280x720@60Hz 16:9 */
757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
758 1430, 1650, 0, 720, 725, 730, 750, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 5 - 1920x1080i@60Hz 16:9 */
762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
763 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
765 DRM_MODE_FLAG_INTERLACE),
766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 6 - 720(1440)x480i@60Hz 4:3 */
768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 7 - 720(1440)x480i@60Hz 16:9 */
774 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 480, 488, 494, 525, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 8 - 720(1440)x240@60Hz 4:3 */
780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 9 - 720(1440)x240@60Hz 16:9 */
786 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
787 801, 858, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_DBLCLK),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 10 - 2880x480i@60Hz 4:3 */
792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 11 - 2880x480i@60Hz 16:9 */
798 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 480, 488, 494, 525, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_INTERLACE),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 12 - 2880x240@60Hz 4:3 */
804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
805 3204, 3432, 0, 240, 244, 247, 262, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 13 - 2880x240@60Hz 16:9 */
809 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
810 3204, 3432, 0, 240, 244, 247, 262, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 14 - 1440x480@60Hz 4:3 */
814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
815 1596, 1716, 0, 480, 489, 495, 525, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 15 - 1440x480@60Hz 16:9 */
819 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
820 1596, 1716, 0, 480, 489, 495, 525, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 16 - 1920x1080@60Hz 16:9 */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
825 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 17 - 720x576@50Hz 4:3 */
829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
830 796, 864, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 18 - 720x576@50Hz 16:9 */
834 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
835 796, 864, 0, 576, 581, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 19 - 1280x720@50Hz 16:9 */
839 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
840 1760, 1980, 0, 720, 725, 730, 750, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 20 - 1920x1080i@50Hz 16:9 */
844 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
847 DRM_MODE_FLAG_INTERLACE),
848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
849 /* 21 - 720(1440)x576i@50Hz 4:3 */
850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
855 /* 22 - 720(1440)x576i@50Hz 16:9 */
856 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 576, 580, 586, 625, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 23 - 720(1440)x288@50Hz 4:3 */
862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
865 DRM_MODE_FLAG_DBLCLK),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 24 - 720(1440)x288@50Hz 16:9 */
868 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
869 795, 864, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
871 DRM_MODE_FLAG_DBLCLK),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 25 - 2880x576i@50Hz 4:3 */
874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 26 - 2880x576i@50Hz 16:9 */
880 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 576, 580, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
883 DRM_MODE_FLAG_INTERLACE),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 27 - 2880x288@50Hz 4:3 */
886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
887 3180, 3456, 0, 288, 290, 293, 312, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
890 /* 28 - 2880x288@50Hz 16:9 */
891 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
892 3180, 3456, 0, 288, 290, 293, 312, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 29 - 1440x576@50Hz 4:3 */
896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
897 1592, 1728, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
900 /* 30 - 1440x576@50Hz 16:9 */
901 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
902 1592, 1728, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 31 - 1920x1080@50Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 32 - 1920x1080@24Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
912 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 33 - 1920x1080@25Hz 16:9 */
916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
917 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 34 - 1920x1080@30Hz 16:9 */
921 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
922 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 35 - 2880x480@60Hz 4:3 */
926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
927 3192, 3432, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 36 - 2880x480@60Hz 16:9 */
931 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
932 3192, 3432, 0, 480, 489, 495, 525, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 37 - 2880x576@50Hz 4:3 */
936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
937 3184, 3456, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
940 /* 38 - 2880x576@50Hz 16:9 */
941 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
942 3184, 3456, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 39 - 1920x1080i@50Hz 16:9 */
946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
947 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE),
950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 40 - 1920x1080i@100Hz 16:9 */
952 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
953 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
955 DRM_MODE_FLAG_INTERLACE),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 41 - 1280x720@100Hz 16:9 */
958 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
959 1760, 1980, 0, 720, 725, 730, 750, 0,
960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 42 - 720x576@100Hz 4:3 */
963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
964 796, 864, 0, 576, 581, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
967 /* 43 - 720x576@100Hz 16:9 */
968 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
969 796, 864, 0, 576, 581, 586, 625, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 44 - 720(1440)x576i@100Hz 4:3 */
973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 45 - 720(1440)x576i@100Hz 16:9 */
979 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
980 795, 864, 0, 576, 580, 586, 625, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 46 - 1920x1080i@120Hz 16:9 */
985 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
986 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
988 DRM_MODE_FLAG_INTERLACE),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 47 - 1280x720@120Hz 16:9 */
991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
992 1430, 1650, 0, 720, 725, 730, 750, 0,
993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 48 - 720x480@120Hz 4:3 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 49 - 720x480@120Hz 16:9 */
1001 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1002 798, 858, 0, 480, 489, 495, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 50 - 720(1440)x480i@120Hz 4:3 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 51 - 720(1440)x480i@120Hz 16:9 */
1012 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1013 801, 858, 0, 480, 488, 494, 525, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 52 - 720x576@200Hz 4:3 */
1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1019 796, 864, 0, 576, 581, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 53 - 720x576@200Hz 16:9 */
1023 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1024 796, 864, 0, 576, 581, 586, 625, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 54 - 720(1440)x576i@200Hz 4:3 */
1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 55 - 720(1440)x576i@200Hz 16:9 */
1034 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1035 795, 864, 0, 576, 580, 586, 625, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 56 - 720x480@240Hz 4:3 */
1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1041 798, 858, 0, 480, 489, 495, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1044 /* 57 - 720x480@240Hz 16:9 */
1045 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1046 798, 858, 0, 480, 489, 495, 525, 0,
1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 58 - 720(1440)x480i@240Hz 4:3 */
1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1055 /* 59 - 720(1440)x480i@240Hz 16:9 */
1056 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1057 801, 858, 0, 480, 488, 494, 525, 0,
1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1059 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 60 - 1280x720@24Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1063 3080, 3300, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 61 - 1280x720@25Hz 16:9 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1068 3740, 3960, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 62 - 1280x720@30Hz 16:9 */
1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1073 3080, 3300, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 63 - 1920x1080@120Hz 16:9 */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1078 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081 /* 64 - 1920x1080@100Hz 16:9 */
1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1083 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1086 /* 65 - 1280x720@24Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1088 3080, 3300, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 66 - 1280x720@25Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1093 3740, 3960, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 67 - 1280x720@30Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1098 3080, 3300, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 68 - 1280x720@50Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1103 1760, 1980, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 69 - 1280x720@60Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1108 1430, 1650, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 70 - 1280x720@100Hz 64:27 */
1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1113 1760, 1980, 0, 720, 725, 730, 750, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 71 - 1280x720@120Hz 64:27 */
1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1118 1430, 1650, 0, 720, 725, 730, 750, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 72 - 1920x1080@24Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1123 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 73 - 1920x1080@25Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 74 - 1920x1080@30Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 75 - 1920x1080@50Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 76 - 1920x1080@60Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 77 - 1920x1080@100Hz 64:27 */
1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 78 - 1920x1080@120Hz 64:27 */
1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 79 - 1680x720@24Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1158 3080, 3300, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 80 - 1680x720@25Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1163 2948, 3168, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 81 - 1680x720@30Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1168 2420, 2640, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 82 - 1680x720@50Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1173 1980, 2200, 0, 720, 725, 730, 750, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 83 - 1680x720@60Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1178 1980, 2200, 0, 720, 725, 730, 750, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 84 - 1680x720@100Hz 64:27 */
1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1183 1780, 2000, 0, 720, 725, 730, 825, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 85 - 1680x720@120Hz 64:27 */
1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1188 1780, 2000, 0, 720, 725, 730, 825, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 86 - 2560x1080@24Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1193 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 87 - 2560x1080@25Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1198 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 88 - 2560x1080@30Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1203 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 89 - 2560x1080@50Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1208 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 90 - 2560x1080@60Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1213 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 91 - 2560x1080@100Hz 64:27 */
1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1218 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 92 - 2560x1080@120Hz 64:27 */
1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1223 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1226 /* 93 - 3840x2160@24Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1228 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 94 - 3840x2160@25Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 95 - 3840x2160@30Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 96 - 3840x2160@50Hz 16:9 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1246 /* 97 - 3840x2160@60Hz 16:9 */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1251 /* 98 - 4096x2160@24Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1253 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 99 - 4096x2160@25Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 100 - 4096x2160@30Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 101 - 4096x2160@50Hz 256:135 */
1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1268 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1271 /* 102 - 4096x2160@60Hz 256:135 */
1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1273 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1276 /* 103 - 3840x2160@24Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1278 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 104 - 3840x2160@25Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 105 - 3840x2160@30Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 106 - 3840x2160@50Hz 64:27 */
1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1293 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296 /* 107 - 3840x2160@60Hz 64:27 */
1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1298 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301 /* 108 - 1280x720@48Hz 16:9 */
1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1303 2280, 2500, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1306 /* 109 - 1280x720@48Hz 64:27 */
1307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1308 2280, 2500, 0, 720, 725, 730, 750, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311 /* 110 - 1680x720@48Hz 64:27 */
1312 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1313 2530, 2750, 0, 720, 725, 730, 750, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316 /* 111 - 1920x1080@48Hz 16:9 */
1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1321 /* 112 - 1920x1080@48Hz 64:27 */
1322 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1323 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1326 /* 113 - 2560x1080@48Hz 64:27 */
1327 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1328 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1331 /* 114 - 3840x2160@48Hz 16:9 */
1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1336 /* 115 - 4096x2160@48Hz 256:135 */
1337 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1341 /* 116 - 3840x2160@48Hz 64:27 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1343 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1346 /* 117 - 3840x2160@100Hz 16:9 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1351 /* 118 - 3840x2160@120Hz 16:9 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1356 /* 119 - 3840x2160@100Hz 64:27 */
1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1358 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 120 - 3840x2160@120Hz 64:27 */
1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1363 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 121 - 5120x2160@24Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1368 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 122 - 5120x2160@25Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1373 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 123 - 5120x2160@30Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1378 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 124 - 5120x2160@48Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1383 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 125 - 5120x2160@50Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 126 - 5120x2160@60Hz 64:27 */
1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1393 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1396 /* 127 - 5120x2160@100Hz 64:27 */
1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1398 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1401};
1402
1403/*
1404 * From CEA/CTA-861 spec.
1405 *
1406 * Do not access directly, instead always use cea_mode_for_vic().
1407 */
1408static const struct drm_display_mode edid_cea_modes_193[] = {
1409 /* 193 - 5120x2160@120Hz 64:27 */
1410 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1411 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1414 /* 194 - 7680x4320@24Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1416 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 195 - 7680x4320@25Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1421 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 196 - 7680x4320@30Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1426 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 197 - 7680x4320@48Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1431 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 198 - 7680x4320@50Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1436 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 199 - 7680x4320@60Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1441 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 200 - 7680x4320@100Hz 16:9 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1446 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449 /* 201 - 7680x4320@120Hz 16:9 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1451 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1454 /* 202 - 7680x4320@24Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1456 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 203 - 7680x4320@25Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1461 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 204 - 7680x4320@30Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1466 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 205 - 7680x4320@48Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1471 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 206 - 7680x4320@50Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1476 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 207 - 7680x4320@60Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1481 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 208 - 7680x4320@100Hz 64:27 */
1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1486 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 209 - 7680x4320@120Hz 64:27 */
1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1491 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 210 - 10240x4320@24Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1496 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 211 - 10240x4320@25Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1501 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 212 - 10240x4320@30Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1506 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 213 - 10240x4320@48Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1511 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 214 - 10240x4320@50Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1516 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 215 - 10240x4320@60Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 216 - 10240x4320@100Hz 64:27 */
1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1526 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529 /* 217 - 10240x4320@120Hz 64:27 */
1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1531 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1534 /* 218 - 4096x2160@100Hz 256:135 */
1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1536 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1539 /* 219 - 4096x2160@120Hz 256:135 */
1540 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1541 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1544};
1545
1546/*
1547 * HDMI 1.4 4k modes. Index using the VIC.
1548 */
1549static const struct drm_display_mode edid_4k_modes[] = {
1550 /* 0 - dummy, VICs start at 1 */
1551 { },
1552 /* 1 - 3840x2160@30Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4016, 4104, 4400, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1558 /* 2 - 3840x2160@25Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 4896, 4984, 5280, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1564 /* 3 - 3840x2160@24Hz */
1565 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 3840, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1570 /* 4 - 4096x2160@24Hz (SMPTE) */
1571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1572 4096, 5116, 5204, 5500, 0,
1573 2160, 2168, 2178, 2250, 0,
1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1575 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1576};
1577
1578/*** DDC fetch and block validation ***/
1579
1580/*
1581 * The opaque EDID type, internal to drm_edid.c.
1582 */
1583struct drm_edid {
1584 /* Size allocated for edid */
1585 size_t size;
1586 const struct edid *edid;
1587};
1588
1589static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1590
1591static int edid_hfeeodb_block_count(const struct edid *edid)
1592{
1593 int eeodb = edid_hfeeodb_extension_block_count(edid);
1594
1595 return eeodb ? eeodb + 1 : 0;
1596}
1597
1598static int edid_extension_block_count(const struct edid *edid)
1599{
1600 return edid->extensions;
1601}
1602
1603static int edid_block_count(const struct edid *edid)
1604{
1605 return edid_extension_block_count(edid) + 1;
1606}
1607
1608static int edid_size_by_blocks(int num_blocks)
1609{
1610 return num_blocks * EDID_LENGTH;
1611}
1612
1613static int edid_size(const struct edid *edid)
1614{
1615 return edid_size_by_blocks(edid_block_count(edid));
1616}
1617
1618static const void *edid_block_data(const struct edid *edid, int index)
1619{
1620 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1621
1622 return edid + index;
1623}
1624
1625static const void *edid_extension_block_data(const struct edid *edid, int index)
1626{
1627 return edid_block_data(edid, index + 1);
1628}
1629
1630/* EDID block count indicated in EDID, may exceed allocated size */
1631static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1632{
1633 int num_blocks;
1634
1635 /* Starting point */
1636 num_blocks = edid_block_count(drm_edid->edid);
1637
1638 /* HF-EEODB override */
1639 if (drm_edid->size >= edid_size_by_blocks(2)) {
1640 int eeodb;
1641
1642 /*
1643 * Note: HF-EEODB may specify a smaller extension count than the
1644 * regular one. Unlike in buffer allocation, here we can use it.
1645 */
1646 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1647 if (eeodb)
1648 num_blocks = eeodb;
1649 }
1650
1651 return num_blocks;
1652}
1653
1654/* EDID block count, limited by allocated size */
1655static int drm_edid_block_count(const struct drm_edid *drm_edid)
1656{
1657 /* Limit by allocated size */
1658 return min(__drm_edid_block_count(drm_edid),
1659 (int)drm_edid->size / EDID_LENGTH);
1660}
1661
1662/* EDID extension block count, limited by allocated size */
1663static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1664{
1665 return drm_edid_block_count(drm_edid) - 1;
1666}
1667
1668static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1669{
1670 return edid_block_data(drm_edid->edid, index);
1671}
1672
1673static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1674 int index)
1675{
1676 return edid_extension_block_data(drm_edid->edid, index);
1677}
1678
1679/*
1680 * Initializer helper for legacy interfaces, where we have no choice but to
1681 * trust edid size. Not for general purpose use.
1682 */
1683static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1684 const struct edid *edid)
1685{
1686 if (!edid)
1687 return NULL;
1688
1689 memset(drm_edid, 0, sizeof(*drm_edid));
1690
1691 drm_edid->edid = edid;
1692 drm_edid->size = edid_size(edid);
1693
1694 return drm_edid;
1695}
1696
1697/*
1698 * EDID base and extension block iterator.
1699 *
1700 * struct drm_edid_iter iter;
1701 * const u8 *block;
1702 *
1703 * drm_edid_iter_begin(drm_edid, &iter);
1704 * drm_edid_iter_for_each(block, &iter) {
1705 * // do stuff with block
1706 * }
1707 * drm_edid_iter_end(&iter);
1708 */
1709struct drm_edid_iter {
1710 const struct drm_edid *drm_edid;
1711
1712 /* Current block index. */
1713 int index;
1714};
1715
1716static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1717 struct drm_edid_iter *iter)
1718{
1719 memset(iter, 0, sizeof(*iter));
1720
1721 iter->drm_edid = drm_edid;
1722}
1723
1724static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1725{
1726 const void *block = NULL;
1727
1728 if (!iter->drm_edid)
1729 return NULL;
1730
1731 if (iter->index < drm_edid_block_count(iter->drm_edid))
1732 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1733
1734 return block;
1735}
1736
1737#define drm_edid_iter_for_each(__block, __iter) \
1738 while (((__block) = __drm_edid_iter_next(__iter)))
1739
1740static void drm_edid_iter_end(struct drm_edid_iter *iter)
1741{
1742 memset(iter, 0, sizeof(*iter));
1743}
1744
1745static const u8 edid_header[] = {
1746 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1747};
1748
1749static void edid_header_fix(void *edid)
1750{
1751 memcpy(edid, edid_header, sizeof(edid_header));
1752}
1753
1754/**
1755 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1756 * @_edid: pointer to raw base EDID block
1757 *
1758 * Sanity check the header of the base EDID block.
1759 *
1760 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1761 */
1762int drm_edid_header_is_valid(const void *_edid)
1763{
1764 const struct edid *edid = _edid;
1765 int i, score = 0;
1766
1767 for (i = 0; i < sizeof(edid_header); i++) {
1768 if (edid->header[i] == edid_header[i])
1769 score++;
1770 }
1771
1772 return score;
1773}
1774EXPORT_SYMBOL(drm_edid_header_is_valid);
1775
1776static int edid_fixup __read_mostly = 6;
1777module_param_named(edid_fixup, edid_fixup, int, 0400);
1778MODULE_PARM_DESC(edid_fixup,
1779 "Minimum number of valid EDID header bytes (0-8, default 6)");
1780
1781static int edid_block_compute_checksum(const void *_block)
1782{
1783 const u8 *block = _block;
1784 int i;
1785 u8 csum = 0, crc = 0;
1786
1787 for (i = 0; i < EDID_LENGTH - 1; i++)
1788 csum += block[i];
1789
1790 crc = 0x100 - csum;
1791
1792 return crc;
1793}
1794
1795static int edid_block_get_checksum(const void *_block)
1796{
1797 const struct edid *block = _block;
1798
1799 return block->checksum;
1800}
1801
1802static int edid_block_tag(const void *_block)
1803{
1804 const u8 *block = _block;
1805
1806 return block[0];
1807}
1808
1809static bool edid_block_is_zero(const void *edid)
1810{
1811 return !memchr_inv(edid, 0, EDID_LENGTH);
1812}
1813
1814/**
1815 * drm_edid_are_equal - compare two edid blobs.
1816 * @edid1: pointer to first blob
1817 * @edid2: pointer to second blob
1818 * This helper can be used during probing to determine if
1819 * edid had changed.
1820 */
1821bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1822{
1823 int edid1_len, edid2_len;
1824 bool edid1_present = edid1 != NULL;
1825 bool edid2_present = edid2 != NULL;
1826
1827 if (edid1_present != edid2_present)
1828 return false;
1829
1830 if (edid1) {
1831 edid1_len = edid_size(edid1);
1832 edid2_len = edid_size(edid2);
1833
1834 if (edid1_len != edid2_len)
1835 return false;
1836
1837 if (memcmp(edid1, edid2, edid1_len))
1838 return false;
1839 }
1840
1841 return true;
1842}
1843EXPORT_SYMBOL(drm_edid_are_equal);
1844
1845enum edid_block_status {
1846 EDID_BLOCK_OK = 0,
1847 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_NULL,
1849 EDID_BLOCK_ZERO,
1850 EDID_BLOCK_HEADER_CORRUPT,
1851 EDID_BLOCK_HEADER_REPAIR,
1852 EDID_BLOCK_HEADER_FIXED,
1853 EDID_BLOCK_CHECKSUM,
1854 EDID_BLOCK_VERSION,
1855};
1856
1857static enum edid_block_status edid_block_check(const void *_block,
1858 bool is_base_block)
1859{
1860 const struct edid *block = _block;
1861
1862 if (!block)
1863 return EDID_BLOCK_NULL;
1864
1865 if (is_base_block) {
1866 int score = drm_edid_header_is_valid(block);
1867
1868 if (score < clamp(edid_fixup, 0, 8)) {
1869 if (edid_block_is_zero(block))
1870 return EDID_BLOCK_ZERO;
1871 else
1872 return EDID_BLOCK_HEADER_CORRUPT;
1873 }
1874
1875 if (score < 8)
1876 return EDID_BLOCK_HEADER_REPAIR;
1877 }
1878
1879 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1880 if (edid_block_is_zero(block))
1881 return EDID_BLOCK_ZERO;
1882 else
1883 return EDID_BLOCK_CHECKSUM;
1884 }
1885
1886 if (is_base_block) {
1887 if (block->version != 1)
1888 return EDID_BLOCK_VERSION;
1889 }
1890
1891 return EDID_BLOCK_OK;
1892}
1893
1894static bool edid_block_status_valid(enum edid_block_status status, int tag)
1895{
1896 return status == EDID_BLOCK_OK ||
1897 status == EDID_BLOCK_HEADER_FIXED ||
1898 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899}
1900
1901static bool edid_block_valid(const void *block, bool base)
1902{
1903 return edid_block_status_valid(edid_block_check(block, base),
1904 edid_block_tag(block));
1905}
1906
1907static void edid_block_status_print(enum edid_block_status status,
1908 const struct edid *block,
1909 int block_num)
1910{
1911 switch (status) {
1912 case EDID_BLOCK_OK:
1913 break;
1914 case EDID_BLOCK_READ_FAIL:
1915 pr_debug("EDID block %d read failed\n", block_num);
1916 break;
1917 case EDID_BLOCK_NULL:
1918 pr_debug("EDID block %d pointer is NULL\n", block_num);
1919 break;
1920 case EDID_BLOCK_ZERO:
1921 pr_notice("EDID block %d is all zeroes\n", block_num);
1922 break;
1923 case EDID_BLOCK_HEADER_CORRUPT:
1924 pr_notice("EDID has corrupt header\n");
1925 break;
1926 case EDID_BLOCK_HEADER_REPAIR:
1927 pr_debug("EDID corrupt header needs repair\n");
1928 break;
1929 case EDID_BLOCK_HEADER_FIXED:
1930 pr_debug("EDID corrupt header fixed\n");
1931 break;
1932 case EDID_BLOCK_CHECKSUM:
1933 if (edid_block_status_valid(status, edid_block_tag(block))) {
1934 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1935 block_num, edid_block_tag(block),
1936 edid_block_compute_checksum(block));
1937 } else {
1938 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1939 block_num, edid_block_tag(block),
1940 edid_block_compute_checksum(block));
1941 }
1942 break;
1943 case EDID_BLOCK_VERSION:
1944 pr_notice("EDID has major version %d, instead of 1\n",
1945 block->version);
1946 break;
1947 default:
1948 WARN(1, "EDID block %d unknown edid block status code %d\n",
1949 block_num, status);
1950 break;
1951 }
1952}
1953
1954static void edid_block_dump(const char *level, const void *block, int block_num)
1955{
1956 enum edid_block_status status;
1957 char prefix[20];
1958
1959 status = edid_block_check(block, block_num == 0);
1960 if (status == EDID_BLOCK_ZERO)
1961 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1962 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1963 sprintf(prefix, "\t[%02x] BAD ", block_num);
1964 else
1965 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1966
1967 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1968 block, EDID_LENGTH, false);
1969}
1970
1971/**
1972 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1973 * @_block: pointer to raw EDID block
1974 * @block_num: type of block to validate (0 for base, extension otherwise)
1975 * @print_bad_edid: if true, dump bad EDID blocks to the console
1976 * @edid_corrupt: if true, the header or checksum is invalid
1977 *
1978 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * the console.
1980 *
1981 * Return: True if the block is valid, false otherwise.
1982 */
1983bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 bool *edid_corrupt)
1985{
1986 struct edid *block = (struct edid *)_block;
1987 enum edid_block_status status;
1988 bool is_base_block = block_num == 0;
1989 bool valid;
1990
1991 if (WARN_ON(!block))
1992 return false;
1993
1994 status = edid_block_check(block, is_base_block);
1995 if (status == EDID_BLOCK_HEADER_REPAIR) {
1996 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1997 edid_header_fix(block);
1998
1999 /* Retry with fixed header, update status if that worked. */
2000 status = edid_block_check(block, is_base_block);
2001 if (status == EDID_BLOCK_OK)
2002 status = EDID_BLOCK_HEADER_FIXED;
2003 }
2004
2005 if (edid_corrupt) {
2006 /*
2007 * Unknown major version isn't corrupt but we can't use it. Only
2008 * the base block can reset edid_corrupt to false.
2009 */
2010 if (is_base_block &&
2011 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2012 *edid_corrupt = false;
2013 else if (status != EDID_BLOCK_OK)
2014 *edid_corrupt = true;
2015 }
2016
2017 edid_block_status_print(status, block, block_num);
2018
2019 /* Determine whether we can use this block with this status. */
2020 valid = edid_block_status_valid(status, edid_block_tag(block));
2021
2022 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2023 pr_notice("Raw EDID:\n");
2024 edid_block_dump(KERN_NOTICE, block, block_num);
2025 }
2026
2027 return valid;
2028}
2029EXPORT_SYMBOL(drm_edid_block_valid);
2030
2031/**
2032 * drm_edid_is_valid - sanity check EDID data
2033 * @edid: EDID data
2034 *
2035 * Sanity-check an entire EDID record (including extensions)
2036 *
2037 * Return: True if the EDID data is valid, false otherwise.
2038 */
2039bool drm_edid_is_valid(struct edid *edid)
2040{
2041 int i;
2042
2043 if (!edid)
2044 return false;
2045
2046 for (i = 0; i < edid_block_count(edid); i++) {
2047 void *block = (void *)edid_block_data(edid, i);
2048
2049 if (!drm_edid_block_valid(block, i, true, NULL))
2050 return false;
2051 }
2052
2053 return true;
2054}
2055EXPORT_SYMBOL(drm_edid_is_valid);
2056
2057/**
2058 * drm_edid_valid - sanity check EDID data
2059 * @drm_edid: EDID data
2060 *
2061 * Sanity check an EDID. Cross check block count against allocated size and
2062 * checksum the blocks.
2063 *
2064 * Return: True if the EDID data is valid, false otherwise.
2065 */
2066bool drm_edid_valid(const struct drm_edid *drm_edid)
2067{
2068 int i;
2069
2070 if (!drm_edid)
2071 return false;
2072
2073 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 return false;
2075
2076 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2077 const void *block = drm_edid_block_data(drm_edid, i);
2078
2079 if (!edid_block_valid(block, i == 0))
2080 return false;
2081 }
2082
2083 return true;
2084}
2085EXPORT_SYMBOL(drm_edid_valid);
2086
2087static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2088 size_t *alloc_size)
2089{
2090 struct edid *new;
2091 int i, valid_blocks = 0;
2092
2093 /*
2094 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2095 * back to regular extension count here. We don't want to start
2096 * modifying the HF-EEODB extension too.
2097 */
2098 for (i = 0; i < edid_block_count(edid); i++) {
2099 const void *src_block = edid_block_data(edid, i);
2100
2101 if (edid_block_valid(src_block, i == 0)) {
2102 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2103
2104 memmove(dst_block, src_block, EDID_LENGTH);
2105 valid_blocks++;
2106 }
2107 }
2108
2109 /* We already trusted the base block to be valid here... */
2110 if (WARN_ON(!valid_blocks)) {
2111 kfree(edid);
2112 return NULL;
2113 }
2114
2115 edid->extensions = valid_blocks - 1;
2116 edid->checksum = edid_block_compute_checksum(edid);
2117
2118 *alloc_size = edid_size_by_blocks(valid_blocks);
2119
2120 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2121 if (!new)
2122 kfree(edid);
2123
2124 return new;
2125}
2126
2127#define DDC_SEGMENT_ADDR 0x30
2128/**
2129 * drm_do_probe_ddc_edid() - get EDID information via I2C
2130 * @data: I2C device adapter
2131 * @buf: EDID data buffer to be filled
2132 * @block: 128 byte EDID block to start fetching from
2133 * @len: EDID data buffer length to fetch
2134 *
2135 * Try to fetch EDID information by calling I2C driver functions.
2136 *
2137 * Return: 0 on success or -1 on failure.
2138 */
2139static int
2140drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2141{
2142 struct i2c_adapter *adapter = data;
2143 unsigned char start = block * EDID_LENGTH;
2144 unsigned char segment = block >> 1;
2145 unsigned char xfers = segment ? 3 : 2;
2146 int ret, retries = 5;
2147
2148 /*
2149 * The core I2C driver will automatically retry the transfer if the
2150 * adapter reports EAGAIN. However, we find that bit-banging transfers
2151 * are susceptible to errors under a heavily loaded machine and
2152 * generate spurious NAKs and timeouts. Retrying the transfer
2153 * of the individual block a few times seems to overcome this.
2154 */
2155 do {
2156 struct i2c_msg msgs[] = {
2157 {
2158 .addr = DDC_SEGMENT_ADDR,
2159 .flags = 0,
2160 .len = 1,
2161 .buf = &segment,
2162 }, {
2163 .addr = DDC_ADDR,
2164 .flags = 0,
2165 .len = 1,
2166 .buf = &start,
2167 }, {
2168 .addr = DDC_ADDR,
2169 .flags = I2C_M_RD,
2170 .len = len,
2171 .buf = buf,
2172 }
2173 };
2174
2175 /*
2176 * Avoid sending the segment addr to not upset non-compliant
2177 * DDC monitors.
2178 */
2179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2180
2181 if (ret == -ENXIO) {
2182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2183 adapter->name);
2184 break;
2185 }
2186 } while (ret != xfers && --retries);
2187
2188 return ret == xfers ? 0 : -1;
2189}
2190
2191static void connector_bad_edid(struct drm_connector *connector,
2192 const struct edid *edid, int num_blocks)
2193{
2194 int i;
2195 u8 last_block;
2196
2197 /*
2198 * 0x7e in the EDID is the number of extension blocks. The EDID
2199 * is 1 (base block) + num_ext_blocks big. That means we can think
2200 * of 0x7e in the EDID of the _index_ of the last block in the
2201 * combined chunk of memory.
2202 */
2203 last_block = edid->extensions;
2204
2205 /* Calculate real checksum for the last edid extension block data */
2206 if (last_block < num_blocks)
2207 connector->real_edid_checksum =
2208 edid_block_compute_checksum(edid + last_block);
2209
2210 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 return;
2212
2213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2214 connector->base.id, connector->name);
2215 for (i = 0; i < num_blocks; i++)
2216 edid_block_dump(KERN_DEBUG, edid + i, i);
2217}
2218
2219/* Get override or firmware EDID */
2220static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2221{
2222 const struct drm_edid *override = NULL;
2223
2224 mutex_lock(&connector->edid_override_mutex);
2225
2226 if (connector->edid_override)
2227 override = drm_edid_dup(connector->edid_override);
2228
2229 mutex_unlock(&connector->edid_override_mutex);
2230
2231 if (!override)
2232 override = drm_edid_load_firmware(connector);
2233
2234 return IS_ERR(override) ? NULL : override;
2235}
2236
2237/* For debugfs edid_override implementation */
2238int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2239{
2240 const struct drm_edid *drm_edid;
2241
2242 mutex_lock(&connector->edid_override_mutex);
2243
2244 drm_edid = connector->edid_override;
2245 if (drm_edid)
2246 seq_write(m, drm_edid->edid, drm_edid->size);
2247
2248 mutex_unlock(&connector->edid_override_mutex);
2249
2250 return 0;
2251}
2252
2253/* For debugfs edid_override implementation */
2254int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 size_t size)
2256{
2257 const struct drm_edid *drm_edid;
2258
2259 drm_edid = drm_edid_alloc(edid, size);
2260 if (!drm_edid_valid(drm_edid)) {
2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2262 connector->base.id, connector->name);
2263 drm_edid_free(drm_edid);
2264 return -EINVAL;
2265 }
2266
2267 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2268 connector->base.id, connector->name);
2269
2270 mutex_lock(&connector->edid_override_mutex);
2271
2272 drm_edid_free(connector->edid_override);
2273 connector->edid_override = drm_edid;
2274
2275 mutex_unlock(&connector->edid_override_mutex);
2276
2277 return 0;
2278}
2279
2280/* For debugfs edid_override implementation */
2281int drm_edid_override_reset(struct drm_connector *connector)
2282{
2283 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2284 connector->base.id, connector->name);
2285
2286 mutex_lock(&connector->edid_override_mutex);
2287
2288 drm_edid_free(connector->edid_override);
2289 connector->edid_override = NULL;
2290
2291 mutex_unlock(&connector->edid_override_mutex);
2292
2293 return 0;
2294}
2295
2296/**
2297 * drm_edid_override_connector_update - add modes from override/firmware EDID
2298 * @connector: connector we're probing
2299 *
2300 * Add modes from the override/firmware EDID, if available. Only to be used from
2301 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2302 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * skipped.
2304 *
2305 * Return: The number of modes added or 0 if we couldn't find any.
2306 */
2307int drm_edid_override_connector_update(struct drm_connector *connector)
2308{
2309 const struct drm_edid *override;
2310 int num_modes = 0;
2311
2312 override = drm_edid_override_get(connector);
2313 if (override) {
2314 if (drm_edid_connector_update(connector, override) == 0)
2315 num_modes = drm_edid_connector_add_modes(connector);
2316
2317 drm_edid_free(override);
2318
2319 drm_dbg_kms(connector->dev,
2320 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2321 connector->base.id, connector->name, num_modes);
2322 }
2323
2324 return num_modes;
2325}
2326EXPORT_SYMBOL(drm_edid_override_connector_update);
2327
2328typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2329
2330static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2331 read_block_fn read_block,
2332 void *context)
2333{
2334 enum edid_block_status status;
2335 bool is_base_block = block_num == 0;
2336 int try;
2337
2338 for (try = 0; try < 4; try++) {
2339 if (read_block(context, block, block_num, EDID_LENGTH))
2340 return EDID_BLOCK_READ_FAIL;
2341
2342 status = edid_block_check(block, is_base_block);
2343 if (status == EDID_BLOCK_HEADER_REPAIR) {
2344 edid_header_fix(block);
2345
2346 /* Retry with fixed header, update status if that worked. */
2347 status = edid_block_check(block, is_base_block);
2348 if (status == EDID_BLOCK_OK)
2349 status = EDID_BLOCK_HEADER_FIXED;
2350 }
2351
2352 if (edid_block_status_valid(status, edid_block_tag(block)))
2353 break;
2354
2355 /* Fail early for unrepairable base block all zeros. */
2356 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2357 break;
2358 }
2359
2360 return status;
2361}
2362
2363static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2364 read_block_fn read_block, void *context,
2365 size_t *size)
2366{
2367 enum edid_block_status status;
2368 int i, num_blocks, invalid_blocks = 0;
2369 const struct drm_edid *override;
2370 struct edid *edid, *new;
2371 size_t alloc_size = EDID_LENGTH;
2372
2373 override = drm_edid_override_get(connector);
2374 if (override) {
2375 alloc_size = override->size;
2376 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2377 drm_edid_free(override);
2378 if (!edid)
2379 return NULL;
2380 goto ok;
2381 }
2382
2383 edid = kmalloc(alloc_size, GFP_KERNEL);
2384 if (!edid)
2385 return NULL;
2386
2387 status = edid_block_read(edid, 0, read_block, context);
2388
2389 edid_block_status_print(status, edid, 0);
2390
2391 if (status == EDID_BLOCK_READ_FAIL)
2392 goto fail;
2393
2394 /* FIXME: Clarify what a corrupt EDID actually means. */
2395 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2396 connector->edid_corrupt = false;
2397 else
2398 connector->edid_corrupt = true;
2399
2400 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2401 if (status == EDID_BLOCK_ZERO)
2402 connector->null_edid_counter++;
2403
2404 connector_bad_edid(connector, edid, 1);
2405 goto fail;
2406 }
2407
2408 if (!edid_extension_block_count(edid))
2409 goto ok;
2410
2411 alloc_size = edid_size(edid);
2412 new = krealloc(edid, alloc_size, GFP_KERNEL);
2413 if (!new)
2414 goto fail;
2415 edid = new;
2416
2417 num_blocks = edid_block_count(edid);
2418 for (i = 1; i < num_blocks; i++) {
2419 void *block = (void *)edid_block_data(edid, i);
2420
2421 status = edid_block_read(block, i, read_block, context);
2422
2423 edid_block_status_print(status, block, i);
2424
2425 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2426 if (status == EDID_BLOCK_READ_FAIL)
2427 goto fail;
2428 invalid_blocks++;
2429 } else if (i == 1) {
2430 /*
2431 * If the first EDID extension is a CTA extension, and
2432 * the first Data Block is HF-EEODB, override the
2433 * extension block count.
2434 *
2435 * Note: HF-EEODB could specify a smaller extension
2436 * count too, but we can't risk allocating a smaller
2437 * amount.
2438 */
2439 int eeodb = edid_hfeeodb_block_count(edid);
2440
2441 if (eeodb > num_blocks) {
2442 num_blocks = eeodb;
2443 alloc_size = edid_size_by_blocks(num_blocks);
2444 new = krealloc(edid, alloc_size, GFP_KERNEL);
2445 if (!new)
2446 goto fail;
2447 edid = new;
2448 }
2449 }
2450 }
2451
2452 if (invalid_blocks) {
2453 connector_bad_edid(connector, edid, num_blocks);
2454
2455 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2456 }
2457
2458ok:
2459 if (size)
2460 *size = alloc_size;
2461
2462 return edid;
2463
2464fail:
2465 kfree(edid);
2466 return NULL;
2467}
2468
2469/**
2470 * drm_do_get_edid - get EDID data using a custom EDID block read function
2471 * @connector: connector we're probing
2472 * @read_block: EDID block read function
2473 * @context: private data passed to the block read function
2474 *
2475 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2476 * exposes a different interface to read EDID blocks this function can be used
2477 * to get EDID data using a custom block read function.
2478 *
2479 * As in the general case the DDC bus is accessible by the kernel at the I2C
2480 * level, drivers must make all reasonable efforts to expose it as an I2C
2481 * adapter and use drm_get_edid() instead of abusing this function.
2482 *
2483 * The EDID may be overridden using debugfs override_edid or firmware EDID
2484 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2485 * order. Having either of them bypasses actual EDID reads.
2486 *
2487 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2488 */
2489struct edid *drm_do_get_edid(struct drm_connector *connector,
2490 read_block_fn read_block,
2491 void *context)
2492{
2493 return _drm_do_get_edid(connector, read_block, context, NULL);
2494}
2495EXPORT_SYMBOL_GPL(drm_do_get_edid);
2496
2497/**
2498 * drm_edid_raw - Get a pointer to the raw EDID data.
2499 * @drm_edid: drm_edid container
2500 *
2501 * Get a pointer to the raw EDID data.
2502 *
2503 * This is for transition only. Avoid using this like the plague.
2504 *
2505 * Return: Pointer to raw EDID data.
2506 */
2507const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2508{
2509 if (!drm_edid || !drm_edid->size)
2510 return NULL;
2511
2512 /*
2513 * Do not return pointers where relying on EDID extension count would
2514 * lead to buffer overflow.
2515 */
2516 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2517 return NULL;
2518
2519 return drm_edid->edid;
2520}
2521EXPORT_SYMBOL(drm_edid_raw);
2522
2523/* Allocate struct drm_edid container *without* duplicating the edid data */
2524static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2525{
2526 struct drm_edid *drm_edid;
2527
2528 if (!edid || !size || size < EDID_LENGTH)
2529 return NULL;
2530
2531 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2532 if (drm_edid) {
2533 drm_edid->edid = edid;
2534 drm_edid->size = size;
2535 }
2536
2537 return drm_edid;
2538}
2539
2540/**
2541 * drm_edid_alloc - Allocate a new drm_edid container
2542 * @edid: Pointer to raw EDID data
2543 * @size: Size of memory allocated for EDID
2544 *
2545 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2546 * the actual size that has been allocated for the data. There is no validation
2547 * of the raw EDID data against the size, but at least the EDID base block must
2548 * fit in the buffer.
2549 *
2550 * The returned pointer must be freed using drm_edid_free().
2551 *
2552 * Return: drm_edid container, or NULL on errors
2553 */
2554const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2555{
2556 const struct drm_edid *drm_edid;
2557
2558 if (!edid || !size || size < EDID_LENGTH)
2559 return NULL;
2560
2561 edid = kmemdup(edid, size, GFP_KERNEL);
2562 if (!edid)
2563 return NULL;
2564
2565 drm_edid = _drm_edid_alloc(edid, size);
2566 if (!drm_edid)
2567 kfree(edid);
2568
2569 return drm_edid;
2570}
2571EXPORT_SYMBOL(drm_edid_alloc);
2572
2573/**
2574 * drm_edid_dup - Duplicate a drm_edid container
2575 * @drm_edid: EDID to duplicate
2576 *
2577 * The returned pointer must be freed using drm_edid_free().
2578 *
2579 * Returns: drm_edid container copy, or NULL on errors
2580 */
2581const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2582{
2583 if (!drm_edid)
2584 return NULL;
2585
2586 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2587}
2588EXPORT_SYMBOL(drm_edid_dup);
2589
2590/**
2591 * drm_edid_free - Free the drm_edid container
2592 * @drm_edid: EDID to free
2593 */
2594void drm_edid_free(const struct drm_edid *drm_edid)
2595{
2596 if (!drm_edid)
2597 return;
2598
2599 kfree(drm_edid->edid);
2600 kfree(drm_edid);
2601}
2602EXPORT_SYMBOL(drm_edid_free);
2603
2604/**
2605 * drm_probe_ddc() - probe DDC presence
2606 * @adapter: I2C adapter to probe
2607 *
2608 * Return: True on success, false on failure.
2609 */
2610bool
2611drm_probe_ddc(struct i2c_adapter *adapter)
2612{
2613 unsigned char out;
2614
2615 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2616}
2617EXPORT_SYMBOL(drm_probe_ddc);
2618
2619/**
2620 * drm_get_edid - get EDID data, if available
2621 * @connector: connector we're probing
2622 * @adapter: I2C adapter to use for DDC
2623 *
2624 * Poke the given I2C channel to grab EDID data if possible. If found,
2625 * attach it to the connector.
2626 *
2627 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2628 */
2629struct edid *drm_get_edid(struct drm_connector *connector,
2630 struct i2c_adapter *adapter)
2631{
2632 struct edid *edid;
2633
2634 if (connector->force == DRM_FORCE_OFF)
2635 return NULL;
2636
2637 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2638 return NULL;
2639
2640 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2641 drm_connector_update_edid_property(connector, edid);
2642 return edid;
2643}
2644EXPORT_SYMBOL(drm_get_edid);
2645
2646/**
2647 * drm_edid_read_custom - Read EDID data using given EDID block read function
2648 * @connector: Connector to use
2649 * @read_block: EDID block read function
2650 * @context: Private data passed to the block read function
2651 *
2652 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2653 * exposes a different interface to read EDID blocks this function can be used
2654 * to get EDID data using a custom block read function.
2655 *
2656 * As in the general case the DDC bus is accessible by the kernel at the I2C
2657 * level, drivers must make all reasonable efforts to expose it as an I2C
2658 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2659 * this function.
2660 *
2661 * The EDID may be overridden using debugfs override_edid or firmware EDID
2662 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2663 * order. Having either of them bypasses actual EDID reads.
2664 *
2665 * The returned pointer must be freed using drm_edid_free().
2666 *
2667 * Return: Pointer to EDID, or NULL if probe/read failed.
2668 */
2669const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2670 read_block_fn read_block,
2671 void *context)
2672{
2673 const struct drm_edid *drm_edid;
2674 struct edid *edid;
2675 size_t size = 0;
2676
2677 edid = _drm_do_get_edid(connector, read_block, context, &size);
2678 if (!edid)
2679 return NULL;
2680
2681 /* Sanity check for now */
2682 drm_WARN_ON(connector->dev, !size);
2683
2684 drm_edid = _drm_edid_alloc(edid, size);
2685 if (!drm_edid)
2686 kfree(edid);
2687
2688 return drm_edid;
2689}
2690EXPORT_SYMBOL(drm_edid_read_custom);
2691
2692/**
2693 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2694 * @connector: Connector to use
2695 * @adapter: I2C adapter to use for DDC
2696 *
2697 * Read EDID using the given I2C adapter.
2698 *
2699 * The EDID may be overridden using debugfs override_edid or firmware EDID
2700 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2701 * order. Having either of them bypasses actual EDID reads.
2702 *
2703 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2704 * using drm_edid_read() instead of this function.
2705 *
2706 * The returned pointer must be freed using drm_edid_free().
2707 *
2708 * Return: Pointer to EDID, or NULL if probe/read failed.
2709 */
2710const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2711 struct i2c_adapter *adapter)
2712{
2713 const struct drm_edid *drm_edid;
2714
2715 if (connector->force == DRM_FORCE_OFF)
2716 return NULL;
2717
2718 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2719 return NULL;
2720
2721 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2722
2723 /* Note: Do *not* call connector updates here. */
2724
2725 return drm_edid;
2726}
2727EXPORT_SYMBOL(drm_edid_read_ddc);
2728
2729/**
2730 * drm_edid_read - Read EDID data using connector's I2C adapter
2731 * @connector: Connector to use
2732 *
2733 * Read EDID using the connector's I2C adapter.
2734 *
2735 * The EDID may be overridden using debugfs override_edid or firmware EDID
2736 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2737 * order. Having either of them bypasses actual EDID reads.
2738 *
2739 * The returned pointer must be freed using drm_edid_free().
2740 *
2741 * Return: Pointer to EDID, or NULL if probe/read failed.
2742 */
2743const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2744{
2745 if (drm_WARN_ON(connector->dev, !connector->ddc))
2746 return NULL;
2747
2748 return drm_edid_read_ddc(connector, connector->ddc);
2749}
2750EXPORT_SYMBOL(drm_edid_read);
2751
2752static u32 edid_extract_panel_id(const struct edid *edid)
2753{
2754 /*
2755 * We represent the ID as a 32-bit number so it can easily be compared
2756 * with "==".
2757 *
2758 * NOTE that we deal with endianness differently for the top half
2759 * of this ID than for the bottom half. The bottom half (the product
2760 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2761 * that's how everyone seems to interpret it. The top half (the mfg_id)
2762 * gets stored as big endian because that makes
2763 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2764 * to write (it's easier to extract the ASCII). It doesn't really
2765 * matter, though, as long as the number here is unique.
2766 */
2767 return (u32)edid->mfg_id[0] << 24 |
2768 (u32)edid->mfg_id[1] << 16 |
2769 (u32)EDID_PRODUCT_ID(edid);
2770}
2771
2772/**
2773 * drm_edid_get_panel_id - Get a panel's ID through DDC
2774 * @adapter: I2C adapter to use for DDC
2775 *
2776 * This function reads the first block of the EDID of a panel and (assuming
2777 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2778 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2779 * supposed to be different for each different modem of panel.
2780 *
2781 * This function is intended to be used during early probing on devices where
2782 * more than one panel might be present. Because of its intended use it must
2783 * assume that the EDID of the panel is correct, at least as far as the ID
2784 * is concerned (in other words, we don't process any overrides here).
2785 *
2786 * NOTE: it's expected that this function and drm_do_get_edid() will both
2787 * be read the EDID, but there is no caching between them. Since we're only
2788 * reading the first block, hopefully this extra overhead won't be too big.
2789 *
2790 * Return: A 32-bit ID that should be different for each make/model of panel.
2791 * See the functions drm_edid_encode_panel_id() and
2792 * drm_edid_decode_panel_id() for some details on the structure of this
2793 * ID.
2794 */
2795
2796u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2797{
2798 enum edid_block_status status;
2799 void *base_block;
2800 u32 panel_id = 0;
2801
2802 /*
2803 * There are no manufacturer IDs of 0, so if there is a problem reading
2804 * the EDID then we'll just return 0.
2805 */
2806
2807 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2808 if (!base_block)
2809 return 0;
2810
2811 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2812
2813 edid_block_status_print(status, base_block, 0);
2814
2815 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2816 panel_id = edid_extract_panel_id(base_block);
2817 else
2818 edid_block_dump(KERN_NOTICE, base_block, 0);
2819
2820 kfree(base_block);
2821
2822 return panel_id;
2823}
2824EXPORT_SYMBOL(drm_edid_get_panel_id);
2825
2826/**
2827 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2828 * @connector: connector we're probing
2829 * @adapter: I2C adapter to use for DDC
2830 *
2831 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2832 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2833 * switch DDC to the GPU which is retrieving EDID.
2834 *
2835 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2836 */
2837struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2838 struct i2c_adapter *adapter)
2839{
2840 struct drm_device *dev = connector->dev;
2841 struct pci_dev *pdev = to_pci_dev(dev->dev);
2842 struct edid *edid;
2843
2844 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2845 return NULL;
2846
2847 vga_switcheroo_lock_ddc(pdev);
2848 edid = drm_get_edid(connector, adapter);
2849 vga_switcheroo_unlock_ddc(pdev);
2850
2851 return edid;
2852}
2853EXPORT_SYMBOL(drm_get_edid_switcheroo);
2854
2855/**
2856 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2857 * @connector: connector we're probing
2858 * @adapter: I2C adapter to use for DDC
2859 *
2860 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2861 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2862 * temporarily switch DDC to the GPU which is retrieving EDID.
2863 *
2864 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2865 */
2866const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2867 struct i2c_adapter *adapter)
2868{
2869 struct drm_device *dev = connector->dev;
2870 struct pci_dev *pdev = to_pci_dev(dev->dev);
2871 const struct drm_edid *drm_edid;
2872
2873 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2874 return NULL;
2875
2876 vga_switcheroo_lock_ddc(pdev);
2877 drm_edid = drm_edid_read_ddc(connector, adapter);
2878 vga_switcheroo_unlock_ddc(pdev);
2879
2880 return drm_edid;
2881}
2882EXPORT_SYMBOL(drm_edid_read_switcheroo);
2883
2884/**
2885 * drm_edid_duplicate - duplicate an EDID and the extensions
2886 * @edid: EDID to duplicate
2887 *
2888 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2889 */
2890struct edid *drm_edid_duplicate(const struct edid *edid)
2891{
2892 if (!edid)
2893 return NULL;
2894
2895 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2896}
2897EXPORT_SYMBOL(drm_edid_duplicate);
2898
2899/*** EDID parsing ***/
2900
2901/**
2902 * edid_get_quirks - return quirk flags for a given EDID
2903 * @drm_edid: EDID to process
2904 *
2905 * This tells subsequent routines what fixes they need to apply.
2906 */
2907static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2908{
2909 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2910 const struct edid_quirk *quirk;
2911 int i;
2912
2913 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2914 quirk = &edid_quirk_list[i];
2915 if (quirk->panel_id == panel_id)
2916 return quirk->quirks;
2917 }
2918
2919 return 0;
2920}
2921
2922#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2923#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2924
2925/*
2926 * Walk the mode list for connector, clearing the preferred status on existing
2927 * modes and setting it anew for the right mode ala quirks.
2928 */
2929static void edid_fixup_preferred(struct drm_connector *connector)
2930{
2931 const struct drm_display_info *info = &connector->display_info;
2932 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2933 int target_refresh = 0;
2934 int cur_vrefresh, preferred_vrefresh;
2935
2936 if (list_empty(&connector->probed_modes))
2937 return;
2938
2939 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2940 target_refresh = 60;
2941 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2942 target_refresh = 75;
2943
2944 preferred_mode = list_first_entry(&connector->probed_modes,
2945 struct drm_display_mode, head);
2946
2947 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2948 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2949
2950 if (cur_mode == preferred_mode)
2951 continue;
2952
2953 /* Largest mode is preferred */
2954 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2955 preferred_mode = cur_mode;
2956
2957 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2958 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2959 /* At a given size, try to get closest to target refresh */
2960 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2961 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2962 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2963 preferred_mode = cur_mode;
2964 }
2965 }
2966
2967 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2968}
2969
2970static bool
2971mode_is_rb(const struct drm_display_mode *mode)
2972{
2973 return (mode->htotal - mode->hdisplay == 160) &&
2974 (mode->hsync_end - mode->hdisplay == 80) &&
2975 (mode->hsync_end - mode->hsync_start == 32) &&
2976 (mode->vsync_start - mode->vdisplay == 3);
2977}
2978
2979/*
2980 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2981 * @dev: Device to duplicate against
2982 * @hsize: Mode width
2983 * @vsize: Mode height
2984 * @fresh: Mode refresh rate
2985 * @rb: Mode reduced-blanking-ness
2986 *
2987 * Walk the DMT mode list looking for a match for the given parameters.
2988 *
2989 * Return: A newly allocated copy of the mode, or NULL if not found.
2990 */
2991struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2992 int hsize, int vsize, int fresh,
2993 bool rb)
2994{
2995 int i;
2996
2997 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2998 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2999
3000 if (hsize != ptr->hdisplay)
3001 continue;
3002 if (vsize != ptr->vdisplay)
3003 continue;
3004 if (fresh != drm_mode_vrefresh(ptr))
3005 continue;
3006 if (rb != mode_is_rb(ptr))
3007 continue;
3008
3009 return drm_mode_duplicate(dev, ptr);
3010 }
3011
3012 return NULL;
3013}
3014EXPORT_SYMBOL(drm_mode_find_dmt);
3015
3016static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3017{
3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3019 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3020 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3021
3022 return descriptor->pixel_clock == 0 &&
3023 descriptor->data.other_data.pad1 == 0 &&
3024 descriptor->data.other_data.type == type;
3025}
3026
3027static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3028{
3029 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3030
3031 return descriptor->pixel_clock != 0;
3032}
3033
3034typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3035
3036static void
3037cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3038{
3039 int i, n;
3040 u8 d = ext[0x02];
3041 const u8 *det_base = ext + d;
3042
3043 if (d < 4 || d > 127)
3044 return;
3045
3046 n = (127 - d) / 18;
3047 for (i = 0; i < n; i++)
3048 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3049}
3050
3051static void
3052vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3053{
3054 unsigned int i, n = min((int)ext[0x02], 6);
3055 const u8 *det_base = ext + 5;
3056
3057 if (ext[0x01] != 1)
3058 return; /* unknown version */
3059
3060 for (i = 0; i < n; i++)
3061 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3062}
3063
3064static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3065 detailed_cb *cb, void *closure)
3066{
3067 struct drm_edid_iter edid_iter;
3068 const u8 *ext;
3069 int i;
3070
3071 if (!drm_edid)
3072 return;
3073
3074 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3075 cb(&drm_edid->edid->detailed_timings[i], closure);
3076
3077 drm_edid_iter_begin(drm_edid, &edid_iter);
3078 drm_edid_iter_for_each(ext, &edid_iter) {
3079 switch (*ext) {
3080 case CEA_EXT:
3081 cea_for_each_detailed_block(ext, cb, closure);
3082 break;
3083 case VTB_EXT:
3084 vtb_for_each_detailed_block(ext, cb, closure);
3085 break;
3086 default:
3087 break;
3088 }
3089 }
3090 drm_edid_iter_end(&edid_iter);
3091}
3092
3093static void
3094is_rb(const struct detailed_timing *descriptor, void *data)
3095{
3096 bool *res = data;
3097
3098 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3099 return;
3100
3101 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3102 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3103
3104 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3105 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3106 *res = true;
3107}
3108
3109/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3110static bool
3111drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3112{
3113 if (drm_edid->edid->revision >= 4) {
3114 bool ret = false;
3115
3116 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3117 return ret;
3118 }
3119
3120 return drm_edid_is_digital(drm_edid);
3121}
3122
3123static void
3124find_gtf2(const struct detailed_timing *descriptor, void *data)
3125{
3126 const struct detailed_timing **res = data;
3127
3128 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3129 return;
3130
3131 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3132
3133 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3134 *res = descriptor;
3135}
3136
3137/* Secondary GTF curve kicks in above some break frequency */
3138static int
3139drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3140{
3141 const struct detailed_timing *descriptor = NULL;
3142
3143 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3144
3145 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3146
3147 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3148}
3149
3150static int
3151drm_gtf2_2c(const struct drm_edid *drm_edid)
3152{
3153 const struct detailed_timing *descriptor = NULL;
3154
3155 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3156
3157 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3158
3159 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3160}
3161
3162static int
3163drm_gtf2_m(const struct drm_edid *drm_edid)
3164{
3165 const struct detailed_timing *descriptor = NULL;
3166
3167 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3168
3169 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3170
3171 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3172}
3173
3174static int
3175drm_gtf2_k(const struct drm_edid *drm_edid)
3176{
3177 const struct detailed_timing *descriptor = NULL;
3178
3179 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3180
3181 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3182
3183 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3184}
3185
3186static int
3187drm_gtf2_2j(const struct drm_edid *drm_edid)
3188{
3189 const struct detailed_timing *descriptor = NULL;
3190
3191 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3192
3193 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3194
3195 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3196}
3197
3198static void
3199get_timing_level(const struct detailed_timing *descriptor, void *data)
3200{
3201 int *res = data;
3202
3203 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3204 return;
3205
3206 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3207
3208 switch (descriptor->data.other_data.data.range.flags) {
3209 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3210 *res = LEVEL_GTF;
3211 break;
3212 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3213 *res = LEVEL_GTF2;
3214 break;
3215 case DRM_EDID_CVT_SUPPORT_FLAG:
3216 *res = LEVEL_CVT;
3217 break;
3218 default:
3219 break;
3220 }
3221}
3222
3223/* Get standard timing level (CVT/GTF/DMT). */
3224static int standard_timing_level(const struct drm_edid *drm_edid)
3225{
3226 const struct edid *edid = drm_edid->edid;
3227
3228 if (edid->revision >= 4) {
3229 /*
3230 * If the range descriptor doesn't
3231 * indicate otherwise default to CVT
3232 */
3233 int ret = LEVEL_CVT;
3234
3235 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3236
3237 return ret;
3238 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3239 return LEVEL_GTF2;
3240 } else if (edid->revision >= 2) {
3241 return LEVEL_GTF;
3242 } else {
3243 return LEVEL_DMT;
3244 }
3245}
3246
3247/*
3248 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3249 * monitors fill with ascii space (0x20) instead.
3250 */
3251static int
3252bad_std_timing(u8 a, u8 b)
3253{
3254 return (a == 0x00 && b == 0x00) ||
3255 (a == 0x01 && b == 0x01) ||
3256 (a == 0x20 && b == 0x20);
3257}
3258
3259static int drm_mode_hsync(const struct drm_display_mode *mode)
3260{
3261 if (mode->htotal <= 0)
3262 return 0;
3263
3264 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3265}
3266
3267static struct drm_display_mode *
3268drm_gtf2_mode(struct drm_device *dev,
3269 const struct drm_edid *drm_edid,
3270 int hsize, int vsize, int vrefresh_rate)
3271{
3272 struct drm_display_mode *mode;
3273
3274 /*
3275 * This is potentially wrong if there's ever a monitor with
3276 * more than one ranges section, each claiming a different
3277 * secondary GTF curve. Please don't do that.
3278 */
3279 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3280 if (!mode)
3281 return NULL;
3282
3283 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3284 drm_mode_destroy(dev, mode);
3285 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3286 vrefresh_rate, 0, 0,
3287 drm_gtf2_m(drm_edid),
3288 drm_gtf2_2c(drm_edid),
3289 drm_gtf2_k(drm_edid),
3290 drm_gtf2_2j(drm_edid));
3291 }
3292
3293 return mode;
3294}
3295
3296/*
3297 * Take the standard timing params (in this case width, aspect, and refresh)
3298 * and convert them into a real mode using CVT/GTF/DMT.
3299 */
3300static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3301 const struct drm_edid *drm_edid,
3302 const struct std_timing *t)
3303{
3304 struct drm_device *dev = connector->dev;
3305 struct drm_display_mode *m, *mode = NULL;
3306 int hsize, vsize;
3307 int vrefresh_rate;
3308 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3309 >> EDID_TIMING_ASPECT_SHIFT;
3310 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3311 >> EDID_TIMING_VFREQ_SHIFT;
3312 int timing_level = standard_timing_level(drm_edid);
3313
3314 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3315 return NULL;
3316
3317 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3318 hsize = t->hsize * 8 + 248;
3319 /* vrefresh_rate = vfreq + 60 */
3320 vrefresh_rate = vfreq + 60;
3321 /* the vdisplay is calculated based on the aspect ratio */
3322 if (aspect_ratio == 0) {
3323 if (drm_edid->edid->revision < 3)
3324 vsize = hsize;
3325 else
3326 vsize = (hsize * 10) / 16;
3327 } else if (aspect_ratio == 1)
3328 vsize = (hsize * 3) / 4;
3329 else if (aspect_ratio == 2)
3330 vsize = (hsize * 4) / 5;
3331 else
3332 vsize = (hsize * 9) / 16;
3333
3334 /* HDTV hack, part 1 */
3335 if (vrefresh_rate == 60 &&
3336 ((hsize == 1360 && vsize == 765) ||
3337 (hsize == 1368 && vsize == 769))) {
3338 hsize = 1366;
3339 vsize = 768;
3340 }
3341
3342 /*
3343 * If this connector already has a mode for this size and refresh
3344 * rate (because it came from detailed or CVT info), use that
3345 * instead. This way we don't have to guess at interlace or
3346 * reduced blanking.
3347 */
3348 list_for_each_entry(m, &connector->probed_modes, head)
3349 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3350 drm_mode_vrefresh(m) == vrefresh_rate)
3351 return NULL;
3352
3353 /* HDTV hack, part 2 */
3354 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3355 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3356 false);
3357 if (!mode)
3358 return NULL;
3359 mode->hdisplay = 1366;
3360 mode->hsync_start = mode->hsync_start - 1;
3361 mode->hsync_end = mode->hsync_end - 1;
3362 return mode;
3363 }
3364
3365 /* check whether it can be found in default mode table */
3366 if (drm_monitor_supports_rb(drm_edid)) {
3367 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3368 true);
3369 if (mode)
3370 return mode;
3371 }
3372 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3373 if (mode)
3374 return mode;
3375
3376 /* okay, generate it */
3377 switch (timing_level) {
3378 case LEVEL_DMT:
3379 break;
3380 case LEVEL_GTF:
3381 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3382 break;
3383 case LEVEL_GTF2:
3384 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3385 break;
3386 case LEVEL_CVT:
3387 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3388 false);
3389 break;
3390 }
3391 return mode;
3392}
3393
3394/*
3395 * EDID is delightfully ambiguous about how interlaced modes are to be
3396 * encoded. Our internal representation is of frame height, but some
3397 * HDTV detailed timings are encoded as field height.
3398 *
3399 * The format list here is from CEA, in frame size. Technically we
3400 * should be checking refresh rate too. Whatever.
3401 */
3402static void
3403drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3404 const struct detailed_pixel_timing *pt)
3405{
3406 int i;
3407 static const struct {
3408 int w, h;
3409 } cea_interlaced[] = {
3410 { 1920, 1080 },
3411 { 720, 480 },
3412 { 1440, 480 },
3413 { 2880, 480 },
3414 { 720, 576 },
3415 { 1440, 576 },
3416 { 2880, 576 },
3417 };
3418
3419 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3420 return;
3421
3422 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3423 if ((mode->hdisplay == cea_interlaced[i].w) &&
3424 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3425 mode->vdisplay *= 2;
3426 mode->vsync_start *= 2;
3427 mode->vsync_end *= 2;
3428 mode->vtotal *= 2;
3429 mode->vtotal |= 1;
3430 }
3431 }
3432
3433 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3434}
3435
3436/*
3437 * Create a new mode from an EDID detailed timing section. An EDID detailed
3438 * timing block contains enough info for us to create and return a new struct
3439 * drm_display_mode.
3440 */
3441static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3442 const struct drm_edid *drm_edid,
3443 const struct detailed_timing *timing)
3444{
3445 const struct drm_display_info *info = &connector->display_info;
3446 struct drm_device *dev = connector->dev;
3447 struct drm_display_mode *mode;
3448 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3449 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3450 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3451 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3452 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3453 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3454 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3455 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3456 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3457
3458 /* ignore tiny modes */
3459 if (hactive < 64 || vactive < 64)
3460 return NULL;
3461
3462 if (pt->misc & DRM_EDID_PT_STEREO) {
3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3464 connector->base.id, connector->name);
3465 return NULL;
3466 }
3467 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3468 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3469 connector->base.id, connector->name);
3470 }
3471
3472 /* it is incorrect if hsync/vsync width is zero */
3473 if (!hsync_pulse_width || !vsync_pulse_width) {
3474 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3475 connector->base.id, connector->name);
3476 return NULL;
3477 }
3478
3479 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3480 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3481 if (!mode)
3482 return NULL;
3483
3484 goto set_size;
3485 }
3486
3487 mode = drm_mode_create(dev);
3488 if (!mode)
3489 return NULL;
3490
3491 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3492 mode->clock = 1088 * 10;
3493 else
3494 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3495
3496 mode->hdisplay = hactive;
3497 mode->hsync_start = mode->hdisplay + hsync_offset;
3498 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3499 mode->htotal = mode->hdisplay + hblank;
3500
3501 mode->vdisplay = vactive;
3502 mode->vsync_start = mode->vdisplay + vsync_offset;
3503 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3504 mode->vtotal = mode->vdisplay + vblank;
3505
3506 /* Some EDIDs have bogus h/vsync_end values */
3507 if (mode->hsync_end > mode->htotal) {
3508 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3509 connector->base.id, connector->name,
3510 mode->hsync_end, mode->htotal);
3511 mode->hsync_end = mode->htotal;
3512 }
3513 if (mode->vsync_end > mode->vtotal) {
3514 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3515 connector->base.id, connector->name,
3516 mode->vsync_end, mode->vtotal);
3517 mode->vsync_end = mode->vtotal;
3518 }
3519
3520 drm_mode_do_interlace_quirk(mode, pt);
3521
3522 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3523 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3524 } else {
3525 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3526 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3527 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3528 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3529 }
3530
3531set_size:
3532 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3533 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3534
3535 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3536 mode->width_mm *= 10;
3537 mode->height_mm *= 10;
3538 }
3539
3540 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3541 mode->width_mm = drm_edid->edid->width_cm * 10;
3542 mode->height_mm = drm_edid->edid->height_cm * 10;
3543 }
3544
3545 mode->type = DRM_MODE_TYPE_DRIVER;
3546 drm_mode_set_name(mode);
3547
3548 return mode;
3549}
3550
3551static bool
3552mode_in_hsync_range(const struct drm_display_mode *mode,
3553 const struct edid *edid, const u8 *t)
3554{
3555 int hsync, hmin, hmax;
3556
3557 hmin = t[7];
3558 if (edid->revision >= 4)
3559 hmin += ((t[4] & 0x04) ? 255 : 0);
3560 hmax = t[8];
3561 if (edid->revision >= 4)
3562 hmax += ((t[4] & 0x08) ? 255 : 0);
3563 hsync = drm_mode_hsync(mode);
3564
3565 return (hsync <= hmax && hsync >= hmin);
3566}
3567
3568static bool
3569mode_in_vsync_range(const struct drm_display_mode *mode,
3570 const struct edid *edid, const u8 *t)
3571{
3572 int vsync, vmin, vmax;
3573
3574 vmin = t[5];
3575 if (edid->revision >= 4)
3576 vmin += ((t[4] & 0x01) ? 255 : 0);
3577 vmax = t[6];
3578 if (edid->revision >= 4)
3579 vmax += ((t[4] & 0x02) ? 255 : 0);
3580 vsync = drm_mode_vrefresh(mode);
3581
3582 return (vsync <= vmax && vsync >= vmin);
3583}
3584
3585static u32
3586range_pixel_clock(const struct edid *edid, const u8 *t)
3587{
3588 /* unspecified */
3589 if (t[9] == 0 || t[9] == 255)
3590 return 0;
3591
3592 /* 1.4 with CVT support gives us real precision, yay */
3593 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3594 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3595
3596 /* 1.3 is pathetic, so fuzz up a bit */
3597 return t[9] * 10000 + 5001;
3598}
3599
3600static bool mode_in_range(const struct drm_display_mode *mode,
3601 const struct drm_edid *drm_edid,
3602 const struct detailed_timing *timing)
3603{
3604 const struct edid *edid = drm_edid->edid;
3605 u32 max_clock;
3606 const u8 *t = (const u8 *)timing;
3607
3608 if (!mode_in_hsync_range(mode, edid, t))
3609 return false;
3610
3611 if (!mode_in_vsync_range(mode, edid, t))
3612 return false;
3613
3614 if ((max_clock = range_pixel_clock(edid, t)))
3615 if (mode->clock > max_clock)
3616 return false;
3617
3618 /* 1.4 max horizontal check */
3619 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3620 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3621 return false;
3622
3623 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3624 return false;
3625
3626 return true;
3627}
3628
3629static bool valid_inferred_mode(const struct drm_connector *connector,
3630 const struct drm_display_mode *mode)
3631{
3632 const struct drm_display_mode *m;
3633 bool ok = false;
3634
3635 list_for_each_entry(m, &connector->probed_modes, head) {
3636 if (mode->hdisplay == m->hdisplay &&
3637 mode->vdisplay == m->vdisplay &&
3638 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3639 return false; /* duplicated */
3640 if (mode->hdisplay <= m->hdisplay &&
3641 mode->vdisplay <= m->vdisplay)
3642 ok = true;
3643 }
3644 return ok;
3645}
3646
3647static int drm_dmt_modes_for_range(struct drm_connector *connector,
3648 const struct drm_edid *drm_edid,
3649 const struct detailed_timing *timing)
3650{
3651 int i, modes = 0;
3652 struct drm_display_mode *newmode;
3653 struct drm_device *dev = connector->dev;
3654
3655 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3656 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3657 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3658 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3659 if (newmode) {
3660 drm_mode_probed_add(connector, newmode);
3661 modes++;
3662 }
3663 }
3664 }
3665
3666 return modes;
3667}
3668
3669/* fix up 1366x768 mode from 1368x768;
3670 * GFT/CVT can't express 1366 width which isn't dividable by 8
3671 */
3672void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3673{
3674 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3675 mode->hdisplay = 1366;
3676 mode->hsync_start--;
3677 mode->hsync_end--;
3678 drm_mode_set_name(mode);
3679 }
3680}
3681
3682static int drm_gtf_modes_for_range(struct drm_connector *connector,
3683 const struct drm_edid *drm_edid,
3684 const struct detailed_timing *timing)
3685{
3686 int i, modes = 0;
3687 struct drm_display_mode *newmode;
3688 struct drm_device *dev = connector->dev;
3689
3690 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3691 const struct minimode *m = &extra_modes[i];
3692
3693 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3694 if (!newmode)
3695 return modes;
3696
3697 drm_mode_fixup_1366x768(newmode);
3698 if (!mode_in_range(newmode, drm_edid, timing) ||
3699 !valid_inferred_mode(connector, newmode)) {
3700 drm_mode_destroy(dev, newmode);
3701 continue;
3702 }
3703
3704 drm_mode_probed_add(connector, newmode);
3705 modes++;
3706 }
3707
3708 return modes;
3709}
3710
3711static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3712 const struct drm_edid *drm_edid,
3713 const struct detailed_timing *timing)
3714{
3715 int i, modes = 0;
3716 struct drm_display_mode *newmode;
3717 struct drm_device *dev = connector->dev;
3718
3719 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3720 const struct minimode *m = &extra_modes[i];
3721
3722 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3723 if (!newmode)
3724 return modes;
3725
3726 drm_mode_fixup_1366x768(newmode);
3727 if (!mode_in_range(newmode, drm_edid, timing) ||
3728 !valid_inferred_mode(connector, newmode)) {
3729 drm_mode_destroy(dev, newmode);
3730 continue;
3731 }
3732
3733 drm_mode_probed_add(connector, newmode);
3734 modes++;
3735 }
3736
3737 return modes;
3738}
3739
3740static int drm_cvt_modes_for_range(struct drm_connector *connector,
3741 const struct drm_edid *drm_edid,
3742 const struct detailed_timing *timing)
3743{
3744 int i, modes = 0;
3745 struct drm_display_mode *newmode;
3746 struct drm_device *dev = connector->dev;
3747 bool rb = drm_monitor_supports_rb(drm_edid);
3748
3749 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3750 const struct minimode *m = &extra_modes[i];
3751
3752 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3753 if (!newmode)
3754 return modes;
3755
3756 drm_mode_fixup_1366x768(newmode);
3757 if (!mode_in_range(newmode, drm_edid, timing) ||
3758 !valid_inferred_mode(connector, newmode)) {
3759 drm_mode_destroy(dev, newmode);
3760 continue;
3761 }
3762
3763 drm_mode_probed_add(connector, newmode);
3764 modes++;
3765 }
3766
3767 return modes;
3768}
3769
3770static void
3771do_inferred_modes(const struct detailed_timing *timing, void *c)
3772{
3773 struct detailed_mode_closure *closure = c;
3774 const struct detailed_non_pixel *data = &timing->data.other_data;
3775 const struct detailed_data_monitor_range *range = &data->data.range;
3776
3777 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3778 return;
3779
3780 closure->modes += drm_dmt_modes_for_range(closure->connector,
3781 closure->drm_edid,
3782 timing);
3783
3784 if (closure->drm_edid->edid->revision < 2)
3785 return; /* GTF not defined yet */
3786
3787 switch (range->flags) {
3788 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3789 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3790 closure->drm_edid,
3791 timing);
3792 break;
3793 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3794 closure->modes += drm_gtf_modes_for_range(closure->connector,
3795 closure->drm_edid,
3796 timing);
3797 break;
3798 case DRM_EDID_CVT_SUPPORT_FLAG:
3799 if (closure->drm_edid->edid->revision < 4)
3800 break;
3801
3802 closure->modes += drm_cvt_modes_for_range(closure->connector,
3803 closure->drm_edid,
3804 timing);
3805 break;
3806 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3807 default:
3808 break;
3809 }
3810}
3811
3812static int add_inferred_modes(struct drm_connector *connector,
3813 const struct drm_edid *drm_edid)
3814{
3815 struct detailed_mode_closure closure = {
3816 .connector = connector,
3817 .drm_edid = drm_edid,
3818 };
3819
3820 if (drm_edid->edid->revision >= 1)
3821 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3822
3823 return closure.modes;
3824}
3825
3826static int
3827drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3828{
3829 int i, j, m, modes = 0;
3830 struct drm_display_mode *mode;
3831 const u8 *est = ((const u8 *)timing) + 6;
3832
3833 for (i = 0; i < 6; i++) {
3834 for (j = 7; j >= 0; j--) {
3835 m = (i * 8) + (7 - j);
3836 if (m >= ARRAY_SIZE(est3_modes))
3837 break;
3838 if (est[i] & (1 << j)) {
3839 mode = drm_mode_find_dmt(connector->dev,
3840 est3_modes[m].w,
3841 est3_modes[m].h,
3842 est3_modes[m].r,
3843 est3_modes[m].rb);
3844 if (mode) {
3845 drm_mode_probed_add(connector, mode);
3846 modes++;
3847 }
3848 }
3849 }
3850 }
3851
3852 return modes;
3853}
3854
3855static void
3856do_established_modes(const struct detailed_timing *timing, void *c)
3857{
3858 struct detailed_mode_closure *closure = c;
3859
3860 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3861 return;
3862
3863 closure->modes += drm_est3_modes(closure->connector, timing);
3864}
3865
3866/*
3867 * Get established modes from EDID and add them. Each EDID block contains a
3868 * bitmap of the supported "established modes" list (defined above). Tease them
3869 * out and add them to the global modes list.
3870 */
3871static int add_established_modes(struct drm_connector *connector,
3872 const struct drm_edid *drm_edid)
3873{
3874 struct drm_device *dev = connector->dev;
3875 const struct edid *edid = drm_edid->edid;
3876 unsigned long est_bits = edid->established_timings.t1 |
3877 (edid->established_timings.t2 << 8) |
3878 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3879 int i, modes = 0;
3880 struct detailed_mode_closure closure = {
3881 .connector = connector,
3882 .drm_edid = drm_edid,
3883 };
3884
3885 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3886 if (est_bits & (1<<i)) {
3887 struct drm_display_mode *newmode;
3888
3889 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3890 if (newmode) {
3891 drm_mode_probed_add(connector, newmode);
3892 modes++;
3893 }
3894 }
3895 }
3896
3897 if (edid->revision >= 1)
3898 drm_for_each_detailed_block(drm_edid, do_established_modes,
3899 &closure);
3900
3901 return modes + closure.modes;
3902}
3903
3904static void
3905do_standard_modes(const struct detailed_timing *timing, void *c)
3906{
3907 struct detailed_mode_closure *closure = c;
3908 const struct detailed_non_pixel *data = &timing->data.other_data;
3909 struct drm_connector *connector = closure->connector;
3910 int i;
3911
3912 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3913 return;
3914
3915 for (i = 0; i < 6; i++) {
3916 const struct std_timing *std = &data->data.timings[i];
3917 struct drm_display_mode *newmode;
3918
3919 newmode = drm_mode_std(connector, closure->drm_edid, std);
3920 if (newmode) {
3921 drm_mode_probed_add(connector, newmode);
3922 closure->modes++;
3923 }
3924 }
3925}
3926
3927/*
3928 * Get standard modes from EDID and add them. Standard modes can be calculated
3929 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3930 * add them to the list.
3931 */
3932static int add_standard_modes(struct drm_connector *connector,
3933 const struct drm_edid *drm_edid)
3934{
3935 int i, modes = 0;
3936 struct detailed_mode_closure closure = {
3937 .connector = connector,
3938 .drm_edid = drm_edid,
3939 };
3940
3941 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3942 struct drm_display_mode *newmode;
3943
3944 newmode = drm_mode_std(connector, drm_edid,
3945 &drm_edid->edid->standard_timings[i]);
3946 if (newmode) {
3947 drm_mode_probed_add(connector, newmode);
3948 modes++;
3949 }
3950 }
3951
3952 if (drm_edid->edid->revision >= 1)
3953 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3954 &closure);
3955
3956 /* XXX should also look for standard codes in VTB blocks */
3957
3958 return modes + closure.modes;
3959}
3960
3961static int drm_cvt_modes(struct drm_connector *connector,
3962 const struct detailed_timing *timing)
3963{
3964 int i, j, modes = 0;
3965 struct drm_display_mode *newmode;
3966 struct drm_device *dev = connector->dev;
3967 const struct cvt_timing *cvt;
3968 static const int rates[] = { 60, 85, 75, 60, 50 };
3969 const u8 empty[3] = { 0, 0, 0 };
3970
3971 for (i = 0; i < 4; i++) {
3972 int width, height;
3973
3974 cvt = &(timing->data.other_data.data.cvt[i]);
3975
3976 if (!memcmp(cvt->code, empty, 3))
3977 continue;
3978
3979 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3980 switch (cvt->code[1] & 0x0c) {
3981 /* default - because compiler doesn't see that we've enumerated all cases */
3982 default:
3983 case 0x00:
3984 width = height * 4 / 3;
3985 break;
3986 case 0x04:
3987 width = height * 16 / 9;
3988 break;
3989 case 0x08:
3990 width = height * 16 / 10;
3991 break;
3992 case 0x0c:
3993 width = height * 15 / 9;
3994 break;
3995 }
3996
3997 for (j = 1; j < 5; j++) {
3998 if (cvt->code[2] & (1 << j)) {
3999 newmode = drm_cvt_mode(dev, width, height,
4000 rates[j], j == 0,
4001 false, false);
4002 if (newmode) {
4003 drm_mode_probed_add(connector, newmode);
4004 modes++;
4005 }
4006 }
4007 }
4008 }
4009
4010 return modes;
4011}
4012
4013static void
4014do_cvt_mode(const struct detailed_timing *timing, void *c)
4015{
4016 struct detailed_mode_closure *closure = c;
4017
4018 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4019 return;
4020
4021 closure->modes += drm_cvt_modes(closure->connector, timing);
4022}
4023
4024static int
4025add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4026{
4027 struct detailed_mode_closure closure = {
4028 .connector = connector,
4029 .drm_edid = drm_edid,
4030 };
4031
4032 if (drm_edid->edid->revision >= 3)
4033 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4034
4035 /* XXX should also look for CVT codes in VTB blocks */
4036
4037 return closure.modes;
4038}
4039
4040static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4041 struct drm_display_mode *mode);
4042
4043static void
4044do_detailed_mode(const struct detailed_timing *timing, void *c)
4045{
4046 struct detailed_mode_closure *closure = c;
4047 struct drm_display_mode *newmode;
4048
4049 if (!is_detailed_timing_descriptor(timing))
4050 return;
4051
4052 newmode = drm_mode_detailed(closure->connector,
4053 closure->drm_edid, timing);
4054 if (!newmode)
4055 return;
4056
4057 if (closure->preferred)
4058 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4059
4060 /*
4061 * Detailed modes are limited to 10kHz pixel clock resolution,
4062 * so fix up anything that looks like CEA/HDMI mode, but the clock
4063 * is just slightly off.
4064 */
4065 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4066
4067 drm_mode_probed_add(closure->connector, newmode);
4068 closure->modes++;
4069 closure->preferred = false;
4070}
4071
4072/*
4073 * add_detailed_modes - Add modes from detailed timings
4074 * @connector: attached connector
4075 * @drm_edid: EDID block to scan
4076 */
4077static int add_detailed_modes(struct drm_connector *connector,
4078 const struct drm_edid *drm_edid)
4079{
4080 struct detailed_mode_closure closure = {
4081 .connector = connector,
4082 .drm_edid = drm_edid,
4083 };
4084
4085 if (drm_edid->edid->revision >= 4)
4086 closure.preferred = true; /* first detailed timing is always preferred */
4087 else
4088 closure.preferred =
4089 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4090
4091 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4092
4093 return closure.modes;
4094}
4095
4096/* CTA-861-H Table 60 - CTA Tag Codes */
4097#define CTA_DB_AUDIO 1
4098#define CTA_DB_VIDEO 2
4099#define CTA_DB_VENDOR 3
4100#define CTA_DB_SPEAKER 4
4101#define CTA_DB_EXTENDED_TAG 7
4102
4103/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4104#define CTA_EXT_DB_VIDEO_CAP 0
4105#define CTA_EXT_DB_VENDOR 1
4106#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4107#define CTA_EXT_DB_420_VIDEO_DATA 14
4108#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4109#define CTA_EXT_DB_HF_EEODB 0x78
4110#define CTA_EXT_DB_HF_SCDB 0x79
4111
4112#define EDID_BASIC_AUDIO (1 << 6)
4113#define EDID_CEA_YCRCB444 (1 << 5)
4114#define EDID_CEA_YCRCB422 (1 << 4)
4115#define EDID_CEA_VCDB_QS (1 << 6)
4116
4117/*
4118 * Search EDID for CEA extension block.
4119 *
4120 * FIXME: Prefer not returning pointers to raw EDID data.
4121 */
4122const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4123 int ext_id, int *ext_index)
4124{
4125 const u8 *edid_ext = NULL;
4126 int i;
4127
4128 /* No EDID or EDID extensions */
4129 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4130 return NULL;
4131
4132 /* Find CEA extension */
4133 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4134 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4135 if (edid_block_tag(edid_ext) == ext_id)
4136 break;
4137 }
4138
4139 if (i >= drm_edid_extension_block_count(drm_edid))
4140 return NULL;
4141
4142 *ext_index = i + 1;
4143
4144 return edid_ext;
4145}
4146
4147/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4148static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4149{
4150 const struct displayid_block *block;
4151 struct displayid_iter iter;
4152 int ext_index = 0;
4153 bool found = false;
4154
4155 /* Look for a top level CEA extension block */
4156 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4157 return true;
4158
4159 /* CEA blocks can also be found embedded in a DisplayID block */
4160 displayid_iter_edid_begin(drm_edid, &iter);
4161 displayid_iter_for_each(block, &iter) {
4162 if (block->tag == DATA_BLOCK_CTA) {
4163 found = true;
4164 break;
4165 }
4166 }
4167 displayid_iter_end(&iter);
4168
4169 return found;
4170}
4171
4172static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4173{
4174 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4175 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4176
4177 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4178 return &edid_cea_modes_1[vic - 1];
4179 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4180 return &edid_cea_modes_193[vic - 193];
4181 return NULL;
4182}
4183
4184static u8 cea_num_vics(void)
4185{
4186 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4187}
4188
4189static u8 cea_next_vic(u8 vic)
4190{
4191 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4192 vic = 193;
4193 return vic;
4194}
4195
4196/*
4197 * Calculate the alternate clock for the CEA mode
4198 * (60Hz vs. 59.94Hz etc.)
4199 */
4200static unsigned int
4201cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4202{
4203 unsigned int clock = cea_mode->clock;
4204
4205 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4206 return clock;
4207
4208 /*
4209 * edid_cea_modes contains the 59.94Hz
4210 * variant for 240 and 480 line modes,
4211 * and the 60Hz variant otherwise.
4212 */
4213 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4214 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4215 else
4216 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4217
4218 return clock;
4219}
4220
4221static bool
4222cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4223{
4224 /*
4225 * For certain VICs the spec allows the vertical
4226 * front porch to vary by one or two lines.
4227 *
4228 * cea_modes[] stores the variant with the shortest
4229 * vertical front porch. We can adjust the mode to
4230 * get the other variants by simply increasing the
4231 * vertical front porch length.
4232 */
4233 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4234 cea_mode_for_vic(9)->vtotal != 262 ||
4235 cea_mode_for_vic(12)->vtotal != 262 ||
4236 cea_mode_for_vic(13)->vtotal != 262 ||
4237 cea_mode_for_vic(23)->vtotal != 312 ||
4238 cea_mode_for_vic(24)->vtotal != 312 ||
4239 cea_mode_for_vic(27)->vtotal != 312 ||
4240 cea_mode_for_vic(28)->vtotal != 312);
4241
4242 if (((vic == 8 || vic == 9 ||
4243 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4244 ((vic == 23 || vic == 24 ||
4245 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4246 mode->vsync_start++;
4247 mode->vsync_end++;
4248 mode->vtotal++;
4249
4250 return true;
4251 }
4252
4253 return false;
4254}
4255
4256static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4257 unsigned int clock_tolerance)
4258{
4259 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4260 u8 vic;
4261
4262 if (!to_match->clock)
4263 return 0;
4264
4265 if (to_match->picture_aspect_ratio)
4266 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4267
4268 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4269 struct drm_display_mode cea_mode;
4270 unsigned int clock1, clock2;
4271
4272 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4273
4274 /* Check both 60Hz and 59.94Hz */
4275 clock1 = cea_mode.clock;
4276 clock2 = cea_mode_alternate_clock(&cea_mode);
4277
4278 if (abs(to_match->clock - clock1) > clock_tolerance &&
4279 abs(to_match->clock - clock2) > clock_tolerance)
4280 continue;
4281
4282 do {
4283 if (drm_mode_match(to_match, &cea_mode, match_flags))
4284 return vic;
4285 } while (cea_mode_alternate_timings(vic, &cea_mode));
4286 }
4287
4288 return 0;
4289}
4290
4291/**
4292 * drm_match_cea_mode - look for a CEA mode matching given mode
4293 * @to_match: display mode
4294 *
4295 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4296 * mode.
4297 */
4298u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4299{
4300 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4301 u8 vic;
4302
4303 if (!to_match->clock)
4304 return 0;
4305
4306 if (to_match->picture_aspect_ratio)
4307 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4308
4309 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4310 struct drm_display_mode cea_mode;
4311 unsigned int clock1, clock2;
4312
4313 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4314
4315 /* Check both 60Hz and 59.94Hz */
4316 clock1 = cea_mode.clock;
4317 clock2 = cea_mode_alternate_clock(&cea_mode);
4318
4319 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4320 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4321 continue;
4322
4323 do {
4324 if (drm_mode_match(to_match, &cea_mode, match_flags))
4325 return vic;
4326 } while (cea_mode_alternate_timings(vic, &cea_mode));
4327 }
4328
4329 return 0;
4330}
4331EXPORT_SYMBOL(drm_match_cea_mode);
4332
4333static bool drm_valid_cea_vic(u8 vic)
4334{
4335 return cea_mode_for_vic(vic) != NULL;
4336}
4337
4338static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4339{
4340 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4341
4342 if (mode)
4343 return mode->picture_aspect_ratio;
4344
4345 return HDMI_PICTURE_ASPECT_NONE;
4346}
4347
4348static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4349{
4350 return edid_4k_modes[video_code].picture_aspect_ratio;
4351}
4352
4353/*
4354 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4355 * specific block).
4356 */
4357static unsigned int
4358hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4359{
4360 return cea_mode_alternate_clock(hdmi_mode);
4361}
4362
4363static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4364 unsigned int clock_tolerance)
4365{
4366 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4367 u8 vic;
4368
4369 if (!to_match->clock)
4370 return 0;
4371
4372 if (to_match->picture_aspect_ratio)
4373 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4374
4375 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4376 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4377 unsigned int clock1, clock2;
4378
4379 /* Make sure to also match alternate clocks */
4380 clock1 = hdmi_mode->clock;
4381 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4382
4383 if (abs(to_match->clock - clock1) > clock_tolerance &&
4384 abs(to_match->clock - clock2) > clock_tolerance)
4385 continue;
4386
4387 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4388 return vic;
4389 }
4390
4391 return 0;
4392}
4393
4394/*
4395 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4396 * @to_match: display mode
4397 *
4398 * An HDMI mode is one defined in the HDMI vendor specific block.
4399 *
4400 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4401 */
4402static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4403{
4404 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4405 u8 vic;
4406
4407 if (!to_match->clock)
4408 return 0;
4409
4410 if (to_match->picture_aspect_ratio)
4411 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4412
4413 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4414 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4415 unsigned int clock1, clock2;
4416
4417 /* Make sure to also match alternate clocks */
4418 clock1 = hdmi_mode->clock;
4419 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4420
4421 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4422 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4423 drm_mode_match(to_match, hdmi_mode, match_flags))
4424 return vic;
4425 }
4426 return 0;
4427}
4428
4429static bool drm_valid_hdmi_vic(u8 vic)
4430{
4431 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4432}
4433
4434static int add_alternate_cea_modes(struct drm_connector *connector,
4435 const struct drm_edid *drm_edid)
4436{
4437 struct drm_device *dev = connector->dev;
4438 struct drm_display_mode *mode, *tmp;
4439 LIST_HEAD(list);
4440 int modes = 0;
4441
4442 /* Don't add CTA modes if the CTA extension block is missing */
4443 if (!drm_edid_has_cta_extension(drm_edid))
4444 return 0;
4445
4446 /*
4447 * Go through all probed modes and create a new mode
4448 * with the alternate clock for certain CEA modes.
4449 */
4450 list_for_each_entry(mode, &connector->probed_modes, head) {
4451 const struct drm_display_mode *cea_mode = NULL;
4452 struct drm_display_mode *newmode;
4453 u8 vic = drm_match_cea_mode(mode);
4454 unsigned int clock1, clock2;
4455
4456 if (drm_valid_cea_vic(vic)) {
4457 cea_mode = cea_mode_for_vic(vic);
4458 clock2 = cea_mode_alternate_clock(cea_mode);
4459 } else {
4460 vic = drm_match_hdmi_mode(mode);
4461 if (drm_valid_hdmi_vic(vic)) {
4462 cea_mode = &edid_4k_modes[vic];
4463 clock2 = hdmi_mode_alternate_clock(cea_mode);
4464 }
4465 }
4466
4467 if (!cea_mode)
4468 continue;
4469
4470 clock1 = cea_mode->clock;
4471
4472 if (clock1 == clock2)
4473 continue;
4474
4475 if (mode->clock != clock1 && mode->clock != clock2)
4476 continue;
4477
4478 newmode = drm_mode_duplicate(dev, cea_mode);
4479 if (!newmode)
4480 continue;
4481
4482 /* Carry over the stereo flags */
4483 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4484
4485 /*
4486 * The current mode could be either variant. Make
4487 * sure to pick the "other" clock for the new mode.
4488 */
4489 if (mode->clock != clock1)
4490 newmode->clock = clock1;
4491 else
4492 newmode->clock = clock2;
4493
4494 list_add_tail(&newmode->head, &list);
4495 }
4496
4497 list_for_each_entry_safe(mode, tmp, &list, head) {
4498 list_del(&mode->head);
4499 drm_mode_probed_add(connector, mode);
4500 modes++;
4501 }
4502
4503 return modes;
4504}
4505
4506static u8 svd_to_vic(u8 svd)
4507{
4508 /* 0-6 bit vic, 7th bit native mode indicator */
4509 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4510 return svd & 127;
4511
4512 return svd;
4513}
4514
4515/*
4516 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4517 * the EDID, or NULL on errors.
4518 */
4519static struct drm_display_mode *
4520drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4521{
4522 const struct drm_display_info *info = &connector->display_info;
4523 struct drm_device *dev = connector->dev;
4524
4525 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4526 return NULL;
4527
4528 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4529}
4530
4531/*
4532 * do_y420vdb_modes - Parse YCBCR 420 only modes
4533 * @connector: connector corresponding to the HDMI sink
4534 * @svds: start of the data block of CEA YCBCR 420 VDB
4535 * @len: length of the CEA YCBCR 420 VDB
4536 *
4537 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4538 * which contains modes which can be supported in YCBCR 420
4539 * output format only.
4540 */
4541static int do_y420vdb_modes(struct drm_connector *connector,
4542 const u8 *svds, u8 svds_len)
4543{
4544 struct drm_device *dev = connector->dev;
4545 int modes = 0, i;
4546
4547 for (i = 0; i < svds_len; i++) {
4548 u8 vic = svd_to_vic(svds[i]);
4549 struct drm_display_mode *newmode;
4550
4551 if (!drm_valid_cea_vic(vic))
4552 continue;
4553
4554 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4555 if (!newmode)
4556 break;
4557 drm_mode_probed_add(connector, newmode);
4558 modes++;
4559 }
4560
4561 return modes;
4562}
4563
4564/**
4565 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4566 * @dev: DRM device
4567 * @video_code: CEA VIC of the mode
4568 *
4569 * Creates a new mode matching the specified CEA VIC.
4570 *
4571 * Returns: A new drm_display_mode on success or NULL on failure
4572 */
4573struct drm_display_mode *
4574drm_display_mode_from_cea_vic(struct drm_device *dev,
4575 u8 video_code)
4576{
4577 const struct drm_display_mode *cea_mode;
4578 struct drm_display_mode *newmode;
4579
4580 cea_mode = cea_mode_for_vic(video_code);
4581 if (!cea_mode)
4582 return NULL;
4583
4584 newmode = drm_mode_duplicate(dev, cea_mode);
4585 if (!newmode)
4586 return NULL;
4587
4588 return newmode;
4589}
4590EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4591
4592/* Add modes based on VICs parsed in parse_cta_vdb() */
4593static int add_cta_vdb_modes(struct drm_connector *connector)
4594{
4595 const struct drm_display_info *info = &connector->display_info;
4596 int i, modes = 0;
4597
4598 if (!info->vics)
4599 return 0;
4600
4601 for (i = 0; i < info->vics_len; i++) {
4602 struct drm_display_mode *mode;
4603
4604 mode = drm_display_mode_from_vic_index(connector, i);
4605 if (mode) {
4606 drm_mode_probed_add(connector, mode);
4607 modes++;
4608 }
4609 }
4610
4611 return modes;
4612}
4613
4614struct stereo_mandatory_mode {
4615 int width, height, vrefresh;
4616 unsigned int flags;
4617};
4618
4619static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4620 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4621 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4622 { 1920, 1080, 50,
4623 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4624 { 1920, 1080, 60,
4625 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4626 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4627 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4628 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4629 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4630};
4631
4632static bool
4633stereo_match_mandatory(const struct drm_display_mode *mode,
4634 const struct stereo_mandatory_mode *stereo_mode)
4635{
4636 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4637
4638 return mode->hdisplay == stereo_mode->width &&
4639 mode->vdisplay == stereo_mode->height &&
4640 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4641 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4642}
4643
4644static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4645{
4646 struct drm_device *dev = connector->dev;
4647 const struct drm_display_mode *mode;
4648 struct list_head stereo_modes;
4649 int modes = 0, i;
4650
4651 INIT_LIST_HEAD(&stereo_modes);
4652
4653 list_for_each_entry(mode, &connector->probed_modes, head) {
4654 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4655 const struct stereo_mandatory_mode *mandatory;
4656 struct drm_display_mode *new_mode;
4657
4658 if (!stereo_match_mandatory(mode,
4659 &stereo_mandatory_modes[i]))
4660 continue;
4661
4662 mandatory = &stereo_mandatory_modes[i];
4663 new_mode = drm_mode_duplicate(dev, mode);
4664 if (!new_mode)
4665 continue;
4666
4667 new_mode->flags |= mandatory->flags;
4668 list_add_tail(&new_mode->head, &stereo_modes);
4669 modes++;
4670 }
4671 }
4672
4673 list_splice_tail(&stereo_modes, &connector->probed_modes);
4674
4675 return modes;
4676}
4677
4678static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4679{
4680 struct drm_device *dev = connector->dev;
4681 struct drm_display_mode *newmode;
4682
4683 if (!drm_valid_hdmi_vic(vic)) {
4684 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4685 connector->base.id, connector->name, vic);
4686 return 0;
4687 }
4688
4689 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4690 if (!newmode)
4691 return 0;
4692
4693 drm_mode_probed_add(connector, newmode);
4694
4695 return 1;
4696}
4697
4698static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4699 int vic_index)
4700{
4701 struct drm_display_mode *newmode;
4702 int modes = 0;
4703
4704 if (structure & (1 << 0)) {
4705 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4706 if (newmode) {
4707 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4708 drm_mode_probed_add(connector, newmode);
4709 modes++;
4710 }
4711 }
4712 if (structure & (1 << 6)) {
4713 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4714 if (newmode) {
4715 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4716 drm_mode_probed_add(connector, newmode);
4717 modes++;
4718 }
4719 }
4720 if (structure & (1 << 8)) {
4721 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4722 if (newmode) {
4723 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4724 drm_mode_probed_add(connector, newmode);
4725 modes++;
4726 }
4727 }
4728
4729 return modes;
4730}
4731
4732static bool hdmi_vsdb_latency_present(const u8 *db)
4733{
4734 return db[8] & BIT(7);
4735}
4736
4737static bool hdmi_vsdb_i_latency_present(const u8 *db)
4738{
4739 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4740}
4741
4742static int hdmi_vsdb_latency_length(const u8 *db)
4743{
4744 if (hdmi_vsdb_i_latency_present(db))
4745 return 4;
4746 else if (hdmi_vsdb_latency_present(db))
4747 return 2;
4748 else
4749 return 0;
4750}
4751
4752/*
4753 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4754 * @connector: connector corresponding to the HDMI sink
4755 * @db: start of the CEA vendor specific block
4756 * @len: length of the CEA block payload, ie. one can access up to db[len]
4757 *
4758 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4759 * also adds the stereo 3d modes when applicable.
4760 */
4761static int
4762do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4763{
4764 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4765 u8 vic_len, hdmi_3d_len = 0;
4766 u16 mask;
4767 u16 structure_all;
4768
4769 if (len < 8)
4770 goto out;
4771
4772 /* no HDMI_Video_Present */
4773 if (!(db[8] & (1 << 5)))
4774 goto out;
4775
4776 offset += hdmi_vsdb_latency_length(db);
4777
4778 /* the declared length is not long enough for the 2 first bytes
4779 * of additional video format capabilities */
4780 if (len < (8 + offset + 2))
4781 goto out;
4782
4783 /* 3D_Present */
4784 offset++;
4785 if (db[8 + offset] & (1 << 7)) {
4786 modes += add_hdmi_mandatory_stereo_modes(connector);
4787
4788 /* 3D_Multi_present */
4789 multi_present = (db[8 + offset] & 0x60) >> 5;
4790 }
4791
4792 offset++;
4793 vic_len = db[8 + offset] >> 5;
4794 hdmi_3d_len = db[8 + offset] & 0x1f;
4795
4796 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4797 u8 vic;
4798
4799 vic = db[9 + offset + i];
4800 modes += add_hdmi_mode(connector, vic);
4801 }
4802 offset += 1 + vic_len;
4803
4804 if (multi_present == 1)
4805 multi_len = 2;
4806 else if (multi_present == 2)
4807 multi_len = 4;
4808 else
4809 multi_len = 0;
4810
4811 if (len < (8 + offset + hdmi_3d_len - 1))
4812 goto out;
4813
4814 if (hdmi_3d_len < multi_len)
4815 goto out;
4816
4817 if (multi_present == 1 || multi_present == 2) {
4818 /* 3D_Structure_ALL */
4819 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4820
4821 /* check if 3D_MASK is present */
4822 if (multi_present == 2)
4823 mask = (db[10 + offset] << 8) | db[11 + offset];
4824 else
4825 mask = 0xffff;
4826
4827 for (i = 0; i < 16; i++) {
4828 if (mask & (1 << i))
4829 modes += add_3d_struct_modes(connector,
4830 structure_all, i);
4831 }
4832 }
4833
4834 offset += multi_len;
4835
4836 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4837 int vic_index;
4838 struct drm_display_mode *newmode = NULL;
4839 unsigned int newflag = 0;
4840 bool detail_present;
4841
4842 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4843
4844 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4845 break;
4846
4847 /* 2D_VIC_order_X */
4848 vic_index = db[8 + offset + i] >> 4;
4849
4850 /* 3D_Structure_X */
4851 switch (db[8 + offset + i] & 0x0f) {
4852 case 0:
4853 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4854 break;
4855 case 6:
4856 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4857 break;
4858 case 8:
4859 /* 3D_Detail_X */
4860 if ((db[9 + offset + i] >> 4) == 1)
4861 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4862 break;
4863 }
4864
4865 if (newflag != 0) {
4866 newmode = drm_display_mode_from_vic_index(connector,
4867 vic_index);
4868
4869 if (newmode) {
4870 newmode->flags |= newflag;
4871 drm_mode_probed_add(connector, newmode);
4872 modes++;
4873 }
4874 }
4875
4876 if (detail_present)
4877 i++;
4878 }
4879
4880out:
4881 return modes;
4882}
4883
4884static int
4885cea_revision(const u8 *cea)
4886{
4887 /*
4888 * FIXME is this correct for the DispID variant?
4889 * The DispID spec doesn't really specify whether
4890 * this is the revision of the CEA extension or
4891 * the DispID CEA data block. And the only value
4892 * given as an example is 0.
4893 */
4894 return cea[1];
4895}
4896
4897/*
4898 * CTA Data Block iterator.
4899 *
4900 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4901 * CTA Data Blocks.
4902 *
4903 * struct cea_db *db:
4904 * struct cea_db_iter iter;
4905 *
4906 * cea_db_iter_edid_begin(edid, &iter);
4907 * cea_db_iter_for_each(db, &iter) {
4908 * // do stuff with db
4909 * }
4910 * cea_db_iter_end(&iter);
4911 */
4912struct cea_db_iter {
4913 struct drm_edid_iter edid_iter;
4914 struct displayid_iter displayid_iter;
4915
4916 /* Current Data Block Collection. */
4917 const u8 *collection;
4918
4919 /* Current Data Block index in current collection. */
4920 int index;
4921
4922 /* End index in current collection. */
4923 int end;
4924};
4925
4926/* CTA-861-H section 7.4 CTA Data BLock Collection */
4927struct cea_db {
4928 u8 tag_length;
4929 u8 data[];
4930} __packed;
4931
4932static int cea_db_tag(const struct cea_db *db)
4933{
4934 return db->tag_length >> 5;
4935}
4936
4937static int cea_db_payload_len(const void *_db)
4938{
4939 /* FIXME: Transition to passing struct cea_db * everywhere. */
4940 const struct cea_db *db = _db;
4941
4942 return db->tag_length & 0x1f;
4943}
4944
4945static const void *cea_db_data(const struct cea_db *db)
4946{
4947 return db->data;
4948}
4949
4950static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4951{
4952 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4953 cea_db_payload_len(db) >= 1 &&
4954 db->data[0] == tag;
4955}
4956
4957static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4958{
4959 const u8 *data = cea_db_data(db);
4960
4961 return cea_db_tag(db) == CTA_DB_VENDOR &&
4962 cea_db_payload_len(db) >= 3 &&
4963 oui(data[2], data[1], data[0]) == vendor_oui;
4964}
4965
4966static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4967 struct cea_db_iter *iter)
4968{
4969 memset(iter, 0, sizeof(*iter));
4970
4971 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4972 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4973}
4974
4975static const struct cea_db *
4976__cea_db_iter_current_block(const struct cea_db_iter *iter)
4977{
4978 const struct cea_db *db;
4979
4980 if (!iter->collection)
4981 return NULL;
4982
4983 db = (const struct cea_db *)&iter->collection[iter->index];
4984
4985 if (iter->index + sizeof(*db) <= iter->end &&
4986 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4987 return db;
4988
4989 return NULL;
4990}
4991
4992/*
4993 * References:
4994 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4995 */
4996static int cea_db_collection_size(const u8 *cta)
4997{
4998 u8 d = cta[2];
4999
5000 if (d < 4 || d > 127)
5001 return 0;
5002
5003 return d - 4;
5004}
5005
5006/*
5007 * References:
5008 * - VESA E-EDID v1.4
5009 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5010 */
5011static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5012{
5013 const u8 *ext;
5014
5015 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5016 int size;
5017
5018 /* Only support CTA Extension revision 3+ */
5019 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5020 continue;
5021
5022 size = cea_db_collection_size(ext);
5023 if (!size)
5024 continue;
5025
5026 iter->index = 4;
5027 iter->end = iter->index + size;
5028
5029 return ext;
5030 }
5031
5032 return NULL;
5033}
5034
5035/*
5036 * References:
5037 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5038 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5039 *
5040 * Note that the above do not specify any connection between DisplayID Data
5041 * Block revision and CTA Extension versions.
5042 */
5043static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5044{
5045 const struct displayid_block *block;
5046
5047 displayid_iter_for_each(block, &iter->displayid_iter) {
5048 if (block->tag != DATA_BLOCK_CTA)
5049 continue;
5050
5051 /*
5052 * The displayid iterator has already verified the block bounds
5053 * in displayid_iter_block().
5054 */
5055 iter->index = sizeof(*block);
5056 iter->end = iter->index + block->num_bytes;
5057
5058 return block;
5059 }
5060
5061 return NULL;
5062}
5063
5064static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5065{
5066 const struct cea_db *db;
5067
5068 if (iter->collection) {
5069 /* Current collection should always be valid. */
5070 db = __cea_db_iter_current_block(iter);
5071 if (WARN_ON(!db)) {
5072 iter->collection = NULL;
5073 return NULL;
5074 }
5075
5076 /* Next block in CTA Data Block Collection */
5077 iter->index += sizeof(*db) + cea_db_payload_len(db);
5078
5079 db = __cea_db_iter_current_block(iter);
5080 if (db)
5081 return db;
5082 }
5083
5084 for (;;) {
5085 /*
5086 * Find the next CTA Data Block Collection. First iterate all
5087 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5088 *
5089 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5090 * Extension, it's recommended that DisplayID extensions are
5091 * exposed after all of the CTA Extensions.
5092 */
5093 iter->collection = __cea_db_iter_edid_next(iter);
5094 if (!iter->collection)
5095 iter->collection = __cea_db_iter_displayid_next(iter);
5096
5097 if (!iter->collection)
5098 return NULL;
5099
5100 db = __cea_db_iter_current_block(iter);
5101 if (db)
5102 return db;
5103 }
5104}
5105
5106#define cea_db_iter_for_each(__db, __iter) \
5107 while (((__db) = __cea_db_iter_next(__iter)))
5108
5109static void cea_db_iter_end(struct cea_db_iter *iter)
5110{
5111 displayid_iter_end(&iter->displayid_iter);
5112 drm_edid_iter_end(&iter->edid_iter);
5113
5114 memset(iter, 0, sizeof(*iter));
5115}
5116
5117static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5118{
5119 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5120 cea_db_payload_len(db) >= 5;
5121}
5122
5123static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5124{
5125 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5126 cea_db_payload_len(db) >= 7;
5127}
5128
5129static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5130{
5131 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5132 cea_db_payload_len(db) >= 2;
5133}
5134
5135static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5136{
5137 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5138 cea_db_payload_len(db) == 21;
5139}
5140
5141static bool cea_db_is_vcdb(const struct cea_db *db)
5142{
5143 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5144 cea_db_payload_len(db) == 2;
5145}
5146
5147static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5148{
5149 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5150 cea_db_payload_len(db) >= 7;
5151}
5152
5153static bool cea_db_is_y420cmdb(const struct cea_db *db)
5154{
5155 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5156}
5157
5158static bool cea_db_is_y420vdb(const struct cea_db *db)
5159{
5160 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5161}
5162
5163static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5164{
5165 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5166 cea_db_payload_len(db) >= 3;
5167}
5168
5169/*
5170 * Get the HF-EEODB override extension block count from EDID.
5171 *
5172 * The passed in EDID may be partially read, as long as it has at least two
5173 * blocks (base block and one extension block) if EDID extension count is > 0.
5174 *
5175 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5176 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5177 * iterators instead.
5178 *
5179 * References:
5180 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5181 */
5182static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5183{
5184 const u8 *cta;
5185
5186 /* No extensions according to base block, no HF-EEODB. */
5187 if (!edid_extension_block_count(edid))
5188 return 0;
5189
5190 /* HF-EEODB is always in the first EDID extension block only */
5191 cta = edid_extension_block_data(edid, 0);
5192 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5193 return 0;
5194
5195 /* Need to have the data block collection, and at least 3 bytes. */
5196 if (cea_db_collection_size(cta) < 3)
5197 return 0;
5198
5199 /*
5200 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5201 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5202 * through 6 of Block 1 of the E-EDID.
5203 */
5204 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5205 return 0;
5206
5207 return cta[4 + 2];
5208}
5209
5210/*
5211 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5212 *
5213 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5214 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5215 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5216 * support YCBCR420 output too.
5217 */
5218static void parse_cta_y420cmdb(struct drm_connector *connector,
5219 const struct cea_db *db, u64 *y420cmdb_map)
5220{
5221 struct drm_display_info *info = &connector->display_info;
5222 int i, map_len = cea_db_payload_len(db) - 1;
5223 const u8 *data = cea_db_data(db) + 1;
5224 u64 map = 0;
5225
5226 if (map_len == 0) {
5227 /* All CEA modes support ycbcr420 sampling also.*/
5228 map = U64_MAX;
5229 goto out;
5230 }
5231
5232 /*
5233 * This map indicates which of the existing CEA block modes
5234 * from VDB can support YCBCR420 output too. So if bit=0 is
5235 * set, first mode from VDB can support YCBCR420 output too.
5236 * We will parse and keep this map, before parsing VDB itself
5237 * to avoid going through the same block again and again.
5238 *
5239 * Spec is not clear about max possible size of this block.
5240 * Clamping max bitmap block size at 8 bytes. Every byte can
5241 * address 8 CEA modes, in this way this map can address
5242 * 8*8 = first 64 SVDs.
5243 */
5244 if (WARN_ON_ONCE(map_len > 8))
5245 map_len = 8;
5246
5247 for (i = 0; i < map_len; i++)
5248 map |= (u64)data[i] << (8 * i);
5249
5250out:
5251 if (map)
5252 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5253
5254 *y420cmdb_map = map;
5255}
5256
5257static int add_cea_modes(struct drm_connector *connector,
5258 const struct drm_edid *drm_edid)
5259{
5260 const struct cea_db *db;
5261 struct cea_db_iter iter;
5262 int modes;
5263
5264 /* CTA VDB block VICs parsed earlier */
5265 modes = add_cta_vdb_modes(connector);
5266
5267 cea_db_iter_edid_begin(drm_edid, &iter);
5268 cea_db_iter_for_each(db, &iter) {
5269 if (cea_db_is_hdmi_vsdb(db)) {
5270 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5271 cea_db_payload_len(db));
5272 } else if (cea_db_is_y420vdb(db)) {
5273 const u8 *vdb420 = cea_db_data(db) + 1;
5274
5275 /* Add 4:2:0(only) modes present in EDID */
5276 modes += do_y420vdb_modes(connector, vdb420,
5277 cea_db_payload_len(db) - 1);
5278 }
5279 }
5280 cea_db_iter_end(&iter);
5281
5282 return modes;
5283}
5284
5285static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5286 struct drm_display_mode *mode)
5287{
5288 const struct drm_display_mode *cea_mode;
5289 int clock1, clock2, clock;
5290 u8 vic;
5291 const char *type;
5292
5293 /*
5294 * allow 5kHz clock difference either way to account for
5295 * the 10kHz clock resolution limit of detailed timings.
5296 */
5297 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5298 if (drm_valid_cea_vic(vic)) {
5299 type = "CEA";
5300 cea_mode = cea_mode_for_vic(vic);
5301 clock1 = cea_mode->clock;
5302 clock2 = cea_mode_alternate_clock(cea_mode);
5303 } else {
5304 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5305 if (drm_valid_hdmi_vic(vic)) {
5306 type = "HDMI";
5307 cea_mode = &edid_4k_modes[vic];
5308 clock1 = cea_mode->clock;
5309 clock2 = hdmi_mode_alternate_clock(cea_mode);
5310 } else {
5311 return;
5312 }
5313 }
5314
5315 /* pick whichever is closest */
5316 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5317 clock = clock1;
5318 else
5319 clock = clock2;
5320
5321 if (mode->clock == clock)
5322 return;
5323
5324 drm_dbg_kms(connector->dev,
5325 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5326 connector->base.id, connector->name,
5327 type, vic, mode->clock, clock);
5328 mode->clock = clock;
5329}
5330
5331static void drm_calculate_luminance_range(struct drm_connector *connector)
5332{
5333 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5334 struct drm_luminance_range_info *luminance_range =
5335 &connector->display_info.luminance_range;
5336 static const u8 pre_computed_values[] = {
5337 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5338 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5339 };
5340 u32 max_avg, min_cll, max, min, q, r;
5341
5342 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5343 return;
5344
5345 max_avg = hdr_metadata->max_fall;
5346 min_cll = hdr_metadata->min_cll;
5347
5348 /*
5349 * From the specification (CTA-861-G), for calculating the maximum
5350 * luminance we need to use:
5351 * Luminance = 50*2**(CV/32)
5352 * Where CV is a one-byte value.
5353 * For calculating this expression we may need float point precision;
5354 * to avoid this complexity level, we take advantage that CV is divided
5355 * by a constant. From the Euclids division algorithm, we know that CV
5356 * can be written as: CV = 32*q + r. Next, we replace CV in the
5357 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5358 * need to pre-compute the value of r/32. For pre-computing the values
5359 * We just used the following Ruby line:
5360 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5361 * The results of the above expressions can be verified at
5362 * pre_computed_values.
5363 */
5364 q = max_avg >> 5;
5365 r = max_avg % 32;
5366 max = (1 << q) * pre_computed_values[r];
5367
5368 /* min luminance: maxLum * (CV/255)^2 / 100 */
5369 q = DIV_ROUND_CLOSEST(min_cll, 255);
5370 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5371
5372 luminance_range->min_luminance = min;
5373 luminance_range->max_luminance = max;
5374}
5375
5376static uint8_t eotf_supported(const u8 *edid_ext)
5377{
5378 return edid_ext[2] &
5379 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5380 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5381 BIT(HDMI_EOTF_SMPTE_ST2084) |
5382 BIT(HDMI_EOTF_BT_2100_HLG));
5383}
5384
5385static uint8_t hdr_metadata_type(const u8 *edid_ext)
5386{
5387 return edid_ext[3] &
5388 BIT(HDMI_STATIC_METADATA_TYPE1);
5389}
5390
5391static void
5392drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5393{
5394 u16 len;
5395
5396 len = cea_db_payload_len(db);
5397
5398 connector->hdr_sink_metadata.hdmi_type1.eotf =
5399 eotf_supported(db);
5400 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5401 hdr_metadata_type(db);
5402
5403 if (len >= 4)
5404 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5405 if (len >= 5)
5406 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5407 if (len >= 6) {
5408 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5409
5410 /* Calculate only when all values are available */
5411 drm_calculate_luminance_range(connector);
5412 }
5413}
5414
5415/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5416static void
5417drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5418{
5419 u8 len = cea_db_payload_len(db);
5420
5421 if (len >= 6 && (db[6] & (1 << 7)))
5422 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5423
5424 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5425 connector->latency_present[0] = true;
5426 connector->video_latency[0] = db[9];
5427 connector->audio_latency[0] = db[10];
5428 }
5429
5430 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5431 connector->latency_present[1] = true;
5432 connector->video_latency[1] = db[11];
5433 connector->audio_latency[1] = db[12];
5434 }
5435
5436 drm_dbg_kms(connector->dev,
5437 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5438 connector->base.id, connector->name,
5439 connector->latency_present[0], connector->latency_present[1],
5440 connector->video_latency[0], connector->video_latency[1],
5441 connector->audio_latency[0], connector->audio_latency[1]);
5442}
5443
5444static void
5445monitor_name(const struct detailed_timing *timing, void *data)
5446{
5447 const char **res = data;
5448
5449 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5450 return;
5451
5452 *res = timing->data.other_data.data.str.str;
5453}
5454
5455static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5456{
5457 const char *edid_name = NULL;
5458 int mnl;
5459
5460 if (!drm_edid || !name)
5461 return 0;
5462
5463 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5464 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5465 if (edid_name[mnl] == 0x0a)
5466 break;
5467
5468 name[mnl] = edid_name[mnl];
5469 }
5470
5471 return mnl;
5472}
5473
5474/**
5475 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5476 * @edid: monitor EDID information
5477 * @name: pointer to a character array to hold the name of the monitor
5478 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5479 *
5480 */
5481void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5482{
5483 int name_length = 0;
5484
5485 if (bufsize <= 0)
5486 return;
5487
5488 if (edid) {
5489 char buf[13];
5490 struct drm_edid drm_edid = {
5491 .edid = edid,
5492 .size = edid_size(edid),
5493 };
5494
5495 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5496 memcpy(name, buf, name_length);
5497 }
5498
5499 name[name_length] = '\0';
5500}
5501EXPORT_SYMBOL(drm_edid_get_monitor_name);
5502
5503static void clear_eld(struct drm_connector *connector)
5504{
5505 memset(connector->eld, 0, sizeof(connector->eld));
5506
5507 connector->latency_present[0] = false;
5508 connector->latency_present[1] = false;
5509 connector->video_latency[0] = 0;
5510 connector->audio_latency[0] = 0;
5511 connector->video_latency[1] = 0;
5512 connector->audio_latency[1] = 0;
5513}
5514
5515/*
5516 * Get 3-byte SAD buffer from struct cea_sad.
5517 */
5518void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5519{
5520 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5521 sad[1] = cta_sad->freq;
5522 sad[2] = cta_sad->byte2;
5523}
5524
5525/*
5526 * Set struct cea_sad from 3-byte SAD buffer.
5527 */
5528void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5529{
5530 cta_sad->format = (sad[0] & 0x78) >> 3;
5531 cta_sad->channels = sad[0] & 0x07;
5532 cta_sad->freq = sad[1] & 0x7f;
5533 cta_sad->byte2 = sad[2];
5534}
5535
5536/*
5537 * drm_edid_to_eld - build ELD from EDID
5538 * @connector: connector corresponding to the HDMI/DP sink
5539 * @drm_edid: EDID to parse
5540 *
5541 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5542 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5543 */
5544static void drm_edid_to_eld(struct drm_connector *connector,
5545 const struct drm_edid *drm_edid)
5546{
5547 const struct drm_display_info *info = &connector->display_info;
5548 const struct cea_db *db;
5549 struct cea_db_iter iter;
5550 uint8_t *eld = connector->eld;
5551 int total_sad_count = 0;
5552 int mnl;
5553
5554 if (!drm_edid)
5555 return;
5556
5557 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5558 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5559 connector->base.id, connector->name,
5560 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5561
5562 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5563 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5564
5565 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5566
5567 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5568 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5569 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5570 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5571
5572 cea_db_iter_edid_begin(drm_edid, &iter);
5573 cea_db_iter_for_each(db, &iter) {
5574 const u8 *data = cea_db_data(db);
5575 int len = cea_db_payload_len(db);
5576 int sad_count;
5577
5578 switch (cea_db_tag(db)) {
5579 case CTA_DB_AUDIO:
5580 /* Audio Data Block, contains SADs */
5581 sad_count = min(len / 3, 15 - total_sad_count);
5582 if (sad_count >= 1)
5583 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5584 data, sad_count * 3);
5585 total_sad_count += sad_count;
5586 break;
5587 case CTA_DB_SPEAKER:
5588 /* Speaker Allocation Data Block */
5589 if (len >= 1)
5590 eld[DRM_ELD_SPEAKER] = data[0];
5591 break;
5592 case CTA_DB_VENDOR:
5593 /* HDMI Vendor-Specific Data Block */
5594 if (cea_db_is_hdmi_vsdb(db))
5595 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5596 break;
5597 default:
5598 break;
5599 }
5600 }
5601 cea_db_iter_end(&iter);
5602
5603 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5604
5605 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5606 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5607 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5608 else
5609 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5610
5611 eld[DRM_ELD_BASELINE_ELD_LEN] =
5612 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5613
5614 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5615 connector->base.id, connector->name,
5616 drm_eld_size(eld), total_sad_count);
5617}
5618
5619static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5620 struct cea_sad **psads)
5621{
5622 const struct cea_db *db;
5623 struct cea_db_iter iter;
5624 int count = 0;
5625
5626 cea_db_iter_edid_begin(drm_edid, &iter);
5627 cea_db_iter_for_each(db, &iter) {
5628 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5629 struct cea_sad *sads;
5630 int i;
5631
5632 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5633 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5634 *psads = sads;
5635 if (!sads)
5636 return -ENOMEM;
5637 for (i = 0; i < count; i++)
5638 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5639 break;
5640 }
5641 }
5642 cea_db_iter_end(&iter);
5643
5644 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5645
5646 return count;
5647}
5648
5649/**
5650 * drm_edid_to_sad - extracts SADs from EDID
5651 * @edid: EDID to parse
5652 * @sads: pointer that will be set to the extracted SADs
5653 *
5654 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5655 *
5656 * Note: The returned pointer needs to be freed using kfree().
5657 *
5658 * Return: The number of found SADs or negative number on error.
5659 */
5660int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5661{
5662 struct drm_edid drm_edid;
5663
5664 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5665}
5666EXPORT_SYMBOL(drm_edid_to_sad);
5667
5668static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5669 u8 **sadb)
5670{
5671 const struct cea_db *db;
5672 struct cea_db_iter iter;
5673 int count = 0;
5674
5675 cea_db_iter_edid_begin(drm_edid, &iter);
5676 cea_db_iter_for_each(db, &iter) {
5677 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5678 cea_db_payload_len(db) == 3) {
5679 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5680 GFP_KERNEL);
5681 if (!*sadb)
5682 return -ENOMEM;
5683 count = cea_db_payload_len(db);
5684 break;
5685 }
5686 }
5687 cea_db_iter_end(&iter);
5688
5689 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5690
5691 return count;
5692}
5693
5694/**
5695 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5696 * @edid: EDID to parse
5697 * @sadb: pointer to the speaker block
5698 *
5699 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5700 *
5701 * Note: The returned pointer needs to be freed using kfree().
5702 *
5703 * Return: The number of found Speaker Allocation Blocks or negative number on
5704 * error.
5705 */
5706int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5707{
5708 struct drm_edid drm_edid;
5709
5710 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5711 sadb);
5712}
5713EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5714
5715/**
5716 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5717 * @connector: connector associated with the HDMI/DP sink
5718 * @mode: the display mode
5719 *
5720 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5721 * the sink doesn't support audio or video.
5722 */
5723int drm_av_sync_delay(struct drm_connector *connector,
5724 const struct drm_display_mode *mode)
5725{
5726 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5727 int a, v;
5728
5729 if (!connector->latency_present[0])
5730 return 0;
5731 if (!connector->latency_present[1])
5732 i = 0;
5733
5734 a = connector->audio_latency[i];
5735 v = connector->video_latency[i];
5736
5737 /*
5738 * HDMI/DP sink doesn't support audio or video?
5739 */
5740 if (a == 255 || v == 255)
5741 return 0;
5742
5743 /*
5744 * Convert raw EDID values to millisecond.
5745 * Treat unknown latency as 0ms.
5746 */
5747 if (a)
5748 a = min(2 * (a - 1), 500);
5749 if (v)
5750 v = min(2 * (v - 1), 500);
5751
5752 return max(v - a, 0);
5753}
5754EXPORT_SYMBOL(drm_av_sync_delay);
5755
5756static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5757{
5758 const struct cea_db *db;
5759 struct cea_db_iter iter;
5760 bool hdmi = false;
5761
5762 /*
5763 * Because HDMI identifier is in Vendor Specific Block,
5764 * search it from all data blocks of CEA extension.
5765 */
5766 cea_db_iter_edid_begin(drm_edid, &iter);
5767 cea_db_iter_for_each(db, &iter) {
5768 if (cea_db_is_hdmi_vsdb(db)) {
5769 hdmi = true;
5770 break;
5771 }
5772 }
5773 cea_db_iter_end(&iter);
5774
5775 return hdmi;
5776}
5777
5778/**
5779 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5780 * @edid: monitor EDID information
5781 *
5782 * Parse the CEA extension according to CEA-861-B.
5783 *
5784 * Drivers that have added the modes parsed from EDID to drm_display_info
5785 * should use &drm_display_info.is_hdmi instead of calling this function.
5786 *
5787 * Return: True if the monitor is HDMI, false if not or unknown.
5788 */
5789bool drm_detect_hdmi_monitor(const struct edid *edid)
5790{
5791 struct drm_edid drm_edid;
5792
5793 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5794}
5795EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5796
5797static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5798{
5799 struct drm_edid_iter edid_iter;
5800 const struct cea_db *db;
5801 struct cea_db_iter iter;
5802 const u8 *edid_ext;
5803 bool has_audio = false;
5804
5805 drm_edid_iter_begin(drm_edid, &edid_iter);
5806 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5807 if (edid_ext[0] == CEA_EXT) {
5808 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5809 if (has_audio)
5810 break;
5811 }
5812 }
5813 drm_edid_iter_end(&edid_iter);
5814
5815 if (has_audio) {
5816 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5817 goto end;
5818 }
5819
5820 cea_db_iter_edid_begin(drm_edid, &iter);
5821 cea_db_iter_for_each(db, &iter) {
5822 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5823 const u8 *data = cea_db_data(db);
5824 int i;
5825
5826 for (i = 0; i < cea_db_payload_len(db); i += 3)
5827 DRM_DEBUG_KMS("CEA audio format %d\n",
5828 (data[i] >> 3) & 0xf);
5829 has_audio = true;
5830 break;
5831 }
5832 }
5833 cea_db_iter_end(&iter);
5834
5835end:
5836 return has_audio;
5837}
5838
5839/**
5840 * drm_detect_monitor_audio - check monitor audio capability
5841 * @edid: EDID block to scan
5842 *
5843 * Monitor should have CEA extension block.
5844 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5845 * audio' only. If there is any audio extension block and supported
5846 * audio format, assume at least 'basic audio' support, even if 'basic
5847 * audio' is not defined in EDID.
5848 *
5849 * Return: True if the monitor supports audio, false otherwise.
5850 */
5851bool drm_detect_monitor_audio(const struct edid *edid)
5852{
5853 struct drm_edid drm_edid;
5854
5855 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5856}
5857EXPORT_SYMBOL(drm_detect_monitor_audio);
5858
5859
5860/**
5861 * drm_default_rgb_quant_range - default RGB quantization range
5862 * @mode: display mode
5863 *
5864 * Determine the default RGB quantization range for the mode,
5865 * as specified in CEA-861.
5866 *
5867 * Return: The default RGB quantization range for the mode
5868 */
5869enum hdmi_quantization_range
5870drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5871{
5872 /* All CEA modes other than VIC 1 use limited quantization range. */
5873 return drm_match_cea_mode(mode) > 1 ?
5874 HDMI_QUANTIZATION_RANGE_LIMITED :
5875 HDMI_QUANTIZATION_RANGE_FULL;
5876}
5877EXPORT_SYMBOL(drm_default_rgb_quant_range);
5878
5879/* CTA-861 Video Data Block (CTA VDB) */
5880static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5881{
5882 struct drm_display_info *info = &connector->display_info;
5883 int i, vic_index, len = cea_db_payload_len(db);
5884 const u8 *svds = cea_db_data(db);
5885 u8 *vics;
5886
5887 if (!len)
5888 return;
5889
5890 /* Gracefully handle multiple VDBs, however unlikely that is */
5891 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5892 if (!vics)
5893 return;
5894
5895 vic_index = info->vics_len;
5896 info->vics_len += len;
5897 info->vics = vics;
5898
5899 for (i = 0; i < len; i++) {
5900 u8 vic = svd_to_vic(svds[i]);
5901
5902 if (!drm_valid_cea_vic(vic))
5903 vic = 0;
5904
5905 info->vics[vic_index++] = vic;
5906 }
5907}
5908
5909/*
5910 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5911 *
5912 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5913 * using the VICs themselves.
5914 */
5915static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5916{
5917 struct drm_display_info *info = &connector->display_info;
5918 struct drm_hdmi_info *hdmi = &info->hdmi;
5919 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5920
5921 for (i = 0; i < len; i++) {
5922 u8 vic = info->vics[i];
5923
5924 if (vic && y420cmdb_map & BIT_ULL(i))
5925 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5926 }
5927}
5928
5929static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5930{
5931 const struct drm_display_info *info = &connector->display_info;
5932 int i;
5933
5934 if (!vic || !info->vics)
5935 return false;
5936
5937 for (i = 0; i < info->vics_len; i++) {
5938 if (info->vics[i] == vic)
5939 return true;
5940 }
5941
5942 return false;
5943}
5944
5945/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5946static void parse_cta_y420vdb(struct drm_connector *connector,
5947 const struct cea_db *db)
5948{
5949 struct drm_display_info *info = &connector->display_info;
5950 struct drm_hdmi_info *hdmi = &info->hdmi;
5951 const u8 *svds = cea_db_data(db) + 1;
5952 int i;
5953
5954 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5955 u8 vic = svd_to_vic(svds[i]);
5956
5957 if (!drm_valid_cea_vic(vic))
5958 continue;
5959
5960 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5961 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5962 }
5963}
5964
5965static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5966{
5967 struct drm_display_info *info = &connector->display_info;
5968
5969 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5970 connector->base.id, connector->name, db[2]);
5971
5972 if (db[2] & EDID_CEA_VCDB_QS)
5973 info->rgb_quant_range_selectable = true;
5974}
5975
5976static
5977void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5978{
5979 switch (max_frl_rate) {
5980 case 1:
5981 *max_lanes = 3;
5982 *max_rate_per_lane = 3;
5983 break;
5984 case 2:
5985 *max_lanes = 3;
5986 *max_rate_per_lane = 6;
5987 break;
5988 case 3:
5989 *max_lanes = 4;
5990 *max_rate_per_lane = 6;
5991 break;
5992 case 4:
5993 *max_lanes = 4;
5994 *max_rate_per_lane = 8;
5995 break;
5996 case 5:
5997 *max_lanes = 4;
5998 *max_rate_per_lane = 10;
5999 break;
6000 case 6:
6001 *max_lanes = 4;
6002 *max_rate_per_lane = 12;
6003 break;
6004 case 0:
6005 default:
6006 *max_lanes = 0;
6007 *max_rate_per_lane = 0;
6008 }
6009}
6010
6011static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6012 const u8 *db)
6013{
6014 u8 dc_mask;
6015 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6016
6017 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6018 hdmi->y420_dc_modes = dc_mask;
6019}
6020
6021static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6022 const u8 *hf_scds)
6023{
6024 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6025
6026 if (!hdmi_dsc->v_1p2)
6027 return;
6028
6029 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6030 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6031
6032 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6033 hdmi_dsc->bpc_supported = 16;
6034 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6035 hdmi_dsc->bpc_supported = 12;
6036 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6037 hdmi_dsc->bpc_supported = 10;
6038 else
6039 /* Supports min 8 BPC if DSC 1.2 is supported*/
6040 hdmi_dsc->bpc_supported = 8;
6041
6042 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6043 u8 dsc_max_slices;
6044 u8 dsc_max_frl_rate;
6045
6046 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6047 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6048 &hdmi_dsc->max_frl_rate_per_lane);
6049
6050 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6051
6052 switch (dsc_max_slices) {
6053 case 1:
6054 hdmi_dsc->max_slices = 1;
6055 hdmi_dsc->clk_per_slice = 340;
6056 break;
6057 case 2:
6058 hdmi_dsc->max_slices = 2;
6059 hdmi_dsc->clk_per_slice = 340;
6060 break;
6061 case 3:
6062 hdmi_dsc->max_slices = 4;
6063 hdmi_dsc->clk_per_slice = 340;
6064 break;
6065 case 4:
6066 hdmi_dsc->max_slices = 8;
6067 hdmi_dsc->clk_per_slice = 340;
6068 break;
6069 case 5:
6070 hdmi_dsc->max_slices = 8;
6071 hdmi_dsc->clk_per_slice = 400;
6072 break;
6073 case 6:
6074 hdmi_dsc->max_slices = 12;
6075 hdmi_dsc->clk_per_slice = 400;
6076 break;
6077 case 7:
6078 hdmi_dsc->max_slices = 16;
6079 hdmi_dsc->clk_per_slice = 400;
6080 break;
6081 case 0:
6082 default:
6083 hdmi_dsc->max_slices = 0;
6084 hdmi_dsc->clk_per_slice = 0;
6085 }
6086 }
6087
6088 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6089 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6090}
6091
6092/* Sink Capability Data Structure */
6093static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6094 const u8 *hf_scds)
6095{
6096 struct drm_display_info *info = &connector->display_info;
6097 struct drm_hdmi_info *hdmi = &info->hdmi;
6098 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6099 int max_tmds_clock = 0;
6100 u8 max_frl_rate = 0;
6101 bool dsc_support = false;
6102
6103 info->has_hdmi_infoframe = true;
6104
6105 if (hf_scds[6] & 0x80) {
6106 hdmi->scdc.supported = true;
6107 if (hf_scds[6] & 0x40)
6108 hdmi->scdc.read_request = true;
6109 }
6110
6111 /*
6112 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6113 * And as per the spec, three factors confirm this:
6114 * * Availability of a HF-VSDB block in EDID (check)
6115 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6116 * * SCDC support available (let's check)
6117 * Lets check it out.
6118 */
6119
6120 if (hf_scds[5]) {
6121 struct drm_scdc *scdc = &hdmi->scdc;
6122
6123 /* max clock is 5000 KHz times block value */
6124 max_tmds_clock = hf_scds[5] * 5000;
6125
6126 if (max_tmds_clock > 340000) {
6127 info->max_tmds_clock = max_tmds_clock;
6128 }
6129
6130 if (scdc->supported) {
6131 scdc->scrambling.supported = true;
6132
6133 /* Few sinks support scrambling for clocks < 340M */
6134 if ((hf_scds[6] & 0x8))
6135 scdc->scrambling.low_rates = true;
6136 }
6137 }
6138
6139 if (hf_scds[7]) {
6140 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6141 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6142 &hdmi->max_frl_rate_per_lane);
6143 }
6144
6145 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6146
6147 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6148 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6149 dsc_support = true;
6150 }
6151
6152 drm_dbg_kms(connector->dev,
6153 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6154 connector->base.id, connector->name,
6155 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6156}
6157
6158static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6159 const u8 *hdmi)
6160{
6161 struct drm_display_info *info = &connector->display_info;
6162 unsigned int dc_bpc = 0;
6163
6164 /* HDMI supports at least 8 bpc */
6165 info->bpc = 8;
6166
6167 if (cea_db_payload_len(hdmi) < 6)
6168 return;
6169
6170 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6171 dc_bpc = 10;
6172 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6173 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6174 connector->base.id, connector->name);
6175 }
6176
6177 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6178 dc_bpc = 12;
6179 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6180 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6181 connector->base.id, connector->name);
6182 }
6183
6184 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6185 dc_bpc = 16;
6186 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6187 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6188 connector->base.id, connector->name);
6189 }
6190
6191 if (dc_bpc == 0) {
6192 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6193 connector->base.id, connector->name);
6194 return;
6195 }
6196
6197 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6198 connector->base.id, connector->name, dc_bpc);
6199 info->bpc = dc_bpc;
6200
6201 /* YCRCB444 is optional according to spec. */
6202 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6203 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6204 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6205 connector->base.id, connector->name);
6206 }
6207
6208 /*
6209 * Spec says that if any deep color mode is supported at all,
6210 * then deep color 36 bit must be supported.
6211 */
6212 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6214 connector->base.id, connector->name);
6215 }
6216}
6217
6218/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6219static void
6220drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6221{
6222 struct drm_display_info *info = &connector->display_info;
6223 u8 len = cea_db_payload_len(db);
6224
6225 info->is_hdmi = true;
6226
6227 info->source_physical_address = (db[4] << 8) | db[5];
6228
6229 if (len >= 6)
6230 info->dvi_dual = db[6] & 1;
6231 if (len >= 7)
6232 info->max_tmds_clock = db[7] * 5000;
6233
6234 /*
6235 * Try to infer whether the sink supports HDMI infoframes.
6236 *
6237 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6238 * supports infoframes if HDMI_Video_present is set.
6239 */
6240 if (len >= 8 && db[8] & BIT(5))
6241 info->has_hdmi_infoframe = true;
6242
6243 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6244 connector->base.id, connector->name,
6245 info->dvi_dual, info->max_tmds_clock);
6246
6247 drm_parse_hdmi_deep_color_info(connector, db);
6248}
6249
6250/*
6251 * See EDID extension for head-mounted and specialized monitors, specified at:
6252 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6253 */
6254static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6255 const u8 *db)
6256{
6257 struct drm_display_info *info = &connector->display_info;
6258 u8 version = db[4];
6259 bool desktop_usage = db[5] & BIT(6);
6260
6261 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6262 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6263 info->non_desktop = true;
6264
6265 drm_dbg_kms(connector->dev,
6266 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6267 connector->base.id, connector->name, version, db[5]);
6268}
6269
6270static void drm_parse_cea_ext(struct drm_connector *connector,
6271 const struct drm_edid *drm_edid)
6272{
6273 struct drm_display_info *info = &connector->display_info;
6274 struct drm_edid_iter edid_iter;
6275 const struct cea_db *db;
6276 struct cea_db_iter iter;
6277 const u8 *edid_ext;
6278 u64 y420cmdb_map = 0;
6279
6280 drm_edid_iter_begin(drm_edid, &edid_iter);
6281 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6282 if (edid_ext[0] != CEA_EXT)
6283 continue;
6284
6285 if (!info->cea_rev)
6286 info->cea_rev = edid_ext[1];
6287
6288 if (info->cea_rev != edid_ext[1])
6289 drm_dbg_kms(connector->dev,
6290 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6291 connector->base.id, connector->name,
6292 info->cea_rev, edid_ext[1]);
6293
6294 /* The existence of a CTA extension should imply RGB support */
6295 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6296 if (edid_ext[3] & EDID_CEA_YCRCB444)
6297 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6298 if (edid_ext[3] & EDID_CEA_YCRCB422)
6299 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6300 if (edid_ext[3] & EDID_BASIC_AUDIO)
6301 info->has_audio = true;
6302
6303 }
6304 drm_edid_iter_end(&edid_iter);
6305
6306 cea_db_iter_edid_begin(drm_edid, &iter);
6307 cea_db_iter_for_each(db, &iter) {
6308 /* FIXME: convert parsers to use struct cea_db */
6309 const u8 *data = (const u8 *)db;
6310
6311 if (cea_db_is_hdmi_vsdb(db))
6312 drm_parse_hdmi_vsdb_video(connector, data);
6313 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6314 cea_db_is_hdmi_forum_scdb(db))
6315 drm_parse_hdmi_forum_scds(connector, data);
6316 else if (cea_db_is_microsoft_vsdb(db))
6317 drm_parse_microsoft_vsdb(connector, data);
6318 else if (cea_db_is_y420cmdb(db))
6319 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6320 else if (cea_db_is_y420vdb(db))
6321 parse_cta_y420vdb(connector, db);
6322 else if (cea_db_is_vcdb(db))
6323 drm_parse_vcdb(connector, data);
6324 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6325 drm_parse_hdr_metadata_block(connector, data);
6326 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6327 parse_cta_vdb(connector, db);
6328 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6329 info->has_audio = true;
6330 }
6331 cea_db_iter_end(&iter);
6332
6333 if (y420cmdb_map)
6334 update_cta_y420cmdb(connector, y420cmdb_map);
6335}
6336
6337static
6338void get_monitor_range(const struct detailed_timing *timing, void *c)
6339{
6340 struct detailed_mode_closure *closure = c;
6341 struct drm_display_info *info = &closure->connector->display_info;
6342 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6343 const struct detailed_non_pixel *data = &timing->data.other_data;
6344 const struct detailed_data_monitor_range *range = &data->data.range;
6345 const struct edid *edid = closure->drm_edid->edid;
6346
6347 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6348 return;
6349
6350 /*
6351 * These limits are used to determine the VRR refresh
6352 * rate range. Only the "range limits only" variant
6353 * of the range descriptor seems to guarantee that
6354 * any and all timings are accepted by the sink, as
6355 * opposed to just timings conforming to the indicated
6356 * formula (GTF/GTF2/CVT). Thus other variants of the
6357 * range descriptor are not accepted here.
6358 */
6359 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6360 return;
6361
6362 monitor_range->min_vfreq = range->min_vfreq;
6363 monitor_range->max_vfreq = range->max_vfreq;
6364
6365 if (edid->revision >= 4) {
6366 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6367 monitor_range->min_vfreq += 255;
6368 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6369 monitor_range->max_vfreq += 255;
6370 }
6371}
6372
6373static void drm_get_monitor_range(struct drm_connector *connector,
6374 const struct drm_edid *drm_edid)
6375{
6376 const struct drm_display_info *info = &connector->display_info;
6377 struct detailed_mode_closure closure = {
6378 .connector = connector,
6379 .drm_edid = drm_edid,
6380 };
6381
6382 if (drm_edid->edid->revision < 4)
6383 return;
6384
6385 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6386 return;
6387
6388 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6389
6390 drm_dbg_kms(connector->dev,
6391 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6392 connector->base.id, connector->name,
6393 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6394}
6395
6396static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6397 const struct displayid_block *block)
6398{
6399 struct displayid_vesa_vendor_specific_block *vesa =
6400 (struct displayid_vesa_vendor_specific_block *)block;
6401 struct drm_display_info *info = &connector->display_info;
6402
6403 if (block->num_bytes < 3) {
6404 drm_dbg_kms(connector->dev,
6405 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6406 connector->base.id, connector->name, block->num_bytes);
6407 return;
6408 }
6409
6410 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6411 return;
6412
6413 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6414 drm_dbg_kms(connector->dev,
6415 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6416 connector->base.id, connector->name);
6417 return;
6418 }
6419
6420 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6421 default:
6422 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6423 connector->base.id, connector->name);
6424 fallthrough;
6425 case 0:
6426 info->mso_stream_count = 0;
6427 break;
6428 case 1:
6429 info->mso_stream_count = 2; /* 2 or 4 links */
6430 break;
6431 case 2:
6432 info->mso_stream_count = 4; /* 4 links */
6433 break;
6434 }
6435
6436 if (!info->mso_stream_count) {
6437 info->mso_pixel_overlap = 0;
6438 return;
6439 }
6440
6441 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6442 if (info->mso_pixel_overlap > 8) {
6443 drm_dbg_kms(connector->dev,
6444 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6445 connector->base.id, connector->name,
6446 info->mso_pixel_overlap);
6447 info->mso_pixel_overlap = 8;
6448 }
6449
6450 drm_dbg_kms(connector->dev,
6451 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6452 connector->base.id, connector->name,
6453 info->mso_stream_count, info->mso_pixel_overlap);
6454}
6455
6456static void drm_update_mso(struct drm_connector *connector,
6457 const struct drm_edid *drm_edid)
6458{
6459 const struct displayid_block *block;
6460 struct displayid_iter iter;
6461
6462 displayid_iter_edid_begin(drm_edid, &iter);
6463 displayid_iter_for_each(block, &iter) {
6464 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6465 drm_parse_vesa_mso_data(connector, block);
6466 }
6467 displayid_iter_end(&iter);
6468}
6469
6470/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6471 * all of the values which would have been set from EDID
6472 */
6473static void drm_reset_display_info(struct drm_connector *connector)
6474{
6475 struct drm_display_info *info = &connector->display_info;
6476
6477 info->width_mm = 0;
6478 info->height_mm = 0;
6479
6480 info->bpc = 0;
6481 info->color_formats = 0;
6482 info->cea_rev = 0;
6483 info->max_tmds_clock = 0;
6484 info->dvi_dual = false;
6485 info->is_hdmi = false;
6486 info->has_audio = false;
6487 info->has_hdmi_infoframe = false;
6488 info->rgb_quant_range_selectable = false;
6489 memset(&info->hdmi, 0, sizeof(info->hdmi));
6490
6491 info->edid_hdmi_rgb444_dc_modes = 0;
6492 info->edid_hdmi_ycbcr444_dc_modes = 0;
6493
6494 info->non_desktop = 0;
6495 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6496 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6497
6498 info->mso_stream_count = 0;
6499 info->mso_pixel_overlap = 0;
6500 info->max_dsc_bpp = 0;
6501
6502 kfree(info->vics);
6503 info->vics = NULL;
6504 info->vics_len = 0;
6505
6506 info->quirks = 0;
6507
6508 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6509}
6510
6511static void update_displayid_info(struct drm_connector *connector,
6512 const struct drm_edid *drm_edid)
6513{
6514 struct drm_display_info *info = &connector->display_info;
6515 const struct displayid_block *block;
6516 struct displayid_iter iter;
6517
6518 displayid_iter_edid_begin(drm_edid, &iter);
6519 displayid_iter_for_each(block, &iter) {
6520 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6521 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6522 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6523 info->non_desktop = true;
6524
6525 /*
6526 * We're only interested in the base section here, no need to
6527 * iterate further.
6528 */
6529 break;
6530 }
6531 displayid_iter_end(&iter);
6532}
6533
6534static void update_display_info(struct drm_connector *connector,
6535 const struct drm_edid *drm_edid)
6536{
6537 struct drm_display_info *info = &connector->display_info;
6538 const struct edid *edid;
6539
6540 drm_reset_display_info(connector);
6541 clear_eld(connector);
6542
6543 if (!drm_edid)
6544 return;
6545
6546 edid = drm_edid->edid;
6547
6548 info->quirks = edid_get_quirks(drm_edid);
6549
6550 info->width_mm = edid->width_cm * 10;
6551 info->height_mm = edid->height_cm * 10;
6552
6553 drm_get_monitor_range(connector, drm_edid);
6554
6555 if (edid->revision < 3)
6556 goto out;
6557
6558 if (!drm_edid_is_digital(drm_edid))
6559 goto out;
6560
6561 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6562 drm_parse_cea_ext(connector, drm_edid);
6563
6564 update_displayid_info(connector, drm_edid);
6565
6566 /*
6567 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6568 *
6569 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6570 * tells us to assume 8 bpc color depth if the EDID doesn't have
6571 * extensions which tell otherwise.
6572 */
6573 if (info->bpc == 0 && edid->revision == 3 &&
6574 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6575 info->bpc = 8;
6576 drm_dbg_kms(connector->dev,
6577 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6578 connector->base.id, connector->name, info->bpc);
6579 }
6580
6581 /* Only defined for 1.4 with digital displays */
6582 if (edid->revision < 4)
6583 goto out;
6584
6585 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6586 case DRM_EDID_DIGITAL_DEPTH_6:
6587 info->bpc = 6;
6588 break;
6589 case DRM_EDID_DIGITAL_DEPTH_8:
6590 info->bpc = 8;
6591 break;
6592 case DRM_EDID_DIGITAL_DEPTH_10:
6593 info->bpc = 10;
6594 break;
6595 case DRM_EDID_DIGITAL_DEPTH_12:
6596 info->bpc = 12;
6597 break;
6598 case DRM_EDID_DIGITAL_DEPTH_14:
6599 info->bpc = 14;
6600 break;
6601 case DRM_EDID_DIGITAL_DEPTH_16:
6602 info->bpc = 16;
6603 break;
6604 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6605 default:
6606 info->bpc = 0;
6607 break;
6608 }
6609
6610 drm_dbg_kms(connector->dev,
6611 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6612 connector->base.id, connector->name, info->bpc);
6613
6614 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6615 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6616 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6617 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6618
6619 drm_update_mso(connector, drm_edid);
6620
6621out:
6622 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6623 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6624 connector->base.id, connector->name,
6625 info->non_desktop ? " (redundant quirk)" : "");
6626 info->non_desktop = true;
6627 }
6628
6629 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6630 info->max_dsc_bpp = 15;
6631
6632 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6633 info->bpc = 6;
6634
6635 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6636 info->bpc = 8;
6637
6638 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6639 info->bpc = 10;
6640
6641 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6642 info->bpc = 12;
6643
6644 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6645 drm_edid_to_eld(connector, drm_edid);
6646}
6647
6648static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6649 struct displayid_detailed_timings_1 *timings,
6650 bool type_7)
6651{
6652 struct drm_display_mode *mode;
6653 unsigned pixel_clock = (timings->pixel_clock[0] |
6654 (timings->pixel_clock[1] << 8) |
6655 (timings->pixel_clock[2] << 16)) + 1;
6656 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6657 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6658 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6659 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6660 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6661 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6662 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6663 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6664 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6665 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6666
6667 mode = drm_mode_create(dev);
6668 if (!mode)
6669 return NULL;
6670
6671 /* resolution is kHz for type VII, and 10 kHz for type I */
6672 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6673 mode->hdisplay = hactive;
6674 mode->hsync_start = mode->hdisplay + hsync;
6675 mode->hsync_end = mode->hsync_start + hsync_width;
6676 mode->htotal = mode->hdisplay + hblank;
6677
6678 mode->vdisplay = vactive;
6679 mode->vsync_start = mode->vdisplay + vsync;
6680 mode->vsync_end = mode->vsync_start + vsync_width;
6681 mode->vtotal = mode->vdisplay + vblank;
6682
6683 mode->flags = 0;
6684 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6685 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6686 mode->type = DRM_MODE_TYPE_DRIVER;
6687
6688 if (timings->flags & 0x80)
6689 mode->type |= DRM_MODE_TYPE_PREFERRED;
6690 drm_mode_set_name(mode);
6691
6692 return mode;
6693}
6694
6695static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6696 const struct displayid_block *block)
6697{
6698 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6699 int i;
6700 int num_timings;
6701 struct drm_display_mode *newmode;
6702 int num_modes = 0;
6703 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6704 /* blocks must be multiple of 20 bytes length */
6705 if (block->num_bytes % 20)
6706 return 0;
6707
6708 num_timings = block->num_bytes / 20;
6709 for (i = 0; i < num_timings; i++) {
6710 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6711
6712 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6713 if (!newmode)
6714 continue;
6715
6716 drm_mode_probed_add(connector, newmode);
6717 num_modes++;
6718 }
6719 return num_modes;
6720}
6721
6722static int add_displayid_detailed_modes(struct drm_connector *connector,
6723 const struct drm_edid *drm_edid)
6724{
6725 const struct displayid_block *block;
6726 struct displayid_iter iter;
6727 int num_modes = 0;
6728
6729 displayid_iter_edid_begin(drm_edid, &iter);
6730 displayid_iter_for_each(block, &iter) {
6731 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6732 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6733 num_modes += add_displayid_detailed_1_modes(connector, block);
6734 }
6735 displayid_iter_end(&iter);
6736
6737 return num_modes;
6738}
6739
6740static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6741 const struct drm_edid *drm_edid)
6742{
6743 const struct drm_display_info *info = &connector->display_info;
6744 int num_modes = 0;
6745
6746 if (!drm_edid)
6747 return 0;
6748
6749 /*
6750 * EDID spec says modes should be preferred in this order:
6751 * - preferred detailed mode
6752 * - other detailed modes from base block
6753 * - detailed modes from extension blocks
6754 * - CVT 3-byte code modes
6755 * - standard timing codes
6756 * - established timing codes
6757 * - modes inferred from GTF or CVT range information
6758 *
6759 * We get this pretty much right.
6760 *
6761 * XXX order for additional mode types in extension blocks?
6762 */
6763 num_modes += add_detailed_modes(connector, drm_edid);
6764 num_modes += add_cvt_modes(connector, drm_edid);
6765 num_modes += add_standard_modes(connector, drm_edid);
6766 num_modes += add_established_modes(connector, drm_edid);
6767 num_modes += add_cea_modes(connector, drm_edid);
6768 num_modes += add_alternate_cea_modes(connector, drm_edid);
6769 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6770 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6771 num_modes += add_inferred_modes(connector, drm_edid);
6772
6773 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6774 edid_fixup_preferred(connector);
6775
6776 return num_modes;
6777}
6778
6779static void _drm_update_tile_info(struct drm_connector *connector,
6780 const struct drm_edid *drm_edid);
6781
6782static int _drm_edid_connector_property_update(struct drm_connector *connector,
6783 const struct drm_edid *drm_edid)
6784{
6785 struct drm_device *dev = connector->dev;
6786 int ret;
6787
6788 if (connector->edid_blob_ptr) {
6789 const struct edid *old_edid = connector->edid_blob_ptr->data;
6790
6791 if (old_edid) {
6792 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6793 connector->epoch_counter++;
6794 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6795 connector->base.id, connector->name,
6796 connector->epoch_counter);
6797 }
6798 }
6799 }
6800
6801 ret = drm_property_replace_global_blob(dev,
6802 &connector->edid_blob_ptr,
6803 drm_edid ? drm_edid->size : 0,
6804 drm_edid ? drm_edid->edid : NULL,
6805 &connector->base,
6806 dev->mode_config.edid_property);
6807 if (ret) {
6808 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6809 connector->base.id, connector->name, ret);
6810 goto out;
6811 }
6812
6813 ret = drm_object_property_set_value(&connector->base,
6814 dev->mode_config.non_desktop_property,
6815 connector->display_info.non_desktop);
6816 if (ret) {
6817 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6818 connector->base.id, connector->name, ret);
6819 goto out;
6820 }
6821
6822 ret = drm_connector_set_tile_property(connector);
6823 if (ret) {
6824 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6825 connector->base.id, connector->name, ret);
6826 goto out;
6827 }
6828
6829out:
6830 return ret;
6831}
6832
6833/**
6834 * drm_edid_connector_update - Update connector information from EDID
6835 * @connector: Connector
6836 * @drm_edid: EDID
6837 *
6838 * Update the connector display info, ELD, HDR metadata, relevant properties,
6839 * etc. from the passed in EDID.
6840 *
6841 * If EDID is NULL, reset the information.
6842 *
6843 * Must be called before calling drm_edid_connector_add_modes().
6844 *
6845 * Return: 0 on success, negative error on errors.
6846 */
6847int drm_edid_connector_update(struct drm_connector *connector,
6848 const struct drm_edid *drm_edid)
6849{
6850 update_display_info(connector, drm_edid);
6851
6852 _drm_update_tile_info(connector, drm_edid);
6853
6854 return _drm_edid_connector_property_update(connector, drm_edid);
6855}
6856EXPORT_SYMBOL(drm_edid_connector_update);
6857
6858/**
6859 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6860 * @connector: Connector
6861 *
6862 * Add the modes from the previously updated EDID property to the connector
6863 * probed modes list.
6864 *
6865 * drm_edid_connector_update() must have been called before this to update the
6866 * EDID property.
6867 *
6868 * Return: The number of modes added, or 0 if we couldn't find any.
6869 */
6870int drm_edid_connector_add_modes(struct drm_connector *connector)
6871{
6872 const struct drm_edid *drm_edid = NULL;
6873 int count;
6874
6875 if (connector->edid_blob_ptr)
6876 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6877 connector->edid_blob_ptr->length);
6878
6879 count = _drm_edid_connector_add_modes(connector, drm_edid);
6880
6881 drm_edid_free(drm_edid);
6882
6883 return count;
6884}
6885EXPORT_SYMBOL(drm_edid_connector_add_modes);
6886
6887/**
6888 * drm_connector_update_edid_property - update the edid property of a connector
6889 * @connector: drm connector
6890 * @edid: new value of the edid property
6891 *
6892 * This function creates a new blob modeset object and assigns its id to the
6893 * connector's edid property.
6894 * Since we also parse tile information from EDID's displayID block, we also
6895 * set the connector's tile property here. See drm_connector_set_tile_property()
6896 * for more details.
6897 *
6898 * This function is deprecated. Use drm_edid_connector_update() instead.
6899 *
6900 * Returns:
6901 * Zero on success, negative errno on failure.
6902 */
6903int drm_connector_update_edid_property(struct drm_connector *connector,
6904 const struct edid *edid)
6905{
6906 struct drm_edid drm_edid;
6907
6908 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6909}
6910EXPORT_SYMBOL(drm_connector_update_edid_property);
6911
6912/**
6913 * drm_add_edid_modes - add modes from EDID data, if available
6914 * @connector: connector we're probing
6915 * @edid: EDID data
6916 *
6917 * Add the specified modes to the connector's mode list. Also fills out the
6918 * &drm_display_info structure and ELD in @connector with any information which
6919 * can be derived from the edid.
6920 *
6921 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6922 *
6923 * Return: The number of modes added or 0 if we couldn't find any.
6924 */
6925int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6926{
6927 struct drm_edid _drm_edid;
6928 const struct drm_edid *drm_edid;
6929
6930 if (edid && !drm_edid_is_valid(edid)) {
6931 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6932 connector->base.id, connector->name);
6933 edid = NULL;
6934 }
6935
6936 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6937
6938 update_display_info(connector, drm_edid);
6939
6940 return _drm_edid_connector_add_modes(connector, drm_edid);
6941}
6942EXPORT_SYMBOL(drm_add_edid_modes);
6943
6944/**
6945 * drm_add_modes_noedid - add modes for the connectors without EDID
6946 * @connector: connector we're probing
6947 * @hdisplay: the horizontal display limit
6948 * @vdisplay: the vertical display limit
6949 *
6950 * Add the specified modes to the connector's mode list. Only when the
6951 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6952 *
6953 * Return: The number of modes added or 0 if we couldn't find any.
6954 */
6955int drm_add_modes_noedid(struct drm_connector *connector,
6956 int hdisplay, int vdisplay)
6957{
6958 int i, count, num_modes = 0;
6959 struct drm_display_mode *mode;
6960 struct drm_device *dev = connector->dev;
6961
6962 count = ARRAY_SIZE(drm_dmt_modes);
6963 if (hdisplay < 0)
6964 hdisplay = 0;
6965 if (vdisplay < 0)
6966 vdisplay = 0;
6967
6968 for (i = 0; i < count; i++) {
6969 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6970
6971 if (hdisplay && vdisplay) {
6972 /*
6973 * Only when two are valid, they will be used to check
6974 * whether the mode should be added to the mode list of
6975 * the connector.
6976 */
6977 if (ptr->hdisplay > hdisplay ||
6978 ptr->vdisplay > vdisplay)
6979 continue;
6980 }
6981 if (drm_mode_vrefresh(ptr) > 61)
6982 continue;
6983 mode = drm_mode_duplicate(dev, ptr);
6984 if (mode) {
6985 drm_mode_probed_add(connector, mode);
6986 num_modes++;
6987 }
6988 }
6989 return num_modes;
6990}
6991EXPORT_SYMBOL(drm_add_modes_noedid);
6992
6993/**
6994 * drm_set_preferred_mode - Sets the preferred mode of a connector
6995 * @connector: connector whose mode list should be processed
6996 * @hpref: horizontal resolution of preferred mode
6997 * @vpref: vertical resolution of preferred mode
6998 *
6999 * Marks a mode as preferred if it matches the resolution specified by @hpref
7000 * and @vpref.
7001 */
7002void drm_set_preferred_mode(struct drm_connector *connector,
7003 int hpref, int vpref)
7004{
7005 struct drm_display_mode *mode;
7006
7007 list_for_each_entry(mode, &connector->probed_modes, head) {
7008 if (mode->hdisplay == hpref &&
7009 mode->vdisplay == vpref)
7010 mode->type |= DRM_MODE_TYPE_PREFERRED;
7011 }
7012}
7013EXPORT_SYMBOL(drm_set_preferred_mode);
7014
7015static bool is_hdmi2_sink(const struct drm_connector *connector)
7016{
7017 /*
7018 * FIXME: sil-sii8620 doesn't have a connector around when
7019 * we need one, so we have to be prepared for a NULL connector.
7020 */
7021 if (!connector)
7022 return true;
7023
7024 return connector->display_info.hdmi.scdc.supported ||
7025 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7026}
7027
7028static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7029 const struct drm_display_mode *mode)
7030{
7031 bool has_hdmi_infoframe = connector ?
7032 connector->display_info.has_hdmi_infoframe : false;
7033
7034 if (!has_hdmi_infoframe)
7035 return 0;
7036
7037 /* No HDMI VIC when signalling 3D video format */
7038 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7039 return 0;
7040
7041 return drm_match_hdmi_mode(mode);
7042}
7043
7044static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7045 const struct drm_display_mode *mode)
7046{
7047 /*
7048 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7049 * we should send its VIC in vendor infoframes, else send the
7050 * VIC in AVI infoframes. Lets check if this mode is present in
7051 * HDMI 1.4b 4K modes
7052 */
7053 if (drm_mode_hdmi_vic(connector, mode))
7054 return 0;
7055
7056 return drm_match_cea_mode(mode);
7057}
7058
7059/*
7060 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7061 * conform to HDMI 1.4.
7062 *
7063 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7064 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7065 *
7066 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7067 * version.
7068 */
7069static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7070{
7071 if (!is_hdmi2_sink(connector) && vic > 64 &&
7072 !cta_vdb_has_vic(connector, vic))
7073 return 0;
7074
7075 return vic;
7076}
7077
7078/**
7079 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7080 * data from a DRM display mode
7081 * @frame: HDMI AVI infoframe
7082 * @connector: the connector
7083 * @mode: DRM display mode
7084 *
7085 * Return: 0 on success or a negative error code on failure.
7086 */
7087int
7088drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7089 const struct drm_connector *connector,
7090 const struct drm_display_mode *mode)
7091{
7092 enum hdmi_picture_aspect picture_aspect;
7093 u8 vic, hdmi_vic;
7094
7095 if (!frame || !mode)
7096 return -EINVAL;
7097
7098 hdmi_avi_infoframe_init(frame);
7099
7100 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7101 frame->pixel_repeat = 1;
7102
7103 vic = drm_mode_cea_vic(connector, mode);
7104 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7105
7106 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7107
7108 /*
7109 * As some drivers don't support atomic, we can't use connector state.
7110 * So just initialize the frame with default values, just the same way
7111 * as it's done with other properties here.
7112 */
7113 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7114 frame->itc = 0;
7115
7116 /*
7117 * Populate picture aspect ratio from either
7118 * user input (if specified) or from the CEA/HDMI mode lists.
7119 */
7120 picture_aspect = mode->picture_aspect_ratio;
7121 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7122 if (vic)
7123 picture_aspect = drm_get_cea_aspect_ratio(vic);
7124 else if (hdmi_vic)
7125 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7126 }
7127
7128 /*
7129 * The infoframe can't convey anything but none, 4:3
7130 * and 16:9, so if the user has asked for anything else
7131 * we can only satisfy it by specifying the right VIC.
7132 */
7133 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7134 if (vic) {
7135 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7136 return -EINVAL;
7137 } else if (hdmi_vic) {
7138 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7139 return -EINVAL;
7140 } else {
7141 return -EINVAL;
7142 }
7143
7144 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7145 }
7146
7147 frame->video_code = vic_for_avi_infoframe(connector, vic);
7148 frame->picture_aspect = picture_aspect;
7149 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7150 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7151
7152 return 0;
7153}
7154EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7155
7156/**
7157 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7158 * quantization range information
7159 * @frame: HDMI AVI infoframe
7160 * @connector: the connector
7161 * @mode: DRM display mode
7162 * @rgb_quant_range: RGB quantization range (Q)
7163 */
7164void
7165drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7166 const struct drm_connector *connector,
7167 const struct drm_display_mode *mode,
7168 enum hdmi_quantization_range rgb_quant_range)
7169{
7170 const struct drm_display_info *info = &connector->display_info;
7171
7172 /*
7173 * CEA-861:
7174 * "A Source shall not send a non-zero Q value that does not correspond
7175 * to the default RGB Quantization Range for the transmitted Picture
7176 * unless the Sink indicates support for the Q bit in a Video
7177 * Capabilities Data Block."
7178 *
7179 * HDMI 2.0 recommends sending non-zero Q when it does match the
7180 * default RGB quantization range for the mode, even when QS=0.
7181 */
7182 if (info->rgb_quant_range_selectable ||
7183 rgb_quant_range == drm_default_rgb_quant_range(mode))
7184 frame->quantization_range = rgb_quant_range;
7185 else
7186 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7187
7188 /*
7189 * CEA-861-F:
7190 * "When transmitting any RGB colorimetry, the Source should set the
7191 * YQ-field to match the RGB Quantization Range being transmitted
7192 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7193 * set YQ=1) and the Sink shall ignore the YQ-field."
7194 *
7195 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7196 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7197 * good way to tell which version of CEA-861 the sink supports, so
7198 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7199 * on CEA-861-F.
7200 */
7201 if (!is_hdmi2_sink(connector) ||
7202 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7203 frame->ycc_quantization_range =
7204 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7205 else
7206 frame->ycc_quantization_range =
7207 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7208}
7209EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7210
7211static enum hdmi_3d_structure
7212s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7213{
7214 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7215
7216 switch (layout) {
7217 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7218 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7219 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7220 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7221 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7222 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7223 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7224 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7225 case DRM_MODE_FLAG_3D_L_DEPTH:
7226 return HDMI_3D_STRUCTURE_L_DEPTH;
7227 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7228 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7229 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7230 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7231 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7232 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7233 default:
7234 return HDMI_3D_STRUCTURE_INVALID;
7235 }
7236}
7237
7238/**
7239 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7240 * data from a DRM display mode
7241 * @frame: HDMI vendor infoframe
7242 * @connector: the connector
7243 * @mode: DRM display mode
7244 *
7245 * Note that there's is a need to send HDMI vendor infoframes only when using a
7246 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7247 * function will return -EINVAL, error that can be safely ignored.
7248 *
7249 * Return: 0 on success or a negative error code on failure.
7250 */
7251int
7252drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7253 const struct drm_connector *connector,
7254 const struct drm_display_mode *mode)
7255{
7256 /*
7257 * FIXME: sil-sii8620 doesn't have a connector around when
7258 * we need one, so we have to be prepared for a NULL connector.
7259 */
7260 bool has_hdmi_infoframe = connector ?
7261 connector->display_info.has_hdmi_infoframe : false;
7262 int err;
7263
7264 if (!frame || !mode)
7265 return -EINVAL;
7266
7267 if (!has_hdmi_infoframe)
7268 return -EINVAL;
7269
7270 err = hdmi_vendor_infoframe_init(frame);
7271 if (err < 0)
7272 return err;
7273
7274 /*
7275 * Even if it's not absolutely necessary to send the infoframe
7276 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7277 * know that the sink can handle it. This is based on a
7278 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7279 * have trouble realizing that they should switch from 3D to 2D
7280 * mode if the source simply stops sending the infoframe when
7281 * it wants to switch from 3D to 2D.
7282 */
7283 frame->vic = drm_mode_hdmi_vic(connector, mode);
7284 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7285
7286 return 0;
7287}
7288EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7289
7290static void drm_parse_tiled_block(struct drm_connector *connector,
7291 const struct displayid_block *block)
7292{
7293 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7294 u16 w, h;
7295 u8 tile_v_loc, tile_h_loc;
7296 u8 num_v_tile, num_h_tile;
7297 struct drm_tile_group *tg;
7298
7299 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7300 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7301
7302 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7303 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7304 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7305 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7306
7307 connector->has_tile = true;
7308 if (tile->tile_cap & 0x80)
7309 connector->tile_is_single_monitor = true;
7310
7311 connector->num_h_tile = num_h_tile + 1;
7312 connector->num_v_tile = num_v_tile + 1;
7313 connector->tile_h_loc = tile_h_loc;
7314 connector->tile_v_loc = tile_v_loc;
7315 connector->tile_h_size = w + 1;
7316 connector->tile_v_size = h + 1;
7317
7318 drm_dbg_kms(connector->dev,
7319 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7320 connector->base.id, connector->name,
7321 tile->tile_cap,
7322 connector->tile_h_size, connector->tile_v_size,
7323 connector->num_h_tile, connector->num_v_tile,
7324 connector->tile_h_loc, connector->tile_v_loc,
7325 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7326
7327 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7328 if (!tg)
7329 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7330 if (!tg)
7331 return;
7332
7333 if (connector->tile_group != tg) {
7334 /* if we haven't got a pointer,
7335 take the reference, drop ref to old tile group */
7336 if (connector->tile_group)
7337 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7338 connector->tile_group = tg;
7339 } else {
7340 /* if same tile group, then release the ref we just took. */
7341 drm_mode_put_tile_group(connector->dev, tg);
7342 }
7343}
7344
7345static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7346 const struct displayid_block *block)
7347{
7348 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7349 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7350 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7351 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7352}
7353
7354static void _drm_update_tile_info(struct drm_connector *connector,
7355 const struct drm_edid *drm_edid)
7356{
7357 const struct displayid_block *block;
7358 struct displayid_iter iter;
7359
7360 connector->has_tile = false;
7361
7362 displayid_iter_edid_begin(drm_edid, &iter);
7363 displayid_iter_for_each(block, &iter) {
7364 if (displayid_is_tiled_block(&iter, block))
7365 drm_parse_tiled_block(connector, block);
7366 }
7367 displayid_iter_end(&iter);
7368
7369 if (!connector->has_tile && connector->tile_group) {
7370 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7371 connector->tile_group = NULL;
7372 }
7373}
7374
7375/**
7376 * drm_edid_is_digital - is digital?
7377 * @drm_edid: The EDID
7378 *
7379 * Return true if input is digital.
7380 */
7381bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7382{
7383 return drm_edid && drm_edid->edid &&
7384 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7385}
7386EXPORT_SYMBOL(drm_edid_is_digital);