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1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/bitfield.h>
32#include <linux/byteorder/generic.h>
33#include <linux/cec.h>
34#include <linux/hdmi.h>
35#include <linux/i2c.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/seq_buf.h>
40#include <linux/slab.h>
41#include <linux/vga_switcheroo.h>
42
43#include <drm/drm_drv.h>
44#include <drm/drm_edid.h>
45#include <drm/drm_eld.h>
46#include <drm/drm_encoder.h>
47#include <drm/drm_print.h>
48
49#include "drm_crtc_internal.h"
50#include "drm_displayid_internal.h"
51#include "drm_internal.h"
52
53static int oui(u8 first, u8 second, u8 third)
54{
55 return (first << 16) | (second << 8) | third;
56}
57
58#define EDID_EST_TIMINGS 16
59#define EDID_STD_TIMINGS 8
60#define EDID_DETAILED_TIMINGS 4
61
62/*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69/* First detailed mode wrong, use largest 60Hz mode */
70#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71/* Reported 135MHz pixel clock is too high, needs adjustment */
72#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73/* Prefer the largest mode at 75 Hz */
74#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75/* Detail timing is in cm not mm */
76#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77/* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81/* use +hsync +vsync for detailed mode */
82#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83/* Force reduced-blanking timings for detailed modes */
84#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
85/* Force 8bpc */
86#define EDID_QUIRK_FORCE_8BPC (1 << 8)
87/* Force 12bpc */
88#define EDID_QUIRK_FORCE_12BPC (1 << 9)
89/* Force 6bpc */
90#define EDID_QUIRK_FORCE_6BPC (1 << 10)
91/* Force 10bpc */
92#define EDID_QUIRK_FORCE_10BPC (1 << 11)
93/* Non desktop display (i.e. HMD) */
94#define EDID_QUIRK_NON_DESKTOP (1 << 12)
95/* Cap the DSC target bitrate to 15bpp */
96#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
97
98#define MICROSOFT_IEEE_OUI 0xca125c
99
100struct detailed_mode_closure {
101 struct drm_connector *connector;
102 const struct drm_edid *drm_edid;
103 bool preferred;
104 int modes;
105};
106
107struct drm_edid_match_closure {
108 const struct drm_edid_ident *ident;
109 bool matched;
110};
111
112#define LEVEL_DMT 0
113#define LEVEL_GTF 1
114#define LEVEL_GTF2 2
115#define LEVEL_CVT 3
116
117#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
118{ \
119 .ident = { \
120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
121 vend_chr_2, product_id), \
122 }, \
123 .quirks = _quirks \
124}
125
126static const struct edid_quirk {
127 const struct drm_edid_ident ident;
128 u32 quirks;
129} edid_quirk_list[] = {
130 /* Acer AL1706 */
131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
132 /* Acer F51 */
133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
134
135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
137
138 /* BenQ GW2765 */
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
140
141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
143
144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
146
147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
149
150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
152
153 /* Belinea 10 15 55 */
154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
156
157 /* Envision Peripherals, Inc. EN-7100e */
158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
159 /* Envision EN2028 */
160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
161
162 /* Funai Electronics PM36B */
163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
164 EDID_QUIRK_DETAILED_IN_CM),
165
166 /* LG 27GP950 */
167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
168
169 /* LG 27GN950 */
170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
171
172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
174
175 /* LG Philips LCD LP154W01-A5 */
176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
178
179 /* Samsung SyncMaster 205BW. Note: irony */
180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
181 /* Samsung SyncMaster 22[5-6]BW */
182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
184
185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
187
188 /* ViewSonic VA2026w */
189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
190
191 /* Medion MD 30217 PG */
192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
193
194 /* Lenovo G50 */
195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
196
197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
199
200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
202
203 /* Valve Index Headset */
204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
221
222 /* HTC Vive and Vive Pro VR Headsets */
223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
225
226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
231
232 /* Windows Mixed Reality Headsets */
233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
239
240 /* Sony PlayStation VR Headset */
241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
242
243 /* Sensics VR Headsets */
244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
245
246 /* OSVR HDK and HDK2 VR Headsets */
247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
249};
250
251/*
252 * Autogenerated from the DMT spec.
253 * This table is copied from xfree86/modes/xf86EdidModes.c.
254 */
255static const struct drm_display_mode drm_dmt_modes[] = {
256 /* 0x01 - 640x350@85Hz */
257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 350, 382, 385, 445, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x02 - 640x400@85Hz */
261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
262 736, 832, 0, 400, 401, 404, 445, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x03 - 720x400@85Hz */
265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
266 828, 936, 0, 400, 401, 404, 446, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x04 - 640x480@60Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
270 752, 800, 0, 480, 490, 492, 525, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x05 - 640x480@72Hz */
273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
274 704, 832, 0, 480, 489, 492, 520, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x06 - 640x480@75Hz */
277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
278 720, 840, 0, 480, 481, 484, 500, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 0x07 - 640x480@85Hz */
281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
282 752, 832, 0, 480, 481, 484, 509, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x08 - 800x600@56Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
286 896, 1024, 0, 600, 601, 603, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x09 - 800x600@60Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
290 968, 1056, 0, 600, 601, 605, 628, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0a - 800x600@72Hz */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
294 976, 1040, 0, 600, 637, 643, 666, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x0b - 800x600@75Hz */
297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
298 896, 1056, 0, 600, 601, 604, 625, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0c - 800x600@85Hz */
301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
302 896, 1048, 0, 600, 601, 604, 631, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 0x0d - 800x600@120Hz RB */
305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
306 880, 960, 0, 600, 603, 607, 636, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 0x0e - 848x480@60Hz */
309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
310 976, 1088, 0, 480, 486, 494, 517, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x0f - 1024x768@43Hz, interlace */
313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
314 1208, 1264, 0, 768, 768, 776, 817, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
316 DRM_MODE_FLAG_INTERLACE) },
317 /* 0x10 - 1024x768@60Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x11 - 1024x768@70Hz */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
323 1184, 1328, 0, 768, 771, 777, 806, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x12 - 1024x768@75Hz */
326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
327 1136, 1312, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x13 - 1024x768@85Hz */
330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
331 1168, 1376, 0, 768, 769, 772, 808, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x14 - 1024x768@120Hz RB */
334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
335 1104, 1184, 0, 768, 771, 775, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x15 - 1152x864@75Hz */
338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
339 1344, 1600, 0, 864, 865, 868, 900, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x55 - 1280x720@60Hz */
342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
343 1430, 1650, 0, 720, 725, 730, 750, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x16 - 1280x768@60Hz RB */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 790, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x17 - 1280x768@60Hz */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
351 1472, 1664, 0, 768, 771, 778, 798, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x18 - 1280x768@75Hz */
354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
355 1488, 1696, 0, 768, 771, 778, 805, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x19 - 1280x768@85Hz */
358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
359 1496, 1712, 0, 768, 771, 778, 809, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1a - 1280x768@120Hz RB */
362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
363 1360, 1440, 0, 768, 771, 778, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x1b - 1280x800@60Hz RB */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 823, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x1c - 1280x800@60Hz */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
371 1480, 1680, 0, 800, 803, 809, 831, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x1d - 1280x800@75Hz */
374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
375 1488, 1696, 0, 800, 803, 809, 838, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x1e - 1280x800@85Hz */
378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
379 1496, 1712, 0, 800, 803, 809, 843, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x1f - 1280x800@120Hz RB */
382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
383 1360, 1440, 0, 800, 803, 809, 847, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x20 - 1280x960@60Hz */
386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
387 1488, 1800, 0, 960, 961, 964, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x21 - 1280x960@85Hz */
390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
391 1504, 1728, 0, 960, 961, 964, 1011, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x22 - 1280x960@120Hz RB */
394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
395 1360, 1440, 0, 960, 963, 967, 1017, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x23 - 1280x1024@60Hz */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x24 - 1280x1024@75Hz */
402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x25 - 1280x1024@85Hz */
406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x26 - 1280x1024@120Hz RB */
410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x27 - 1360x768@60Hz */
414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
415 1536, 1792, 0, 768, 771, 777, 795, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x28 - 1360x768@120Hz RB */
418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
419 1440, 1520, 0, 768, 771, 776, 813, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x51 - 1366x768@60Hz */
422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
423 1579, 1792, 0, 768, 771, 774, 798, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x56 - 1366x768@60Hz */
426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
427 1436, 1500, 0, 768, 769, 772, 800, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x29 - 1400x1050@60Hz RB */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x2a - 1400x1050@60Hz */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x2b - 1400x1050@75Hz */
438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x2c - 1400x1050@85Hz */
442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x2d - 1400x1050@120Hz RB */
446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 0x2e - 1440x900@60Hz RB */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 926, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x2f - 1440x900@60Hz */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
455 1672, 1904, 0, 900, 903, 909, 934, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x30 - 1440x900@75Hz */
458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
459 1688, 1936, 0, 900, 903, 909, 942, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x31 - 1440x900@85Hz */
462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
463 1696, 1952, 0, 900, 903, 909, 948, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x32 - 1440x900@120Hz RB */
466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
467 1520, 1600, 0, 900, 903, 909, 953, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x53 - 1600x900@60Hz */
470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
471 1704, 1800, 0, 900, 901, 904, 1000, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x33 - 1600x1200@60Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x34 - 1600x1200@65Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x35 - 1600x1200@70Hz */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x36 - 1600x1200@75Hz */
486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x37 - 1600x1200@85Hz */
490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x38 - 1600x1200@120Hz RB */
494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x39 - 1680x1050@60Hz RB */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x3a - 1680x1050@60Hz */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x3b - 1680x1050@75Hz */
506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3c - 1680x1050@85Hz */
510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x3d - 1680x1050@120Hz RB */
514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x3e - 1792x1344@60Hz */
518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x3f - 1792x1344@75Hz */
522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x40 - 1792x1344@120Hz RB */
526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x41 - 1856x1392@60Hz */
530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 0x42 - 1856x1392@75Hz */
534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x43 - 1856x1392@120Hz RB */
538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
541 /* 0x52 - 1920x1080@60Hz */
542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x44 - 1920x1200@60Hz RB */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x45 - 1920x1200@60Hz */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 0x46 - 1920x1200@75Hz */
554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x47 - 1920x1200@85Hz */
558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x48 - 1920x1200@120Hz RB */
562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x49 - 1920x1440@60Hz */
566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4a - 1920x1440@75Hz */
570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 0x4b - 1920x1440@120Hz RB */
574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 /* 0x54 - 2048x1152@60Hz */
578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4c - 2560x1600@60Hz RB */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585 /* 0x4d - 2560x1600@60Hz */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 /* 0x4e - 2560x1600@75Hz */
590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
593 /* 0x4f - 2560x1600@85Hz */
594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
597 /* 0x50 - 2560x1600@120Hz RB */
598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 /* 0x57 - 4096x2160@60Hz RB */
602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
605 /* 0x58 - 4096x2160@59.94Hz RB */
606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
609};
610
611/*
612 * These more or less come from the DMT spec. The 720x400 modes are
613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
616 * mode.
617 *
618 * The DMT modes have been fact-checked; the rest are mild guesses.
619 */
620static const struct drm_display_mode edid_est_modes[] = {
621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
622 968, 1056, 0, 600, 601, 605, 628, 0,
623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
625 896, 1024, 0, 600, 601, 603, 625, 0,
626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
628 720, 840, 0, 480, 481, 484, 500, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
631 704, 832, 0, 480, 489, 492, 520, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
634 768, 864, 0, 480, 483, 486, 525, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
637 752, 800, 0, 480, 490, 492, 525, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
640 846, 900, 0, 400, 421, 423, 449, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
643 846, 900, 0, 400, 412, 414, 449, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
649 1136, 1312, 0, 768, 769, 772, 800, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
652 1184, 1328, 0, 768, 771, 777, 806, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
655 1184, 1344, 0, 768, 771, 777, 806, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
658 1208, 1264, 0, 768, 768, 776, 817, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
661 928, 1152, 0, 624, 625, 628, 667, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
664 896, 1056, 0, 600, 601, 604, 625, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
667 976, 1040, 0, 600, 637, 643, 666, 0,
668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
670 1344, 1600, 0, 864, 865, 868, 900, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
672};
673
674struct minimode {
675 short w;
676 short h;
677 short r;
678 short rb;
679};
680
681static const struct minimode est3_modes[] = {
682 /* byte 6 */
683 { 640, 350, 85, 0 },
684 { 640, 400, 85, 0 },
685 { 720, 400, 85, 0 },
686 { 640, 480, 85, 0 },
687 { 848, 480, 60, 0 },
688 { 800, 600, 85, 0 },
689 { 1024, 768, 85, 0 },
690 { 1152, 864, 75, 0 },
691 /* byte 7 */
692 { 1280, 768, 60, 1 },
693 { 1280, 768, 60, 0 },
694 { 1280, 768, 75, 0 },
695 { 1280, 768, 85, 0 },
696 { 1280, 960, 60, 0 },
697 { 1280, 960, 85, 0 },
698 { 1280, 1024, 60, 0 },
699 { 1280, 1024, 85, 0 },
700 /* byte 8 */
701 { 1360, 768, 60, 0 },
702 { 1440, 900, 60, 1 },
703 { 1440, 900, 60, 0 },
704 { 1440, 900, 75, 0 },
705 { 1440, 900, 85, 0 },
706 { 1400, 1050, 60, 1 },
707 { 1400, 1050, 60, 0 },
708 { 1400, 1050, 75, 0 },
709 /* byte 9 */
710 { 1400, 1050, 85, 0 },
711 { 1680, 1050, 60, 1 },
712 { 1680, 1050, 60, 0 },
713 { 1680, 1050, 75, 0 },
714 { 1680, 1050, 85, 0 },
715 { 1600, 1200, 60, 0 },
716 { 1600, 1200, 65, 0 },
717 { 1600, 1200, 70, 0 },
718 /* byte 10 */
719 { 1600, 1200, 75, 0 },
720 { 1600, 1200, 85, 0 },
721 { 1792, 1344, 60, 0 },
722 { 1792, 1344, 75, 0 },
723 { 1856, 1392, 60, 0 },
724 { 1856, 1392, 75, 0 },
725 { 1920, 1200, 60, 1 },
726 { 1920, 1200, 60, 0 },
727 /* byte 11 */
728 { 1920, 1200, 75, 0 },
729 { 1920, 1200, 85, 0 },
730 { 1920, 1440, 60, 0 },
731 { 1920, 1440, 75, 0 },
732};
733
734static const struct minimode extra_modes[] = {
735 { 1024, 576, 60, 0 },
736 { 1366, 768, 60, 0 },
737 { 1600, 900, 60, 0 },
738 { 1680, 945, 60, 0 },
739 { 1920, 1080, 60, 0 },
740 { 2048, 1152, 60, 0 },
741 { 2048, 1536, 60, 0 },
742};
743
744/*
745 * From CEA/CTA-861 spec.
746 *
747 * Do not access directly, instead always use cea_mode_for_vic().
748 */
749static const struct drm_display_mode edid_cea_modes_1[] = {
750 /* 1 - 640x480@60Hz 4:3 */
751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752 752, 800, 0, 480, 490, 492, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
755 /* 2 - 720x480@60Hz 4:3 */
756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
757 798, 858, 0, 480, 489, 495, 525, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
760 /* 3 - 720x480@60Hz 16:9 */
761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
762 798, 858, 0, 480, 489, 495, 525, 0,
763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 4 - 1280x720@60Hz 16:9 */
766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
767 1430, 1650, 0, 720, 725, 730, 750, 0,
768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 5 - 1920x1080i@60Hz 16:9 */
771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
774 DRM_MODE_FLAG_INTERLACE),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 6 - 720(1440)x480i@60Hz 4:3 */
777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 7 - 720(1440)x480i@60Hz 16:9 */
783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 8 - 720(1440)x240@60Hz 4:3 */
789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
790 801, 858, 0, 240, 244, 247, 262, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_DBLCLK),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 9 - 720(1440)x240@60Hz 16:9 */
795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
796 801, 858, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_DBLCLK),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 10 - 2880x480i@60Hz 4:3 */
801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 480, 488, 494, 525, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
804 DRM_MODE_FLAG_INTERLACE),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 11 - 2880x480i@60Hz 16:9 */
807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 480, 488, 494, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
810 DRM_MODE_FLAG_INTERLACE),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 12 - 2880x240@60Hz 4:3 */
813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
814 3204, 3432, 0, 240, 244, 247, 262, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 13 - 2880x240@60Hz 16:9 */
818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819 3204, 3432, 0, 240, 244, 247, 262, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 14 - 1440x480@60Hz 4:3 */
823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
824 1596, 1716, 0, 480, 489, 495, 525, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 15 - 1440x480@60Hz 16:9 */
828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
829 1596, 1716, 0, 480, 489, 495, 525, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 16 - 1920x1080@60Hz 16:9 */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 17 - 720x576@50Hz 4:3 */
838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
839 796, 864, 0, 576, 581, 586, 625, 0,
840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
842 /* 18 - 720x576@50Hz 16:9 */
843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
844 796, 864, 0, 576, 581, 586, 625, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 19 - 1280x720@50Hz 16:9 */
848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
849 1760, 1980, 0, 720, 725, 730, 750, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 20 - 1920x1080i@50Hz 16:9 */
853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
856 DRM_MODE_FLAG_INTERLACE),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 21 - 720(1440)x576i@50Hz 4:3 */
859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 22 - 720(1440)x576i@50Hz 16:9 */
865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 23 - 720(1440)x288@50Hz 4:3 */
871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
872 795, 864, 0, 288, 290, 293, 312, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_DBLCLK),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 24 - 720(1440)x288@50Hz 16:9 */
877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
878 795, 864, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_DBLCLK),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 25 - 2880x576i@50Hz 4:3 */
883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
886 DRM_MODE_FLAG_INTERLACE),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 26 - 2880x576i@50Hz 16:9 */
889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
892 DRM_MODE_FLAG_INTERLACE),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 27 - 2880x288@50Hz 4:3 */
895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
896 3180, 3456, 0, 288, 290, 293, 312, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899 /* 28 - 2880x288@50Hz 16:9 */
900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901 3180, 3456, 0, 288, 290, 293, 312, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 29 - 1440x576@50Hz 4:3 */
905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
906 1592, 1728, 0, 576, 581, 586, 625, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 30 - 1440x576@50Hz 16:9 */
910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
911 1592, 1728, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 31 - 1920x1080@50Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 32 - 1920x1080@24Hz 16:9 */
920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 33 - 1920x1080@25Hz 16:9 */
925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 34 - 1920x1080@30Hz 16:9 */
930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 35 - 2880x480@60Hz 4:3 */
935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
936 3192, 3432, 0, 480, 489, 495, 525, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 36 - 2880x480@60Hz 16:9 */
940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
941 3192, 3432, 0, 480, 489, 495, 525, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 37 - 2880x576@50Hz 4:3 */
945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
946 3184, 3456, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 38 - 2880x576@50Hz 16:9 */
950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
951 3184, 3456, 0, 576, 581, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 39 - 1920x1080i@50Hz 16:9 */
955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
958 DRM_MODE_FLAG_INTERLACE),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 40 - 1920x1080i@100Hz 16:9 */
961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
964 DRM_MODE_FLAG_INTERLACE),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 41 - 1280x720@100Hz 16:9 */
967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
968 1760, 1980, 0, 720, 725, 730, 750, 0,
969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971 /* 42 - 720x576@100Hz 4:3 */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 43 - 720x576@100Hz 16:9 */
977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 44 - 720(1440)x576i@100Hz 4:3 */
982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
983 795, 864, 0, 576, 580, 586, 625, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987 /* 45 - 720(1440)x576i@100Hz 16:9 */
988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
989 795, 864, 0, 576, 580, 586, 625, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 46 - 1920x1080i@120Hz 16:9 */
994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
997 DRM_MODE_FLAG_INTERLACE),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 47 - 1280x720@120Hz 16:9 */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1001 1430, 1650, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 48 - 720x480@120Hz 4:3 */
1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 49 - 720x480@120Hz 16:9 */
1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 50 - 720(1440)x480i@120Hz 4:3 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 51 - 720(1440)x480i@120Hz 16:9 */
1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 52 - 720x576@200Hz 4:3 */
1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1028 796, 864, 0, 576, 581, 586, 625, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 53 - 720x576@200Hz 16:9 */
1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1033 796, 864, 0, 576, 581, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 54 - 720(1440)x576i@200Hz 4:3 */
1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1038 795, 864, 0, 576, 580, 586, 625, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 55 - 720(1440)x576i@200Hz 16:9 */
1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1044 795, 864, 0, 576, 580, 586, 625, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 56 - 720x480@240Hz 4:3 */
1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1050 798, 858, 0, 480, 489, 495, 525, 0,
1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 57 - 720x480@240Hz 16:9 */
1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1055 798, 858, 0, 480, 489, 495, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 58 - 720(1440)x480i@240Hz 4:3 */
1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1060 801, 858, 0, 480, 488, 494, 525, 0,
1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1064 /* 59 - 720(1440)x480i@240Hz 16:9 */
1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1066 801, 858, 0, 480, 488, 494, 525, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 60 - 1280x720@24Hz 16:9 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 61 - 1280x720@25Hz 16:9 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1077 3740, 3960, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 62 - 1280x720@30Hz 16:9 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1085 /* 63 - 1920x1080@120Hz 16:9 */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1090 /* 64 - 1920x1080@100Hz 16:9 */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1095 /* 65 - 1280x720@24Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1097 3080, 3300, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 66 - 1280x720@25Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1102 3740, 3960, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 67 - 1280x720@30Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 68 - 1280x720@50Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1112 1760, 1980, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 69 - 1280x720@60Hz 64:27 */
1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1117 1430, 1650, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 70 - 1280x720@100Hz 64:27 */
1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1122 1760, 1980, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 71 - 1280x720@120Hz 64:27 */
1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1127 1430, 1650, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 72 - 1920x1080@24Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 73 - 1920x1080@25Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 74 - 1920x1080@30Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 75 - 1920x1080@50Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 76 - 1920x1080@60Hz 64:27 */
1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 77 - 1920x1080@100Hz 64:27 */
1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 78 - 1920x1080@120Hz 64:27 */
1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 79 - 1680x720@24Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1167 3080, 3300, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 80 - 1680x720@25Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1172 2948, 3168, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 81 - 1680x720@30Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1177 2420, 2640, 0, 720, 725, 730, 750, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 82 - 1680x720@50Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1182 1980, 2200, 0, 720, 725, 730, 750, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 83 - 1680x720@60Hz 64:27 */
1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1187 1980, 2200, 0, 720, 725, 730, 750, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 84 - 1680x720@100Hz 64:27 */
1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1192 1780, 2000, 0, 720, 725, 730, 825, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 85 - 1680x720@120Hz 64:27 */
1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1197 1780, 2000, 0, 720, 725, 730, 825, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 86 - 2560x1080@24Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 87 - 2560x1080@25Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 88 - 2560x1080@30Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 89 - 2560x1080@50Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 90 - 2560x1080@60Hz 64:27 */
1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1225 /* 91 - 2560x1080@100Hz 64:27 */
1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 92 - 2560x1080@120Hz 64:27 */
1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 93 - 3840x2160@24Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 94 - 3840x2160@25Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 95 - 3840x2160@30Hz 16:9 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1250 /* 96 - 3840x2160@50Hz 16:9 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1255 /* 97 - 3840x2160@60Hz 16:9 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1260 /* 98 - 4096x2160@24Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 99 - 4096x2160@25Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 100 - 4096x2160@30Hz 256:135 */
1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1275 /* 101 - 4096x2160@50Hz 256:135 */
1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1280 /* 102 - 4096x2160@60Hz 256:135 */
1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1285 /* 103 - 3840x2160@24Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 104 - 3840x2160@25Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 105 - 3840x2160@30Hz 64:27 */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1300 /* 106 - 3840x2160@50Hz 64:27 */
1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 107 - 3840x2160@60Hz 64:27 */
1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 108 - 1280x720@48Hz 16:9 */
1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1312 2280, 2500, 0, 720, 725, 730, 750, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 109 - 1280x720@48Hz 64:27 */
1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1317 2280, 2500, 0, 720, 725, 730, 750, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 110 - 1680x720@48Hz 64:27 */
1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1322 2530, 2750, 0, 720, 725, 730, 750, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 111 - 1920x1080@48Hz 16:9 */
1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 112 - 1920x1080@48Hz 64:27 */
1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1335 /* 113 - 2560x1080@48Hz 64:27 */
1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 114 - 3840x2160@48Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 115 - 4096x2160@48Hz 256:135 */
1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1350 /* 116 - 3840x2160@48Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 117 - 3840x2160@100Hz 16:9 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1360 /* 118 - 3840x2160@120Hz 16:9 */
1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1365 /* 119 - 3840x2160@100Hz 64:27 */
1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 120 - 3840x2160@120Hz 64:27 */
1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 121 - 5120x2160@24Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 122 - 5120x2160@25Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 123 - 5120x2160@30Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 124 - 5120x2160@48Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 /* 125 - 5120x2160@50Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 126 - 5120x2160@60Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 127 - 5120x2160@100Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1410};
1411
1412/*
1413 * From CEA/CTA-861 spec.
1414 *
1415 * Do not access directly, instead always use cea_mode_for_vic().
1416 */
1417static const struct drm_display_mode edid_cea_modes_193[] = {
1418 /* 193 - 5120x2160@120Hz 64:27 */
1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1423 /* 194 - 7680x4320@24Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 195 - 7680x4320@25Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 196 - 7680x4320@30Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 197 - 7680x4320@48Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 198 - 7680x4320@50Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 199 - 7680x4320@60Hz 16:9 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1453 /* 200 - 7680x4320@100Hz 16:9 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1458 /* 201 - 7680x4320@120Hz 16:9 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1463 /* 202 - 7680x4320@24Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 203 - 7680x4320@25Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 204 - 7680x4320@30Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 205 - 7680x4320@48Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 206 - 7680x4320@50Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 207 - 7680x4320@60Hz 64:27 */
1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 208 - 7680x4320@100Hz 64:27 */
1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 209 - 7680x4320@120Hz 64:27 */
1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 210 - 10240x4320@24Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 211 - 10240x4320@25Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 212 - 10240x4320@30Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 213 - 10240x4320@48Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 214 - 10240x4320@50Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 215 - 10240x4320@60Hz 64:27 */
1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1533 /* 216 - 10240x4320@100Hz 64:27 */
1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1538 /* 217 - 10240x4320@120Hz 64:27 */
1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1543 /* 218 - 4096x2160@100Hz 256:135 */
1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1548 /* 219 - 4096x2160@120Hz 256:135 */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1553};
1554
1555/*
1556 * HDMI 1.4 4k modes. Index using the VIC.
1557 */
1558static const struct drm_display_mode edid_4k_modes[] = {
1559 /* 0 - dummy, VICs start at 1 */
1560 { },
1561 /* 1 - 3840x2160@30Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 4016, 4104, 4400, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 2 - 3840x2160@25Hz */
1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 3840, 4896, 4984, 5280, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1573 /* 3 - 3840x2160@24Hz */
1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1575 3840, 5116, 5204, 5500, 0,
1576 2160, 2168, 2178, 2250, 0,
1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1579 /* 4 - 4096x2160@24Hz (SMPTE) */
1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1581 4096, 5116, 5204, 5500, 0,
1582 2160, 2168, 2178, 2250, 0,
1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1585};
1586
1587/*** DDC fetch and block validation ***/
1588
1589/*
1590 * The opaque EDID type, internal to drm_edid.c.
1591 */
1592struct drm_edid {
1593 /* Size allocated for edid */
1594 size_t size;
1595 const struct edid *edid;
1596};
1597
1598static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1599
1600static int edid_hfeeodb_block_count(const struct edid *edid)
1601{
1602 int eeodb = edid_hfeeodb_extension_block_count(edid);
1603
1604 return eeodb ? eeodb + 1 : 0;
1605}
1606
1607static int edid_extension_block_count(const struct edid *edid)
1608{
1609 return edid->extensions;
1610}
1611
1612static int edid_block_count(const struct edid *edid)
1613{
1614 return edid_extension_block_count(edid) + 1;
1615}
1616
1617static int edid_size_by_blocks(int num_blocks)
1618{
1619 return num_blocks * EDID_LENGTH;
1620}
1621
1622static int edid_size(const struct edid *edid)
1623{
1624 return edid_size_by_blocks(edid_block_count(edid));
1625}
1626
1627static const void *edid_block_data(const struct edid *edid, int index)
1628{
1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1630
1631 return edid + index;
1632}
1633
1634static const void *edid_extension_block_data(const struct edid *edid, int index)
1635{
1636 return edid_block_data(edid, index + 1);
1637}
1638
1639/* EDID block count indicated in EDID, may exceed allocated size */
1640static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1641{
1642 int num_blocks;
1643
1644 /* Starting point */
1645 num_blocks = edid_block_count(drm_edid->edid);
1646
1647 /* HF-EEODB override */
1648 if (drm_edid->size >= edid_size_by_blocks(2)) {
1649 int eeodb;
1650
1651 /*
1652 * Note: HF-EEODB may specify a smaller extension count than the
1653 * regular one. Unlike in buffer allocation, here we can use it.
1654 */
1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1656 if (eeodb)
1657 num_blocks = eeodb;
1658 }
1659
1660 return num_blocks;
1661}
1662
1663/* EDID block count, limited by allocated size */
1664static int drm_edid_block_count(const struct drm_edid *drm_edid)
1665{
1666 /* Limit by allocated size */
1667 return min(__drm_edid_block_count(drm_edid),
1668 (int)drm_edid->size / EDID_LENGTH);
1669}
1670
1671/* EDID extension block count, limited by allocated size */
1672static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1673{
1674 return drm_edid_block_count(drm_edid) - 1;
1675}
1676
1677static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1678{
1679 return edid_block_data(drm_edid->edid, index);
1680}
1681
1682static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1683 int index)
1684{
1685 return edid_extension_block_data(drm_edid->edid, index);
1686}
1687
1688/*
1689 * Initializer helper for legacy interfaces, where we have no choice but to
1690 * trust edid size. Not for general purpose use.
1691 */
1692static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1693 const struct edid *edid)
1694{
1695 if (!edid)
1696 return NULL;
1697
1698 memset(drm_edid, 0, sizeof(*drm_edid));
1699
1700 drm_edid->edid = edid;
1701 drm_edid->size = edid_size(edid);
1702
1703 return drm_edid;
1704}
1705
1706/*
1707 * EDID base and extension block iterator.
1708 *
1709 * struct drm_edid_iter iter;
1710 * const u8 *block;
1711 *
1712 * drm_edid_iter_begin(drm_edid, &iter);
1713 * drm_edid_iter_for_each(block, &iter) {
1714 * // do stuff with block
1715 * }
1716 * drm_edid_iter_end(&iter);
1717 */
1718struct drm_edid_iter {
1719 const struct drm_edid *drm_edid;
1720
1721 /* Current block index. */
1722 int index;
1723};
1724
1725static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1726 struct drm_edid_iter *iter)
1727{
1728 memset(iter, 0, sizeof(*iter));
1729
1730 iter->drm_edid = drm_edid;
1731}
1732
1733static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1734{
1735 const void *block = NULL;
1736
1737 if (!iter->drm_edid)
1738 return NULL;
1739
1740 if (iter->index < drm_edid_block_count(iter->drm_edid))
1741 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1742
1743 return block;
1744}
1745
1746#define drm_edid_iter_for_each(__block, __iter) \
1747 while (((__block) = __drm_edid_iter_next(__iter)))
1748
1749static void drm_edid_iter_end(struct drm_edid_iter *iter)
1750{
1751 memset(iter, 0, sizeof(*iter));
1752}
1753
1754static const u8 edid_header[] = {
1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1756};
1757
1758static void edid_header_fix(void *edid)
1759{
1760 memcpy(edid, edid_header, sizeof(edid_header));
1761}
1762
1763/**
1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1765 * @_edid: pointer to raw base EDID block
1766 *
1767 * Sanity check the header of the base EDID block.
1768 *
1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1770 */
1771int drm_edid_header_is_valid(const void *_edid)
1772{
1773 const struct edid *edid = _edid;
1774 int i, score = 0;
1775
1776 for (i = 0; i < sizeof(edid_header); i++) {
1777 if (edid->header[i] == edid_header[i])
1778 score++;
1779 }
1780
1781 return score;
1782}
1783EXPORT_SYMBOL(drm_edid_header_is_valid);
1784
1785static int edid_fixup __read_mostly = 6;
1786module_param_named(edid_fixup, edid_fixup, int, 0400);
1787MODULE_PARM_DESC(edid_fixup,
1788 "Minimum number of valid EDID header bytes (0-8, default 6)");
1789
1790static int edid_block_compute_checksum(const void *_block)
1791{
1792 const u8 *block = _block;
1793 int i;
1794 u8 csum = 0, crc = 0;
1795
1796 for (i = 0; i < EDID_LENGTH - 1; i++)
1797 csum += block[i];
1798
1799 crc = 0x100 - csum;
1800
1801 return crc;
1802}
1803
1804static int edid_block_get_checksum(const void *_block)
1805{
1806 const struct edid *block = _block;
1807
1808 return block->checksum;
1809}
1810
1811static int edid_block_tag(const void *_block)
1812{
1813 const u8 *block = _block;
1814
1815 return block[0];
1816}
1817
1818static bool edid_block_is_zero(const void *edid)
1819{
1820 return mem_is_zero(edid, EDID_LENGTH);
1821}
1822
1823static bool drm_edid_eq(const struct drm_edid *drm_edid,
1824 const void *raw_edid, size_t raw_edid_size)
1825{
1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1827 bool edid2_present = raw_edid && raw_edid_size;
1828
1829 if (edid1_present != edid2_present)
1830 return false;
1831
1832 if (edid1_present) {
1833 if (drm_edid->size != raw_edid_size)
1834 return false;
1835
1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
1837 return false;
1838 }
1839
1840 return true;
1841}
1842
1843enum edid_block_status {
1844 EDID_BLOCK_OK = 0,
1845 EDID_BLOCK_READ_FAIL,
1846 EDID_BLOCK_NULL,
1847 EDID_BLOCK_ZERO,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1852 EDID_BLOCK_VERSION,
1853};
1854
1855static enum edid_block_status edid_block_check(const void *_block,
1856 bool is_base_block)
1857{
1858 const struct edid *block = _block;
1859
1860 if (!block)
1861 return EDID_BLOCK_NULL;
1862
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1865
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1869 else
1870 return EDID_BLOCK_HEADER_CORRUPT;
1871 }
1872
1873 if (score < 8)
1874 return EDID_BLOCK_HEADER_REPAIR;
1875 }
1876
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1880 else
1881 return EDID_BLOCK_CHECKSUM;
1882 }
1883
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1887 }
1888
1889 return EDID_BLOCK_OK;
1890}
1891
1892static bool edid_block_status_valid(enum edid_block_status status, int tag)
1893{
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1897}
1898
1899static bool edid_block_valid(const void *block, bool base)
1900{
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1903}
1904
1905static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1907 int block_num)
1908{
1909 switch (status) {
1910 case EDID_BLOCK_OK:
1911 break;
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1914 break;
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1917 break;
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1920 break;
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1923 break;
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1926 break;
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1929 break;
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1935 } else {
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1939 }
1940 break;
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1943 block->version);
1944 break;
1945 default:
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1947 block_num, status);
1948 break;
1949 }
1950}
1951
1952static void edid_block_dump(const char *level, const void *block, int block_num)
1953{
1954 enum edid_block_status status;
1955 char prefix[20];
1956
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1962 else
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1964
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1967}
1968
1969/*
1970 * Validate a base or extension EDID block and optionally dump bad blocks to
1971 * the console.
1972 */
1973static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
1974 bool *edid_corrupt)
1975{
1976 struct edid *block = _block;
1977 enum edid_block_status status;
1978 bool is_base_block = block_num == 0;
1979 bool valid;
1980
1981 if (WARN_ON(!block))
1982 return false;
1983
1984 status = edid_block_check(block, is_base_block);
1985 if (status == EDID_BLOCK_HEADER_REPAIR) {
1986 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1987 edid_header_fix(block);
1988
1989 /* Retry with fixed header, update status if that worked. */
1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_OK)
1992 status = EDID_BLOCK_HEADER_FIXED;
1993 }
1994
1995 if (edid_corrupt) {
1996 /*
1997 * Unknown major version isn't corrupt but we can't use it. Only
1998 * the base block can reset edid_corrupt to false.
1999 */
2000 if (is_base_block &&
2001 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2002 *edid_corrupt = false;
2003 else if (status != EDID_BLOCK_OK)
2004 *edid_corrupt = true;
2005 }
2006
2007 edid_block_status_print(status, block, block_num);
2008
2009 /* Determine whether we can use this block with this status. */
2010 valid = edid_block_status_valid(status, edid_block_tag(block));
2011
2012 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2013 pr_notice("Raw EDID:\n");
2014 edid_block_dump(KERN_NOTICE, block, block_num);
2015 }
2016
2017 return valid;
2018}
2019
2020/**
2021 * drm_edid_is_valid - sanity check EDID data
2022 * @edid: EDID data
2023 *
2024 * Sanity-check an entire EDID record (including extensions)
2025 *
2026 * Return: True if the EDID data is valid, false otherwise.
2027 */
2028bool drm_edid_is_valid(struct edid *edid)
2029{
2030 int i;
2031
2032 if (!edid)
2033 return false;
2034
2035 for (i = 0; i < edid_block_count(edid); i++) {
2036 void *block = (void *)edid_block_data(edid, i);
2037
2038 if (!drm_edid_block_valid(block, i, true, NULL))
2039 return false;
2040 }
2041
2042 return true;
2043}
2044EXPORT_SYMBOL(drm_edid_is_valid);
2045
2046/**
2047 * drm_edid_valid - sanity check EDID data
2048 * @drm_edid: EDID data
2049 *
2050 * Sanity check an EDID. Cross check block count against allocated size and
2051 * checksum the blocks.
2052 *
2053 * Return: True if the EDID data is valid, false otherwise.
2054 */
2055bool drm_edid_valid(const struct drm_edid *drm_edid)
2056{
2057 int i;
2058
2059 if (!drm_edid)
2060 return false;
2061
2062 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2063 return false;
2064
2065 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2066 const void *block = drm_edid_block_data(drm_edid, i);
2067
2068 if (!edid_block_valid(block, i == 0))
2069 return false;
2070 }
2071
2072 return true;
2073}
2074EXPORT_SYMBOL(drm_edid_valid);
2075
2076static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2077 size_t *alloc_size)
2078{
2079 struct edid *new;
2080 int i, valid_blocks = 0;
2081
2082 /*
2083 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2084 * back to regular extension count here. We don't want to start
2085 * modifying the HF-EEODB extension too.
2086 */
2087 for (i = 0; i < edid_block_count(edid); i++) {
2088 const void *src_block = edid_block_data(edid, i);
2089
2090 if (edid_block_valid(src_block, i == 0)) {
2091 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2092
2093 memmove(dst_block, src_block, EDID_LENGTH);
2094 valid_blocks++;
2095 }
2096 }
2097
2098 /* We already trusted the base block to be valid here... */
2099 if (WARN_ON(!valid_blocks)) {
2100 kfree(edid);
2101 return NULL;
2102 }
2103
2104 edid->extensions = valid_blocks - 1;
2105 edid->checksum = edid_block_compute_checksum(edid);
2106
2107 *alloc_size = edid_size_by_blocks(valid_blocks);
2108
2109 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2110 if (!new)
2111 kfree(edid);
2112
2113 return new;
2114}
2115
2116#define DDC_SEGMENT_ADDR 0x30
2117/**
2118 * drm_do_probe_ddc_edid() - get EDID information via I2C
2119 * @data: I2C device adapter
2120 * @buf: EDID data buffer to be filled
2121 * @block: 128 byte EDID block to start fetching from
2122 * @len: EDID data buffer length to fetch
2123 *
2124 * Try to fetch EDID information by calling I2C driver functions.
2125 *
2126 * Return: 0 on success or -1 on failure.
2127 */
2128static int
2129drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2130{
2131 struct i2c_adapter *adapter = data;
2132 unsigned char start = block * EDID_LENGTH;
2133 unsigned char segment = block >> 1;
2134 unsigned char xfers = segment ? 3 : 2;
2135 int ret, retries = 5;
2136
2137 /*
2138 * The core I2C driver will automatically retry the transfer if the
2139 * adapter reports EAGAIN. However, we find that bit-banging transfers
2140 * are susceptible to errors under a heavily loaded machine and
2141 * generate spurious NAKs and timeouts. Retrying the transfer
2142 * of the individual block a few times seems to overcome this.
2143 */
2144 do {
2145 struct i2c_msg msgs[] = {
2146 {
2147 .addr = DDC_SEGMENT_ADDR,
2148 .flags = 0,
2149 .len = 1,
2150 .buf = &segment,
2151 }, {
2152 .addr = DDC_ADDR,
2153 .flags = 0,
2154 .len = 1,
2155 .buf = &start,
2156 }, {
2157 .addr = DDC_ADDR,
2158 .flags = I2C_M_RD,
2159 .len = len,
2160 .buf = buf,
2161 }
2162 };
2163
2164 /*
2165 * Avoid sending the segment addr to not upset non-compliant
2166 * DDC monitors.
2167 */
2168 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2169
2170 if (ret == -ENXIO) {
2171 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2172 adapter->name);
2173 break;
2174 }
2175 } while (ret != xfers && --retries);
2176
2177 return ret == xfers ? 0 : -1;
2178}
2179
2180static void connector_bad_edid(struct drm_connector *connector,
2181 const struct edid *edid, int num_blocks)
2182{
2183 int i;
2184 u8 last_block;
2185
2186 /*
2187 * 0x7e in the EDID is the number of extension blocks. The EDID
2188 * is 1 (base block) + num_ext_blocks big. That means we can think
2189 * of 0x7e in the EDID of the _index_ of the last block in the
2190 * combined chunk of memory.
2191 */
2192 last_block = edid->extensions;
2193
2194 /* Calculate real checksum for the last edid extension block data */
2195 if (last_block < num_blocks)
2196 connector->real_edid_checksum =
2197 edid_block_compute_checksum(edid + last_block);
2198
2199 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2200 return;
2201
2202 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2203 connector->base.id, connector->name);
2204 for (i = 0; i < num_blocks; i++)
2205 edid_block_dump(KERN_DEBUG, edid + i, i);
2206}
2207
2208/* Get override or firmware EDID */
2209static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2210{
2211 const struct drm_edid *override = NULL;
2212
2213 mutex_lock(&connector->edid_override_mutex);
2214
2215 if (connector->edid_override)
2216 override = drm_edid_dup(connector->edid_override);
2217
2218 mutex_unlock(&connector->edid_override_mutex);
2219
2220 if (!override)
2221 override = drm_edid_load_firmware(connector);
2222
2223 return IS_ERR(override) ? NULL : override;
2224}
2225
2226/* For debugfs edid_override implementation */
2227int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2228{
2229 const struct drm_edid *drm_edid;
2230
2231 mutex_lock(&connector->edid_override_mutex);
2232
2233 drm_edid = connector->edid_override;
2234 if (drm_edid)
2235 seq_write(m, drm_edid->edid, drm_edid->size);
2236
2237 mutex_unlock(&connector->edid_override_mutex);
2238
2239 return 0;
2240}
2241
2242/* For debugfs edid_override implementation */
2243int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2244 size_t size)
2245{
2246 const struct drm_edid *drm_edid;
2247
2248 drm_edid = drm_edid_alloc(edid, size);
2249 if (!drm_edid_valid(drm_edid)) {
2250 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2251 connector->base.id, connector->name);
2252 drm_edid_free(drm_edid);
2253 return -EINVAL;
2254 }
2255
2256 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2257 connector->base.id, connector->name);
2258
2259 mutex_lock(&connector->edid_override_mutex);
2260
2261 drm_edid_free(connector->edid_override);
2262 connector->edid_override = drm_edid;
2263
2264 mutex_unlock(&connector->edid_override_mutex);
2265
2266 return 0;
2267}
2268
2269/* For debugfs edid_override implementation */
2270int drm_edid_override_reset(struct drm_connector *connector)
2271{
2272 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2273 connector->base.id, connector->name);
2274
2275 mutex_lock(&connector->edid_override_mutex);
2276
2277 drm_edid_free(connector->edid_override);
2278 connector->edid_override = NULL;
2279
2280 mutex_unlock(&connector->edid_override_mutex);
2281
2282 return 0;
2283}
2284
2285/**
2286 * drm_edid_override_connector_update - add modes from override/firmware EDID
2287 * @connector: connector we're probing
2288 *
2289 * Add modes from the override/firmware EDID, if available. Only to be used from
2290 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2291 * failed during drm_get_edid() and caused the override/firmware EDID to be
2292 * skipped.
2293 *
2294 * Return: The number of modes added or 0 if we couldn't find any.
2295 */
2296int drm_edid_override_connector_update(struct drm_connector *connector)
2297{
2298 const struct drm_edid *override;
2299 int num_modes = 0;
2300
2301 override = drm_edid_override_get(connector);
2302 if (override) {
2303 if (drm_edid_connector_update(connector, override) == 0)
2304 num_modes = drm_edid_connector_add_modes(connector);
2305
2306 drm_edid_free(override);
2307
2308 drm_dbg_kms(connector->dev,
2309 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2310 connector->base.id, connector->name, num_modes);
2311 }
2312
2313 return num_modes;
2314}
2315EXPORT_SYMBOL(drm_edid_override_connector_update);
2316
2317typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2318
2319static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2320 read_block_fn read_block,
2321 void *context)
2322{
2323 enum edid_block_status status;
2324 bool is_base_block = block_num == 0;
2325 int try;
2326
2327 for (try = 0; try < 4; try++) {
2328 if (read_block(context, block, block_num, EDID_LENGTH))
2329 return EDID_BLOCK_READ_FAIL;
2330
2331 status = edid_block_check(block, is_base_block);
2332 if (status == EDID_BLOCK_HEADER_REPAIR) {
2333 edid_header_fix(block);
2334
2335 /* Retry with fixed header, update status if that worked. */
2336 status = edid_block_check(block, is_base_block);
2337 if (status == EDID_BLOCK_OK)
2338 status = EDID_BLOCK_HEADER_FIXED;
2339 }
2340
2341 if (edid_block_status_valid(status, edid_block_tag(block)))
2342 break;
2343
2344 /* Fail early for unrepairable base block all zeros. */
2345 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2346 break;
2347 }
2348
2349 return status;
2350}
2351
2352static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2353 read_block_fn read_block, void *context,
2354 size_t *size)
2355{
2356 enum edid_block_status status;
2357 int i, num_blocks, invalid_blocks = 0;
2358 const struct drm_edid *override;
2359 struct edid *edid, *new;
2360 size_t alloc_size = EDID_LENGTH;
2361
2362 override = drm_edid_override_get(connector);
2363 if (override) {
2364 alloc_size = override->size;
2365 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2366 drm_edid_free(override);
2367 if (!edid)
2368 return NULL;
2369 goto ok;
2370 }
2371
2372 edid = kmalloc(alloc_size, GFP_KERNEL);
2373 if (!edid)
2374 return NULL;
2375
2376 status = edid_block_read(edid, 0, read_block, context);
2377
2378 edid_block_status_print(status, edid, 0);
2379
2380 if (status == EDID_BLOCK_READ_FAIL)
2381 goto fail;
2382
2383 /* FIXME: Clarify what a corrupt EDID actually means. */
2384 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2385 connector->edid_corrupt = false;
2386 else
2387 connector->edid_corrupt = true;
2388
2389 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2390 if (status == EDID_BLOCK_ZERO)
2391 connector->null_edid_counter++;
2392
2393 connector_bad_edid(connector, edid, 1);
2394 goto fail;
2395 }
2396
2397 if (!edid_extension_block_count(edid))
2398 goto ok;
2399
2400 alloc_size = edid_size(edid);
2401 new = krealloc(edid, alloc_size, GFP_KERNEL);
2402 if (!new)
2403 goto fail;
2404 edid = new;
2405
2406 num_blocks = edid_block_count(edid);
2407 for (i = 1; i < num_blocks; i++) {
2408 void *block = (void *)edid_block_data(edid, i);
2409
2410 status = edid_block_read(block, i, read_block, context);
2411
2412 edid_block_status_print(status, block, i);
2413
2414 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2415 if (status == EDID_BLOCK_READ_FAIL)
2416 goto fail;
2417 invalid_blocks++;
2418 } else if (i == 1) {
2419 /*
2420 * If the first EDID extension is a CTA extension, and
2421 * the first Data Block is HF-EEODB, override the
2422 * extension block count.
2423 *
2424 * Note: HF-EEODB could specify a smaller extension
2425 * count too, but we can't risk allocating a smaller
2426 * amount.
2427 */
2428 int eeodb = edid_hfeeodb_block_count(edid);
2429
2430 if (eeodb > num_blocks) {
2431 num_blocks = eeodb;
2432 alloc_size = edid_size_by_blocks(num_blocks);
2433 new = krealloc(edid, alloc_size, GFP_KERNEL);
2434 if (!new)
2435 goto fail;
2436 edid = new;
2437 }
2438 }
2439 }
2440
2441 if (invalid_blocks) {
2442 connector_bad_edid(connector, edid, num_blocks);
2443
2444 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2445 }
2446
2447ok:
2448 if (size)
2449 *size = alloc_size;
2450
2451 return edid;
2452
2453fail:
2454 kfree(edid);
2455 return NULL;
2456}
2457
2458/**
2459 * drm_edid_raw - Get a pointer to the raw EDID data.
2460 * @drm_edid: drm_edid container
2461 *
2462 * Get a pointer to the raw EDID data.
2463 *
2464 * This is for transition only. Avoid using this like the plague.
2465 *
2466 * Return: Pointer to raw EDID data.
2467 */
2468const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2469{
2470 if (!drm_edid || !drm_edid->size)
2471 return NULL;
2472
2473 /*
2474 * Do not return pointers where relying on EDID extension count would
2475 * lead to buffer overflow.
2476 */
2477 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2478 return NULL;
2479
2480 return drm_edid->edid;
2481}
2482EXPORT_SYMBOL(drm_edid_raw);
2483
2484/* Allocate struct drm_edid container *without* duplicating the edid data */
2485static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2486{
2487 struct drm_edid *drm_edid;
2488
2489 if (!edid || !size || size < EDID_LENGTH)
2490 return NULL;
2491
2492 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2493 if (drm_edid) {
2494 drm_edid->edid = edid;
2495 drm_edid->size = size;
2496 }
2497
2498 return drm_edid;
2499}
2500
2501/**
2502 * drm_edid_alloc - Allocate a new drm_edid container
2503 * @edid: Pointer to raw EDID data
2504 * @size: Size of memory allocated for EDID
2505 *
2506 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2507 * the actual size that has been allocated for the data. There is no validation
2508 * of the raw EDID data against the size, but at least the EDID base block must
2509 * fit in the buffer.
2510 *
2511 * The returned pointer must be freed using drm_edid_free().
2512 *
2513 * Return: drm_edid container, or NULL on errors
2514 */
2515const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2516{
2517 const struct drm_edid *drm_edid;
2518
2519 if (!edid || !size || size < EDID_LENGTH)
2520 return NULL;
2521
2522 edid = kmemdup(edid, size, GFP_KERNEL);
2523 if (!edid)
2524 return NULL;
2525
2526 drm_edid = _drm_edid_alloc(edid, size);
2527 if (!drm_edid)
2528 kfree(edid);
2529
2530 return drm_edid;
2531}
2532EXPORT_SYMBOL(drm_edid_alloc);
2533
2534/**
2535 * drm_edid_dup - Duplicate a drm_edid container
2536 * @drm_edid: EDID to duplicate
2537 *
2538 * The returned pointer must be freed using drm_edid_free().
2539 *
2540 * Returns: drm_edid container copy, or NULL on errors
2541 */
2542const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2543{
2544 if (!drm_edid)
2545 return NULL;
2546
2547 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2548}
2549EXPORT_SYMBOL(drm_edid_dup);
2550
2551/**
2552 * drm_edid_free - Free the drm_edid container
2553 * @drm_edid: EDID to free
2554 */
2555void drm_edid_free(const struct drm_edid *drm_edid)
2556{
2557 if (!drm_edid)
2558 return;
2559
2560 kfree(drm_edid->edid);
2561 kfree(drm_edid);
2562}
2563EXPORT_SYMBOL(drm_edid_free);
2564
2565/**
2566 * drm_probe_ddc() - probe DDC presence
2567 * @adapter: I2C adapter to probe
2568 *
2569 * Return: True on success, false on failure.
2570 */
2571bool
2572drm_probe_ddc(struct i2c_adapter *adapter)
2573{
2574 unsigned char out;
2575
2576 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2577}
2578EXPORT_SYMBOL(drm_probe_ddc);
2579
2580/**
2581 * drm_get_edid - get EDID data, if available
2582 * @connector: connector we're probing
2583 * @adapter: I2C adapter to use for DDC
2584 *
2585 * Poke the given I2C channel to grab EDID data if possible. If found,
2586 * attach it to the connector.
2587 *
2588 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2589 */
2590struct edid *drm_get_edid(struct drm_connector *connector,
2591 struct i2c_adapter *adapter)
2592{
2593 struct edid *edid;
2594
2595 if (connector->force == DRM_FORCE_OFF)
2596 return NULL;
2597
2598 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2599 return NULL;
2600
2601 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2602 drm_connector_update_edid_property(connector, edid);
2603 return edid;
2604}
2605EXPORT_SYMBOL(drm_get_edid);
2606
2607/**
2608 * drm_edid_read_custom - Read EDID data using given EDID block read function
2609 * @connector: Connector to use
2610 * @read_block: EDID block read function
2611 * @context: Private data passed to the block read function
2612 *
2613 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2614 * exposes a different interface to read EDID blocks this function can be used
2615 * to get EDID data using a custom block read function.
2616 *
2617 * As in the general case the DDC bus is accessible by the kernel at the I2C
2618 * level, drivers must make all reasonable efforts to expose it as an I2C
2619 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2620 * this function.
2621 *
2622 * The EDID may be overridden using debugfs override_edid or firmware EDID
2623 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2624 * order. Having either of them bypasses actual EDID reads.
2625 *
2626 * The returned pointer must be freed using drm_edid_free().
2627 *
2628 * Return: Pointer to EDID, or NULL if probe/read failed.
2629 */
2630const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2631 read_block_fn read_block,
2632 void *context)
2633{
2634 const struct drm_edid *drm_edid;
2635 struct edid *edid;
2636 size_t size = 0;
2637
2638 edid = _drm_do_get_edid(connector, read_block, context, &size);
2639 if (!edid)
2640 return NULL;
2641
2642 /* Sanity check for now */
2643 drm_WARN_ON(connector->dev, !size);
2644
2645 drm_edid = _drm_edid_alloc(edid, size);
2646 if (!drm_edid)
2647 kfree(edid);
2648
2649 return drm_edid;
2650}
2651EXPORT_SYMBOL(drm_edid_read_custom);
2652
2653/**
2654 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2655 * @connector: Connector to use
2656 * @adapter: I2C adapter to use for DDC
2657 *
2658 * Read EDID using the given I2C adapter.
2659 *
2660 * The EDID may be overridden using debugfs override_edid or firmware EDID
2661 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2662 * order. Having either of them bypasses actual EDID reads.
2663 *
2664 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2665 * using drm_edid_read() instead of this function.
2666 *
2667 * The returned pointer must be freed using drm_edid_free().
2668 *
2669 * Return: Pointer to EDID, or NULL if probe/read failed.
2670 */
2671const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2672 struct i2c_adapter *adapter)
2673{
2674 const struct drm_edid *drm_edid;
2675
2676 if (connector->force == DRM_FORCE_OFF)
2677 return NULL;
2678
2679 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2680 return NULL;
2681
2682 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2683
2684 /* Note: Do *not* call connector updates here. */
2685
2686 return drm_edid;
2687}
2688EXPORT_SYMBOL(drm_edid_read_ddc);
2689
2690/**
2691 * drm_edid_read - Read EDID data using connector's I2C adapter
2692 * @connector: Connector to use
2693 *
2694 * Read EDID using the connector's I2C adapter.
2695 *
2696 * The EDID may be overridden using debugfs override_edid or firmware EDID
2697 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2698 * order. Having either of them bypasses actual EDID reads.
2699 *
2700 * The returned pointer must be freed using drm_edid_free().
2701 *
2702 * Return: Pointer to EDID, or NULL if probe/read failed.
2703 */
2704const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2705{
2706 if (drm_WARN_ON(connector->dev, !connector->ddc))
2707 return NULL;
2708
2709 return drm_edid_read_ddc(connector, connector->ddc);
2710}
2711EXPORT_SYMBOL(drm_edid_read);
2712
2713/**
2714 * drm_edid_get_product_id - Get the vendor and product identification
2715 * @drm_edid: EDID
2716 * @id: Where to place the product id
2717 */
2718void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2719 struct drm_edid_product_id *id)
2720{
2721 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2722 memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2723 else
2724 memset(id, 0, sizeof(*id));
2725}
2726EXPORT_SYMBOL(drm_edid_get_product_id);
2727
2728static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2729{
2730 int week = id->week_of_manufacture;
2731 int year = id->year_of_manufacture + 1990;
2732
2733 if (week == 0xff)
2734 seq_buf_printf(s, "model year: %d", year);
2735 else if (!week)
2736 seq_buf_printf(s, "year of manufacture: %d", year);
2737 else
2738 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2739}
2740
2741/**
2742 * drm_edid_print_product_id - Print decoded product id to printer
2743 * @p: drm printer
2744 * @id: EDID product id
2745 * @raw: If true, also print the raw hex
2746 *
2747 * See VESA E-EDID 1.4 section 3.4.
2748 */
2749void drm_edid_print_product_id(struct drm_printer *p,
2750 const struct drm_edid_product_id *id, bool raw)
2751{
2752 DECLARE_SEQ_BUF(date, 40);
2753 char vend[4];
2754
2755 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2756
2757 decode_date(&date, id);
2758
2759 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2760 vend, le16_to_cpu(id->product_code),
2761 le32_to_cpu(id->serial_number), seq_buf_str(&date));
2762
2763 if (raw)
2764 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2765
2766 WARN_ON(seq_buf_has_overflowed(&date));
2767}
2768EXPORT_SYMBOL(drm_edid_print_product_id);
2769
2770/**
2771 * drm_edid_get_panel_id - Get a panel's ID from EDID
2772 * @drm_edid: EDID that contains panel ID.
2773 *
2774 * This function uses the first block of the EDID of a panel and (assuming
2775 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2776 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2777 * supposed to be different for each different modem of panel.
2778 *
2779 * Return: A 32-bit ID that should be different for each make/model of panel.
2780 * See the functions drm_edid_encode_panel_id() and
2781 * drm_edid_decode_panel_id() for some details on the structure of this
2782 * ID. Return 0 if the EDID size is less than a base block.
2783 */
2784u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
2785{
2786 const struct edid *edid = drm_edid->edid;
2787
2788 if (drm_edid->size < EDID_LENGTH)
2789 return 0;
2790
2791 /*
2792 * We represent the ID as a 32-bit number so it can easily be compared
2793 * with "==".
2794 *
2795 * NOTE that we deal with endianness differently for the top half
2796 * of this ID than for the bottom half. The bottom half (the product
2797 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2798 * that's how everyone seems to interpret it. The top half (the mfg_id)
2799 * gets stored as big endian because that makes
2800 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2801 * to write (it's easier to extract the ASCII). It doesn't really
2802 * matter, though, as long as the number here is unique.
2803 */
2804 return (u32)edid->mfg_id[0] << 24 |
2805 (u32)edid->mfg_id[1] << 16 |
2806 (u32)EDID_PRODUCT_ID(edid);
2807}
2808EXPORT_SYMBOL(drm_edid_get_panel_id);
2809
2810/**
2811 * drm_edid_read_base_block - Get a panel's EDID base block
2812 * @adapter: I2C adapter to use for DDC
2813 *
2814 * This function returns the drm_edid containing the first block of the EDID of
2815 * a panel.
2816 *
2817 * This function is intended to be used during early probing on devices where
2818 * more than one panel might be present. Because of its intended use it must
2819 * assume that the EDID of the panel is correct, at least as far as the base
2820 * block is concerned (in other words, we don't process any overrides here).
2821 *
2822 * Caller should call drm_edid_free() after use.
2823 *
2824 * NOTE: it's expected that this function and drm_do_get_edid() will both
2825 * be read the EDID, but there is no caching between them. Since we're only
2826 * reading the first block, hopefully this extra overhead won't be too big.
2827 *
2828 * WARNING: Only use this function when the connector is unknown. For example,
2829 * during the early probe of panel. The EDID read from the function is temporary
2830 * and should be replaced by the full EDID returned from other drm_edid_read.
2831 *
2832 * Return: Pointer to allocated EDID base block, or NULL on any failure.
2833 */
2834const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
2835{
2836 enum edid_block_status status;
2837 void *base_block;
2838
2839 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2840 if (!base_block)
2841 return NULL;
2842
2843 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2844
2845 edid_block_status_print(status, base_block, 0);
2846
2847 if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
2848 edid_block_dump(KERN_NOTICE, base_block, 0);
2849 kfree(base_block);
2850 return NULL;
2851 }
2852
2853 return _drm_edid_alloc(base_block, EDID_LENGTH);
2854}
2855EXPORT_SYMBOL(drm_edid_read_base_block);
2856
2857/**
2858 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2859 * @connector: connector we're probing
2860 * @adapter: I2C adapter to use for DDC
2861 *
2862 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2863 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2864 * switch DDC to the GPU which is retrieving EDID.
2865 *
2866 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2867 */
2868struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2869 struct i2c_adapter *adapter)
2870{
2871 struct drm_device *dev = connector->dev;
2872 struct pci_dev *pdev = to_pci_dev(dev->dev);
2873 struct edid *edid;
2874
2875 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2876 return NULL;
2877
2878 vga_switcheroo_lock_ddc(pdev);
2879 edid = drm_get_edid(connector, adapter);
2880 vga_switcheroo_unlock_ddc(pdev);
2881
2882 return edid;
2883}
2884EXPORT_SYMBOL(drm_get_edid_switcheroo);
2885
2886/**
2887 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2888 * @connector: connector we're probing
2889 * @adapter: I2C adapter to use for DDC
2890 *
2891 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2892 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2893 * temporarily switch DDC to the GPU which is retrieving EDID.
2894 *
2895 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2896 */
2897const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2898 struct i2c_adapter *adapter)
2899{
2900 struct drm_device *dev = connector->dev;
2901 struct pci_dev *pdev = to_pci_dev(dev->dev);
2902 const struct drm_edid *drm_edid;
2903
2904 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2905 return NULL;
2906
2907 vga_switcheroo_lock_ddc(pdev);
2908 drm_edid = drm_edid_read_ddc(connector, adapter);
2909 vga_switcheroo_unlock_ddc(pdev);
2910
2911 return drm_edid;
2912}
2913EXPORT_SYMBOL(drm_edid_read_switcheroo);
2914
2915/**
2916 * drm_edid_duplicate - duplicate an EDID and the extensions
2917 * @edid: EDID to duplicate
2918 *
2919 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2920 */
2921struct edid *drm_edid_duplicate(const struct edid *edid)
2922{
2923 if (!edid)
2924 return NULL;
2925
2926 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2927}
2928EXPORT_SYMBOL(drm_edid_duplicate);
2929
2930/*** EDID parsing ***/
2931
2932/**
2933 * edid_get_quirks - return quirk flags for a given EDID
2934 * @drm_edid: EDID to process
2935 *
2936 * This tells subsequent routines what fixes they need to apply.
2937 *
2938 * Return: A u32 represents the quirks to apply.
2939 */
2940static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2941{
2942 const struct edid_quirk *quirk;
2943 int i;
2944
2945 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2946 quirk = &edid_quirk_list[i];
2947 if (drm_edid_match(drm_edid, &quirk->ident))
2948 return quirk->quirks;
2949 }
2950
2951 return 0;
2952}
2953
2954#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2955#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2956
2957/*
2958 * Walk the mode list for connector, clearing the preferred status on existing
2959 * modes and setting it anew for the right mode ala quirks.
2960 */
2961static void edid_fixup_preferred(struct drm_connector *connector)
2962{
2963 const struct drm_display_info *info = &connector->display_info;
2964 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2965 int target_refresh = 0;
2966 int cur_vrefresh, preferred_vrefresh;
2967
2968 if (list_empty(&connector->probed_modes))
2969 return;
2970
2971 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2972 target_refresh = 60;
2973 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2974 target_refresh = 75;
2975
2976 preferred_mode = list_first_entry(&connector->probed_modes,
2977 struct drm_display_mode, head);
2978
2979 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2980 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2981
2982 if (cur_mode == preferred_mode)
2983 continue;
2984
2985 /* Largest mode is preferred */
2986 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2987 preferred_mode = cur_mode;
2988
2989 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2990 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2991 /* At a given size, try to get closest to target refresh */
2992 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2993 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2994 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2995 preferred_mode = cur_mode;
2996 }
2997 }
2998
2999 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3000}
3001
3002static bool
3003mode_is_rb(const struct drm_display_mode *mode)
3004{
3005 return (mode->htotal - mode->hdisplay == 160) &&
3006 (mode->hsync_end - mode->hdisplay == 80) &&
3007 (mode->hsync_end - mode->hsync_start == 32) &&
3008 (mode->vsync_start - mode->vdisplay == 3);
3009}
3010
3011/*
3012 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3013 * @dev: Device to duplicate against
3014 * @hsize: Mode width
3015 * @vsize: Mode height
3016 * @fresh: Mode refresh rate
3017 * @rb: Mode reduced-blanking-ness
3018 *
3019 * Walk the DMT mode list looking for a match for the given parameters.
3020 *
3021 * Return: A newly allocated copy of the mode, or NULL if not found.
3022 */
3023struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3024 int hsize, int vsize, int fresh,
3025 bool rb)
3026{
3027 int i;
3028
3029 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3030 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3031
3032 if (hsize != ptr->hdisplay)
3033 continue;
3034 if (vsize != ptr->vdisplay)
3035 continue;
3036 if (fresh != drm_mode_vrefresh(ptr))
3037 continue;
3038 if (rb != mode_is_rb(ptr))
3039 continue;
3040
3041 return drm_mode_duplicate(dev, ptr);
3042 }
3043
3044 return NULL;
3045}
3046EXPORT_SYMBOL(drm_mode_find_dmt);
3047
3048static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3049{
3050 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3052 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3053
3054 return descriptor->pixel_clock == 0 &&
3055 descriptor->data.other_data.pad1 == 0 &&
3056 descriptor->data.other_data.type == type;
3057}
3058
3059static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3060{
3061 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3062
3063 return descriptor->pixel_clock != 0;
3064}
3065
3066typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3067
3068static void
3069cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3070{
3071 int i, n;
3072 u8 d = ext[0x02];
3073 const u8 *det_base = ext + d;
3074
3075 if (d < 4 || d > 127)
3076 return;
3077
3078 n = (127 - d) / 18;
3079 for (i = 0; i < n; i++)
3080 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3081}
3082
3083static void
3084vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3085{
3086 unsigned int i, n = min((int)ext[0x02], 6);
3087 const u8 *det_base = ext + 5;
3088
3089 if (ext[0x01] != 1)
3090 return; /* unknown version */
3091
3092 for (i = 0; i < n; i++)
3093 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3094}
3095
3096static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3097 detailed_cb *cb, void *closure)
3098{
3099 struct drm_edid_iter edid_iter;
3100 const u8 *ext;
3101 int i;
3102
3103 if (!drm_edid)
3104 return;
3105
3106 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3107 cb(&drm_edid->edid->detailed_timings[i], closure);
3108
3109 drm_edid_iter_begin(drm_edid, &edid_iter);
3110 drm_edid_iter_for_each(ext, &edid_iter) {
3111 switch (*ext) {
3112 case CEA_EXT:
3113 cea_for_each_detailed_block(ext, cb, closure);
3114 break;
3115 case VTB_EXT:
3116 vtb_for_each_detailed_block(ext, cb, closure);
3117 break;
3118 default:
3119 break;
3120 }
3121 }
3122 drm_edid_iter_end(&edid_iter);
3123}
3124
3125static void
3126is_rb(const struct detailed_timing *descriptor, void *data)
3127{
3128 bool *res = data;
3129
3130 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3131 return;
3132
3133 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3134 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3135
3136 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3137 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3138 *res = true;
3139}
3140
3141/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3142static bool
3143drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3144{
3145 if (drm_edid->edid->revision >= 4) {
3146 bool ret = false;
3147
3148 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3149 return ret;
3150 }
3151
3152 return drm_edid_is_digital(drm_edid);
3153}
3154
3155static void
3156find_gtf2(const struct detailed_timing *descriptor, void *data)
3157{
3158 const struct detailed_timing **res = data;
3159
3160 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3161 return;
3162
3163 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3164
3165 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3166 *res = descriptor;
3167}
3168
3169/* Secondary GTF curve kicks in above some break frequency */
3170static int
3171drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3172{
3173 const struct detailed_timing *descriptor = NULL;
3174
3175 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3176
3177 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3178
3179 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3180}
3181
3182static int
3183drm_gtf2_2c(const struct drm_edid *drm_edid)
3184{
3185 const struct detailed_timing *descriptor = NULL;
3186
3187 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3188
3189 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3190
3191 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3192}
3193
3194static int
3195drm_gtf2_m(const struct drm_edid *drm_edid)
3196{
3197 const struct detailed_timing *descriptor = NULL;
3198
3199 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3200
3201 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3202
3203 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3204}
3205
3206static int
3207drm_gtf2_k(const struct drm_edid *drm_edid)
3208{
3209 const struct detailed_timing *descriptor = NULL;
3210
3211 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3212
3213 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3214
3215 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3216}
3217
3218static int
3219drm_gtf2_2j(const struct drm_edid *drm_edid)
3220{
3221 const struct detailed_timing *descriptor = NULL;
3222
3223 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3224
3225 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3226
3227 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3228}
3229
3230static void
3231get_timing_level(const struct detailed_timing *descriptor, void *data)
3232{
3233 int *res = data;
3234
3235 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3236 return;
3237
3238 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3239
3240 switch (descriptor->data.other_data.data.range.flags) {
3241 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3242 *res = LEVEL_GTF;
3243 break;
3244 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3245 *res = LEVEL_GTF2;
3246 break;
3247 case DRM_EDID_CVT_SUPPORT_FLAG:
3248 *res = LEVEL_CVT;
3249 break;
3250 default:
3251 break;
3252 }
3253}
3254
3255/* Get standard timing level (CVT/GTF/DMT). */
3256static int standard_timing_level(const struct drm_edid *drm_edid)
3257{
3258 const struct edid *edid = drm_edid->edid;
3259
3260 if (edid->revision >= 4) {
3261 /*
3262 * If the range descriptor doesn't
3263 * indicate otherwise default to CVT
3264 */
3265 int ret = LEVEL_CVT;
3266
3267 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3268
3269 return ret;
3270 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3271 return LEVEL_GTF2;
3272 } else if (edid->revision >= 2) {
3273 return LEVEL_GTF;
3274 } else {
3275 return LEVEL_DMT;
3276 }
3277}
3278
3279/*
3280 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3281 * monitors fill with ascii space (0x20) instead.
3282 */
3283static int
3284bad_std_timing(u8 a, u8 b)
3285{
3286 return (a == 0x00 && b == 0x00) ||
3287 (a == 0x01 && b == 0x01) ||
3288 (a == 0x20 && b == 0x20);
3289}
3290
3291static int drm_mode_hsync(const struct drm_display_mode *mode)
3292{
3293 if (mode->htotal <= 0)
3294 return 0;
3295
3296 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3297}
3298
3299static struct drm_display_mode *
3300drm_gtf2_mode(struct drm_device *dev,
3301 const struct drm_edid *drm_edid,
3302 int hsize, int vsize, int vrefresh_rate)
3303{
3304 struct drm_display_mode *mode;
3305
3306 /*
3307 * This is potentially wrong if there's ever a monitor with
3308 * more than one ranges section, each claiming a different
3309 * secondary GTF curve. Please don't do that.
3310 */
3311 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3312 if (!mode)
3313 return NULL;
3314
3315 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3316 drm_mode_destroy(dev, mode);
3317 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3318 vrefresh_rate, 0, 0,
3319 drm_gtf2_m(drm_edid),
3320 drm_gtf2_2c(drm_edid),
3321 drm_gtf2_k(drm_edid),
3322 drm_gtf2_2j(drm_edid));
3323 }
3324
3325 return mode;
3326}
3327
3328/*
3329 * Take the standard timing params (in this case width, aspect, and refresh)
3330 * and convert them into a real mode using CVT/GTF/DMT.
3331 */
3332static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3333 const struct drm_edid *drm_edid,
3334 const struct std_timing *t)
3335{
3336 struct drm_device *dev = connector->dev;
3337 struct drm_display_mode *m, *mode = NULL;
3338 int hsize, vsize;
3339 int vrefresh_rate;
3340 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3341 >> EDID_TIMING_ASPECT_SHIFT;
3342 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3343 >> EDID_TIMING_VFREQ_SHIFT;
3344 int timing_level = standard_timing_level(drm_edid);
3345
3346 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3347 return NULL;
3348
3349 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3350 hsize = t->hsize * 8 + 248;
3351 /* vrefresh_rate = vfreq + 60 */
3352 vrefresh_rate = vfreq + 60;
3353 /* the vdisplay is calculated based on the aspect ratio */
3354 if (aspect_ratio == 0) {
3355 if (drm_edid->edid->revision < 3)
3356 vsize = hsize;
3357 else
3358 vsize = (hsize * 10) / 16;
3359 } else if (aspect_ratio == 1)
3360 vsize = (hsize * 3) / 4;
3361 else if (aspect_ratio == 2)
3362 vsize = (hsize * 4) / 5;
3363 else
3364 vsize = (hsize * 9) / 16;
3365
3366 /* HDTV hack, part 1 */
3367 if (vrefresh_rate == 60 &&
3368 ((hsize == 1360 && vsize == 765) ||
3369 (hsize == 1368 && vsize == 769))) {
3370 hsize = 1366;
3371 vsize = 768;
3372 }
3373
3374 /*
3375 * If this connector already has a mode for this size and refresh
3376 * rate (because it came from detailed or CVT info), use that
3377 * instead. This way we don't have to guess at interlace or
3378 * reduced blanking.
3379 */
3380 list_for_each_entry(m, &connector->probed_modes, head)
3381 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3382 drm_mode_vrefresh(m) == vrefresh_rate)
3383 return NULL;
3384
3385 /* HDTV hack, part 2 */
3386 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3387 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3388 false);
3389 if (!mode)
3390 return NULL;
3391 mode->hdisplay = 1366;
3392 mode->hsync_start = mode->hsync_start - 1;
3393 mode->hsync_end = mode->hsync_end - 1;
3394 return mode;
3395 }
3396
3397 /* check whether it can be found in default mode table */
3398 if (drm_monitor_supports_rb(drm_edid)) {
3399 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3400 true);
3401 if (mode)
3402 return mode;
3403 }
3404 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3405 if (mode)
3406 return mode;
3407
3408 /* okay, generate it */
3409 switch (timing_level) {
3410 case LEVEL_DMT:
3411 break;
3412 case LEVEL_GTF:
3413 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3414 break;
3415 case LEVEL_GTF2:
3416 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3417 break;
3418 case LEVEL_CVT:
3419 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3420 false);
3421 break;
3422 }
3423 return mode;
3424}
3425
3426/*
3427 * EDID is delightfully ambiguous about how interlaced modes are to be
3428 * encoded. Our internal representation is of frame height, but some
3429 * HDTV detailed timings are encoded as field height.
3430 *
3431 * The format list here is from CEA, in frame size. Technically we
3432 * should be checking refresh rate too. Whatever.
3433 */
3434static void
3435drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3436 const struct detailed_pixel_timing *pt)
3437{
3438 int i;
3439 static const struct {
3440 int w, h;
3441 } cea_interlaced[] = {
3442 { 1920, 1080 },
3443 { 720, 480 },
3444 { 1440, 480 },
3445 { 2880, 480 },
3446 { 720, 576 },
3447 { 1440, 576 },
3448 { 2880, 576 },
3449 };
3450
3451 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3452 return;
3453
3454 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3455 if ((mode->hdisplay == cea_interlaced[i].w) &&
3456 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3457 mode->vdisplay *= 2;
3458 mode->vsync_start *= 2;
3459 mode->vsync_end *= 2;
3460 mode->vtotal *= 2;
3461 mode->vtotal |= 1;
3462 }
3463 }
3464
3465 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3466}
3467
3468/*
3469 * Create a new mode from an EDID detailed timing section. An EDID detailed
3470 * timing block contains enough info for us to create and return a new struct
3471 * drm_display_mode.
3472 */
3473static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3474 const struct drm_edid *drm_edid,
3475 const struct detailed_timing *timing)
3476{
3477 const struct drm_display_info *info = &connector->display_info;
3478 struct drm_device *dev = connector->dev;
3479 struct drm_display_mode *mode;
3480 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3481 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3482 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3483 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3484 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3485 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3486 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3487 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3488 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3489
3490 /* ignore tiny modes */
3491 if (hactive < 64 || vactive < 64)
3492 return NULL;
3493
3494 if (pt->misc & DRM_EDID_PT_STEREO) {
3495 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3496 connector->base.id, connector->name);
3497 return NULL;
3498 }
3499 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3500 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3501 connector->base.id, connector->name);
3502 }
3503
3504 /* it is incorrect if hsync/vsync width is zero */
3505 if (!hsync_pulse_width || !vsync_pulse_width) {
3506 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3507 connector->base.id, connector->name);
3508 return NULL;
3509 }
3510
3511 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3512 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3513 if (!mode)
3514 return NULL;
3515
3516 goto set_size;
3517 }
3518
3519 mode = drm_mode_create(dev);
3520 if (!mode)
3521 return NULL;
3522
3523 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3524 mode->clock = 1088 * 10;
3525 else
3526 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3527
3528 mode->hdisplay = hactive;
3529 mode->hsync_start = mode->hdisplay + hsync_offset;
3530 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3531 mode->htotal = mode->hdisplay + hblank;
3532
3533 mode->vdisplay = vactive;
3534 mode->vsync_start = mode->vdisplay + vsync_offset;
3535 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3536 mode->vtotal = mode->vdisplay + vblank;
3537
3538 /* Some EDIDs have bogus h/vsync_end values */
3539 if (mode->hsync_end > mode->htotal) {
3540 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3541 connector->base.id, connector->name,
3542 mode->hsync_end, mode->htotal);
3543 mode->hsync_end = mode->htotal;
3544 }
3545 if (mode->vsync_end > mode->vtotal) {
3546 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3547 connector->base.id, connector->name,
3548 mode->vsync_end, mode->vtotal);
3549 mode->vsync_end = mode->vtotal;
3550 }
3551
3552 drm_mode_do_interlace_quirk(mode, pt);
3553
3554 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3555 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3556 } else {
3557 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3558 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3559 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3560 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3561 }
3562
3563set_size:
3564 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3565 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3566
3567 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3568 mode->width_mm *= 10;
3569 mode->height_mm *= 10;
3570 }
3571
3572 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3573 mode->width_mm = drm_edid->edid->width_cm * 10;
3574 mode->height_mm = drm_edid->edid->height_cm * 10;
3575 }
3576
3577 mode->type = DRM_MODE_TYPE_DRIVER;
3578 drm_mode_set_name(mode);
3579
3580 return mode;
3581}
3582
3583static bool
3584mode_in_hsync_range(const struct drm_display_mode *mode,
3585 const struct edid *edid, const u8 *t)
3586{
3587 int hsync, hmin, hmax;
3588
3589 hmin = t[7];
3590 if (edid->revision >= 4)
3591 hmin += ((t[4] & 0x04) ? 255 : 0);
3592 hmax = t[8];
3593 if (edid->revision >= 4)
3594 hmax += ((t[4] & 0x08) ? 255 : 0);
3595 hsync = drm_mode_hsync(mode);
3596
3597 return (hsync <= hmax && hsync >= hmin);
3598}
3599
3600static bool
3601mode_in_vsync_range(const struct drm_display_mode *mode,
3602 const struct edid *edid, const u8 *t)
3603{
3604 int vsync, vmin, vmax;
3605
3606 vmin = t[5];
3607 if (edid->revision >= 4)
3608 vmin += ((t[4] & 0x01) ? 255 : 0);
3609 vmax = t[6];
3610 if (edid->revision >= 4)
3611 vmax += ((t[4] & 0x02) ? 255 : 0);
3612 vsync = drm_mode_vrefresh(mode);
3613
3614 return (vsync <= vmax && vsync >= vmin);
3615}
3616
3617static u32
3618range_pixel_clock(const struct edid *edid, const u8 *t)
3619{
3620 /* unspecified */
3621 if (t[9] == 0 || t[9] == 255)
3622 return 0;
3623
3624 /* 1.4 with CVT support gives us real precision, yay */
3625 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3626 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3627
3628 /* 1.3 is pathetic, so fuzz up a bit */
3629 return t[9] * 10000 + 5001;
3630}
3631
3632static bool mode_in_range(const struct drm_display_mode *mode,
3633 const struct drm_edid *drm_edid,
3634 const struct detailed_timing *timing)
3635{
3636 const struct edid *edid = drm_edid->edid;
3637 u32 max_clock;
3638 const u8 *t = (const u8 *)timing;
3639
3640 if (!mode_in_hsync_range(mode, edid, t))
3641 return false;
3642
3643 if (!mode_in_vsync_range(mode, edid, t))
3644 return false;
3645
3646 max_clock = range_pixel_clock(edid, t);
3647 if (max_clock)
3648 if (mode->clock > max_clock)
3649 return false;
3650
3651 /* 1.4 max horizontal check */
3652 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3653 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3654 return false;
3655
3656 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3657 return false;
3658
3659 return true;
3660}
3661
3662static bool valid_inferred_mode(const struct drm_connector *connector,
3663 const struct drm_display_mode *mode)
3664{
3665 const struct drm_display_mode *m;
3666 bool ok = false;
3667
3668 list_for_each_entry(m, &connector->probed_modes, head) {
3669 if (mode->hdisplay == m->hdisplay &&
3670 mode->vdisplay == m->vdisplay &&
3671 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3672 return false; /* duplicated */
3673 if (mode->hdisplay <= m->hdisplay &&
3674 mode->vdisplay <= m->vdisplay)
3675 ok = true;
3676 }
3677 return ok;
3678}
3679
3680static int drm_dmt_modes_for_range(struct drm_connector *connector,
3681 const struct drm_edid *drm_edid,
3682 const struct detailed_timing *timing)
3683{
3684 int i, modes = 0;
3685 struct drm_display_mode *newmode;
3686 struct drm_device *dev = connector->dev;
3687
3688 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3689 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3690 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3691 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3692 if (newmode) {
3693 drm_mode_probed_add(connector, newmode);
3694 modes++;
3695 }
3696 }
3697 }
3698
3699 return modes;
3700}
3701
3702/* fix up 1366x768 mode from 1368x768;
3703 * GFT/CVT can't express 1366 width which isn't dividable by 8
3704 */
3705void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3706{
3707 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3708 mode->hdisplay = 1366;
3709 mode->hsync_start--;
3710 mode->hsync_end--;
3711 drm_mode_set_name(mode);
3712 }
3713}
3714
3715static int drm_gtf_modes_for_range(struct drm_connector *connector,
3716 const struct drm_edid *drm_edid,
3717 const struct detailed_timing *timing)
3718{
3719 int i, modes = 0;
3720 struct drm_display_mode *newmode;
3721 struct drm_device *dev = connector->dev;
3722
3723 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3724 const struct minimode *m = &extra_modes[i];
3725
3726 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3727 if (!newmode)
3728 return modes;
3729
3730 drm_mode_fixup_1366x768(newmode);
3731 if (!mode_in_range(newmode, drm_edid, timing) ||
3732 !valid_inferred_mode(connector, newmode)) {
3733 drm_mode_destroy(dev, newmode);
3734 continue;
3735 }
3736
3737 drm_mode_probed_add(connector, newmode);
3738 modes++;
3739 }
3740
3741 return modes;
3742}
3743
3744static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3745 const struct drm_edid *drm_edid,
3746 const struct detailed_timing *timing)
3747{
3748 int i, modes = 0;
3749 struct drm_display_mode *newmode;
3750 struct drm_device *dev = connector->dev;
3751
3752 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3753 const struct minimode *m = &extra_modes[i];
3754
3755 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3756 if (!newmode)
3757 return modes;
3758
3759 drm_mode_fixup_1366x768(newmode);
3760 if (!mode_in_range(newmode, drm_edid, timing) ||
3761 !valid_inferred_mode(connector, newmode)) {
3762 drm_mode_destroy(dev, newmode);
3763 continue;
3764 }
3765
3766 drm_mode_probed_add(connector, newmode);
3767 modes++;
3768 }
3769
3770 return modes;
3771}
3772
3773static int drm_cvt_modes_for_range(struct drm_connector *connector,
3774 const struct drm_edid *drm_edid,
3775 const struct detailed_timing *timing)
3776{
3777 int i, modes = 0;
3778 struct drm_display_mode *newmode;
3779 struct drm_device *dev = connector->dev;
3780 bool rb = drm_monitor_supports_rb(drm_edid);
3781
3782 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3783 const struct minimode *m = &extra_modes[i];
3784
3785 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3786 if (!newmode)
3787 return modes;
3788
3789 drm_mode_fixup_1366x768(newmode);
3790 if (!mode_in_range(newmode, drm_edid, timing) ||
3791 !valid_inferred_mode(connector, newmode)) {
3792 drm_mode_destroy(dev, newmode);
3793 continue;
3794 }
3795
3796 drm_mode_probed_add(connector, newmode);
3797 modes++;
3798 }
3799
3800 return modes;
3801}
3802
3803static void
3804do_inferred_modes(const struct detailed_timing *timing, void *c)
3805{
3806 struct detailed_mode_closure *closure = c;
3807 const struct detailed_non_pixel *data = &timing->data.other_data;
3808 const struct detailed_data_monitor_range *range = &data->data.range;
3809
3810 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3811 return;
3812
3813 closure->modes += drm_dmt_modes_for_range(closure->connector,
3814 closure->drm_edid,
3815 timing);
3816
3817 if (closure->drm_edid->edid->revision < 2)
3818 return; /* GTF not defined yet */
3819
3820 switch (range->flags) {
3821 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3822 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3823 closure->drm_edid,
3824 timing);
3825 break;
3826 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3827 closure->modes += drm_gtf_modes_for_range(closure->connector,
3828 closure->drm_edid,
3829 timing);
3830 break;
3831 case DRM_EDID_CVT_SUPPORT_FLAG:
3832 if (closure->drm_edid->edid->revision < 4)
3833 break;
3834
3835 closure->modes += drm_cvt_modes_for_range(closure->connector,
3836 closure->drm_edid,
3837 timing);
3838 break;
3839 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3840 default:
3841 break;
3842 }
3843}
3844
3845static int add_inferred_modes(struct drm_connector *connector,
3846 const struct drm_edid *drm_edid)
3847{
3848 struct detailed_mode_closure closure = {
3849 .connector = connector,
3850 .drm_edid = drm_edid,
3851 };
3852
3853 if (drm_edid->edid->revision >= 1)
3854 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3855
3856 return closure.modes;
3857}
3858
3859static int
3860drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3861{
3862 int i, j, m, modes = 0;
3863 struct drm_display_mode *mode;
3864 const u8 *est = ((const u8 *)timing) + 6;
3865
3866 for (i = 0; i < 6; i++) {
3867 for (j = 7; j >= 0; j--) {
3868 m = (i * 8) + (7 - j);
3869 if (m >= ARRAY_SIZE(est3_modes))
3870 break;
3871 if (est[i] & (1 << j)) {
3872 mode = drm_mode_find_dmt(connector->dev,
3873 est3_modes[m].w,
3874 est3_modes[m].h,
3875 est3_modes[m].r,
3876 est3_modes[m].rb);
3877 if (mode) {
3878 drm_mode_probed_add(connector, mode);
3879 modes++;
3880 }
3881 }
3882 }
3883 }
3884
3885 return modes;
3886}
3887
3888static void
3889do_established_modes(const struct detailed_timing *timing, void *c)
3890{
3891 struct detailed_mode_closure *closure = c;
3892
3893 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3894 return;
3895
3896 closure->modes += drm_est3_modes(closure->connector, timing);
3897}
3898
3899/*
3900 * Get established modes from EDID and add them. Each EDID block contains a
3901 * bitmap of the supported "established modes" list (defined above). Tease them
3902 * out and add them to the global modes list.
3903 */
3904static int add_established_modes(struct drm_connector *connector,
3905 const struct drm_edid *drm_edid)
3906{
3907 struct drm_device *dev = connector->dev;
3908 const struct edid *edid = drm_edid->edid;
3909 unsigned long est_bits = edid->established_timings.t1 |
3910 (edid->established_timings.t2 << 8) |
3911 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3912 int i, modes = 0;
3913 struct detailed_mode_closure closure = {
3914 .connector = connector,
3915 .drm_edid = drm_edid,
3916 };
3917
3918 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3919 if (est_bits & (1<<i)) {
3920 struct drm_display_mode *newmode;
3921
3922 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3923 if (newmode) {
3924 drm_mode_probed_add(connector, newmode);
3925 modes++;
3926 }
3927 }
3928 }
3929
3930 if (edid->revision >= 1)
3931 drm_for_each_detailed_block(drm_edid, do_established_modes,
3932 &closure);
3933
3934 return modes + closure.modes;
3935}
3936
3937static void
3938do_standard_modes(const struct detailed_timing *timing, void *c)
3939{
3940 struct detailed_mode_closure *closure = c;
3941 const struct detailed_non_pixel *data = &timing->data.other_data;
3942 struct drm_connector *connector = closure->connector;
3943 int i;
3944
3945 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3946 return;
3947
3948 for (i = 0; i < 6; i++) {
3949 const struct std_timing *std = &data->data.timings[i];
3950 struct drm_display_mode *newmode;
3951
3952 newmode = drm_mode_std(connector, closure->drm_edid, std);
3953 if (newmode) {
3954 drm_mode_probed_add(connector, newmode);
3955 closure->modes++;
3956 }
3957 }
3958}
3959
3960/*
3961 * Get standard modes from EDID and add them. Standard modes can be calculated
3962 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3963 * add them to the list.
3964 */
3965static int add_standard_modes(struct drm_connector *connector,
3966 const struct drm_edid *drm_edid)
3967{
3968 int i, modes = 0;
3969 struct detailed_mode_closure closure = {
3970 .connector = connector,
3971 .drm_edid = drm_edid,
3972 };
3973
3974 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3975 struct drm_display_mode *newmode;
3976
3977 newmode = drm_mode_std(connector, drm_edid,
3978 &drm_edid->edid->standard_timings[i]);
3979 if (newmode) {
3980 drm_mode_probed_add(connector, newmode);
3981 modes++;
3982 }
3983 }
3984
3985 if (drm_edid->edid->revision >= 1)
3986 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3987 &closure);
3988
3989 /* XXX should also look for standard codes in VTB blocks */
3990
3991 return modes + closure.modes;
3992}
3993
3994static int drm_cvt_modes(struct drm_connector *connector,
3995 const struct detailed_timing *timing)
3996{
3997 int i, j, modes = 0;
3998 struct drm_display_mode *newmode;
3999 struct drm_device *dev = connector->dev;
4000 const struct cvt_timing *cvt;
4001 static const int rates[] = { 60, 85, 75, 60, 50 };
4002 const u8 empty[3] = { 0, 0, 0 };
4003
4004 for (i = 0; i < 4; i++) {
4005 int width, height;
4006
4007 cvt = &(timing->data.other_data.data.cvt[i]);
4008
4009 if (!memcmp(cvt->code, empty, 3))
4010 continue;
4011
4012 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4013 switch (cvt->code[1] & 0x0c) {
4014 /* default - because compiler doesn't see that we've enumerated all cases */
4015 default:
4016 case 0x00:
4017 width = height * 4 / 3;
4018 break;
4019 case 0x04:
4020 width = height * 16 / 9;
4021 break;
4022 case 0x08:
4023 width = height * 16 / 10;
4024 break;
4025 case 0x0c:
4026 width = height * 15 / 9;
4027 break;
4028 }
4029
4030 for (j = 1; j < 5; j++) {
4031 if (cvt->code[2] & (1 << j)) {
4032 newmode = drm_cvt_mode(dev, width, height,
4033 rates[j], j == 0,
4034 false, false);
4035 if (newmode) {
4036 drm_mode_probed_add(connector, newmode);
4037 modes++;
4038 }
4039 }
4040 }
4041 }
4042
4043 return modes;
4044}
4045
4046static void
4047do_cvt_mode(const struct detailed_timing *timing, void *c)
4048{
4049 struct detailed_mode_closure *closure = c;
4050
4051 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4052 return;
4053
4054 closure->modes += drm_cvt_modes(closure->connector, timing);
4055}
4056
4057static int
4058add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4059{
4060 struct detailed_mode_closure closure = {
4061 .connector = connector,
4062 .drm_edid = drm_edid,
4063 };
4064
4065 if (drm_edid->edid->revision >= 3)
4066 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4067
4068 /* XXX should also look for CVT codes in VTB blocks */
4069
4070 return closure.modes;
4071}
4072
4073static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4074 struct drm_display_mode *mode);
4075
4076static void
4077do_detailed_mode(const struct detailed_timing *timing, void *c)
4078{
4079 struct detailed_mode_closure *closure = c;
4080 struct drm_display_mode *newmode;
4081
4082 if (!is_detailed_timing_descriptor(timing))
4083 return;
4084
4085 newmode = drm_mode_detailed(closure->connector,
4086 closure->drm_edid, timing);
4087 if (!newmode)
4088 return;
4089
4090 if (closure->preferred)
4091 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4092
4093 /*
4094 * Detailed modes are limited to 10kHz pixel clock resolution,
4095 * so fix up anything that looks like CEA/HDMI mode, but the clock
4096 * is just slightly off.
4097 */
4098 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4099
4100 drm_mode_probed_add(closure->connector, newmode);
4101 closure->modes++;
4102 closure->preferred = false;
4103}
4104
4105/*
4106 * add_detailed_modes - Add modes from detailed timings
4107 * @connector: attached connector
4108 * @drm_edid: EDID block to scan
4109 */
4110static int add_detailed_modes(struct drm_connector *connector,
4111 const struct drm_edid *drm_edid)
4112{
4113 struct detailed_mode_closure closure = {
4114 .connector = connector,
4115 .drm_edid = drm_edid,
4116 };
4117
4118 if (drm_edid->edid->revision >= 4)
4119 closure.preferred = true; /* first detailed timing is always preferred */
4120 else
4121 closure.preferred =
4122 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4123
4124 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4125
4126 return closure.modes;
4127}
4128
4129/* CTA-861-H Table 60 - CTA Tag Codes */
4130#define CTA_DB_AUDIO 1
4131#define CTA_DB_VIDEO 2
4132#define CTA_DB_VENDOR 3
4133#define CTA_DB_SPEAKER 4
4134#define CTA_DB_EXTENDED_TAG 7
4135
4136/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4137#define CTA_EXT_DB_VIDEO_CAP 0
4138#define CTA_EXT_DB_VENDOR 1
4139#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4140#define CTA_EXT_DB_420_VIDEO_DATA 14
4141#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4142#define CTA_EXT_DB_HF_EEODB 0x78
4143#define CTA_EXT_DB_HF_SCDB 0x79
4144
4145#define EDID_BASIC_AUDIO (1 << 6)
4146#define EDID_CEA_YCRCB444 (1 << 5)
4147#define EDID_CEA_YCRCB422 (1 << 4)
4148#define EDID_CEA_VCDB_QS (1 << 6)
4149
4150/*
4151 * Search EDID for CEA extension block.
4152 *
4153 * FIXME: Prefer not returning pointers to raw EDID data.
4154 */
4155const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4156 int ext_id, int *ext_index)
4157{
4158 const u8 *edid_ext = NULL;
4159 int i;
4160
4161 /* No EDID or EDID extensions */
4162 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4163 return NULL;
4164
4165 /* Find CEA extension */
4166 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4167 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4168 if (edid_block_tag(edid_ext) == ext_id)
4169 break;
4170 }
4171
4172 if (i >= drm_edid_extension_block_count(drm_edid))
4173 return NULL;
4174
4175 *ext_index = i + 1;
4176
4177 return edid_ext;
4178}
4179
4180/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4181static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4182{
4183 const struct displayid_block *block;
4184 struct displayid_iter iter;
4185 struct drm_edid_iter edid_iter;
4186 const u8 *ext;
4187 bool found = false;
4188
4189 /* Look for a top level CEA extension block */
4190 drm_edid_iter_begin(drm_edid, &edid_iter);
4191 drm_edid_iter_for_each(ext, &edid_iter) {
4192 if (ext[0] == CEA_EXT) {
4193 found = true;
4194 break;
4195 }
4196 }
4197 drm_edid_iter_end(&edid_iter);
4198
4199 if (found)
4200 return true;
4201
4202 /* CEA blocks can also be found embedded in a DisplayID block */
4203 displayid_iter_edid_begin(drm_edid, &iter);
4204 displayid_iter_for_each(block, &iter) {
4205 if (block->tag == DATA_BLOCK_CTA) {
4206 found = true;
4207 break;
4208 }
4209 }
4210 displayid_iter_end(&iter);
4211
4212 return found;
4213}
4214
4215static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4216{
4217 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4218 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4219
4220 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4221 return &edid_cea_modes_1[vic - 1];
4222 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4223 return &edid_cea_modes_193[vic - 193];
4224 return NULL;
4225}
4226
4227static u8 cea_num_vics(void)
4228{
4229 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4230}
4231
4232static u8 cea_next_vic(u8 vic)
4233{
4234 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4235 vic = 193;
4236 return vic;
4237}
4238
4239/*
4240 * Calculate the alternate clock for the CEA mode
4241 * (60Hz vs. 59.94Hz etc.)
4242 */
4243static unsigned int
4244cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4245{
4246 unsigned int clock = cea_mode->clock;
4247
4248 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4249 return clock;
4250
4251 /*
4252 * edid_cea_modes contains the 59.94Hz
4253 * variant for 240 and 480 line modes,
4254 * and the 60Hz variant otherwise.
4255 */
4256 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4257 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4258 else
4259 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4260
4261 return clock;
4262}
4263
4264static bool
4265cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4266{
4267 /*
4268 * For certain VICs the spec allows the vertical
4269 * front porch to vary by one or two lines.
4270 *
4271 * cea_modes[] stores the variant with the shortest
4272 * vertical front porch. We can adjust the mode to
4273 * get the other variants by simply increasing the
4274 * vertical front porch length.
4275 */
4276 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4277 cea_mode_for_vic(9)->vtotal != 262 ||
4278 cea_mode_for_vic(12)->vtotal != 262 ||
4279 cea_mode_for_vic(13)->vtotal != 262 ||
4280 cea_mode_for_vic(23)->vtotal != 312 ||
4281 cea_mode_for_vic(24)->vtotal != 312 ||
4282 cea_mode_for_vic(27)->vtotal != 312 ||
4283 cea_mode_for_vic(28)->vtotal != 312);
4284
4285 if (((vic == 8 || vic == 9 ||
4286 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4287 ((vic == 23 || vic == 24 ||
4288 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4289 mode->vsync_start++;
4290 mode->vsync_end++;
4291 mode->vtotal++;
4292
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
4299static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4300 unsigned int clock_tolerance)
4301{
4302 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4303 u8 vic;
4304
4305 if (!to_match->clock)
4306 return 0;
4307
4308 if (to_match->picture_aspect_ratio)
4309 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4310
4311 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4312 struct drm_display_mode cea_mode;
4313 unsigned int clock1, clock2;
4314
4315 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4316
4317 /* Check both 60Hz and 59.94Hz */
4318 clock1 = cea_mode.clock;
4319 clock2 = cea_mode_alternate_clock(&cea_mode);
4320
4321 if (abs(to_match->clock - clock1) > clock_tolerance &&
4322 abs(to_match->clock - clock2) > clock_tolerance)
4323 continue;
4324
4325 do {
4326 if (drm_mode_match(to_match, &cea_mode, match_flags))
4327 return vic;
4328 } while (cea_mode_alternate_timings(vic, &cea_mode));
4329 }
4330
4331 return 0;
4332}
4333
4334/**
4335 * drm_match_cea_mode - look for a CEA mode matching given mode
4336 * @to_match: display mode
4337 *
4338 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4339 * mode.
4340 */
4341u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4342{
4343 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4344 u8 vic;
4345
4346 if (!to_match->clock)
4347 return 0;
4348
4349 if (to_match->picture_aspect_ratio)
4350 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4351
4352 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4353 struct drm_display_mode cea_mode;
4354 unsigned int clock1, clock2;
4355
4356 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4357
4358 /* Check both 60Hz and 59.94Hz */
4359 clock1 = cea_mode.clock;
4360 clock2 = cea_mode_alternate_clock(&cea_mode);
4361
4362 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4363 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4364 continue;
4365
4366 do {
4367 if (drm_mode_match(to_match, &cea_mode, match_flags))
4368 return vic;
4369 } while (cea_mode_alternate_timings(vic, &cea_mode));
4370 }
4371
4372 return 0;
4373}
4374EXPORT_SYMBOL(drm_match_cea_mode);
4375
4376static bool drm_valid_cea_vic(u8 vic)
4377{
4378 return cea_mode_for_vic(vic) != NULL;
4379}
4380
4381static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4382{
4383 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4384
4385 if (mode)
4386 return mode->picture_aspect_ratio;
4387
4388 return HDMI_PICTURE_ASPECT_NONE;
4389}
4390
4391static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4392{
4393 return edid_4k_modes[video_code].picture_aspect_ratio;
4394}
4395
4396/*
4397 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4398 * specific block).
4399 */
4400static unsigned int
4401hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4402{
4403 return cea_mode_alternate_clock(hdmi_mode);
4404}
4405
4406static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4407 unsigned int clock_tolerance)
4408{
4409 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4410 u8 vic;
4411
4412 if (!to_match->clock)
4413 return 0;
4414
4415 if (to_match->picture_aspect_ratio)
4416 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4417
4418 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4419 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4420 unsigned int clock1, clock2;
4421
4422 /* Make sure to also match alternate clocks */
4423 clock1 = hdmi_mode->clock;
4424 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4425
4426 if (abs(to_match->clock - clock1) > clock_tolerance &&
4427 abs(to_match->clock - clock2) > clock_tolerance)
4428 continue;
4429
4430 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4431 return vic;
4432 }
4433
4434 return 0;
4435}
4436
4437/*
4438 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4439 * @to_match: display mode
4440 *
4441 * An HDMI mode is one defined in the HDMI vendor specific block.
4442 *
4443 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4444 */
4445static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4446{
4447 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4448 u8 vic;
4449
4450 if (!to_match->clock)
4451 return 0;
4452
4453 if (to_match->picture_aspect_ratio)
4454 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4455
4456 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4457 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4458 unsigned int clock1, clock2;
4459
4460 /* Make sure to also match alternate clocks */
4461 clock1 = hdmi_mode->clock;
4462 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4463
4464 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4465 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4466 drm_mode_match(to_match, hdmi_mode, match_flags))
4467 return vic;
4468 }
4469 return 0;
4470}
4471
4472static bool drm_valid_hdmi_vic(u8 vic)
4473{
4474 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4475}
4476
4477static int add_alternate_cea_modes(struct drm_connector *connector,
4478 const struct drm_edid *drm_edid)
4479{
4480 struct drm_device *dev = connector->dev;
4481 struct drm_display_mode *mode, *tmp;
4482 LIST_HEAD(list);
4483 int modes = 0;
4484
4485 /* Don't add CTA modes if the CTA extension block is missing */
4486 if (!drm_edid_has_cta_extension(drm_edid))
4487 return 0;
4488
4489 /*
4490 * Go through all probed modes and create a new mode
4491 * with the alternate clock for certain CEA modes.
4492 */
4493 list_for_each_entry(mode, &connector->probed_modes, head) {
4494 const struct drm_display_mode *cea_mode = NULL;
4495 struct drm_display_mode *newmode;
4496 u8 vic = drm_match_cea_mode(mode);
4497 unsigned int clock1, clock2;
4498
4499 if (drm_valid_cea_vic(vic)) {
4500 cea_mode = cea_mode_for_vic(vic);
4501 clock2 = cea_mode_alternate_clock(cea_mode);
4502 } else {
4503 vic = drm_match_hdmi_mode(mode);
4504 if (drm_valid_hdmi_vic(vic)) {
4505 cea_mode = &edid_4k_modes[vic];
4506 clock2 = hdmi_mode_alternate_clock(cea_mode);
4507 }
4508 }
4509
4510 if (!cea_mode)
4511 continue;
4512
4513 clock1 = cea_mode->clock;
4514
4515 if (clock1 == clock2)
4516 continue;
4517
4518 if (mode->clock != clock1 && mode->clock != clock2)
4519 continue;
4520
4521 newmode = drm_mode_duplicate(dev, cea_mode);
4522 if (!newmode)
4523 continue;
4524
4525 /* Carry over the stereo flags */
4526 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4527
4528 /*
4529 * The current mode could be either variant. Make
4530 * sure to pick the "other" clock for the new mode.
4531 */
4532 if (mode->clock != clock1)
4533 newmode->clock = clock1;
4534 else
4535 newmode->clock = clock2;
4536
4537 list_add_tail(&newmode->head, &list);
4538 }
4539
4540 list_for_each_entry_safe(mode, tmp, &list, head) {
4541 list_del(&mode->head);
4542 drm_mode_probed_add(connector, mode);
4543 modes++;
4544 }
4545
4546 return modes;
4547}
4548
4549static u8 svd_to_vic(u8 svd)
4550{
4551 /* 0-6 bit vic, 7th bit native mode indicator */
4552 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4553 return svd & 127;
4554
4555 return svd;
4556}
4557
4558/*
4559 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4560 * the EDID, or NULL on errors.
4561 */
4562static struct drm_display_mode *
4563drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4564{
4565 const struct drm_display_info *info = &connector->display_info;
4566 struct drm_device *dev = connector->dev;
4567
4568 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4569 return NULL;
4570
4571 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4572}
4573
4574/*
4575 * do_y420vdb_modes - Parse YCBCR 420 only modes
4576 * @connector: connector corresponding to the HDMI sink
4577 * @svds: start of the data block of CEA YCBCR 420 VDB
4578 * @len: length of the CEA YCBCR 420 VDB
4579 *
4580 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4581 * which contains modes which can be supported in YCBCR 420
4582 * output format only.
4583 */
4584static int do_y420vdb_modes(struct drm_connector *connector,
4585 const u8 *svds, u8 svds_len)
4586{
4587 struct drm_device *dev = connector->dev;
4588 int modes = 0, i;
4589
4590 for (i = 0; i < svds_len; i++) {
4591 u8 vic = svd_to_vic(svds[i]);
4592 struct drm_display_mode *newmode;
4593
4594 if (!drm_valid_cea_vic(vic))
4595 continue;
4596
4597 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4598 if (!newmode)
4599 break;
4600 drm_mode_probed_add(connector, newmode);
4601 modes++;
4602 }
4603
4604 return modes;
4605}
4606
4607/**
4608 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4609 * @dev: DRM device
4610 * @video_code: CEA VIC of the mode
4611 *
4612 * Creates a new mode matching the specified CEA VIC.
4613 *
4614 * Returns: A new drm_display_mode on success or NULL on failure
4615 */
4616struct drm_display_mode *
4617drm_display_mode_from_cea_vic(struct drm_device *dev,
4618 u8 video_code)
4619{
4620 const struct drm_display_mode *cea_mode;
4621 struct drm_display_mode *newmode;
4622
4623 cea_mode = cea_mode_for_vic(video_code);
4624 if (!cea_mode)
4625 return NULL;
4626
4627 newmode = drm_mode_duplicate(dev, cea_mode);
4628 if (!newmode)
4629 return NULL;
4630
4631 return newmode;
4632}
4633EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4634
4635/* Add modes based on VICs parsed in parse_cta_vdb() */
4636static int add_cta_vdb_modes(struct drm_connector *connector)
4637{
4638 const struct drm_display_info *info = &connector->display_info;
4639 int i, modes = 0;
4640
4641 if (!info->vics)
4642 return 0;
4643
4644 for (i = 0; i < info->vics_len; i++) {
4645 struct drm_display_mode *mode;
4646
4647 mode = drm_display_mode_from_vic_index(connector, i);
4648 if (mode) {
4649 drm_mode_probed_add(connector, mode);
4650 modes++;
4651 }
4652 }
4653
4654 return modes;
4655}
4656
4657struct stereo_mandatory_mode {
4658 int width, height, vrefresh;
4659 unsigned int flags;
4660};
4661
4662static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4663 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4664 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4665 { 1920, 1080, 50,
4666 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4667 { 1920, 1080, 60,
4668 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4669 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4670 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4671 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4672 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4673};
4674
4675static bool
4676stereo_match_mandatory(const struct drm_display_mode *mode,
4677 const struct stereo_mandatory_mode *stereo_mode)
4678{
4679 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4680
4681 return mode->hdisplay == stereo_mode->width &&
4682 mode->vdisplay == stereo_mode->height &&
4683 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4684 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4685}
4686
4687static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4688{
4689 struct drm_device *dev = connector->dev;
4690 const struct drm_display_mode *mode;
4691 struct list_head stereo_modes;
4692 int modes = 0, i;
4693
4694 INIT_LIST_HEAD(&stereo_modes);
4695
4696 list_for_each_entry(mode, &connector->probed_modes, head) {
4697 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4698 const struct stereo_mandatory_mode *mandatory;
4699 struct drm_display_mode *new_mode;
4700
4701 if (!stereo_match_mandatory(mode,
4702 &stereo_mandatory_modes[i]))
4703 continue;
4704
4705 mandatory = &stereo_mandatory_modes[i];
4706 new_mode = drm_mode_duplicate(dev, mode);
4707 if (!new_mode)
4708 continue;
4709
4710 new_mode->flags |= mandatory->flags;
4711 list_add_tail(&new_mode->head, &stereo_modes);
4712 modes++;
4713 }
4714 }
4715
4716 list_splice_tail(&stereo_modes, &connector->probed_modes);
4717
4718 return modes;
4719}
4720
4721static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4722{
4723 struct drm_device *dev = connector->dev;
4724 struct drm_display_mode *newmode;
4725
4726 if (!drm_valid_hdmi_vic(vic)) {
4727 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4728 connector->base.id, connector->name, vic);
4729 return 0;
4730 }
4731
4732 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4733 if (!newmode)
4734 return 0;
4735
4736 drm_mode_probed_add(connector, newmode);
4737
4738 return 1;
4739}
4740
4741static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4742 int vic_index)
4743{
4744 struct drm_display_mode *newmode;
4745 int modes = 0;
4746
4747 if (structure & (1 << 0)) {
4748 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4749 if (newmode) {
4750 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4751 drm_mode_probed_add(connector, newmode);
4752 modes++;
4753 }
4754 }
4755 if (structure & (1 << 6)) {
4756 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4757 if (newmode) {
4758 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4759 drm_mode_probed_add(connector, newmode);
4760 modes++;
4761 }
4762 }
4763 if (structure & (1 << 8)) {
4764 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4765 if (newmode) {
4766 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4767 drm_mode_probed_add(connector, newmode);
4768 modes++;
4769 }
4770 }
4771
4772 return modes;
4773}
4774
4775static bool hdmi_vsdb_latency_present(const u8 *db)
4776{
4777 return db[8] & BIT(7);
4778}
4779
4780static bool hdmi_vsdb_i_latency_present(const u8 *db)
4781{
4782 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4783}
4784
4785static int hdmi_vsdb_latency_length(const u8 *db)
4786{
4787 if (hdmi_vsdb_i_latency_present(db))
4788 return 4;
4789 else if (hdmi_vsdb_latency_present(db))
4790 return 2;
4791 else
4792 return 0;
4793}
4794
4795/*
4796 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4797 * @connector: connector corresponding to the HDMI sink
4798 * @db: start of the CEA vendor specific block
4799 * @len: length of the CEA block payload, ie. one can access up to db[len]
4800 *
4801 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4802 * also adds the stereo 3d modes when applicable.
4803 */
4804static int
4805do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4806{
4807 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4808 u8 vic_len, hdmi_3d_len = 0;
4809 u16 mask;
4810 u16 structure_all;
4811
4812 if (len < 8)
4813 goto out;
4814
4815 /* no HDMI_Video_Present */
4816 if (!(db[8] & (1 << 5)))
4817 goto out;
4818
4819 offset += hdmi_vsdb_latency_length(db);
4820
4821 /* the declared length is not long enough for the 2 first bytes
4822 * of additional video format capabilities */
4823 if (len < (8 + offset + 2))
4824 goto out;
4825
4826 /* 3D_Present */
4827 offset++;
4828 if (db[8 + offset] & (1 << 7)) {
4829 modes += add_hdmi_mandatory_stereo_modes(connector);
4830
4831 /* 3D_Multi_present */
4832 multi_present = (db[8 + offset] & 0x60) >> 5;
4833 }
4834
4835 offset++;
4836 vic_len = db[8 + offset] >> 5;
4837 hdmi_3d_len = db[8 + offset] & 0x1f;
4838
4839 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4840 u8 vic;
4841
4842 vic = db[9 + offset + i];
4843 modes += add_hdmi_mode(connector, vic);
4844 }
4845 offset += 1 + vic_len;
4846
4847 if (multi_present == 1)
4848 multi_len = 2;
4849 else if (multi_present == 2)
4850 multi_len = 4;
4851 else
4852 multi_len = 0;
4853
4854 if (len < (8 + offset + hdmi_3d_len - 1))
4855 goto out;
4856
4857 if (hdmi_3d_len < multi_len)
4858 goto out;
4859
4860 if (multi_present == 1 || multi_present == 2) {
4861 /* 3D_Structure_ALL */
4862 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4863
4864 /* check if 3D_MASK is present */
4865 if (multi_present == 2)
4866 mask = (db[10 + offset] << 8) | db[11 + offset];
4867 else
4868 mask = 0xffff;
4869
4870 for (i = 0; i < 16; i++) {
4871 if (mask & (1 << i))
4872 modes += add_3d_struct_modes(connector,
4873 structure_all, i);
4874 }
4875 }
4876
4877 offset += multi_len;
4878
4879 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4880 int vic_index;
4881 struct drm_display_mode *newmode = NULL;
4882 unsigned int newflag = 0;
4883 bool detail_present;
4884
4885 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4886
4887 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4888 break;
4889
4890 /* 2D_VIC_order_X */
4891 vic_index = db[8 + offset + i] >> 4;
4892
4893 /* 3D_Structure_X */
4894 switch (db[8 + offset + i] & 0x0f) {
4895 case 0:
4896 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4897 break;
4898 case 6:
4899 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4900 break;
4901 case 8:
4902 /* 3D_Detail_X */
4903 if ((db[9 + offset + i] >> 4) == 1)
4904 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4905 break;
4906 }
4907
4908 if (newflag != 0) {
4909 newmode = drm_display_mode_from_vic_index(connector,
4910 vic_index);
4911
4912 if (newmode) {
4913 newmode->flags |= newflag;
4914 drm_mode_probed_add(connector, newmode);
4915 modes++;
4916 }
4917 }
4918
4919 if (detail_present)
4920 i++;
4921 }
4922
4923out:
4924 return modes;
4925}
4926
4927static int
4928cea_revision(const u8 *cea)
4929{
4930 /*
4931 * FIXME is this correct for the DispID variant?
4932 * The DispID spec doesn't really specify whether
4933 * this is the revision of the CEA extension or
4934 * the DispID CEA data block. And the only value
4935 * given as an example is 0.
4936 */
4937 return cea[1];
4938}
4939
4940/*
4941 * CTA Data Block iterator.
4942 *
4943 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4944 * CTA Data Blocks.
4945 *
4946 * struct cea_db *db:
4947 * struct cea_db_iter iter;
4948 *
4949 * cea_db_iter_edid_begin(edid, &iter);
4950 * cea_db_iter_for_each(db, &iter) {
4951 * // do stuff with db
4952 * }
4953 * cea_db_iter_end(&iter);
4954 */
4955struct cea_db_iter {
4956 struct drm_edid_iter edid_iter;
4957 struct displayid_iter displayid_iter;
4958
4959 /* Current Data Block Collection. */
4960 const u8 *collection;
4961
4962 /* Current Data Block index in current collection. */
4963 int index;
4964
4965 /* End index in current collection. */
4966 int end;
4967};
4968
4969/* CTA-861-H section 7.4 CTA Data BLock Collection */
4970struct cea_db {
4971 u8 tag_length;
4972 u8 data[];
4973} __packed;
4974
4975static int cea_db_tag(const struct cea_db *db)
4976{
4977 return db->tag_length >> 5;
4978}
4979
4980static int cea_db_payload_len(const void *_db)
4981{
4982 /* FIXME: Transition to passing struct cea_db * everywhere. */
4983 const struct cea_db *db = _db;
4984
4985 return db->tag_length & 0x1f;
4986}
4987
4988static const void *cea_db_data(const struct cea_db *db)
4989{
4990 return db->data;
4991}
4992
4993static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4994{
4995 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4996 cea_db_payload_len(db) >= 1 &&
4997 db->data[0] == tag;
4998}
4999
5000static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5001{
5002 const u8 *data = cea_db_data(db);
5003
5004 return cea_db_tag(db) == CTA_DB_VENDOR &&
5005 cea_db_payload_len(db) >= 3 &&
5006 oui(data[2], data[1], data[0]) == vendor_oui;
5007}
5008
5009static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5010 struct cea_db_iter *iter)
5011{
5012 memset(iter, 0, sizeof(*iter));
5013
5014 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5015 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5016}
5017
5018static const struct cea_db *
5019__cea_db_iter_current_block(const struct cea_db_iter *iter)
5020{
5021 const struct cea_db *db;
5022
5023 if (!iter->collection)
5024 return NULL;
5025
5026 db = (const struct cea_db *)&iter->collection[iter->index];
5027
5028 if (iter->index + sizeof(*db) <= iter->end &&
5029 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5030 return db;
5031
5032 return NULL;
5033}
5034
5035/*
5036 * References:
5037 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5038 */
5039static int cea_db_collection_size(const u8 *cta)
5040{
5041 u8 d = cta[2];
5042
5043 if (d < 4 || d > 127)
5044 return 0;
5045
5046 return d - 4;
5047}
5048
5049/*
5050 * References:
5051 * - VESA E-EDID v1.4
5052 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5053 */
5054static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5055{
5056 const u8 *ext;
5057
5058 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5059 int size;
5060
5061 /* Only support CTA Extension revision 3+ */
5062 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5063 continue;
5064
5065 size = cea_db_collection_size(ext);
5066 if (!size)
5067 continue;
5068
5069 iter->index = 4;
5070 iter->end = iter->index + size;
5071
5072 return ext;
5073 }
5074
5075 return NULL;
5076}
5077
5078/*
5079 * References:
5080 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5081 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5082 *
5083 * Note that the above do not specify any connection between DisplayID Data
5084 * Block revision and CTA Extension versions.
5085 */
5086static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5087{
5088 const struct displayid_block *block;
5089
5090 displayid_iter_for_each(block, &iter->displayid_iter) {
5091 if (block->tag != DATA_BLOCK_CTA)
5092 continue;
5093
5094 /*
5095 * The displayid iterator has already verified the block bounds
5096 * in displayid_iter_block().
5097 */
5098 iter->index = sizeof(*block);
5099 iter->end = iter->index + block->num_bytes;
5100
5101 return block;
5102 }
5103
5104 return NULL;
5105}
5106
5107static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5108{
5109 const struct cea_db *db;
5110
5111 if (iter->collection) {
5112 /* Current collection should always be valid. */
5113 db = __cea_db_iter_current_block(iter);
5114 if (WARN_ON(!db)) {
5115 iter->collection = NULL;
5116 return NULL;
5117 }
5118
5119 /* Next block in CTA Data Block Collection */
5120 iter->index += sizeof(*db) + cea_db_payload_len(db);
5121
5122 db = __cea_db_iter_current_block(iter);
5123 if (db)
5124 return db;
5125 }
5126
5127 for (;;) {
5128 /*
5129 * Find the next CTA Data Block Collection. First iterate all
5130 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5131 *
5132 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5133 * Extension, it's recommended that DisplayID extensions are
5134 * exposed after all of the CTA Extensions.
5135 */
5136 iter->collection = __cea_db_iter_edid_next(iter);
5137 if (!iter->collection)
5138 iter->collection = __cea_db_iter_displayid_next(iter);
5139
5140 if (!iter->collection)
5141 return NULL;
5142
5143 db = __cea_db_iter_current_block(iter);
5144 if (db)
5145 return db;
5146 }
5147}
5148
5149#define cea_db_iter_for_each(__db, __iter) \
5150 while (((__db) = __cea_db_iter_next(__iter)))
5151
5152static void cea_db_iter_end(struct cea_db_iter *iter)
5153{
5154 displayid_iter_end(&iter->displayid_iter);
5155 drm_edid_iter_end(&iter->edid_iter);
5156
5157 memset(iter, 0, sizeof(*iter));
5158}
5159
5160static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5161{
5162 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5163 cea_db_payload_len(db) >= 5;
5164}
5165
5166static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5167{
5168 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5169 cea_db_payload_len(db) >= 7;
5170}
5171
5172static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5173{
5174 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5175 cea_db_payload_len(db) >= 2;
5176}
5177
5178static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5179{
5180 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5181 cea_db_payload_len(db) == 21;
5182}
5183
5184static bool cea_db_is_vcdb(const struct cea_db *db)
5185{
5186 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5187 cea_db_payload_len(db) == 2;
5188}
5189
5190static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5191{
5192 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5193 cea_db_payload_len(db) >= 7;
5194}
5195
5196static bool cea_db_is_y420cmdb(const struct cea_db *db)
5197{
5198 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5199}
5200
5201static bool cea_db_is_y420vdb(const struct cea_db *db)
5202{
5203 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5204}
5205
5206static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5207{
5208 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5209 cea_db_payload_len(db) >= 3;
5210}
5211
5212/*
5213 * Get the HF-EEODB override extension block count from EDID.
5214 *
5215 * The passed in EDID may be partially read, as long as it has at least two
5216 * blocks (base block and one extension block) if EDID extension count is > 0.
5217 *
5218 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5219 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5220 * iterators instead.
5221 *
5222 * References:
5223 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5224 */
5225static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5226{
5227 const u8 *cta;
5228
5229 /* No extensions according to base block, no HF-EEODB. */
5230 if (!edid_extension_block_count(edid))
5231 return 0;
5232
5233 /* HF-EEODB is always in the first EDID extension block only */
5234 cta = edid_extension_block_data(edid, 0);
5235 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5236 return 0;
5237
5238 /* Need to have the data block collection, and at least 3 bytes. */
5239 if (cea_db_collection_size(cta) < 3)
5240 return 0;
5241
5242 /*
5243 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5244 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5245 * through 6 of Block 1 of the E-EDID.
5246 */
5247 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5248 return 0;
5249
5250 return cta[4 + 2];
5251}
5252
5253/*
5254 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5255 *
5256 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5257 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5258 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5259 * support YCBCR420 output too.
5260 */
5261static void parse_cta_y420cmdb(struct drm_connector *connector,
5262 const struct cea_db *db, u64 *y420cmdb_map)
5263{
5264 struct drm_display_info *info = &connector->display_info;
5265 int i, map_len = cea_db_payload_len(db) - 1;
5266 const u8 *data = cea_db_data(db) + 1;
5267 u64 map = 0;
5268
5269 if (map_len == 0) {
5270 /* All CEA modes support ycbcr420 sampling also.*/
5271 map = U64_MAX;
5272 goto out;
5273 }
5274
5275 /*
5276 * This map indicates which of the existing CEA block modes
5277 * from VDB can support YCBCR420 output too. So if bit=0 is
5278 * set, first mode from VDB can support YCBCR420 output too.
5279 * We will parse and keep this map, before parsing VDB itself
5280 * to avoid going through the same block again and again.
5281 *
5282 * Spec is not clear about max possible size of this block.
5283 * Clamping max bitmap block size at 8 bytes. Every byte can
5284 * address 8 CEA modes, in this way this map can address
5285 * 8*8 = first 64 SVDs.
5286 */
5287 if (WARN_ON_ONCE(map_len > 8))
5288 map_len = 8;
5289
5290 for (i = 0; i < map_len; i++)
5291 map |= (u64)data[i] << (8 * i);
5292
5293out:
5294 if (map)
5295 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5296
5297 *y420cmdb_map = map;
5298}
5299
5300static int add_cea_modes(struct drm_connector *connector,
5301 const struct drm_edid *drm_edid)
5302{
5303 const struct cea_db *db;
5304 struct cea_db_iter iter;
5305 int modes;
5306
5307 /* CTA VDB block VICs parsed earlier */
5308 modes = add_cta_vdb_modes(connector);
5309
5310 cea_db_iter_edid_begin(drm_edid, &iter);
5311 cea_db_iter_for_each(db, &iter) {
5312 if (cea_db_is_hdmi_vsdb(db)) {
5313 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5314 cea_db_payload_len(db));
5315 } else if (cea_db_is_y420vdb(db)) {
5316 const u8 *vdb420 = cea_db_data(db) + 1;
5317
5318 /* Add 4:2:0(only) modes present in EDID */
5319 modes += do_y420vdb_modes(connector, vdb420,
5320 cea_db_payload_len(db) - 1);
5321 }
5322 }
5323 cea_db_iter_end(&iter);
5324
5325 return modes;
5326}
5327
5328static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5329 struct drm_display_mode *mode)
5330{
5331 const struct drm_display_mode *cea_mode;
5332 int clock1, clock2, clock;
5333 u8 vic;
5334 const char *type;
5335
5336 /*
5337 * allow 5kHz clock difference either way to account for
5338 * the 10kHz clock resolution limit of detailed timings.
5339 */
5340 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5341 if (drm_valid_cea_vic(vic)) {
5342 type = "CEA";
5343 cea_mode = cea_mode_for_vic(vic);
5344 clock1 = cea_mode->clock;
5345 clock2 = cea_mode_alternate_clock(cea_mode);
5346 } else {
5347 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5348 if (drm_valid_hdmi_vic(vic)) {
5349 type = "HDMI";
5350 cea_mode = &edid_4k_modes[vic];
5351 clock1 = cea_mode->clock;
5352 clock2 = hdmi_mode_alternate_clock(cea_mode);
5353 } else {
5354 return;
5355 }
5356 }
5357
5358 /* pick whichever is closest */
5359 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5360 clock = clock1;
5361 else
5362 clock = clock2;
5363
5364 if (mode->clock == clock)
5365 return;
5366
5367 drm_dbg_kms(connector->dev,
5368 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5369 connector->base.id, connector->name,
5370 type, vic, mode->clock, clock);
5371 mode->clock = clock;
5372}
5373
5374static void drm_calculate_luminance_range(struct drm_connector *connector)
5375{
5376 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5377 struct drm_luminance_range_info *luminance_range =
5378 &connector->display_info.luminance_range;
5379 static const u8 pre_computed_values[] = {
5380 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5381 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5382 };
5383 u32 max_avg, min_cll, max, min, q, r;
5384
5385 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5386 return;
5387
5388 max_avg = hdr_metadata->max_fall;
5389 min_cll = hdr_metadata->min_cll;
5390
5391 /*
5392 * From the specification (CTA-861-G), for calculating the maximum
5393 * luminance we need to use:
5394 * Luminance = 50*2**(CV/32)
5395 * Where CV is a one-byte value.
5396 * For calculating this expression we may need float point precision;
5397 * to avoid this complexity level, we take advantage that CV is divided
5398 * by a constant. From the Euclids division algorithm, we know that CV
5399 * can be written as: CV = 32*q + r. Next, we replace CV in the
5400 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5401 * need to pre-compute the value of r/32. For pre-computing the values
5402 * We just used the following Ruby line:
5403 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5404 * The results of the above expressions can be verified at
5405 * pre_computed_values.
5406 */
5407 q = max_avg >> 5;
5408 r = max_avg % 32;
5409 max = (1 << q) * pre_computed_values[r];
5410
5411 /* min luminance: maxLum * (CV/255)^2 / 100 */
5412 q = DIV_ROUND_CLOSEST(min_cll, 255);
5413 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5414
5415 luminance_range->min_luminance = min;
5416 luminance_range->max_luminance = max;
5417}
5418
5419static uint8_t eotf_supported(const u8 *edid_ext)
5420{
5421 return edid_ext[2] &
5422 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5423 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5424 BIT(HDMI_EOTF_SMPTE_ST2084) |
5425 BIT(HDMI_EOTF_BT_2100_HLG));
5426}
5427
5428static uint8_t hdr_metadata_type(const u8 *edid_ext)
5429{
5430 return edid_ext[3] &
5431 BIT(HDMI_STATIC_METADATA_TYPE1);
5432}
5433
5434static void
5435drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5436{
5437 u16 len;
5438
5439 len = cea_db_payload_len(db);
5440
5441 connector->hdr_sink_metadata.hdmi_type1.eotf =
5442 eotf_supported(db);
5443 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5444 hdr_metadata_type(db);
5445
5446 if (len >= 4)
5447 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5448 if (len >= 5)
5449 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5450 if (len >= 6) {
5451 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5452
5453 /* Calculate only when all values are available */
5454 drm_calculate_luminance_range(connector);
5455 }
5456}
5457
5458/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5459static void
5460drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5461{
5462 u8 len = cea_db_payload_len(db);
5463
5464 if (len >= 6 && (db[6] & (1 << 7)))
5465 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5466
5467 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5468 connector->latency_present[0] = true;
5469 connector->video_latency[0] = db[9];
5470 connector->audio_latency[0] = db[10];
5471 }
5472
5473 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5474 connector->latency_present[1] = true;
5475 connector->video_latency[1] = db[11];
5476 connector->audio_latency[1] = db[12];
5477 }
5478
5479 drm_dbg_kms(connector->dev,
5480 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5481 connector->base.id, connector->name,
5482 connector->latency_present[0], connector->latency_present[1],
5483 connector->video_latency[0], connector->video_latency[1],
5484 connector->audio_latency[0], connector->audio_latency[1]);
5485}
5486
5487static void
5488match_identity(const struct detailed_timing *timing, void *data)
5489{
5490 struct drm_edid_match_closure *closure = data;
5491 unsigned int i;
5492 const char *name = closure->ident->name;
5493 unsigned int name_len = strlen(name);
5494 const char *desc = timing->data.other_data.data.str.str;
5495 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5496
5497 if (name_len > desc_len ||
5498 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5499 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5500 return;
5501
5502 if (strncmp(name, desc, name_len))
5503 return;
5504
5505 for (i = name_len; i < desc_len; i++) {
5506 if (desc[i] == '\n')
5507 break;
5508 /* Allow white space before EDID string terminator. */
5509 if (!isspace(desc[i]))
5510 return;
5511 }
5512
5513 closure->matched = true;
5514}
5515
5516/**
5517 * drm_edid_match - match drm_edid with given identity
5518 * @drm_edid: EDID
5519 * @ident: the EDID identity to match with
5520 *
5521 * Check if the EDID matches with the given identity.
5522 *
5523 * Return: True if the given identity matched with EDID, false otherwise.
5524 */
5525bool drm_edid_match(const struct drm_edid *drm_edid,
5526 const struct drm_edid_ident *ident)
5527{
5528 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5529 return false;
5530
5531 /* Match with name only if it's not NULL. */
5532 if (ident->name) {
5533 struct drm_edid_match_closure closure = {
5534 .ident = ident,
5535 .matched = false,
5536 };
5537
5538 drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5539
5540 return closure.matched;
5541 }
5542
5543 return true;
5544}
5545EXPORT_SYMBOL(drm_edid_match);
5546
5547static void
5548monitor_name(const struct detailed_timing *timing, void *data)
5549{
5550 const char **res = data;
5551
5552 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5553 return;
5554
5555 *res = timing->data.other_data.data.str.str;
5556}
5557
5558static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5559{
5560 const char *edid_name = NULL;
5561 int mnl;
5562
5563 if (!drm_edid || !name)
5564 return 0;
5565
5566 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5567 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5568 if (edid_name[mnl] == 0x0a)
5569 break;
5570
5571 name[mnl] = edid_name[mnl];
5572 }
5573
5574 return mnl;
5575}
5576
5577/**
5578 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5579 * @edid: monitor EDID information
5580 * @name: pointer to a character array to hold the name of the monitor
5581 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5582 *
5583 */
5584void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5585{
5586 int name_length = 0;
5587
5588 if (bufsize <= 0)
5589 return;
5590
5591 if (edid) {
5592 char buf[13];
5593 struct drm_edid drm_edid = {
5594 .edid = edid,
5595 .size = edid_size(edid),
5596 };
5597
5598 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5599 memcpy(name, buf, name_length);
5600 }
5601
5602 name[name_length] = '\0';
5603}
5604EXPORT_SYMBOL(drm_edid_get_monitor_name);
5605
5606static void clear_eld(struct drm_connector *connector)
5607{
5608 mutex_lock(&connector->eld_mutex);
5609 memset(connector->eld, 0, sizeof(connector->eld));
5610 mutex_unlock(&connector->eld_mutex);
5611
5612 connector->latency_present[0] = false;
5613 connector->latency_present[1] = false;
5614 connector->video_latency[0] = 0;
5615 connector->audio_latency[0] = 0;
5616 connector->video_latency[1] = 0;
5617 connector->audio_latency[1] = 0;
5618}
5619
5620/*
5621 * Get 3-byte SAD buffer from struct cea_sad.
5622 */
5623void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5624{
5625 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5626 sad[1] = cta_sad->freq;
5627 sad[2] = cta_sad->byte2;
5628}
5629
5630/*
5631 * Set struct cea_sad from 3-byte SAD buffer.
5632 */
5633void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5634{
5635 cta_sad->format = (sad[0] & 0x78) >> 3;
5636 cta_sad->channels = sad[0] & 0x07;
5637 cta_sad->freq = sad[1] & 0x7f;
5638 cta_sad->byte2 = sad[2];
5639}
5640
5641/*
5642 * drm_edid_to_eld - build ELD from EDID
5643 * @connector: connector corresponding to the HDMI/DP sink
5644 * @drm_edid: EDID to parse
5645 *
5646 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5647 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5648 */
5649static void drm_edid_to_eld(struct drm_connector *connector,
5650 const struct drm_edid *drm_edid)
5651{
5652 const struct drm_display_info *info = &connector->display_info;
5653 const struct cea_db *db;
5654 struct cea_db_iter iter;
5655 uint8_t *eld = connector->eld;
5656 int total_sad_count = 0;
5657 int mnl;
5658
5659 if (!drm_edid)
5660 return;
5661
5662 mutex_lock(&connector->eld_mutex);
5663
5664 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5665 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5666 connector->base.id, connector->name,
5667 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5668
5669 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5670 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5671
5672 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5673
5674 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5675 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5676 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5677 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5678
5679 cea_db_iter_edid_begin(drm_edid, &iter);
5680 cea_db_iter_for_each(db, &iter) {
5681 const u8 *data = cea_db_data(db);
5682 int len = cea_db_payload_len(db);
5683 int sad_count;
5684
5685 switch (cea_db_tag(db)) {
5686 case CTA_DB_AUDIO:
5687 /* Audio Data Block, contains SADs */
5688 sad_count = min(len / 3, 15 - total_sad_count);
5689 if (sad_count >= 1)
5690 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5691 data, sad_count * 3);
5692 total_sad_count += sad_count;
5693 break;
5694 case CTA_DB_SPEAKER:
5695 /* Speaker Allocation Data Block */
5696 if (len >= 1)
5697 eld[DRM_ELD_SPEAKER] = data[0];
5698 break;
5699 case CTA_DB_VENDOR:
5700 /* HDMI Vendor-Specific Data Block */
5701 if (cea_db_is_hdmi_vsdb(db))
5702 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5703 break;
5704 default:
5705 break;
5706 }
5707 }
5708 cea_db_iter_end(&iter);
5709
5710 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5711
5712 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5713 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5714 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5715 else
5716 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5717
5718 eld[DRM_ELD_BASELINE_ELD_LEN] =
5719 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5720
5721 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5722 connector->base.id, connector->name,
5723 drm_eld_size(eld), total_sad_count);
5724
5725 mutex_unlock(&connector->eld_mutex);
5726}
5727
5728static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5729 struct cea_sad **psads)
5730{
5731 const struct cea_db *db;
5732 struct cea_db_iter iter;
5733 int count = 0;
5734
5735 cea_db_iter_edid_begin(drm_edid, &iter);
5736 cea_db_iter_for_each(db, &iter) {
5737 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5738 struct cea_sad *sads;
5739 int i;
5740
5741 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5742 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5743 *psads = sads;
5744 if (!sads)
5745 return -ENOMEM;
5746 for (i = 0; i < count; i++)
5747 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5748 break;
5749 }
5750 }
5751 cea_db_iter_end(&iter);
5752
5753 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5754
5755 return count;
5756}
5757
5758/**
5759 * drm_edid_to_sad - extracts SADs from EDID
5760 * @edid: EDID to parse
5761 * @sads: pointer that will be set to the extracted SADs
5762 *
5763 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5764 *
5765 * Note: The returned pointer needs to be freed using kfree().
5766 *
5767 * Return: The number of found SADs or negative number on error.
5768 */
5769int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5770{
5771 struct drm_edid drm_edid;
5772
5773 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5774}
5775EXPORT_SYMBOL(drm_edid_to_sad);
5776
5777static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5778 u8 **sadb)
5779{
5780 const struct cea_db *db;
5781 struct cea_db_iter iter;
5782 int count = 0;
5783
5784 cea_db_iter_edid_begin(drm_edid, &iter);
5785 cea_db_iter_for_each(db, &iter) {
5786 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5787 cea_db_payload_len(db) == 3) {
5788 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5789 GFP_KERNEL);
5790 if (!*sadb)
5791 return -ENOMEM;
5792 count = cea_db_payload_len(db);
5793 break;
5794 }
5795 }
5796 cea_db_iter_end(&iter);
5797
5798 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5799
5800 return count;
5801}
5802
5803/**
5804 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5805 * @edid: EDID to parse
5806 * @sadb: pointer to the speaker block
5807 *
5808 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5809 *
5810 * Note: The returned pointer needs to be freed using kfree().
5811 *
5812 * Return: The number of found Speaker Allocation Blocks or negative number on
5813 * error.
5814 */
5815int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5816{
5817 struct drm_edid drm_edid;
5818
5819 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5820 sadb);
5821}
5822EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5823
5824/**
5825 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5826 * @connector: connector associated with the HDMI/DP sink
5827 * @mode: the display mode
5828 *
5829 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5830 * the sink doesn't support audio or video.
5831 */
5832int drm_av_sync_delay(struct drm_connector *connector,
5833 const struct drm_display_mode *mode)
5834{
5835 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5836 int a, v;
5837
5838 if (!connector->latency_present[0])
5839 return 0;
5840 if (!connector->latency_present[1])
5841 i = 0;
5842
5843 a = connector->audio_latency[i];
5844 v = connector->video_latency[i];
5845
5846 /*
5847 * HDMI/DP sink doesn't support audio or video?
5848 */
5849 if (a == 255 || v == 255)
5850 return 0;
5851
5852 /*
5853 * Convert raw EDID values to millisecond.
5854 * Treat unknown latency as 0ms.
5855 */
5856 if (a)
5857 a = min(2 * (a - 1), 500);
5858 if (v)
5859 v = min(2 * (v - 1), 500);
5860
5861 return max(v - a, 0);
5862}
5863EXPORT_SYMBOL(drm_av_sync_delay);
5864
5865static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5866{
5867 const struct cea_db *db;
5868 struct cea_db_iter iter;
5869 bool hdmi = false;
5870
5871 /*
5872 * Because HDMI identifier is in Vendor Specific Block,
5873 * search it from all data blocks of CEA extension.
5874 */
5875 cea_db_iter_edid_begin(drm_edid, &iter);
5876 cea_db_iter_for_each(db, &iter) {
5877 if (cea_db_is_hdmi_vsdb(db)) {
5878 hdmi = true;
5879 break;
5880 }
5881 }
5882 cea_db_iter_end(&iter);
5883
5884 return hdmi;
5885}
5886
5887/**
5888 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5889 * @edid: monitor EDID information
5890 *
5891 * Parse the CEA extension according to CEA-861-B.
5892 *
5893 * Drivers that have added the modes parsed from EDID to drm_display_info
5894 * should use &drm_display_info.is_hdmi instead of calling this function.
5895 *
5896 * Return: True if the monitor is HDMI, false if not or unknown.
5897 */
5898bool drm_detect_hdmi_monitor(const struct edid *edid)
5899{
5900 struct drm_edid drm_edid;
5901
5902 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5903}
5904EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5905
5906static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5907{
5908 struct drm_edid_iter edid_iter;
5909 const struct cea_db *db;
5910 struct cea_db_iter iter;
5911 const u8 *edid_ext;
5912 bool has_audio = false;
5913
5914 drm_edid_iter_begin(drm_edid, &edid_iter);
5915 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5916 if (edid_ext[0] == CEA_EXT) {
5917 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5918 if (has_audio)
5919 break;
5920 }
5921 }
5922 drm_edid_iter_end(&edid_iter);
5923
5924 if (has_audio) {
5925 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5926 goto end;
5927 }
5928
5929 cea_db_iter_edid_begin(drm_edid, &iter);
5930 cea_db_iter_for_each(db, &iter) {
5931 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5932 const u8 *data = cea_db_data(db);
5933 int i;
5934
5935 for (i = 0; i < cea_db_payload_len(db); i += 3)
5936 DRM_DEBUG_KMS("CEA audio format %d\n",
5937 (data[i] >> 3) & 0xf);
5938 has_audio = true;
5939 break;
5940 }
5941 }
5942 cea_db_iter_end(&iter);
5943
5944end:
5945 return has_audio;
5946}
5947
5948/**
5949 * drm_detect_monitor_audio - check monitor audio capability
5950 * @edid: EDID block to scan
5951 *
5952 * Monitor should have CEA extension block.
5953 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5954 * audio' only. If there is any audio extension block and supported
5955 * audio format, assume at least 'basic audio' support, even if 'basic
5956 * audio' is not defined in EDID.
5957 *
5958 * Return: True if the monitor supports audio, false otherwise.
5959 */
5960bool drm_detect_monitor_audio(const struct edid *edid)
5961{
5962 struct drm_edid drm_edid;
5963
5964 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5965}
5966EXPORT_SYMBOL(drm_detect_monitor_audio);
5967
5968
5969/**
5970 * drm_default_rgb_quant_range - default RGB quantization range
5971 * @mode: display mode
5972 *
5973 * Determine the default RGB quantization range for the mode,
5974 * as specified in CEA-861.
5975 *
5976 * Return: The default RGB quantization range for the mode
5977 */
5978enum hdmi_quantization_range
5979drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5980{
5981 /* All CEA modes other than VIC 1 use limited quantization range. */
5982 return drm_match_cea_mode(mode) > 1 ?
5983 HDMI_QUANTIZATION_RANGE_LIMITED :
5984 HDMI_QUANTIZATION_RANGE_FULL;
5985}
5986EXPORT_SYMBOL(drm_default_rgb_quant_range);
5987
5988/* CTA-861 Video Data Block (CTA VDB) */
5989static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5990{
5991 struct drm_display_info *info = &connector->display_info;
5992 int i, vic_index, len = cea_db_payload_len(db);
5993 const u8 *svds = cea_db_data(db);
5994 u8 *vics;
5995
5996 if (!len)
5997 return;
5998
5999 /* Gracefully handle multiple VDBs, however unlikely that is */
6000 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6001 if (!vics)
6002 return;
6003
6004 vic_index = info->vics_len;
6005 info->vics_len += len;
6006 info->vics = vics;
6007
6008 for (i = 0; i < len; i++) {
6009 u8 vic = svd_to_vic(svds[i]);
6010
6011 if (!drm_valid_cea_vic(vic))
6012 vic = 0;
6013
6014 info->vics[vic_index++] = vic;
6015 }
6016}
6017
6018/*
6019 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6020 *
6021 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6022 * using the VICs themselves.
6023 */
6024static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6025{
6026 struct drm_display_info *info = &connector->display_info;
6027 struct drm_hdmi_info *hdmi = &info->hdmi;
6028 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6029
6030 for (i = 0; i < len; i++) {
6031 u8 vic = info->vics[i];
6032
6033 if (vic && y420cmdb_map & BIT_ULL(i))
6034 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6035 }
6036}
6037
6038static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6039{
6040 const struct drm_display_info *info = &connector->display_info;
6041 int i;
6042
6043 if (!vic || !info->vics)
6044 return false;
6045
6046 for (i = 0; i < info->vics_len; i++) {
6047 if (info->vics[i] == vic)
6048 return true;
6049 }
6050
6051 return false;
6052}
6053
6054/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
6055static void parse_cta_y420vdb(struct drm_connector *connector,
6056 const struct cea_db *db)
6057{
6058 struct drm_display_info *info = &connector->display_info;
6059 struct drm_hdmi_info *hdmi = &info->hdmi;
6060 const u8 *svds = cea_db_data(db) + 1;
6061 int i;
6062
6063 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6064 u8 vic = svd_to_vic(svds[i]);
6065
6066 if (!drm_valid_cea_vic(vic))
6067 continue;
6068
6069 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6070 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6071 }
6072}
6073
6074static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6075{
6076 struct drm_display_info *info = &connector->display_info;
6077
6078 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6079 connector->base.id, connector->name, db[2]);
6080
6081 if (db[2] & EDID_CEA_VCDB_QS)
6082 info->rgb_quant_range_selectable = true;
6083}
6084
6085static
6086void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6087{
6088 switch (max_frl_rate) {
6089 case 1:
6090 *max_lanes = 3;
6091 *max_rate_per_lane = 3;
6092 break;
6093 case 2:
6094 *max_lanes = 3;
6095 *max_rate_per_lane = 6;
6096 break;
6097 case 3:
6098 *max_lanes = 4;
6099 *max_rate_per_lane = 6;
6100 break;
6101 case 4:
6102 *max_lanes = 4;
6103 *max_rate_per_lane = 8;
6104 break;
6105 case 5:
6106 *max_lanes = 4;
6107 *max_rate_per_lane = 10;
6108 break;
6109 case 6:
6110 *max_lanes = 4;
6111 *max_rate_per_lane = 12;
6112 break;
6113 case 0:
6114 default:
6115 *max_lanes = 0;
6116 *max_rate_per_lane = 0;
6117 }
6118}
6119
6120static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6121 const u8 *db)
6122{
6123 u8 dc_mask;
6124 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6125
6126 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6127 hdmi->y420_dc_modes = dc_mask;
6128}
6129
6130static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6131 const u8 *hf_scds)
6132{
6133 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6134
6135 if (!hdmi_dsc->v_1p2)
6136 return;
6137
6138 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6139 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6140
6141 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6142 hdmi_dsc->bpc_supported = 16;
6143 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6144 hdmi_dsc->bpc_supported = 12;
6145 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6146 hdmi_dsc->bpc_supported = 10;
6147 else
6148 /* Supports min 8 BPC if DSC 1.2 is supported*/
6149 hdmi_dsc->bpc_supported = 8;
6150
6151 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6152 u8 dsc_max_slices;
6153 u8 dsc_max_frl_rate;
6154
6155 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6156 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6157 &hdmi_dsc->max_frl_rate_per_lane);
6158
6159 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6160
6161 switch (dsc_max_slices) {
6162 case 1:
6163 hdmi_dsc->max_slices = 1;
6164 hdmi_dsc->clk_per_slice = 340;
6165 break;
6166 case 2:
6167 hdmi_dsc->max_slices = 2;
6168 hdmi_dsc->clk_per_slice = 340;
6169 break;
6170 case 3:
6171 hdmi_dsc->max_slices = 4;
6172 hdmi_dsc->clk_per_slice = 340;
6173 break;
6174 case 4:
6175 hdmi_dsc->max_slices = 8;
6176 hdmi_dsc->clk_per_slice = 340;
6177 break;
6178 case 5:
6179 hdmi_dsc->max_slices = 8;
6180 hdmi_dsc->clk_per_slice = 400;
6181 break;
6182 case 6:
6183 hdmi_dsc->max_slices = 12;
6184 hdmi_dsc->clk_per_slice = 400;
6185 break;
6186 case 7:
6187 hdmi_dsc->max_slices = 16;
6188 hdmi_dsc->clk_per_slice = 400;
6189 break;
6190 case 0:
6191 default:
6192 hdmi_dsc->max_slices = 0;
6193 hdmi_dsc->clk_per_slice = 0;
6194 }
6195 }
6196
6197 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6198 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6199}
6200
6201/* Sink Capability Data Structure */
6202static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6203 const u8 *hf_scds)
6204{
6205 struct drm_display_info *info = &connector->display_info;
6206 struct drm_hdmi_info *hdmi = &info->hdmi;
6207 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6208 int max_tmds_clock = 0;
6209 u8 max_frl_rate = 0;
6210 bool dsc_support = false;
6211
6212 info->has_hdmi_infoframe = true;
6213
6214 if (hf_scds[6] & 0x80) {
6215 hdmi->scdc.supported = true;
6216 if (hf_scds[6] & 0x40)
6217 hdmi->scdc.read_request = true;
6218 }
6219
6220 /*
6221 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6222 * And as per the spec, three factors confirm this:
6223 * * Availability of a HF-VSDB block in EDID (check)
6224 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6225 * * SCDC support available (let's check)
6226 * Lets check it out.
6227 */
6228
6229 if (hf_scds[5]) {
6230 struct drm_scdc *scdc = &hdmi->scdc;
6231
6232 /* max clock is 5000 KHz times block value */
6233 max_tmds_clock = hf_scds[5] * 5000;
6234
6235 if (max_tmds_clock > 340000) {
6236 info->max_tmds_clock = max_tmds_clock;
6237 }
6238
6239 if (scdc->supported) {
6240 scdc->scrambling.supported = true;
6241
6242 /* Few sinks support scrambling for clocks < 340M */
6243 if ((hf_scds[6] & 0x8))
6244 scdc->scrambling.low_rates = true;
6245 }
6246 }
6247
6248 if (hf_scds[7]) {
6249 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6250 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6251 &hdmi->max_frl_rate_per_lane);
6252 }
6253
6254 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6255
6256 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6257 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6258 dsc_support = true;
6259 }
6260
6261 drm_dbg_kms(connector->dev,
6262 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6263 connector->base.id, connector->name,
6264 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6265}
6266
6267static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6268 const u8 *hdmi)
6269{
6270 struct drm_display_info *info = &connector->display_info;
6271 unsigned int dc_bpc = 0;
6272
6273 /* HDMI supports at least 8 bpc */
6274 info->bpc = 8;
6275
6276 if (cea_db_payload_len(hdmi) < 6)
6277 return;
6278
6279 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6280 dc_bpc = 10;
6281 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6282 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6283 connector->base.id, connector->name);
6284 }
6285
6286 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6287 dc_bpc = 12;
6288 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6289 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6290 connector->base.id, connector->name);
6291 }
6292
6293 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6294 dc_bpc = 16;
6295 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6296 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6297 connector->base.id, connector->name);
6298 }
6299
6300 if (dc_bpc == 0) {
6301 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6302 connector->base.id, connector->name);
6303 return;
6304 }
6305
6306 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6307 connector->base.id, connector->name, dc_bpc);
6308 info->bpc = dc_bpc;
6309
6310 /* YCRCB444 is optional according to spec. */
6311 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6312 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6313 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6314 connector->base.id, connector->name);
6315 }
6316
6317 /*
6318 * Spec says that if any deep color mode is supported at all,
6319 * then deep color 36 bit must be supported.
6320 */
6321 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6322 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6323 connector->base.id, connector->name);
6324 }
6325}
6326
6327/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6328static void
6329drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6330{
6331 struct drm_display_info *info = &connector->display_info;
6332 u8 len = cea_db_payload_len(db);
6333
6334 info->is_hdmi = true;
6335
6336 info->source_physical_address = (db[4] << 8) | db[5];
6337
6338 if (len >= 6)
6339 info->dvi_dual = db[6] & 1;
6340 if (len >= 7)
6341 info->max_tmds_clock = db[7] * 5000;
6342
6343 /*
6344 * Try to infer whether the sink supports HDMI infoframes.
6345 *
6346 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6347 * supports infoframes if HDMI_Video_present is set.
6348 */
6349 if (len >= 8 && db[8] & BIT(5))
6350 info->has_hdmi_infoframe = true;
6351
6352 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6353 connector->base.id, connector->name,
6354 info->dvi_dual, info->max_tmds_clock);
6355
6356 drm_parse_hdmi_deep_color_info(connector, db);
6357}
6358
6359/*
6360 * See EDID extension for head-mounted and specialized monitors, specified at:
6361 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6362 */
6363static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6364 const u8 *db)
6365{
6366 struct drm_display_info *info = &connector->display_info;
6367 u8 version = db[4];
6368 bool desktop_usage = db[5] & BIT(6);
6369
6370 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6371 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6372 info->non_desktop = true;
6373
6374 drm_dbg_kms(connector->dev,
6375 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6376 connector->base.id, connector->name, version, db[5]);
6377}
6378
6379static void drm_parse_cea_ext(struct drm_connector *connector,
6380 const struct drm_edid *drm_edid)
6381{
6382 struct drm_display_info *info = &connector->display_info;
6383 struct drm_edid_iter edid_iter;
6384 const struct cea_db *db;
6385 struct cea_db_iter iter;
6386 const u8 *edid_ext;
6387 u64 y420cmdb_map = 0;
6388
6389 drm_edid_iter_begin(drm_edid, &edid_iter);
6390 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6391 if (edid_ext[0] != CEA_EXT)
6392 continue;
6393
6394 if (!info->cea_rev)
6395 info->cea_rev = edid_ext[1];
6396
6397 if (info->cea_rev != edid_ext[1])
6398 drm_dbg_kms(connector->dev,
6399 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6400 connector->base.id, connector->name,
6401 info->cea_rev, edid_ext[1]);
6402
6403 /* The existence of a CTA extension should imply RGB support */
6404 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6405 if (edid_ext[3] & EDID_CEA_YCRCB444)
6406 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6407 if (edid_ext[3] & EDID_CEA_YCRCB422)
6408 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6409 if (edid_ext[3] & EDID_BASIC_AUDIO)
6410 info->has_audio = true;
6411
6412 }
6413 drm_edid_iter_end(&edid_iter);
6414
6415 cea_db_iter_edid_begin(drm_edid, &iter);
6416 cea_db_iter_for_each(db, &iter) {
6417 /* FIXME: convert parsers to use struct cea_db */
6418 const u8 *data = (const u8 *)db;
6419
6420 if (cea_db_is_hdmi_vsdb(db))
6421 drm_parse_hdmi_vsdb_video(connector, data);
6422 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6423 cea_db_is_hdmi_forum_scdb(db))
6424 drm_parse_hdmi_forum_scds(connector, data);
6425 else if (cea_db_is_microsoft_vsdb(db))
6426 drm_parse_microsoft_vsdb(connector, data);
6427 else if (cea_db_is_y420cmdb(db))
6428 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6429 else if (cea_db_is_y420vdb(db))
6430 parse_cta_y420vdb(connector, db);
6431 else if (cea_db_is_vcdb(db))
6432 drm_parse_vcdb(connector, data);
6433 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6434 drm_parse_hdr_metadata_block(connector, data);
6435 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6436 parse_cta_vdb(connector, db);
6437 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6438 info->has_audio = true;
6439 }
6440 cea_db_iter_end(&iter);
6441
6442 if (y420cmdb_map)
6443 update_cta_y420cmdb(connector, y420cmdb_map);
6444}
6445
6446static
6447void get_monitor_range(const struct detailed_timing *timing, void *c)
6448{
6449 struct detailed_mode_closure *closure = c;
6450 struct drm_display_info *info = &closure->connector->display_info;
6451 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6452 const struct detailed_non_pixel *data = &timing->data.other_data;
6453 const struct detailed_data_monitor_range *range = &data->data.range;
6454 const struct edid *edid = closure->drm_edid->edid;
6455
6456 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6457 return;
6458
6459 /*
6460 * These limits are used to determine the VRR refresh
6461 * rate range. Only the "range limits only" variant
6462 * of the range descriptor seems to guarantee that
6463 * any and all timings are accepted by the sink, as
6464 * opposed to just timings conforming to the indicated
6465 * formula (GTF/GTF2/CVT). Thus other variants of the
6466 * range descriptor are not accepted here.
6467 */
6468 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6469 return;
6470
6471 monitor_range->min_vfreq = range->min_vfreq;
6472 monitor_range->max_vfreq = range->max_vfreq;
6473
6474 if (edid->revision >= 4) {
6475 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6476 monitor_range->min_vfreq += 255;
6477 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6478 monitor_range->max_vfreq += 255;
6479 }
6480}
6481
6482static void drm_get_monitor_range(struct drm_connector *connector,
6483 const struct drm_edid *drm_edid)
6484{
6485 const struct drm_display_info *info = &connector->display_info;
6486 struct detailed_mode_closure closure = {
6487 .connector = connector,
6488 .drm_edid = drm_edid,
6489 };
6490
6491 if (drm_edid->edid->revision < 4)
6492 return;
6493
6494 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6495 return;
6496
6497 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6498
6499 drm_dbg_kms(connector->dev,
6500 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6501 connector->base.id, connector->name,
6502 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6503}
6504
6505static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6506 const struct displayid_block *block)
6507{
6508 struct displayid_vesa_vendor_specific_block *vesa =
6509 (struct displayid_vesa_vendor_specific_block *)block;
6510 struct drm_display_info *info = &connector->display_info;
6511
6512 if (block->num_bytes < 3) {
6513 drm_dbg_kms(connector->dev,
6514 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6515 connector->base.id, connector->name, block->num_bytes);
6516 return;
6517 }
6518
6519 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6520 return;
6521
6522 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6523 drm_dbg_kms(connector->dev,
6524 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6525 connector->base.id, connector->name);
6526 return;
6527 }
6528
6529 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6530 default:
6531 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6532 connector->base.id, connector->name);
6533 fallthrough;
6534 case 0:
6535 info->mso_stream_count = 0;
6536 break;
6537 case 1:
6538 info->mso_stream_count = 2; /* 2 or 4 links */
6539 break;
6540 case 2:
6541 info->mso_stream_count = 4; /* 4 links */
6542 break;
6543 }
6544
6545 if (!info->mso_stream_count) {
6546 info->mso_pixel_overlap = 0;
6547 return;
6548 }
6549
6550 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6551 if (info->mso_pixel_overlap > 8) {
6552 drm_dbg_kms(connector->dev,
6553 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6554 connector->base.id, connector->name,
6555 info->mso_pixel_overlap);
6556 info->mso_pixel_overlap = 8;
6557 }
6558
6559 drm_dbg_kms(connector->dev,
6560 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6561 connector->base.id, connector->name,
6562 info->mso_stream_count, info->mso_pixel_overlap);
6563}
6564
6565static void drm_update_mso(struct drm_connector *connector,
6566 const struct drm_edid *drm_edid)
6567{
6568 const struct displayid_block *block;
6569 struct displayid_iter iter;
6570
6571 displayid_iter_edid_begin(drm_edid, &iter);
6572 displayid_iter_for_each(block, &iter) {
6573 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6574 drm_parse_vesa_mso_data(connector, block);
6575 }
6576 displayid_iter_end(&iter);
6577}
6578
6579/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6580 * all of the values which would have been set from EDID
6581 */
6582static void drm_reset_display_info(struct drm_connector *connector)
6583{
6584 struct drm_display_info *info = &connector->display_info;
6585
6586 info->width_mm = 0;
6587 info->height_mm = 0;
6588
6589 info->bpc = 0;
6590 info->color_formats = 0;
6591 info->cea_rev = 0;
6592 info->max_tmds_clock = 0;
6593 info->dvi_dual = false;
6594 info->is_hdmi = false;
6595 info->has_audio = false;
6596 info->has_hdmi_infoframe = false;
6597 info->rgb_quant_range_selectable = false;
6598 memset(&info->hdmi, 0, sizeof(info->hdmi));
6599
6600 info->edid_hdmi_rgb444_dc_modes = 0;
6601 info->edid_hdmi_ycbcr444_dc_modes = 0;
6602
6603 info->non_desktop = 0;
6604 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6605 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6606
6607 info->mso_stream_count = 0;
6608 info->mso_pixel_overlap = 0;
6609 info->max_dsc_bpp = 0;
6610
6611 kfree(info->vics);
6612 info->vics = NULL;
6613 info->vics_len = 0;
6614
6615 info->quirks = 0;
6616
6617 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6618}
6619
6620static void update_displayid_info(struct drm_connector *connector,
6621 const struct drm_edid *drm_edid)
6622{
6623 struct drm_display_info *info = &connector->display_info;
6624 const struct displayid_block *block;
6625 struct displayid_iter iter;
6626
6627 displayid_iter_edid_begin(drm_edid, &iter);
6628 displayid_iter_for_each(block, &iter) {
6629 drm_dbg_kms(connector->dev,
6630 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n",
6631 connector->base.id, connector->name,
6632 displayid_version(&iter),
6633 displayid_primary_use(&iter));
6634 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6635 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6636 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6637 info->non_desktop = true;
6638
6639 /*
6640 * We're only interested in the base section here, no need to
6641 * iterate further.
6642 */
6643 break;
6644 }
6645 displayid_iter_end(&iter);
6646}
6647
6648static void update_display_info(struct drm_connector *connector,
6649 const struct drm_edid *drm_edid)
6650{
6651 struct drm_display_info *info = &connector->display_info;
6652 const struct edid *edid;
6653
6654 drm_reset_display_info(connector);
6655 clear_eld(connector);
6656
6657 if (!drm_edid)
6658 return;
6659
6660 edid = drm_edid->edid;
6661
6662 info->quirks = edid_get_quirks(drm_edid);
6663
6664 info->width_mm = edid->width_cm * 10;
6665 info->height_mm = edid->height_cm * 10;
6666
6667 drm_get_monitor_range(connector, drm_edid);
6668
6669 if (edid->revision < 3)
6670 goto out;
6671
6672 if (!drm_edid_is_digital(drm_edid))
6673 goto out;
6674
6675 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6676 drm_parse_cea_ext(connector, drm_edid);
6677
6678 update_displayid_info(connector, drm_edid);
6679
6680 /*
6681 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6682 *
6683 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6684 * tells us to assume 8 bpc color depth if the EDID doesn't have
6685 * extensions which tell otherwise.
6686 */
6687 if (info->bpc == 0 && edid->revision == 3 &&
6688 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6689 info->bpc = 8;
6690 drm_dbg_kms(connector->dev,
6691 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6692 connector->base.id, connector->name, info->bpc);
6693 }
6694
6695 /* Only defined for 1.4 with digital displays */
6696 if (edid->revision < 4)
6697 goto out;
6698
6699 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6700 case DRM_EDID_DIGITAL_DEPTH_6:
6701 info->bpc = 6;
6702 break;
6703 case DRM_EDID_DIGITAL_DEPTH_8:
6704 info->bpc = 8;
6705 break;
6706 case DRM_EDID_DIGITAL_DEPTH_10:
6707 info->bpc = 10;
6708 break;
6709 case DRM_EDID_DIGITAL_DEPTH_12:
6710 info->bpc = 12;
6711 break;
6712 case DRM_EDID_DIGITAL_DEPTH_14:
6713 info->bpc = 14;
6714 break;
6715 case DRM_EDID_DIGITAL_DEPTH_16:
6716 info->bpc = 16;
6717 break;
6718 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6719 default:
6720 info->bpc = 0;
6721 break;
6722 }
6723
6724 drm_dbg_kms(connector->dev,
6725 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6726 connector->base.id, connector->name, info->bpc);
6727
6728 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6729 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6730 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6731 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6732
6733 drm_update_mso(connector, drm_edid);
6734
6735out:
6736 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6737 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6738 connector->base.id, connector->name,
6739 info->non_desktop ? " (redundant quirk)" : "");
6740 info->non_desktop = true;
6741 }
6742
6743 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6744 info->max_dsc_bpp = 15;
6745
6746 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6747 info->bpc = 6;
6748
6749 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6750 info->bpc = 8;
6751
6752 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6753 info->bpc = 10;
6754
6755 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6756 info->bpc = 12;
6757
6758 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6759 drm_edid_to_eld(connector, drm_edid);
6760}
6761
6762static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6763 struct displayid_detailed_timings_1 *timings,
6764 bool type_7)
6765{
6766 struct drm_display_mode *mode;
6767 unsigned pixel_clock = (timings->pixel_clock[0] |
6768 (timings->pixel_clock[1] << 8) |
6769 (timings->pixel_clock[2] << 16)) + 1;
6770 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6771 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6772 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6773 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6774 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6775 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6776 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6777 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6778 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6779 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6780
6781 mode = drm_mode_create(dev);
6782 if (!mode)
6783 return NULL;
6784
6785 /* resolution is kHz for type VII, and 10 kHz for type I */
6786 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6787 mode->hdisplay = hactive;
6788 mode->hsync_start = mode->hdisplay + hsync;
6789 mode->hsync_end = mode->hsync_start + hsync_width;
6790 mode->htotal = mode->hdisplay + hblank;
6791
6792 mode->vdisplay = vactive;
6793 mode->vsync_start = mode->vdisplay + vsync;
6794 mode->vsync_end = mode->vsync_start + vsync_width;
6795 mode->vtotal = mode->vdisplay + vblank;
6796
6797 mode->flags = 0;
6798 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6799 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6800 mode->type = DRM_MODE_TYPE_DRIVER;
6801
6802 if (timings->flags & 0x80)
6803 mode->type |= DRM_MODE_TYPE_PREFERRED;
6804 drm_mode_set_name(mode);
6805
6806 return mode;
6807}
6808
6809static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6810 const struct displayid_block *block)
6811{
6812 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6813 int i;
6814 int num_timings;
6815 struct drm_display_mode *newmode;
6816 int num_modes = 0;
6817 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6818 /* blocks must be multiple of 20 bytes length */
6819 if (block->num_bytes % 20)
6820 return 0;
6821
6822 num_timings = block->num_bytes / 20;
6823 for (i = 0; i < num_timings; i++) {
6824 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6825
6826 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6827 if (!newmode)
6828 continue;
6829
6830 drm_mode_probed_add(connector, newmode);
6831 num_modes++;
6832 }
6833 return num_modes;
6834}
6835
6836static int add_displayid_detailed_modes(struct drm_connector *connector,
6837 const struct drm_edid *drm_edid)
6838{
6839 const struct displayid_block *block;
6840 struct displayid_iter iter;
6841 int num_modes = 0;
6842
6843 displayid_iter_edid_begin(drm_edid, &iter);
6844 displayid_iter_for_each(block, &iter) {
6845 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6846 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6847 num_modes += add_displayid_detailed_1_modes(connector, block);
6848 }
6849 displayid_iter_end(&iter);
6850
6851 return num_modes;
6852}
6853
6854static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6855 const struct drm_edid *drm_edid)
6856{
6857 const struct drm_display_info *info = &connector->display_info;
6858 int num_modes = 0;
6859
6860 if (!drm_edid)
6861 return 0;
6862
6863 /*
6864 * EDID spec says modes should be preferred in this order:
6865 * - preferred detailed mode
6866 * - other detailed modes from base block
6867 * - detailed modes from extension blocks
6868 * - CVT 3-byte code modes
6869 * - standard timing codes
6870 * - established timing codes
6871 * - modes inferred from GTF or CVT range information
6872 *
6873 * We get this pretty much right.
6874 *
6875 * XXX order for additional mode types in extension blocks?
6876 */
6877 num_modes += add_detailed_modes(connector, drm_edid);
6878 num_modes += add_cvt_modes(connector, drm_edid);
6879 num_modes += add_standard_modes(connector, drm_edid);
6880 num_modes += add_established_modes(connector, drm_edid);
6881 num_modes += add_cea_modes(connector, drm_edid);
6882 num_modes += add_alternate_cea_modes(connector, drm_edid);
6883 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6884 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6885 num_modes += add_inferred_modes(connector, drm_edid);
6886
6887 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6888 edid_fixup_preferred(connector);
6889
6890 return num_modes;
6891}
6892
6893static void _drm_update_tile_info(struct drm_connector *connector,
6894 const struct drm_edid *drm_edid);
6895
6896static int _drm_edid_connector_property_update(struct drm_connector *connector,
6897 const struct drm_edid *drm_edid)
6898{
6899 struct drm_device *dev = connector->dev;
6900 int ret;
6901
6902 if (connector->edid_blob_ptr) {
6903 const void *old_edid = connector->edid_blob_ptr->data;
6904 size_t old_edid_size = connector->edid_blob_ptr->length;
6905
6906 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6907 connector->epoch_counter++;
6908 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6909 connector->base.id, connector->name,
6910 connector->epoch_counter);
6911 }
6912 }
6913
6914 ret = drm_property_replace_global_blob(dev,
6915 &connector->edid_blob_ptr,
6916 drm_edid ? drm_edid->size : 0,
6917 drm_edid ? drm_edid->edid : NULL,
6918 &connector->base,
6919 dev->mode_config.edid_property);
6920 if (ret) {
6921 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6922 connector->base.id, connector->name, ret);
6923 goto out;
6924 }
6925
6926 ret = drm_object_property_set_value(&connector->base,
6927 dev->mode_config.non_desktop_property,
6928 connector->display_info.non_desktop);
6929 if (ret) {
6930 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6931 connector->base.id, connector->name, ret);
6932 goto out;
6933 }
6934
6935 ret = drm_connector_set_tile_property(connector);
6936 if (ret) {
6937 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6938 connector->base.id, connector->name, ret);
6939 goto out;
6940 }
6941
6942out:
6943 return ret;
6944}
6945
6946/* For sysfs edid show implementation */
6947ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
6948 char *buf, loff_t off, size_t count)
6949{
6950 const void *edid;
6951 size_t size;
6952 ssize_t ret = 0;
6953
6954 mutex_lock(&connector->dev->mode_config.mutex);
6955
6956 if (!connector->edid_blob_ptr)
6957 goto unlock;
6958
6959 edid = connector->edid_blob_ptr->data;
6960 size = connector->edid_blob_ptr->length;
6961 if (!edid)
6962 goto unlock;
6963
6964 if (off >= size)
6965 goto unlock;
6966
6967 if (off + count > size)
6968 count = size - off;
6969
6970 memcpy(buf, edid + off, count);
6971
6972 ret = count;
6973unlock:
6974 mutex_unlock(&connector->dev->mode_config.mutex);
6975
6976 return ret;
6977}
6978
6979/**
6980 * drm_edid_connector_update - Update connector information from EDID
6981 * @connector: Connector
6982 * @drm_edid: EDID
6983 *
6984 * Update the connector display info, ELD, HDR metadata, relevant properties,
6985 * etc. from the passed in EDID.
6986 *
6987 * If EDID is NULL, reset the information.
6988 *
6989 * Must be called before calling drm_edid_connector_add_modes().
6990 *
6991 * Return: 0 on success, negative error on errors.
6992 */
6993int drm_edid_connector_update(struct drm_connector *connector,
6994 const struct drm_edid *drm_edid)
6995{
6996 update_display_info(connector, drm_edid);
6997
6998 _drm_update_tile_info(connector, drm_edid);
6999
7000 return _drm_edid_connector_property_update(connector, drm_edid);
7001}
7002EXPORT_SYMBOL(drm_edid_connector_update);
7003
7004/**
7005 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7006 * @connector: Connector
7007 *
7008 * Add the modes from the previously updated EDID property to the connector
7009 * probed modes list.
7010 *
7011 * drm_edid_connector_update() must have been called before this to update the
7012 * EDID property.
7013 *
7014 * Return: The number of modes added, or 0 if we couldn't find any.
7015 */
7016int drm_edid_connector_add_modes(struct drm_connector *connector)
7017{
7018 const struct drm_edid *drm_edid = NULL;
7019 int count;
7020
7021 if (connector->edid_blob_ptr)
7022 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7023 connector->edid_blob_ptr->length);
7024
7025 count = _drm_edid_connector_add_modes(connector, drm_edid);
7026
7027 drm_edid_free(drm_edid);
7028
7029 return count;
7030}
7031EXPORT_SYMBOL(drm_edid_connector_add_modes);
7032
7033/**
7034 * drm_connector_update_edid_property - update the edid property of a connector
7035 * @connector: drm connector
7036 * @edid: new value of the edid property
7037 *
7038 * This function creates a new blob modeset object and assigns its id to the
7039 * connector's edid property.
7040 * Since we also parse tile information from EDID's displayID block, we also
7041 * set the connector's tile property here. See drm_connector_set_tile_property()
7042 * for more details.
7043 *
7044 * This function is deprecated. Use drm_edid_connector_update() instead.
7045 *
7046 * Returns:
7047 * Zero on success, negative errno on failure.
7048 */
7049int drm_connector_update_edid_property(struct drm_connector *connector,
7050 const struct edid *edid)
7051{
7052 struct drm_edid drm_edid;
7053
7054 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
7055}
7056EXPORT_SYMBOL(drm_connector_update_edid_property);
7057
7058/**
7059 * drm_add_edid_modes - add modes from EDID data, if available
7060 * @connector: connector we're probing
7061 * @edid: EDID data
7062 *
7063 * Add the specified modes to the connector's mode list. Also fills out the
7064 * &drm_display_info structure and ELD in @connector with any information which
7065 * can be derived from the edid.
7066 *
7067 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
7068 *
7069 * Return: The number of modes added or 0 if we couldn't find any.
7070 */
7071int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7072{
7073 struct drm_edid _drm_edid;
7074 const struct drm_edid *drm_edid;
7075
7076 if (edid && !drm_edid_is_valid(edid)) {
7077 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7078 connector->base.id, connector->name);
7079 edid = NULL;
7080 }
7081
7082 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7083
7084 update_display_info(connector, drm_edid);
7085
7086 return _drm_edid_connector_add_modes(connector, drm_edid);
7087}
7088EXPORT_SYMBOL(drm_add_edid_modes);
7089
7090/**
7091 * drm_add_modes_noedid - add modes for the connectors without EDID
7092 * @connector: connector we're probing
7093 * @hdisplay: the horizontal display limit
7094 * @vdisplay: the vertical display limit
7095 *
7096 * Add the specified modes to the connector's mode list. Only when the
7097 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7098 *
7099 * Return: The number of modes added or 0 if we couldn't find any.
7100 */
7101int drm_add_modes_noedid(struct drm_connector *connector,
7102 int hdisplay, int vdisplay)
7103{
7104 int i, count, num_modes = 0;
7105 struct drm_display_mode *mode;
7106 struct drm_device *dev = connector->dev;
7107
7108 count = ARRAY_SIZE(drm_dmt_modes);
7109 if (hdisplay < 0)
7110 hdisplay = 0;
7111 if (vdisplay < 0)
7112 vdisplay = 0;
7113
7114 for (i = 0; i < count; i++) {
7115 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
7116
7117 if (hdisplay && vdisplay) {
7118 /*
7119 * Only when two are valid, they will be used to check
7120 * whether the mode should be added to the mode list of
7121 * the connector.
7122 */
7123 if (ptr->hdisplay > hdisplay ||
7124 ptr->vdisplay > vdisplay)
7125 continue;
7126 }
7127 if (drm_mode_vrefresh(ptr) > 61)
7128 continue;
7129 mode = drm_mode_duplicate(dev, ptr);
7130 if (mode) {
7131 drm_mode_probed_add(connector, mode);
7132 num_modes++;
7133 }
7134 }
7135 return num_modes;
7136}
7137EXPORT_SYMBOL(drm_add_modes_noedid);
7138
7139static bool is_hdmi2_sink(const struct drm_connector *connector)
7140{
7141 /*
7142 * FIXME: sil-sii8620 doesn't have a connector around when
7143 * we need one, so we have to be prepared for a NULL connector.
7144 */
7145 if (!connector)
7146 return true;
7147
7148 return connector->display_info.hdmi.scdc.supported ||
7149 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7150}
7151
7152static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7153 const struct drm_display_mode *mode)
7154{
7155 bool has_hdmi_infoframe = connector ?
7156 connector->display_info.has_hdmi_infoframe : false;
7157
7158 if (!has_hdmi_infoframe)
7159 return 0;
7160
7161 /* No HDMI VIC when signalling 3D video format */
7162 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7163 return 0;
7164
7165 return drm_match_hdmi_mode(mode);
7166}
7167
7168static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7169 const struct drm_display_mode *mode)
7170{
7171 /*
7172 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7173 * we should send its VIC in vendor infoframes, else send the
7174 * VIC in AVI infoframes. Lets check if this mode is present in
7175 * HDMI 1.4b 4K modes
7176 */
7177 if (drm_mode_hdmi_vic(connector, mode))
7178 return 0;
7179
7180 return drm_match_cea_mode(mode);
7181}
7182
7183/*
7184 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7185 * conform to HDMI 1.4.
7186 *
7187 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7188 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7189 *
7190 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7191 * version.
7192 */
7193static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7194{
7195 if (!is_hdmi2_sink(connector) && vic > 64 &&
7196 !cta_vdb_has_vic(connector, vic))
7197 return 0;
7198
7199 return vic;
7200}
7201
7202/**
7203 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7204 * data from a DRM display mode
7205 * @frame: HDMI AVI infoframe
7206 * @connector: the connector
7207 * @mode: DRM display mode
7208 *
7209 * Return: 0 on success or a negative error code on failure.
7210 */
7211int
7212drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7213 const struct drm_connector *connector,
7214 const struct drm_display_mode *mode)
7215{
7216 enum hdmi_picture_aspect picture_aspect;
7217 u8 vic, hdmi_vic;
7218
7219 if (!frame || !mode)
7220 return -EINVAL;
7221
7222 hdmi_avi_infoframe_init(frame);
7223
7224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7225 frame->pixel_repeat = 1;
7226
7227 vic = drm_mode_cea_vic(connector, mode);
7228 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7229
7230 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7231
7232 /*
7233 * As some drivers don't support atomic, we can't use connector state.
7234 * So just initialize the frame with default values, just the same way
7235 * as it's done with other properties here.
7236 */
7237 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7238 frame->itc = 0;
7239
7240 /*
7241 * Populate picture aspect ratio from either
7242 * user input (if specified) or from the CEA/HDMI mode lists.
7243 */
7244 picture_aspect = mode->picture_aspect_ratio;
7245 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7246 if (vic)
7247 picture_aspect = drm_get_cea_aspect_ratio(vic);
7248 else if (hdmi_vic)
7249 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7250 }
7251
7252 /*
7253 * The infoframe can't convey anything but none, 4:3
7254 * and 16:9, so if the user has asked for anything else
7255 * we can only satisfy it by specifying the right VIC.
7256 */
7257 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7258 if (vic) {
7259 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7260 return -EINVAL;
7261 } else if (hdmi_vic) {
7262 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7263 return -EINVAL;
7264 } else {
7265 return -EINVAL;
7266 }
7267
7268 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7269 }
7270
7271 frame->video_code = vic_for_avi_infoframe(connector, vic);
7272 frame->picture_aspect = picture_aspect;
7273 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7274 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7275
7276 return 0;
7277}
7278EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7279
7280/**
7281 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7282 * quantization range information
7283 * @frame: HDMI AVI infoframe
7284 * @connector: the connector
7285 * @mode: DRM display mode
7286 * @rgb_quant_range: RGB quantization range (Q)
7287 */
7288void
7289drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7290 const struct drm_connector *connector,
7291 const struct drm_display_mode *mode,
7292 enum hdmi_quantization_range rgb_quant_range)
7293{
7294 const struct drm_display_info *info = &connector->display_info;
7295
7296 /*
7297 * CEA-861:
7298 * "A Source shall not send a non-zero Q value that does not correspond
7299 * to the default RGB Quantization Range for the transmitted Picture
7300 * unless the Sink indicates support for the Q bit in a Video
7301 * Capabilities Data Block."
7302 *
7303 * HDMI 2.0 recommends sending non-zero Q when it does match the
7304 * default RGB quantization range for the mode, even when QS=0.
7305 */
7306 if (info->rgb_quant_range_selectable ||
7307 rgb_quant_range == drm_default_rgb_quant_range(mode))
7308 frame->quantization_range = rgb_quant_range;
7309 else
7310 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7311
7312 /*
7313 * CEA-861-F:
7314 * "When transmitting any RGB colorimetry, the Source should set the
7315 * YQ-field to match the RGB Quantization Range being transmitted
7316 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7317 * set YQ=1) and the Sink shall ignore the YQ-field."
7318 *
7319 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7320 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7321 * good way to tell which version of CEA-861 the sink supports, so
7322 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7323 * on CEA-861-F.
7324 */
7325 if (!is_hdmi2_sink(connector) ||
7326 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7327 frame->ycc_quantization_range =
7328 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7329 else
7330 frame->ycc_quantization_range =
7331 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7332}
7333EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7334
7335static enum hdmi_3d_structure
7336s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7337{
7338 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7339
7340 switch (layout) {
7341 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7342 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7343 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7344 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7345 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7346 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7347 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7348 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7349 case DRM_MODE_FLAG_3D_L_DEPTH:
7350 return HDMI_3D_STRUCTURE_L_DEPTH;
7351 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7352 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7353 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7354 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7355 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7356 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7357 default:
7358 return HDMI_3D_STRUCTURE_INVALID;
7359 }
7360}
7361
7362/**
7363 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7364 * data from a DRM display mode
7365 * @frame: HDMI vendor infoframe
7366 * @connector: the connector
7367 * @mode: DRM display mode
7368 *
7369 * Note that there's is a need to send HDMI vendor infoframes only when using a
7370 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7371 * function will return -EINVAL, error that can be safely ignored.
7372 *
7373 * Return: 0 on success or a negative error code on failure.
7374 */
7375int
7376drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7377 const struct drm_connector *connector,
7378 const struct drm_display_mode *mode)
7379{
7380 /*
7381 * FIXME: sil-sii8620 doesn't have a connector around when
7382 * we need one, so we have to be prepared for a NULL connector.
7383 */
7384 bool has_hdmi_infoframe = connector ?
7385 connector->display_info.has_hdmi_infoframe : false;
7386 int err;
7387
7388 if (!frame || !mode)
7389 return -EINVAL;
7390
7391 if (!has_hdmi_infoframe)
7392 return -EINVAL;
7393
7394 err = hdmi_vendor_infoframe_init(frame);
7395 if (err < 0)
7396 return err;
7397
7398 /*
7399 * Even if it's not absolutely necessary to send the infoframe
7400 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7401 * know that the sink can handle it. This is based on a
7402 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7403 * have trouble realizing that they should switch from 3D to 2D
7404 * mode if the source simply stops sending the infoframe when
7405 * it wants to switch from 3D to 2D.
7406 */
7407 frame->vic = drm_mode_hdmi_vic(connector, mode);
7408 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7409
7410 return 0;
7411}
7412EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7413
7414static void drm_parse_tiled_block(struct drm_connector *connector,
7415 const struct displayid_block *block)
7416{
7417 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7418 u16 w, h;
7419 u8 tile_v_loc, tile_h_loc;
7420 u8 num_v_tile, num_h_tile;
7421 struct drm_tile_group *tg;
7422
7423 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7424 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7425
7426 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7427 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7428 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7429 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7430
7431 connector->has_tile = true;
7432 if (tile->tile_cap & 0x80)
7433 connector->tile_is_single_monitor = true;
7434
7435 connector->num_h_tile = num_h_tile + 1;
7436 connector->num_v_tile = num_v_tile + 1;
7437 connector->tile_h_loc = tile_h_loc;
7438 connector->tile_v_loc = tile_v_loc;
7439 connector->tile_h_size = w + 1;
7440 connector->tile_v_size = h + 1;
7441
7442 drm_dbg_kms(connector->dev,
7443 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7444 connector->base.id, connector->name,
7445 tile->tile_cap,
7446 connector->tile_h_size, connector->tile_v_size,
7447 connector->num_h_tile, connector->num_v_tile,
7448 connector->tile_h_loc, connector->tile_v_loc,
7449 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7450
7451 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7452 if (!tg)
7453 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7454 if (!tg)
7455 return;
7456
7457 if (connector->tile_group != tg) {
7458 /* if we haven't got a pointer,
7459 take the reference, drop ref to old tile group */
7460 if (connector->tile_group)
7461 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7462 connector->tile_group = tg;
7463 } else {
7464 /* if same tile group, then release the ref we just took. */
7465 drm_mode_put_tile_group(connector->dev, tg);
7466 }
7467}
7468
7469static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7470 const struct displayid_block *block)
7471{
7472 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7473 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7474 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7475 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7476}
7477
7478static void _drm_update_tile_info(struct drm_connector *connector,
7479 const struct drm_edid *drm_edid)
7480{
7481 const struct displayid_block *block;
7482 struct displayid_iter iter;
7483
7484 connector->has_tile = false;
7485
7486 displayid_iter_edid_begin(drm_edid, &iter);
7487 displayid_iter_for_each(block, &iter) {
7488 if (displayid_is_tiled_block(&iter, block))
7489 drm_parse_tiled_block(connector, block);
7490 }
7491 displayid_iter_end(&iter);
7492
7493 if (!connector->has_tile && connector->tile_group) {
7494 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7495 connector->tile_group = NULL;
7496 }
7497}
7498
7499/**
7500 * drm_edid_is_digital - is digital?
7501 * @drm_edid: The EDID
7502 *
7503 * Return true if input is digital.
7504 */
7505bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7506{
7507 return drm_edid && drm_edid->edid &&
7508 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7509}
7510EXPORT_SYMBOL(drm_edid_is_digital);
1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/hdmi.h>
33#include <linux/i2c.h>
34#include <linux/module.h>
35#include <drm/drmP.h>
36#include <drm/drm_edid.h>
37
38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
41
42#define EDID_EST_TIMINGS 16
43#define EDID_STD_TIMINGS 8
44#define EDID_DETAILED_TIMINGS 4
45
46/*
47 * EDID blocks out in the wild have a variety of bugs, try to collect
48 * them here (note that userspace may work around broken monitors first,
49 * but fixes should make their way here so that the kernel "just works"
50 * on as many displays as possible).
51 */
52
53/* First detailed mode wrong, use largest 60Hz mode */
54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
55/* Reported 135MHz pixel clock is too high, needs adjustment */
56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
57/* Prefer the largest mode at 75 Hz */
58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
59/* Detail timing is in cm not mm */
60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
61/* Detailed timing descriptors have bogus size values, so just take the
62 * maximum size and use that.
63 */
64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
65/* Monitor forgot to set the first detailed is preferred bit. */
66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
67/* use +hsync +vsync for detailed mode */
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
69/* Force reduced-blanking timings for detailed modes */
70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
71/* Force 8bpc */
72#define EDID_QUIRK_FORCE_8BPC (1 << 8)
73
74struct detailed_mode_closure {
75 struct drm_connector *connector;
76 struct edid *edid;
77 bool preferred;
78 u32 quirks;
79 int modes;
80};
81
82#define LEVEL_DMT 0
83#define LEVEL_GTF 1
84#define LEVEL_GTF2 2
85#define LEVEL_CVT 3
86
87static struct edid_quirk {
88 char vendor[4];
89 int product_id;
90 u32 quirks;
91} edid_quirk_list[] = {
92 /* Acer AL1706 */
93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
94 /* Acer F51 */
95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
96 /* Unknown Acer */
97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
98
99 /* Belinea 10 15 55 */
100 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
101 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
102
103 /* Envision Peripherals, Inc. EN-7100e */
104 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
105 /* Envision EN2028 */
106 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
107
108 /* Funai Electronics PM36B */
109 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
110 EDID_QUIRK_DETAILED_IN_CM },
111
112 /* LG Philips LCD LP154W01-A5 */
113 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
114 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
115
116 /* Philips 107p5 CRT */
117 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
118
119 /* Proview AY765C */
120 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
121
122 /* Samsung SyncMaster 205BW. Note: irony */
123 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
124 /* Samsung SyncMaster 22[5-6]BW */
125 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
126 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
127
128 /* ViewSonic VA2026w */
129 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
130
131 /* Medion MD 30217 PG */
132 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
133
134 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
135 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
136};
137
138/*
139 * Autogenerated from the DMT spec.
140 * This table is copied from xfree86/modes/xf86EdidModes.c.
141 */
142static const struct drm_display_mode drm_dmt_modes[] = {
143 /* 640x350@85Hz */
144 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
145 736, 832, 0, 350, 382, 385, 445, 0,
146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
147 /* 640x400@85Hz */
148 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
149 736, 832, 0, 400, 401, 404, 445, 0,
150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
151 /* 720x400@85Hz */
152 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
153 828, 936, 0, 400, 401, 404, 446, 0,
154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
155 /* 640x480@60Hz */
156 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
157 752, 800, 0, 480, 489, 492, 525, 0,
158 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
159 /* 640x480@72Hz */
160 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
161 704, 832, 0, 480, 489, 492, 520, 0,
162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
163 /* 640x480@75Hz */
164 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
165 720, 840, 0, 480, 481, 484, 500, 0,
166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
167 /* 640x480@85Hz */
168 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
169 752, 832, 0, 480, 481, 484, 509, 0,
170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
171 /* 800x600@56Hz */
172 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
173 896, 1024, 0, 600, 601, 603, 625, 0,
174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
175 /* 800x600@60Hz */
176 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
177 968, 1056, 0, 600, 601, 605, 628, 0,
178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
179 /* 800x600@72Hz */
180 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
181 976, 1040, 0, 600, 637, 643, 666, 0,
182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
183 /* 800x600@75Hz */
184 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
185 896, 1056, 0, 600, 601, 604, 625, 0,
186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
187 /* 800x600@85Hz */
188 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
189 896, 1048, 0, 600, 601, 604, 631, 0,
190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
191 /* 800x600@120Hz RB */
192 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
193 880, 960, 0, 600, 603, 607, 636, 0,
194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
195 /* 848x480@60Hz */
196 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
197 976, 1088, 0, 480, 486, 494, 517, 0,
198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
199 /* 1024x768@43Hz, interlace */
200 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
201 1208, 1264, 0, 768, 768, 772, 817, 0,
202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
203 DRM_MODE_FLAG_INTERLACE) },
204 /* 1024x768@60Hz */
205 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
206 1184, 1344, 0, 768, 771, 777, 806, 0,
207 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
208 /* 1024x768@70Hz */
209 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
210 1184, 1328, 0, 768, 771, 777, 806, 0,
211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
212 /* 1024x768@75Hz */
213 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
214 1136, 1312, 0, 768, 769, 772, 800, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
216 /* 1024x768@85Hz */
217 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
218 1168, 1376, 0, 768, 769, 772, 808, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
220 /* 1024x768@120Hz RB */
221 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
222 1104, 1184, 0, 768, 771, 775, 813, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
224 /* 1152x864@75Hz */
225 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
226 1344, 1600, 0, 864, 865, 868, 900, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228 /* 1280x768@60Hz RB */
229 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
230 1360, 1440, 0, 768, 771, 778, 790, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
232 /* 1280x768@60Hz */
233 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
234 1472, 1664, 0, 768, 771, 778, 798, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 1280x768@75Hz */
237 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
238 1488, 1696, 0, 768, 771, 778, 805, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 1280x768@85Hz */
241 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
242 1496, 1712, 0, 768, 771, 778, 809, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
244 /* 1280x768@120Hz RB */
245 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
246 1360, 1440, 0, 768, 771, 778, 813, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 1280x800@60Hz RB */
249 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
250 1360, 1440, 0, 800, 803, 809, 823, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 1280x800@60Hz */
253 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
254 1480, 1680, 0, 800, 803, 809, 831, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 1280x800@75Hz */
257 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
258 1488, 1696, 0, 800, 803, 809, 838, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 1280x800@85Hz */
261 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
262 1496, 1712, 0, 800, 803, 809, 843, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 1280x800@120Hz RB */
265 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
266 1360, 1440, 0, 800, 803, 809, 847, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 1280x960@60Hz */
269 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
270 1488, 1800, 0, 960, 961, 964, 1000, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 1280x960@85Hz */
273 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
274 1504, 1728, 0, 960, 961, 964, 1011, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 1280x960@120Hz RB */
277 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
278 1360, 1440, 0, 960, 963, 967, 1017, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 1280x1024@60Hz */
281 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
282 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 1280x1024@75Hz */
285 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
286 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 1280x1024@85Hz */
289 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
290 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 1280x1024@120Hz RB */
293 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
294 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 1360x768@60Hz */
297 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
298 1536, 1792, 0, 768, 771, 777, 795, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 1360x768@120Hz RB */
301 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
302 1440, 1520, 0, 768, 771, 776, 813, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
304 /* 1400x1050@60Hz RB */
305 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
306 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 1400x1050@60Hz */
309 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
310 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 1400x1050@75Hz */
313 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
314 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
316 /* 1400x1050@85Hz */
317 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
318 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 1400x1050@120Hz RB */
321 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
322 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
324 /* 1440x900@60Hz RB */
325 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
326 1520, 1600, 0, 900, 903, 909, 926, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 1440x900@60Hz */
329 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
330 1672, 1904, 0, 900, 903, 909, 934, 0,
331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 1440x900@75Hz */
333 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
334 1688, 1936, 0, 900, 903, 909, 942, 0,
335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 1440x900@85Hz */
337 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
338 1696, 1952, 0, 900, 903, 909, 948, 0,
339 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
340 /* 1440x900@120Hz RB */
341 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
342 1520, 1600, 0, 900, 903, 909, 953, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
344 /* 1600x1200@60Hz */
345 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
346 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 1600x1200@65Hz */
349 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
350 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 1600x1200@70Hz */
353 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
354 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
356 /* 1600x1200@75Hz */
357 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
358 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
360 /* 1600x1200@85Hz */
361 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
362 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 1600x1200@120Hz RB */
365 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
366 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368 /* 1680x1050@60Hz RB */
369 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
370 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
372 /* 1680x1050@60Hz */
373 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
374 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
376 /* 1680x1050@75Hz */
377 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
378 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 1680x1050@85Hz */
381 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
382 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 1680x1050@120Hz RB */
385 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
386 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 1792x1344@60Hz */
389 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
390 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 1792x1344@75Hz */
393 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
394 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 1792x1344@120Hz RB */
397 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
398 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
400 /* 1856x1392@60Hz */
401 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
402 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
404 /* 1856x1392@75Hz */
405 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
406 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 1856x1392@120Hz RB */
409 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
410 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 1920x1200@60Hz RB */
413 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
414 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416 /* 1920x1200@60Hz */
417 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
418 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 1920x1200@75Hz */
421 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
422 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
424 /* 1920x1200@85Hz */
425 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
426 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 1920x1200@120Hz RB */
429 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
430 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
432 /* 1920x1440@60Hz */
433 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
434 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 1920x1440@75Hz */
437 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
438 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 1920x1440@120Hz RB */
441 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
442 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 2560x1600@60Hz RB */
445 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
446 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 2560x1600@60Hz */
449 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
450 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 2560x1600@75HZ */
453 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
454 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 2560x1600@85HZ */
457 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
458 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 2560x1600@120Hz RB */
461 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
462 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464};
465
466/*
467 * These more or less come from the DMT spec. The 720x400 modes are
468 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
469 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
470 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
471 * mode.
472 *
473 * The DMT modes have been fact-checked; the rest are mild guesses.
474 */
475static const struct drm_display_mode edid_est_modes[] = {
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
477 968, 1056, 0, 600, 601, 605, 628, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
479 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
480 896, 1024, 0, 600, 601, 603, 625, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
482 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
483 720, 840, 0, 480, 481, 484, 500, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
485 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
486 704, 832, 0, 480, 489, 491, 520, 0,
487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
488 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
489 768, 864, 0, 480, 483, 486, 525, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
492 752, 800, 0, 480, 490, 492, 525, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
494 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
495 846, 900, 0, 400, 421, 423, 449, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
497 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
498 846, 900, 0, 400, 412, 414, 449, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
500 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
501 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
503 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
504 1136, 1312, 0, 768, 769, 772, 800, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
506 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
507 1184, 1328, 0, 768, 771, 777, 806, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
510 1184, 1344, 0, 768, 771, 777, 806, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
512 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
513 1208, 1264, 0, 768, 768, 776, 817, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
515 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
516 928, 1152, 0, 624, 625, 628, 667, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
519 896, 1056, 0, 600, 601, 604, 625, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
521 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
522 976, 1040, 0, 600, 637, 643, 666, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
524 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
525 1344, 1600, 0, 864, 865, 868, 900, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
527};
528
529struct minimode {
530 short w;
531 short h;
532 short r;
533 short rb;
534};
535
536static const struct minimode est3_modes[] = {
537 /* byte 6 */
538 { 640, 350, 85, 0 },
539 { 640, 400, 85, 0 },
540 { 720, 400, 85, 0 },
541 { 640, 480, 85, 0 },
542 { 848, 480, 60, 0 },
543 { 800, 600, 85, 0 },
544 { 1024, 768, 85, 0 },
545 { 1152, 864, 75, 0 },
546 /* byte 7 */
547 { 1280, 768, 60, 1 },
548 { 1280, 768, 60, 0 },
549 { 1280, 768, 75, 0 },
550 { 1280, 768, 85, 0 },
551 { 1280, 960, 60, 0 },
552 { 1280, 960, 85, 0 },
553 { 1280, 1024, 60, 0 },
554 { 1280, 1024, 85, 0 },
555 /* byte 8 */
556 { 1360, 768, 60, 0 },
557 { 1440, 900, 60, 1 },
558 { 1440, 900, 60, 0 },
559 { 1440, 900, 75, 0 },
560 { 1440, 900, 85, 0 },
561 { 1400, 1050, 60, 1 },
562 { 1400, 1050, 60, 0 },
563 { 1400, 1050, 75, 0 },
564 /* byte 9 */
565 { 1400, 1050, 85, 0 },
566 { 1680, 1050, 60, 1 },
567 { 1680, 1050, 60, 0 },
568 { 1680, 1050, 75, 0 },
569 { 1680, 1050, 85, 0 },
570 { 1600, 1200, 60, 0 },
571 { 1600, 1200, 65, 0 },
572 { 1600, 1200, 70, 0 },
573 /* byte 10 */
574 { 1600, 1200, 75, 0 },
575 { 1600, 1200, 85, 0 },
576 { 1792, 1344, 60, 0 },
577 { 1792, 1344, 75, 0 },
578 { 1856, 1392, 60, 0 },
579 { 1856, 1392, 75, 0 },
580 { 1920, 1200, 60, 1 },
581 { 1920, 1200, 60, 0 },
582 /* byte 11 */
583 { 1920, 1200, 75, 0 },
584 { 1920, 1200, 85, 0 },
585 { 1920, 1440, 60, 0 },
586 { 1920, 1440, 75, 0 },
587};
588
589static const struct minimode extra_modes[] = {
590 { 1024, 576, 60, 0 },
591 { 1366, 768, 60, 0 },
592 { 1600, 900, 60, 0 },
593 { 1680, 945, 60, 0 },
594 { 1920, 1080, 60, 0 },
595 { 2048, 1152, 60, 0 },
596 { 2048, 1536, 60, 0 },
597};
598
599/*
600 * Probably taken from CEA-861 spec.
601 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
602 */
603static const struct drm_display_mode edid_cea_modes[] = {
604 /* 1 - 640x480@60Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
608 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
609 /* 2 - 720x480@60Hz */
610 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
611 798, 858, 0, 480, 489, 495, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
613 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
614 /* 3 - 720x480@60Hz */
615 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
616 798, 858, 0, 480, 489, 495, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
618 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
619 /* 4 - 1280x720@60Hz */
620 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
621 1430, 1650, 0, 720, 725, 730, 750, 0,
622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
623 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
624 /* 5 - 1920x1080i@60Hz */
625 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
626 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
628 DRM_MODE_FLAG_INTERLACE),
629 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
630 /* 6 - 1440x480i@60Hz */
631 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
632 1602, 1716, 0, 480, 488, 494, 525, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
634 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
636 /* 7 - 1440x480i@60Hz */
637 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
638 1602, 1716, 0, 480, 488, 494, 525, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
640 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
641 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
642 /* 8 - 1440x240@60Hz */
643 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
644 1602, 1716, 0, 240, 244, 247, 262, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
646 DRM_MODE_FLAG_DBLCLK),
647 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
648 /* 9 - 1440x240@60Hz */
649 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
650 1602, 1716, 0, 240, 244, 247, 262, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
652 DRM_MODE_FLAG_DBLCLK),
653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
654 /* 10 - 2880x480i@60Hz */
655 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
656 3204, 3432, 0, 480, 488, 494, 525, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
658 DRM_MODE_FLAG_INTERLACE),
659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
660 /* 11 - 2880x480i@60Hz */
661 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
662 3204, 3432, 0, 480, 488, 494, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
664 DRM_MODE_FLAG_INTERLACE),
665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
666 /* 12 - 2880x240@60Hz */
667 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
668 3204, 3432, 0, 240, 244, 247, 262, 0,
669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
671 /* 13 - 2880x240@60Hz */
672 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
673 3204, 3432, 0, 240, 244, 247, 262, 0,
674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
676 /* 14 - 1440x480@60Hz */
677 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
678 1596, 1716, 0, 480, 489, 495, 525, 0,
679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
681 /* 15 - 1440x480@60Hz */
682 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
683 1596, 1716, 0, 480, 489, 495, 525, 0,
684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
686 /* 16 - 1920x1080@60Hz */
687 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
688 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
691 /* 17 - 720x576@50Hz */
692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
693 796, 864, 0, 576, 581, 586, 625, 0,
694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
695 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
696 /* 18 - 720x576@50Hz */
697 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
698 796, 864, 0, 576, 581, 586, 625, 0,
699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
700 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
701 /* 19 - 1280x720@50Hz */
702 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
703 1760, 1980, 0, 720, 725, 730, 750, 0,
704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
705 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
706 /* 20 - 1920x1080i@50Hz */
707 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
708 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
710 DRM_MODE_FLAG_INTERLACE),
711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
712 /* 21 - 1440x576i@50Hz */
713 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
714 1590, 1728, 0, 576, 580, 586, 625, 0,
715 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
716 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
718 /* 22 - 1440x576i@50Hz */
719 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
720 1590, 1728, 0, 576, 580, 586, 625, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
722 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
723 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
724 /* 23 - 1440x288@50Hz */
725 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
726 1590, 1728, 0, 288, 290, 293, 312, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
728 DRM_MODE_FLAG_DBLCLK),
729 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
730 /* 24 - 1440x288@50Hz */
731 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
732 1590, 1728, 0, 288, 290, 293, 312, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
734 DRM_MODE_FLAG_DBLCLK),
735 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
736 /* 25 - 2880x576i@50Hz */
737 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
738 3180, 3456, 0, 576, 580, 586, 625, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
740 DRM_MODE_FLAG_INTERLACE),
741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
742 /* 26 - 2880x576i@50Hz */
743 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
744 3180, 3456, 0, 576, 580, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
746 DRM_MODE_FLAG_INTERLACE),
747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
748 /* 27 - 2880x288@50Hz */
749 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
750 3180, 3456, 0, 288, 290, 293, 312, 0,
751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
753 /* 28 - 2880x288@50Hz */
754 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
755 3180, 3456, 0, 288, 290, 293, 312, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 29 - 1440x576@50Hz */
759 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
760 1592, 1728, 0, 576, 581, 586, 625, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 30 - 1440x576@50Hz */
764 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
765 1592, 1728, 0, 576, 581, 586, 625, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 31 - 1920x1080@50Hz */
769 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
770 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
773 /* 32 - 1920x1080@24Hz */
774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
775 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
777 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
778 /* 33 - 1920x1080@25Hz */
779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
780 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
782 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
783 /* 34 - 1920x1080@30Hz */
784 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
785 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
787 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 35 - 2880x480@60Hz */
789 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
790 3192, 3432, 0, 480, 489, 495, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793 /* 36 - 2880x480@60Hz */
794 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
795 3192, 3432, 0, 480, 489, 495, 525, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 37 - 2880x576@50Hz */
799 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
800 3184, 3456, 0, 576, 581, 586, 625, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803 /* 38 - 2880x576@50Hz */
804 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
805 3184, 3456, 0, 576, 581, 586, 625, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 39 - 1920x1080i@50Hz */
809 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
810 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
812 DRM_MODE_FLAG_INTERLACE),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 40 - 1920x1080i@100Hz */
815 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
816 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
818 DRM_MODE_FLAG_INTERLACE),
819 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 41 - 1280x720@100Hz */
821 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
822 1760, 1980, 0, 720, 725, 730, 750, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
824 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
825 /* 42 - 720x576@100Hz */
826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
827 796, 864, 0, 576, 581, 586, 625, 0,
828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
829 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
830 /* 43 - 720x576@100Hz */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
834 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 44 - 1440x576i@100Hz */
836 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
837 1590, 1728, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_DBLCLK),
840 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 45 - 1440x576i@100Hz */
842 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
843 1590, 1728, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_DBLCLK),
846 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 46 - 1920x1080i@120Hz */
848 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
849 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
851 DRM_MODE_FLAG_INTERLACE),
852 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 47 - 1280x720@120Hz */
854 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
855 1430, 1650, 0, 720, 725, 730, 750, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
857 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 48 - 720x480@120Hz */
859 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
860 798, 858, 0, 480, 489, 495, 525, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
862 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
863 /* 49 - 720x480@120Hz */
864 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
865 798, 858, 0, 480, 489, 495, 525, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 50 - 1440x480i@120Hz */
869 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
870 1602, 1716, 0, 480, 488, 494, 525, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
872 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
873 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
874 /* 51 - 1440x480i@120Hz */
875 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
876 1602, 1716, 0, 480, 488, 494, 525, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
878 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
879 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 52 - 720x576@200Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885 /* 53 - 720x576@200Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 54 - 1440x576i@200Hz */
891 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
892 1590, 1728, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
895 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
896 /* 55 - 1440x576i@200Hz */
897 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
898 1590, 1728, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
901 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 56 - 720x480@240Hz */
903 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
904 798, 858, 0, 480, 489, 495, 525, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
906 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
907 /* 57 - 720x480@240Hz */
908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
909 798, 858, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 58 - 1440x480i@240 */
913 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
914 1602, 1716, 0, 480, 488, 494, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
916 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
917 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 59 - 1440x480i@240 */
919 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
920 1602, 1716, 0, 480, 488, 494, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
923 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 60 - 1280x720@24Hz */
925 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
926 3080, 3300, 0, 720, 725, 730, 750, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
928 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 61 - 1280x720@25Hz */
930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
931 3740, 3960, 0, 720, 725, 730, 750, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
933 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 62 - 1280x720@30Hz */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
936 3080, 3300, 0, 720, 725, 730, 750, 0,
937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
938 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 63 - 1920x1080@120Hz */
940 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
941 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
943 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 64 - 1920x1080@100Hz */
945 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949};
950
951/*
952 * HDMI 1.4 4k modes.
953 */
954static const struct drm_display_mode edid_4k_modes[] = {
955 /* 1 - 3840x2160@30Hz */
956 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
957 3840, 4016, 4104, 4400, 0,
958 2160, 2168, 2178, 2250, 0,
959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
960 .vrefresh = 30, },
961 /* 2 - 3840x2160@25Hz */
962 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
963 3840, 4896, 4984, 5280, 0,
964 2160, 2168, 2178, 2250, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
966 .vrefresh = 25, },
967 /* 3 - 3840x2160@24Hz */
968 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
969 3840, 5116, 5204, 5500, 0,
970 2160, 2168, 2178, 2250, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .vrefresh = 24, },
973 /* 4 - 4096x2160@24Hz (SMPTE) */
974 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
975 4096, 5116, 5204, 5500, 0,
976 2160, 2168, 2178, 2250, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, },
979};
980
981/*** DDC fetch and block validation ***/
982
983static const u8 edid_header[] = {
984 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
985};
986
987 /*
988 * Sanity check the header of the base EDID block. Return 8 if the header
989 * is perfect, down to 0 if it's totally wrong.
990 */
991int drm_edid_header_is_valid(const u8 *raw_edid)
992{
993 int i, score = 0;
994
995 for (i = 0; i < sizeof(edid_header); i++)
996 if (raw_edid[i] == edid_header[i])
997 score++;
998
999 return score;
1000}
1001EXPORT_SYMBOL(drm_edid_header_is_valid);
1002
1003static int edid_fixup __read_mostly = 6;
1004module_param_named(edid_fixup, edid_fixup, int, 0400);
1005MODULE_PARM_DESC(edid_fixup,
1006 "Minimum number of valid EDID header bytes (0-8, default 6)");
1007
1008/*
1009 * Sanity check the EDID block (base or extension). Return 0 if the block
1010 * doesn't check out, or 1 if it's valid.
1011 */
1012bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
1013{
1014 int i;
1015 u8 csum = 0;
1016 struct edid *edid = (struct edid *)raw_edid;
1017
1018 if (WARN_ON(!raw_edid))
1019 return false;
1020
1021 if (edid_fixup > 8 || edid_fixup < 0)
1022 edid_fixup = 6;
1023
1024 if (block == 0) {
1025 int score = drm_edid_header_is_valid(raw_edid);
1026 if (score == 8) ;
1027 else if (score >= edid_fixup) {
1028 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1029 memcpy(raw_edid, edid_header, sizeof(edid_header));
1030 } else {
1031 goto bad;
1032 }
1033 }
1034
1035 for (i = 0; i < EDID_LENGTH; i++)
1036 csum += raw_edid[i];
1037 if (csum) {
1038 if (print_bad_edid) {
1039 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1040 }
1041
1042 /* allow CEA to slide through, switches mangle this */
1043 if (raw_edid[0] != 0x02)
1044 goto bad;
1045 }
1046
1047 /* per-block-type checks */
1048 switch (raw_edid[0]) {
1049 case 0: /* base */
1050 if (edid->version != 1) {
1051 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1052 goto bad;
1053 }
1054
1055 if (edid->revision > 4)
1056 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1057 break;
1058
1059 default:
1060 break;
1061 }
1062
1063 return true;
1064
1065bad:
1066 if (print_bad_edid) {
1067 printk(KERN_ERR "Raw EDID:\n");
1068 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1069 raw_edid, EDID_LENGTH, false);
1070 }
1071 return false;
1072}
1073EXPORT_SYMBOL(drm_edid_block_valid);
1074
1075/**
1076 * drm_edid_is_valid - sanity check EDID data
1077 * @edid: EDID data
1078 *
1079 * Sanity-check an entire EDID record (including extensions)
1080 */
1081bool drm_edid_is_valid(struct edid *edid)
1082{
1083 int i;
1084 u8 *raw = (u8 *)edid;
1085
1086 if (!edid)
1087 return false;
1088
1089 for (i = 0; i <= edid->extensions; i++)
1090 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true))
1091 return false;
1092
1093 return true;
1094}
1095EXPORT_SYMBOL(drm_edid_is_valid);
1096
1097#define DDC_SEGMENT_ADDR 0x30
1098/**
1099 * Get EDID information via I2C.
1100 *
1101 * @adapter : i2c device adaptor
1102 * @buf: EDID data buffer to be filled
1103 * @block: 128 byte EDID block to start fetching from
1104 * @len: EDID data buffer length to fetch
1105 *
1106 * Returns:
1107 *
1108 * 0 on success or -1 on failure.
1109 *
1110 * Try to fetch EDID information by calling i2c driver function.
1111 */
1112static int
1113drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
1114 int block, int len)
1115{
1116 unsigned char start = block * EDID_LENGTH;
1117 unsigned char segment = block >> 1;
1118 unsigned char xfers = segment ? 3 : 2;
1119 int ret, retries = 5;
1120
1121 /* The core i2c driver will automatically retry the transfer if the
1122 * adapter reports EAGAIN. However, we find that bit-banging transfers
1123 * are susceptible to errors under a heavily loaded machine and
1124 * generate spurious NAKs and timeouts. Retrying the transfer
1125 * of the individual block a few times seems to overcome this.
1126 */
1127 do {
1128 struct i2c_msg msgs[] = {
1129 {
1130 .addr = DDC_SEGMENT_ADDR,
1131 .flags = 0,
1132 .len = 1,
1133 .buf = &segment,
1134 }, {
1135 .addr = DDC_ADDR,
1136 .flags = 0,
1137 .len = 1,
1138 .buf = &start,
1139 }, {
1140 .addr = DDC_ADDR,
1141 .flags = I2C_M_RD,
1142 .len = len,
1143 .buf = buf,
1144 }
1145 };
1146
1147 /*
1148 * Avoid sending the segment addr to not upset non-compliant ddc
1149 * monitors.
1150 */
1151 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1152
1153 if (ret == -ENXIO) {
1154 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1155 adapter->name);
1156 break;
1157 }
1158 } while (ret != xfers && --retries);
1159
1160 return ret == xfers ? 0 : -1;
1161}
1162
1163static bool drm_edid_is_zero(u8 *in_edid, int length)
1164{
1165 if (memchr_inv(in_edid, 0, length))
1166 return false;
1167
1168 return true;
1169}
1170
1171static u8 *
1172drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1173{
1174 int i, j = 0, valid_extensions = 0;
1175 u8 *block, *new;
1176 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1177
1178 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1179 return NULL;
1180
1181 /* base block fetch */
1182 for (i = 0; i < 4; i++) {
1183 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
1184 goto out;
1185 if (drm_edid_block_valid(block, 0, print_bad_edid))
1186 break;
1187 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1188 connector->null_edid_counter++;
1189 goto carp;
1190 }
1191 }
1192 if (i == 4)
1193 goto carp;
1194
1195 /* if there's no extensions, we're done */
1196 if (block[0x7e] == 0)
1197 return block;
1198
1199 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1200 if (!new)
1201 goto out;
1202 block = new;
1203
1204 for (j = 1; j <= block[0x7e]; j++) {
1205 for (i = 0; i < 4; i++) {
1206 if (drm_do_probe_ddc_edid(adapter,
1207 block + (valid_extensions + 1) * EDID_LENGTH,
1208 j, EDID_LENGTH))
1209 goto out;
1210 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
1211 valid_extensions++;
1212 break;
1213 }
1214 }
1215
1216 if (i == 4 && print_bad_edid) {
1217 dev_warn(connector->dev->dev,
1218 "%s: Ignoring invalid EDID block %d.\n",
1219 drm_get_connector_name(connector), j);
1220
1221 connector->bad_edid_counter++;
1222 }
1223 }
1224
1225 if (valid_extensions != block[0x7e]) {
1226 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1227 block[0x7e] = valid_extensions;
1228 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1229 if (!new)
1230 goto out;
1231 block = new;
1232 }
1233
1234 return block;
1235
1236carp:
1237 if (print_bad_edid) {
1238 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1239 drm_get_connector_name(connector), j);
1240 }
1241 connector->bad_edid_counter++;
1242
1243out:
1244 kfree(block);
1245 return NULL;
1246}
1247
1248/**
1249 * Probe DDC presence.
1250 * @adapter: i2c adapter to probe
1251 *
1252 * Returns:
1253 *
1254 * 1 on success
1255 */
1256bool
1257drm_probe_ddc(struct i2c_adapter *adapter)
1258{
1259 unsigned char out;
1260
1261 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1262}
1263EXPORT_SYMBOL(drm_probe_ddc);
1264
1265/**
1266 * drm_get_edid - get EDID data, if available
1267 * @connector: connector we're probing
1268 * @adapter: i2c adapter to use for DDC
1269 *
1270 * Poke the given i2c channel to grab EDID data if possible. If found,
1271 * attach it to the connector.
1272 *
1273 * Return edid data or NULL if we couldn't find any.
1274 */
1275struct edid *drm_get_edid(struct drm_connector *connector,
1276 struct i2c_adapter *adapter)
1277{
1278 struct edid *edid = NULL;
1279
1280 if (drm_probe_ddc(adapter))
1281 edid = (struct edid *)drm_do_get_edid(connector, adapter);
1282
1283 return edid;
1284}
1285EXPORT_SYMBOL(drm_get_edid);
1286
1287/**
1288 * drm_edid_duplicate - duplicate an EDID and the extensions
1289 * @edid: EDID to duplicate
1290 *
1291 * Return duplicate edid or NULL on allocation failure.
1292 */
1293struct edid *drm_edid_duplicate(const struct edid *edid)
1294{
1295 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1296}
1297EXPORT_SYMBOL(drm_edid_duplicate);
1298
1299/*** EDID parsing ***/
1300
1301/**
1302 * edid_vendor - match a string against EDID's obfuscated vendor field
1303 * @edid: EDID to match
1304 * @vendor: vendor string
1305 *
1306 * Returns true if @vendor is in @edid, false otherwise
1307 */
1308static bool edid_vendor(struct edid *edid, char *vendor)
1309{
1310 char edid_vendor[3];
1311
1312 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1313 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1314 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1315 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1316
1317 return !strncmp(edid_vendor, vendor, 3);
1318}
1319
1320/**
1321 * edid_get_quirks - return quirk flags for a given EDID
1322 * @edid: EDID to process
1323 *
1324 * This tells subsequent routines what fixes they need to apply.
1325 */
1326static u32 edid_get_quirks(struct edid *edid)
1327{
1328 struct edid_quirk *quirk;
1329 int i;
1330
1331 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1332 quirk = &edid_quirk_list[i];
1333
1334 if (edid_vendor(edid, quirk->vendor) &&
1335 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1336 return quirk->quirks;
1337 }
1338
1339 return 0;
1340}
1341
1342#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1343#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1344
1345/**
1346 * edid_fixup_preferred - set preferred modes based on quirk list
1347 * @connector: has mode list to fix up
1348 * @quirks: quirks list
1349 *
1350 * Walk the mode list for @connector, clearing the preferred status
1351 * on existing modes and setting it anew for the right mode ala @quirks.
1352 */
1353static void edid_fixup_preferred(struct drm_connector *connector,
1354 u32 quirks)
1355{
1356 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1357 int target_refresh = 0;
1358 int cur_vrefresh, preferred_vrefresh;
1359
1360 if (list_empty(&connector->probed_modes))
1361 return;
1362
1363 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1364 target_refresh = 60;
1365 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1366 target_refresh = 75;
1367
1368 preferred_mode = list_first_entry(&connector->probed_modes,
1369 struct drm_display_mode, head);
1370
1371 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1372 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1373
1374 if (cur_mode == preferred_mode)
1375 continue;
1376
1377 /* Largest mode is preferred */
1378 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1379 preferred_mode = cur_mode;
1380
1381 cur_vrefresh = cur_mode->vrefresh ?
1382 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1383 preferred_vrefresh = preferred_mode->vrefresh ?
1384 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1385 /* At a given size, try to get closest to target refresh */
1386 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1387 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1388 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1389 preferred_mode = cur_mode;
1390 }
1391 }
1392
1393 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1394}
1395
1396static bool
1397mode_is_rb(const struct drm_display_mode *mode)
1398{
1399 return (mode->htotal - mode->hdisplay == 160) &&
1400 (mode->hsync_end - mode->hdisplay == 80) &&
1401 (mode->hsync_end - mode->hsync_start == 32) &&
1402 (mode->vsync_start - mode->vdisplay == 3);
1403}
1404
1405/*
1406 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1407 * @dev: Device to duplicate against
1408 * @hsize: Mode width
1409 * @vsize: Mode height
1410 * @fresh: Mode refresh rate
1411 * @rb: Mode reduced-blanking-ness
1412 *
1413 * Walk the DMT mode list looking for a match for the given parameters.
1414 * Return a newly allocated copy of the mode, or NULL if not found.
1415 */
1416struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1417 int hsize, int vsize, int fresh,
1418 bool rb)
1419{
1420 int i;
1421
1422 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1423 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1424 if (hsize != ptr->hdisplay)
1425 continue;
1426 if (vsize != ptr->vdisplay)
1427 continue;
1428 if (fresh != drm_mode_vrefresh(ptr))
1429 continue;
1430 if (rb != mode_is_rb(ptr))
1431 continue;
1432
1433 return drm_mode_duplicate(dev, ptr);
1434 }
1435
1436 return NULL;
1437}
1438EXPORT_SYMBOL(drm_mode_find_dmt);
1439
1440typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1441
1442static void
1443cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1444{
1445 int i, n = 0;
1446 u8 d = ext[0x02];
1447 u8 *det_base = ext + d;
1448
1449 n = (127 - d) / 18;
1450 for (i = 0; i < n; i++)
1451 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1452}
1453
1454static void
1455vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1456{
1457 unsigned int i, n = min((int)ext[0x02], 6);
1458 u8 *det_base = ext + 5;
1459
1460 if (ext[0x01] != 1)
1461 return; /* unknown version */
1462
1463 for (i = 0; i < n; i++)
1464 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1465}
1466
1467static void
1468drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1469{
1470 int i;
1471 struct edid *edid = (struct edid *)raw_edid;
1472
1473 if (edid == NULL)
1474 return;
1475
1476 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1477 cb(&(edid->detailed_timings[i]), closure);
1478
1479 for (i = 1; i <= raw_edid[0x7e]; i++) {
1480 u8 *ext = raw_edid + (i * EDID_LENGTH);
1481 switch (*ext) {
1482 case CEA_EXT:
1483 cea_for_each_detailed_block(ext, cb, closure);
1484 break;
1485 case VTB_EXT:
1486 vtb_for_each_detailed_block(ext, cb, closure);
1487 break;
1488 default:
1489 break;
1490 }
1491 }
1492}
1493
1494static void
1495is_rb(struct detailed_timing *t, void *data)
1496{
1497 u8 *r = (u8 *)t;
1498 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1499 if (r[15] & 0x10)
1500 *(bool *)data = true;
1501}
1502
1503/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1504static bool
1505drm_monitor_supports_rb(struct edid *edid)
1506{
1507 if (edid->revision >= 4) {
1508 bool ret = false;
1509 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1510 return ret;
1511 }
1512
1513 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1514}
1515
1516static void
1517find_gtf2(struct detailed_timing *t, void *data)
1518{
1519 u8 *r = (u8 *)t;
1520 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1521 *(u8 **)data = r;
1522}
1523
1524/* Secondary GTF curve kicks in above some break frequency */
1525static int
1526drm_gtf2_hbreak(struct edid *edid)
1527{
1528 u8 *r = NULL;
1529 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1530 return r ? (r[12] * 2) : 0;
1531}
1532
1533static int
1534drm_gtf2_2c(struct edid *edid)
1535{
1536 u8 *r = NULL;
1537 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1538 return r ? r[13] : 0;
1539}
1540
1541static int
1542drm_gtf2_m(struct edid *edid)
1543{
1544 u8 *r = NULL;
1545 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1546 return r ? (r[15] << 8) + r[14] : 0;
1547}
1548
1549static int
1550drm_gtf2_k(struct edid *edid)
1551{
1552 u8 *r = NULL;
1553 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1554 return r ? r[16] : 0;
1555}
1556
1557static int
1558drm_gtf2_2j(struct edid *edid)
1559{
1560 u8 *r = NULL;
1561 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1562 return r ? r[17] : 0;
1563}
1564
1565/**
1566 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1567 * @edid: EDID block to scan
1568 */
1569static int standard_timing_level(struct edid *edid)
1570{
1571 if (edid->revision >= 2) {
1572 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1573 return LEVEL_CVT;
1574 if (drm_gtf2_hbreak(edid))
1575 return LEVEL_GTF2;
1576 return LEVEL_GTF;
1577 }
1578 return LEVEL_DMT;
1579}
1580
1581/*
1582 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1583 * monitors fill with ascii space (0x20) instead.
1584 */
1585static int
1586bad_std_timing(u8 a, u8 b)
1587{
1588 return (a == 0x00 && b == 0x00) ||
1589 (a == 0x01 && b == 0x01) ||
1590 (a == 0x20 && b == 0x20);
1591}
1592
1593/**
1594 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1595 * @connector: connector of for the EDID block
1596 * @edid: EDID block to scan
1597 * @t: standard timing params
1598 * @revision: standard timing level
1599 *
1600 * Take the standard timing params (in this case width, aspect, and refresh)
1601 * and convert them into a real mode using CVT/GTF/DMT.
1602 */
1603static struct drm_display_mode *
1604drm_mode_std(struct drm_connector *connector, struct edid *edid,
1605 struct std_timing *t, int revision)
1606{
1607 struct drm_device *dev = connector->dev;
1608 struct drm_display_mode *m, *mode = NULL;
1609 int hsize, vsize;
1610 int vrefresh_rate;
1611 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1612 >> EDID_TIMING_ASPECT_SHIFT;
1613 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1614 >> EDID_TIMING_VFREQ_SHIFT;
1615 int timing_level = standard_timing_level(edid);
1616
1617 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1618 return NULL;
1619
1620 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1621 hsize = t->hsize * 8 + 248;
1622 /* vrefresh_rate = vfreq + 60 */
1623 vrefresh_rate = vfreq + 60;
1624 /* the vdisplay is calculated based on the aspect ratio */
1625 if (aspect_ratio == 0) {
1626 if (revision < 3)
1627 vsize = hsize;
1628 else
1629 vsize = (hsize * 10) / 16;
1630 } else if (aspect_ratio == 1)
1631 vsize = (hsize * 3) / 4;
1632 else if (aspect_ratio == 2)
1633 vsize = (hsize * 4) / 5;
1634 else
1635 vsize = (hsize * 9) / 16;
1636
1637 /* HDTV hack, part 1 */
1638 if (vrefresh_rate == 60 &&
1639 ((hsize == 1360 && vsize == 765) ||
1640 (hsize == 1368 && vsize == 769))) {
1641 hsize = 1366;
1642 vsize = 768;
1643 }
1644
1645 /*
1646 * If this connector already has a mode for this size and refresh
1647 * rate (because it came from detailed or CVT info), use that
1648 * instead. This way we don't have to guess at interlace or
1649 * reduced blanking.
1650 */
1651 list_for_each_entry(m, &connector->probed_modes, head)
1652 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1653 drm_mode_vrefresh(m) == vrefresh_rate)
1654 return NULL;
1655
1656 /* HDTV hack, part 2 */
1657 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1658 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1659 false);
1660 mode->hdisplay = 1366;
1661 mode->hsync_start = mode->hsync_start - 1;
1662 mode->hsync_end = mode->hsync_end - 1;
1663 return mode;
1664 }
1665
1666 /* check whether it can be found in default mode table */
1667 if (drm_monitor_supports_rb(edid)) {
1668 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1669 true);
1670 if (mode)
1671 return mode;
1672 }
1673 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1674 if (mode)
1675 return mode;
1676
1677 /* okay, generate it */
1678 switch (timing_level) {
1679 case LEVEL_DMT:
1680 break;
1681 case LEVEL_GTF:
1682 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1683 break;
1684 case LEVEL_GTF2:
1685 /*
1686 * This is potentially wrong if there's ever a monitor with
1687 * more than one ranges section, each claiming a different
1688 * secondary GTF curve. Please don't do that.
1689 */
1690 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1691 if (!mode)
1692 return NULL;
1693 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1694 drm_mode_destroy(dev, mode);
1695 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1696 vrefresh_rate, 0, 0,
1697 drm_gtf2_m(edid),
1698 drm_gtf2_2c(edid),
1699 drm_gtf2_k(edid),
1700 drm_gtf2_2j(edid));
1701 }
1702 break;
1703 case LEVEL_CVT:
1704 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1705 false);
1706 break;
1707 }
1708 return mode;
1709}
1710
1711/*
1712 * EDID is delightfully ambiguous about how interlaced modes are to be
1713 * encoded. Our internal representation is of frame height, but some
1714 * HDTV detailed timings are encoded as field height.
1715 *
1716 * The format list here is from CEA, in frame size. Technically we
1717 * should be checking refresh rate too. Whatever.
1718 */
1719static void
1720drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1721 struct detailed_pixel_timing *pt)
1722{
1723 int i;
1724 static const struct {
1725 int w, h;
1726 } cea_interlaced[] = {
1727 { 1920, 1080 },
1728 { 720, 480 },
1729 { 1440, 480 },
1730 { 2880, 480 },
1731 { 720, 576 },
1732 { 1440, 576 },
1733 { 2880, 576 },
1734 };
1735
1736 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1737 return;
1738
1739 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1740 if ((mode->hdisplay == cea_interlaced[i].w) &&
1741 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1742 mode->vdisplay *= 2;
1743 mode->vsync_start *= 2;
1744 mode->vsync_end *= 2;
1745 mode->vtotal *= 2;
1746 mode->vtotal |= 1;
1747 }
1748 }
1749
1750 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1751}
1752
1753/**
1754 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1755 * @dev: DRM device (needed to create new mode)
1756 * @edid: EDID block
1757 * @timing: EDID detailed timing info
1758 * @quirks: quirks to apply
1759 *
1760 * An EDID detailed timing block contains enough info for us to create and
1761 * return a new struct drm_display_mode.
1762 */
1763static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1764 struct edid *edid,
1765 struct detailed_timing *timing,
1766 u32 quirks)
1767{
1768 struct drm_display_mode *mode;
1769 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1770 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1771 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1772 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1773 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1774 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1775 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1776 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1777 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1778
1779 /* ignore tiny modes */
1780 if (hactive < 64 || vactive < 64)
1781 return NULL;
1782
1783 if (pt->misc & DRM_EDID_PT_STEREO) {
1784 DRM_DEBUG_KMS("stereo mode not supported\n");
1785 return NULL;
1786 }
1787 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1788 DRM_DEBUG_KMS("composite sync not supported\n");
1789 }
1790
1791 /* it is incorrect if hsync/vsync width is zero */
1792 if (!hsync_pulse_width || !vsync_pulse_width) {
1793 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1794 "Wrong Hsync/Vsync pulse width\n");
1795 return NULL;
1796 }
1797
1798 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1799 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1800 if (!mode)
1801 return NULL;
1802
1803 goto set_size;
1804 }
1805
1806 mode = drm_mode_create(dev);
1807 if (!mode)
1808 return NULL;
1809
1810 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1811 timing->pixel_clock = cpu_to_le16(1088);
1812
1813 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1814
1815 mode->hdisplay = hactive;
1816 mode->hsync_start = mode->hdisplay + hsync_offset;
1817 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1818 mode->htotal = mode->hdisplay + hblank;
1819
1820 mode->vdisplay = vactive;
1821 mode->vsync_start = mode->vdisplay + vsync_offset;
1822 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1823 mode->vtotal = mode->vdisplay + vblank;
1824
1825 /* Some EDIDs have bogus h/vtotal values */
1826 if (mode->hsync_end > mode->htotal)
1827 mode->htotal = mode->hsync_end + 1;
1828 if (mode->vsync_end > mode->vtotal)
1829 mode->vtotal = mode->vsync_end + 1;
1830
1831 drm_mode_do_interlace_quirk(mode, pt);
1832
1833 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
1834 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
1835 }
1836
1837 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1838 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1839 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1840 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
1841
1842set_size:
1843 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1844 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
1845
1846 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1847 mode->width_mm *= 10;
1848 mode->height_mm *= 10;
1849 }
1850
1851 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1852 mode->width_mm = edid->width_cm * 10;
1853 mode->height_mm = edid->height_cm * 10;
1854 }
1855
1856 mode->type = DRM_MODE_TYPE_DRIVER;
1857 mode->vrefresh = drm_mode_vrefresh(mode);
1858 drm_mode_set_name(mode);
1859
1860 return mode;
1861}
1862
1863static bool
1864mode_in_hsync_range(const struct drm_display_mode *mode,
1865 struct edid *edid, u8 *t)
1866{
1867 int hsync, hmin, hmax;
1868
1869 hmin = t[7];
1870 if (edid->revision >= 4)
1871 hmin += ((t[4] & 0x04) ? 255 : 0);
1872 hmax = t[8];
1873 if (edid->revision >= 4)
1874 hmax += ((t[4] & 0x08) ? 255 : 0);
1875 hsync = drm_mode_hsync(mode);
1876
1877 return (hsync <= hmax && hsync >= hmin);
1878}
1879
1880static bool
1881mode_in_vsync_range(const struct drm_display_mode *mode,
1882 struct edid *edid, u8 *t)
1883{
1884 int vsync, vmin, vmax;
1885
1886 vmin = t[5];
1887 if (edid->revision >= 4)
1888 vmin += ((t[4] & 0x01) ? 255 : 0);
1889 vmax = t[6];
1890 if (edid->revision >= 4)
1891 vmax += ((t[4] & 0x02) ? 255 : 0);
1892 vsync = drm_mode_vrefresh(mode);
1893
1894 return (vsync <= vmax && vsync >= vmin);
1895}
1896
1897static u32
1898range_pixel_clock(struct edid *edid, u8 *t)
1899{
1900 /* unspecified */
1901 if (t[9] == 0 || t[9] == 255)
1902 return 0;
1903
1904 /* 1.4 with CVT support gives us real precision, yay */
1905 if (edid->revision >= 4 && t[10] == 0x04)
1906 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1907
1908 /* 1.3 is pathetic, so fuzz up a bit */
1909 return t[9] * 10000 + 5001;
1910}
1911
1912static bool
1913mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
1914 struct detailed_timing *timing)
1915{
1916 u32 max_clock;
1917 u8 *t = (u8 *)timing;
1918
1919 if (!mode_in_hsync_range(mode, edid, t))
1920 return false;
1921
1922 if (!mode_in_vsync_range(mode, edid, t))
1923 return false;
1924
1925 if ((max_clock = range_pixel_clock(edid, t)))
1926 if (mode->clock > max_clock)
1927 return false;
1928
1929 /* 1.4 max horizontal check */
1930 if (edid->revision >= 4 && t[10] == 0x04)
1931 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1932 return false;
1933
1934 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1935 return false;
1936
1937 return true;
1938}
1939
1940static bool valid_inferred_mode(const struct drm_connector *connector,
1941 const struct drm_display_mode *mode)
1942{
1943 struct drm_display_mode *m;
1944 bool ok = false;
1945
1946 list_for_each_entry(m, &connector->probed_modes, head) {
1947 if (mode->hdisplay == m->hdisplay &&
1948 mode->vdisplay == m->vdisplay &&
1949 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1950 return false; /* duplicated */
1951 if (mode->hdisplay <= m->hdisplay &&
1952 mode->vdisplay <= m->vdisplay)
1953 ok = true;
1954 }
1955 return ok;
1956}
1957
1958static int
1959drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
1960 struct detailed_timing *timing)
1961{
1962 int i, modes = 0;
1963 struct drm_display_mode *newmode;
1964 struct drm_device *dev = connector->dev;
1965
1966 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1967 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
1968 valid_inferred_mode(connector, drm_dmt_modes + i)) {
1969 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1970 if (newmode) {
1971 drm_mode_probed_add(connector, newmode);
1972 modes++;
1973 }
1974 }
1975 }
1976
1977 return modes;
1978}
1979
1980/* fix up 1366x768 mode from 1368x768;
1981 * GFT/CVT can't express 1366 width which isn't dividable by 8
1982 */
1983static void fixup_mode_1366x768(struct drm_display_mode *mode)
1984{
1985 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
1986 mode->hdisplay = 1366;
1987 mode->hsync_start--;
1988 mode->hsync_end--;
1989 drm_mode_set_name(mode);
1990 }
1991}
1992
1993static int
1994drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1995 struct detailed_timing *timing)
1996{
1997 int i, modes = 0;
1998 struct drm_display_mode *newmode;
1999 struct drm_device *dev = connector->dev;
2000
2001 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2002 const struct minimode *m = &extra_modes[i];
2003 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2004 if (!newmode)
2005 return modes;
2006
2007 fixup_mode_1366x768(newmode);
2008 if (!mode_in_range(newmode, edid, timing) ||
2009 !valid_inferred_mode(connector, newmode)) {
2010 drm_mode_destroy(dev, newmode);
2011 continue;
2012 }
2013
2014 drm_mode_probed_add(connector, newmode);
2015 modes++;
2016 }
2017
2018 return modes;
2019}
2020
2021static int
2022drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2023 struct detailed_timing *timing)
2024{
2025 int i, modes = 0;
2026 struct drm_display_mode *newmode;
2027 struct drm_device *dev = connector->dev;
2028 bool rb = drm_monitor_supports_rb(edid);
2029
2030 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2031 const struct minimode *m = &extra_modes[i];
2032 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2033 if (!newmode)
2034 return modes;
2035
2036 fixup_mode_1366x768(newmode);
2037 if (!mode_in_range(newmode, edid, timing) ||
2038 !valid_inferred_mode(connector, newmode)) {
2039 drm_mode_destroy(dev, newmode);
2040 continue;
2041 }
2042
2043 drm_mode_probed_add(connector, newmode);
2044 modes++;
2045 }
2046
2047 return modes;
2048}
2049
2050static void
2051do_inferred_modes(struct detailed_timing *timing, void *c)
2052{
2053 struct detailed_mode_closure *closure = c;
2054 struct detailed_non_pixel *data = &timing->data.other_data;
2055 struct detailed_data_monitor_range *range = &data->data.range;
2056
2057 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2058 return;
2059
2060 closure->modes += drm_dmt_modes_for_range(closure->connector,
2061 closure->edid,
2062 timing);
2063
2064 if (!version_greater(closure->edid, 1, 1))
2065 return; /* GTF not defined yet */
2066
2067 switch (range->flags) {
2068 case 0x02: /* secondary gtf, XXX could do more */
2069 case 0x00: /* default gtf */
2070 closure->modes += drm_gtf_modes_for_range(closure->connector,
2071 closure->edid,
2072 timing);
2073 break;
2074 case 0x04: /* cvt, only in 1.4+ */
2075 if (!version_greater(closure->edid, 1, 3))
2076 break;
2077
2078 closure->modes += drm_cvt_modes_for_range(closure->connector,
2079 closure->edid,
2080 timing);
2081 break;
2082 case 0x01: /* just the ranges, no formula */
2083 default:
2084 break;
2085 }
2086}
2087
2088static int
2089add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2090{
2091 struct detailed_mode_closure closure = {
2092 connector, edid, 0, 0, 0
2093 };
2094
2095 if (version_greater(edid, 1, 0))
2096 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2097 &closure);
2098
2099 return closure.modes;
2100}
2101
2102static int
2103drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2104{
2105 int i, j, m, modes = 0;
2106 struct drm_display_mode *mode;
2107 u8 *est = ((u8 *)timing) + 5;
2108
2109 for (i = 0; i < 6; i++) {
2110 for (j = 7; j >= 0; j--) {
2111 m = (i * 8) + (7 - j);
2112 if (m >= ARRAY_SIZE(est3_modes))
2113 break;
2114 if (est[i] & (1 << j)) {
2115 mode = drm_mode_find_dmt(connector->dev,
2116 est3_modes[m].w,
2117 est3_modes[m].h,
2118 est3_modes[m].r,
2119 est3_modes[m].rb);
2120 if (mode) {
2121 drm_mode_probed_add(connector, mode);
2122 modes++;
2123 }
2124 }
2125 }
2126 }
2127
2128 return modes;
2129}
2130
2131static void
2132do_established_modes(struct detailed_timing *timing, void *c)
2133{
2134 struct detailed_mode_closure *closure = c;
2135 struct detailed_non_pixel *data = &timing->data.other_data;
2136
2137 if (data->type == EDID_DETAIL_EST_TIMINGS)
2138 closure->modes += drm_est3_modes(closure->connector, timing);
2139}
2140
2141/**
2142 * add_established_modes - get est. modes from EDID and add them
2143 * @connector: connector of for the EDID block
2144 * @edid: EDID block to scan
2145 *
2146 * Each EDID block contains a bitmap of the supported "established modes" list
2147 * (defined above). Tease them out and add them to the global modes list.
2148 */
2149static int
2150add_established_modes(struct drm_connector *connector, struct edid *edid)
2151{
2152 struct drm_device *dev = connector->dev;
2153 unsigned long est_bits = edid->established_timings.t1 |
2154 (edid->established_timings.t2 << 8) |
2155 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2156 int i, modes = 0;
2157 struct detailed_mode_closure closure = {
2158 connector, edid, 0, 0, 0
2159 };
2160
2161 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2162 if (est_bits & (1<<i)) {
2163 struct drm_display_mode *newmode;
2164 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2165 if (newmode) {
2166 drm_mode_probed_add(connector, newmode);
2167 modes++;
2168 }
2169 }
2170 }
2171
2172 if (version_greater(edid, 1, 0))
2173 drm_for_each_detailed_block((u8 *)edid,
2174 do_established_modes, &closure);
2175
2176 return modes + closure.modes;
2177}
2178
2179static void
2180do_standard_modes(struct detailed_timing *timing, void *c)
2181{
2182 struct detailed_mode_closure *closure = c;
2183 struct detailed_non_pixel *data = &timing->data.other_data;
2184 struct drm_connector *connector = closure->connector;
2185 struct edid *edid = closure->edid;
2186
2187 if (data->type == EDID_DETAIL_STD_MODES) {
2188 int i;
2189 for (i = 0; i < 6; i++) {
2190 struct std_timing *std;
2191 struct drm_display_mode *newmode;
2192
2193 std = &data->data.timings[i];
2194 newmode = drm_mode_std(connector, edid, std,
2195 edid->revision);
2196 if (newmode) {
2197 drm_mode_probed_add(connector, newmode);
2198 closure->modes++;
2199 }
2200 }
2201 }
2202}
2203
2204/**
2205 * add_standard_modes - get std. modes from EDID and add them
2206 * @connector: connector of for the EDID block
2207 * @edid: EDID block to scan
2208 *
2209 * Standard modes can be calculated using the appropriate standard (DMT,
2210 * GTF or CVT. Grab them from @edid and add them to the list.
2211 */
2212static int
2213add_standard_modes(struct drm_connector *connector, struct edid *edid)
2214{
2215 int i, modes = 0;
2216 struct detailed_mode_closure closure = {
2217 connector, edid, 0, 0, 0
2218 };
2219
2220 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2221 struct drm_display_mode *newmode;
2222
2223 newmode = drm_mode_std(connector, edid,
2224 &edid->standard_timings[i],
2225 edid->revision);
2226 if (newmode) {
2227 drm_mode_probed_add(connector, newmode);
2228 modes++;
2229 }
2230 }
2231
2232 if (version_greater(edid, 1, 0))
2233 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2234 &closure);
2235
2236 /* XXX should also look for standard codes in VTB blocks */
2237
2238 return modes + closure.modes;
2239}
2240
2241static int drm_cvt_modes(struct drm_connector *connector,
2242 struct detailed_timing *timing)
2243{
2244 int i, j, modes = 0;
2245 struct drm_display_mode *newmode;
2246 struct drm_device *dev = connector->dev;
2247 struct cvt_timing *cvt;
2248 const int rates[] = { 60, 85, 75, 60, 50 };
2249 const u8 empty[3] = { 0, 0, 0 };
2250
2251 for (i = 0; i < 4; i++) {
2252 int uninitialized_var(width), height;
2253 cvt = &(timing->data.other_data.data.cvt[i]);
2254
2255 if (!memcmp(cvt->code, empty, 3))
2256 continue;
2257
2258 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2259 switch (cvt->code[1] & 0x0c) {
2260 case 0x00:
2261 width = height * 4 / 3;
2262 break;
2263 case 0x04:
2264 width = height * 16 / 9;
2265 break;
2266 case 0x08:
2267 width = height * 16 / 10;
2268 break;
2269 case 0x0c:
2270 width = height * 15 / 9;
2271 break;
2272 }
2273
2274 for (j = 1; j < 5; j++) {
2275 if (cvt->code[2] & (1 << j)) {
2276 newmode = drm_cvt_mode(dev, width, height,
2277 rates[j], j == 0,
2278 false, false);
2279 if (newmode) {
2280 drm_mode_probed_add(connector, newmode);
2281 modes++;
2282 }
2283 }
2284 }
2285 }
2286
2287 return modes;
2288}
2289
2290static void
2291do_cvt_mode(struct detailed_timing *timing, void *c)
2292{
2293 struct detailed_mode_closure *closure = c;
2294 struct detailed_non_pixel *data = &timing->data.other_data;
2295
2296 if (data->type == EDID_DETAIL_CVT_3BYTE)
2297 closure->modes += drm_cvt_modes(closure->connector, timing);
2298}
2299
2300static int
2301add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2302{
2303 struct detailed_mode_closure closure = {
2304 connector, edid, 0, 0, 0
2305 };
2306
2307 if (version_greater(edid, 1, 2))
2308 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2309
2310 /* XXX should also look for CVT codes in VTB blocks */
2311
2312 return closure.modes;
2313}
2314
2315static void
2316do_detailed_mode(struct detailed_timing *timing, void *c)
2317{
2318 struct detailed_mode_closure *closure = c;
2319 struct drm_display_mode *newmode;
2320
2321 if (timing->pixel_clock) {
2322 newmode = drm_mode_detailed(closure->connector->dev,
2323 closure->edid, timing,
2324 closure->quirks);
2325 if (!newmode)
2326 return;
2327
2328 if (closure->preferred)
2329 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2330
2331 drm_mode_probed_add(closure->connector, newmode);
2332 closure->modes++;
2333 closure->preferred = 0;
2334 }
2335}
2336
2337/*
2338 * add_detailed_modes - Add modes from detailed timings
2339 * @connector: attached connector
2340 * @edid: EDID block to scan
2341 * @quirks: quirks to apply
2342 */
2343static int
2344add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2345 u32 quirks)
2346{
2347 struct detailed_mode_closure closure = {
2348 connector,
2349 edid,
2350 1,
2351 quirks,
2352 0
2353 };
2354
2355 if (closure.preferred && !version_greater(edid, 1, 3))
2356 closure.preferred =
2357 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2358
2359 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2360
2361 return closure.modes;
2362}
2363
2364#define AUDIO_BLOCK 0x01
2365#define VIDEO_BLOCK 0x02
2366#define VENDOR_BLOCK 0x03
2367#define SPEAKER_BLOCK 0x04
2368#define VIDEO_CAPABILITY_BLOCK 0x07
2369#define EDID_BASIC_AUDIO (1 << 6)
2370#define EDID_CEA_YCRCB444 (1 << 5)
2371#define EDID_CEA_YCRCB422 (1 << 4)
2372#define EDID_CEA_VCDB_QS (1 << 6)
2373
2374/*
2375 * Search EDID for CEA extension block.
2376 */
2377static u8 *drm_find_cea_extension(struct edid *edid)
2378{
2379 u8 *edid_ext = NULL;
2380 int i;
2381
2382 /* No EDID or EDID extensions */
2383 if (edid == NULL || edid->extensions == 0)
2384 return NULL;
2385
2386 /* Find CEA extension */
2387 for (i = 0; i < edid->extensions; i++) {
2388 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2389 if (edid_ext[0] == CEA_EXT)
2390 break;
2391 }
2392
2393 if (i == edid->extensions)
2394 return NULL;
2395
2396 return edid_ext;
2397}
2398
2399/*
2400 * Calculate the alternate clock for the CEA mode
2401 * (60Hz vs. 59.94Hz etc.)
2402 */
2403static unsigned int
2404cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2405{
2406 unsigned int clock = cea_mode->clock;
2407
2408 if (cea_mode->vrefresh % 6 != 0)
2409 return clock;
2410
2411 /*
2412 * edid_cea_modes contains the 59.94Hz
2413 * variant for 240 and 480 line modes,
2414 * and the 60Hz variant otherwise.
2415 */
2416 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2417 clock = clock * 1001 / 1000;
2418 else
2419 clock = DIV_ROUND_UP(clock * 1000, 1001);
2420
2421 return clock;
2422}
2423
2424/**
2425 * drm_match_cea_mode - look for a CEA mode matching given mode
2426 * @to_match: display mode
2427 *
2428 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2429 * mode.
2430 */
2431u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2432{
2433 u8 mode;
2434
2435 if (!to_match->clock)
2436 return 0;
2437
2438 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
2439 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2440 unsigned int clock1, clock2;
2441
2442 /* Check both 60Hz and 59.94Hz */
2443 clock1 = cea_mode->clock;
2444 clock2 = cea_mode_alternate_clock(cea_mode);
2445
2446 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2447 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2448 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2449 return mode + 1;
2450 }
2451 return 0;
2452}
2453EXPORT_SYMBOL(drm_match_cea_mode);
2454
2455/*
2456 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2457 * specific block).
2458 *
2459 * It's almost like cea_mode_alternate_clock(), we just need to add an
2460 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2461 * one.
2462 */
2463static unsigned int
2464hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2465{
2466 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2467 return hdmi_mode->clock;
2468
2469 return cea_mode_alternate_clock(hdmi_mode);
2470}
2471
2472/*
2473 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2474 * @to_match: display mode
2475 *
2476 * An HDMI mode is one defined in the HDMI vendor specific block.
2477 *
2478 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2479 */
2480static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2481{
2482 u8 mode;
2483
2484 if (!to_match->clock)
2485 return 0;
2486
2487 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2488 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2489 unsigned int clock1, clock2;
2490
2491 /* Make sure to also match alternate clocks */
2492 clock1 = hdmi_mode->clock;
2493 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2494
2495 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2496 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2497 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2498 return mode + 1;
2499 }
2500 return 0;
2501}
2502
2503static int
2504add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2505{
2506 struct drm_device *dev = connector->dev;
2507 struct drm_display_mode *mode, *tmp;
2508 LIST_HEAD(list);
2509 int modes = 0;
2510
2511 /* Don't add CEA modes if the CEA extension block is missing */
2512 if (!drm_find_cea_extension(edid))
2513 return 0;
2514
2515 /*
2516 * Go through all probed modes and create a new mode
2517 * with the alternate clock for certain CEA modes.
2518 */
2519 list_for_each_entry(mode, &connector->probed_modes, head) {
2520 const struct drm_display_mode *cea_mode = NULL;
2521 struct drm_display_mode *newmode;
2522 u8 mode_idx = drm_match_cea_mode(mode) - 1;
2523 unsigned int clock1, clock2;
2524
2525 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2526 cea_mode = &edid_cea_modes[mode_idx];
2527 clock2 = cea_mode_alternate_clock(cea_mode);
2528 } else {
2529 mode_idx = drm_match_hdmi_mode(mode) - 1;
2530 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2531 cea_mode = &edid_4k_modes[mode_idx];
2532 clock2 = hdmi_mode_alternate_clock(cea_mode);
2533 }
2534 }
2535
2536 if (!cea_mode)
2537 continue;
2538
2539 clock1 = cea_mode->clock;
2540
2541 if (clock1 == clock2)
2542 continue;
2543
2544 if (mode->clock != clock1 && mode->clock != clock2)
2545 continue;
2546
2547 newmode = drm_mode_duplicate(dev, cea_mode);
2548 if (!newmode)
2549 continue;
2550
2551 /* Carry over the stereo flags */
2552 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2553
2554 /*
2555 * The current mode could be either variant. Make
2556 * sure to pick the "other" clock for the new mode.
2557 */
2558 if (mode->clock != clock1)
2559 newmode->clock = clock1;
2560 else
2561 newmode->clock = clock2;
2562
2563 list_add_tail(&newmode->head, &list);
2564 }
2565
2566 list_for_each_entry_safe(mode, tmp, &list, head) {
2567 list_del(&mode->head);
2568 drm_mode_probed_add(connector, mode);
2569 modes++;
2570 }
2571
2572 return modes;
2573}
2574
2575static struct drm_display_mode *
2576drm_display_mode_from_vic_index(struct drm_connector *connector,
2577 const u8 *video_db, u8 video_len,
2578 u8 video_index)
2579{
2580 struct drm_device *dev = connector->dev;
2581 struct drm_display_mode *newmode;
2582 u8 cea_mode;
2583
2584 if (video_db == NULL || video_index >= video_len)
2585 return NULL;
2586
2587 /* CEA modes are numbered 1..127 */
2588 cea_mode = (video_db[video_index] & 127) - 1;
2589 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2590 return NULL;
2591
2592 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
2593 if (!newmode)
2594 return NULL;
2595
2596 newmode->vrefresh = 0;
2597
2598 return newmode;
2599}
2600
2601static int
2602do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2603{
2604 int i, modes = 0;
2605
2606 for (i = 0; i < len; i++) {
2607 struct drm_display_mode *mode;
2608 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2609 if (mode) {
2610 drm_mode_probed_add(connector, mode);
2611 modes++;
2612 }
2613 }
2614
2615 return modes;
2616}
2617
2618struct stereo_mandatory_mode {
2619 int width, height, vrefresh;
2620 unsigned int flags;
2621};
2622
2623static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2624 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2625 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2626 { 1920, 1080, 50,
2627 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2628 { 1920, 1080, 60,
2629 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2630 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2631 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2632 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2633 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2634};
2635
2636static bool
2637stereo_match_mandatory(const struct drm_display_mode *mode,
2638 const struct stereo_mandatory_mode *stereo_mode)
2639{
2640 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2641
2642 return mode->hdisplay == stereo_mode->width &&
2643 mode->vdisplay == stereo_mode->height &&
2644 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2645 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2646}
2647
2648static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2649{
2650 struct drm_device *dev = connector->dev;
2651 const struct drm_display_mode *mode;
2652 struct list_head stereo_modes;
2653 int modes = 0, i;
2654
2655 INIT_LIST_HEAD(&stereo_modes);
2656
2657 list_for_each_entry(mode, &connector->probed_modes, head) {
2658 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2659 const struct stereo_mandatory_mode *mandatory;
2660 struct drm_display_mode *new_mode;
2661
2662 if (!stereo_match_mandatory(mode,
2663 &stereo_mandatory_modes[i]))
2664 continue;
2665
2666 mandatory = &stereo_mandatory_modes[i];
2667 new_mode = drm_mode_duplicate(dev, mode);
2668 if (!new_mode)
2669 continue;
2670
2671 new_mode->flags |= mandatory->flags;
2672 list_add_tail(&new_mode->head, &stereo_modes);
2673 modes++;
2674 }
2675 }
2676
2677 list_splice_tail(&stereo_modes, &connector->probed_modes);
2678
2679 return modes;
2680}
2681
2682static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2683{
2684 struct drm_device *dev = connector->dev;
2685 struct drm_display_mode *newmode;
2686
2687 vic--; /* VICs start at 1 */
2688 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2689 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2690 return 0;
2691 }
2692
2693 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2694 if (!newmode)
2695 return 0;
2696
2697 drm_mode_probed_add(connector, newmode);
2698
2699 return 1;
2700}
2701
2702static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2703 const u8 *video_db, u8 video_len, u8 video_index)
2704{
2705 struct drm_display_mode *newmode;
2706 int modes = 0;
2707
2708 if (structure & (1 << 0)) {
2709 newmode = drm_display_mode_from_vic_index(connector, video_db,
2710 video_len,
2711 video_index);
2712 if (newmode) {
2713 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2714 drm_mode_probed_add(connector, newmode);
2715 modes++;
2716 }
2717 }
2718 if (structure & (1 << 6)) {
2719 newmode = drm_display_mode_from_vic_index(connector, video_db,
2720 video_len,
2721 video_index);
2722 if (newmode) {
2723 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2724 drm_mode_probed_add(connector, newmode);
2725 modes++;
2726 }
2727 }
2728 if (structure & (1 << 8)) {
2729 newmode = drm_display_mode_from_vic_index(connector, video_db,
2730 video_len,
2731 video_index);
2732 if (newmode) {
2733 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2734 drm_mode_probed_add(connector, newmode);
2735 modes++;
2736 }
2737 }
2738
2739 return modes;
2740}
2741
2742/*
2743 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2744 * @connector: connector corresponding to the HDMI sink
2745 * @db: start of the CEA vendor specific block
2746 * @len: length of the CEA block payload, ie. one can access up to db[len]
2747 *
2748 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2749 * also adds the stereo 3d modes when applicable.
2750 */
2751static int
2752do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2753 const u8 *video_db, u8 video_len)
2754{
2755 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
2756 u8 vic_len, hdmi_3d_len = 0;
2757 u16 mask;
2758 u16 structure_all;
2759
2760 if (len < 8)
2761 goto out;
2762
2763 /* no HDMI_Video_Present */
2764 if (!(db[8] & (1 << 5)))
2765 goto out;
2766
2767 /* Latency_Fields_Present */
2768 if (db[8] & (1 << 7))
2769 offset += 2;
2770
2771 /* I_Latency_Fields_Present */
2772 if (db[8] & (1 << 6))
2773 offset += 2;
2774
2775 /* the declared length is not long enough for the 2 first bytes
2776 * of additional video format capabilities */
2777 if (len < (8 + offset + 2))
2778 goto out;
2779
2780 /* 3D_Present */
2781 offset++;
2782 if (db[8 + offset] & (1 << 7)) {
2783 modes += add_hdmi_mandatory_stereo_modes(connector);
2784
2785 /* 3D_Multi_present */
2786 multi_present = (db[8 + offset] & 0x60) >> 5;
2787 }
2788
2789 offset++;
2790 vic_len = db[8 + offset] >> 5;
2791 hdmi_3d_len = db[8 + offset] & 0x1f;
2792
2793 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
2794 u8 vic;
2795
2796 vic = db[9 + offset + i];
2797 modes += add_hdmi_mode(connector, vic);
2798 }
2799 offset += 1 + vic_len;
2800
2801 if (multi_present == 1)
2802 multi_len = 2;
2803 else if (multi_present == 2)
2804 multi_len = 4;
2805 else
2806 multi_len = 0;
2807
2808 if (len < (8 + offset + hdmi_3d_len - 1))
2809 goto out;
2810
2811 if (hdmi_3d_len < multi_len)
2812 goto out;
2813
2814 if (multi_present == 1 || multi_present == 2) {
2815 /* 3D_Structure_ALL */
2816 structure_all = (db[8 + offset] << 8) | db[9 + offset];
2817
2818 /* check if 3D_MASK is present */
2819 if (multi_present == 2)
2820 mask = (db[10 + offset] << 8) | db[11 + offset];
2821 else
2822 mask = 0xffff;
2823
2824 for (i = 0; i < 16; i++) {
2825 if (mask & (1 << i))
2826 modes += add_3d_struct_modes(connector,
2827 structure_all,
2828 video_db,
2829 video_len, i);
2830 }
2831 }
2832
2833 offset += multi_len;
2834
2835 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2836 int vic_index;
2837 struct drm_display_mode *newmode = NULL;
2838 unsigned int newflag = 0;
2839 bool detail_present;
2840
2841 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2842
2843 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2844 break;
2845
2846 /* 2D_VIC_order_X */
2847 vic_index = db[8 + offset + i] >> 4;
2848
2849 /* 3D_Structure_X */
2850 switch (db[8 + offset + i] & 0x0f) {
2851 case 0:
2852 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2853 break;
2854 case 6:
2855 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2856 break;
2857 case 8:
2858 /* 3D_Detail_X */
2859 if ((db[9 + offset + i] >> 4) == 1)
2860 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2861 break;
2862 }
2863
2864 if (newflag != 0) {
2865 newmode = drm_display_mode_from_vic_index(connector,
2866 video_db,
2867 video_len,
2868 vic_index);
2869
2870 if (newmode) {
2871 newmode->flags |= newflag;
2872 drm_mode_probed_add(connector, newmode);
2873 modes++;
2874 }
2875 }
2876
2877 if (detail_present)
2878 i++;
2879 }
2880
2881out:
2882 return modes;
2883}
2884
2885static int
2886cea_db_payload_len(const u8 *db)
2887{
2888 return db[0] & 0x1f;
2889}
2890
2891static int
2892cea_db_tag(const u8 *db)
2893{
2894 return db[0] >> 5;
2895}
2896
2897static int
2898cea_revision(const u8 *cea)
2899{
2900 return cea[1];
2901}
2902
2903static int
2904cea_db_offsets(const u8 *cea, int *start, int *end)
2905{
2906 /* Data block offset in CEA extension block */
2907 *start = 4;
2908 *end = cea[2];
2909 if (*end == 0)
2910 *end = 127;
2911 if (*end < 4 || *end > 127)
2912 return -ERANGE;
2913 return 0;
2914}
2915
2916static bool cea_db_is_hdmi_vsdb(const u8 *db)
2917{
2918 int hdmi_id;
2919
2920 if (cea_db_tag(db) != VENDOR_BLOCK)
2921 return false;
2922
2923 if (cea_db_payload_len(db) < 5)
2924 return false;
2925
2926 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
2927
2928 return hdmi_id == HDMI_IEEE_OUI;
2929}
2930
2931#define for_each_cea_db(cea, i, start, end) \
2932 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
2933
2934static int
2935add_cea_modes(struct drm_connector *connector, struct edid *edid)
2936{
2937 const u8 *cea = drm_find_cea_extension(edid);
2938 const u8 *db, *hdmi = NULL, *video = NULL;
2939 u8 dbl, hdmi_len, video_len = 0;
2940 int modes = 0;
2941
2942 if (cea && cea_revision(cea) >= 3) {
2943 int i, start, end;
2944
2945 if (cea_db_offsets(cea, &start, &end))
2946 return 0;
2947
2948 for_each_cea_db(cea, i, start, end) {
2949 db = &cea[i];
2950 dbl = cea_db_payload_len(db);
2951
2952 if (cea_db_tag(db) == VIDEO_BLOCK) {
2953 video = db + 1;
2954 video_len = dbl;
2955 modes += do_cea_modes(connector, video, dbl);
2956 }
2957 else if (cea_db_is_hdmi_vsdb(db)) {
2958 hdmi = db;
2959 hdmi_len = dbl;
2960 }
2961 }
2962 }
2963
2964 /*
2965 * We parse the HDMI VSDB after having added the cea modes as we will
2966 * be patching their flags when the sink supports stereo 3D.
2967 */
2968 if (hdmi)
2969 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
2970 video_len);
2971
2972 return modes;
2973}
2974
2975static void
2976parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
2977{
2978 u8 len = cea_db_payload_len(db);
2979
2980 if (len >= 6) {
2981 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
2982 connector->dvi_dual = db[6] & 1;
2983 }
2984 if (len >= 7)
2985 connector->max_tmds_clock = db[7] * 5;
2986 if (len >= 8) {
2987 connector->latency_present[0] = db[8] >> 7;
2988 connector->latency_present[1] = (db[8] >> 6) & 1;
2989 }
2990 if (len >= 9)
2991 connector->video_latency[0] = db[9];
2992 if (len >= 10)
2993 connector->audio_latency[0] = db[10];
2994 if (len >= 11)
2995 connector->video_latency[1] = db[11];
2996 if (len >= 12)
2997 connector->audio_latency[1] = db[12];
2998
2999 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3000 "max TMDS clock %d, "
3001 "latency present %d %d, "
3002 "video latency %d %d, "
3003 "audio latency %d %d\n",
3004 connector->dvi_dual,
3005 connector->max_tmds_clock,
3006 (int) connector->latency_present[0],
3007 (int) connector->latency_present[1],
3008 connector->video_latency[0],
3009 connector->video_latency[1],
3010 connector->audio_latency[0],
3011 connector->audio_latency[1]);
3012}
3013
3014static void
3015monitor_name(struct detailed_timing *t, void *data)
3016{
3017 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3018 *(u8 **)data = t->data.other_data.data.str.str;
3019}
3020
3021/**
3022 * drm_edid_to_eld - build ELD from EDID
3023 * @connector: connector corresponding to the HDMI/DP sink
3024 * @edid: EDID to parse
3025 *
3026 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver.
3027 * Some ELD fields are left to the graphics driver caller:
3028 * - Conn_Type
3029 * - HDCP
3030 * - Port_ID
3031 */
3032void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3033{
3034 uint8_t *eld = connector->eld;
3035 u8 *cea;
3036 u8 *name;
3037 u8 *db;
3038 int sad_count = 0;
3039 int mnl;
3040 int dbl;
3041
3042 memset(eld, 0, sizeof(connector->eld));
3043
3044 cea = drm_find_cea_extension(edid);
3045 if (!cea) {
3046 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3047 return;
3048 }
3049
3050 name = NULL;
3051 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3052 for (mnl = 0; name && mnl < 13; mnl++) {
3053 if (name[mnl] == 0x0a)
3054 break;
3055 eld[20 + mnl] = name[mnl];
3056 }
3057 eld[4] = (cea[1] << 5) | mnl;
3058 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3059
3060 eld[0] = 2 << 3; /* ELD version: 2 */
3061
3062 eld[16] = edid->mfg_id[0];
3063 eld[17] = edid->mfg_id[1];
3064 eld[18] = edid->prod_code[0];
3065 eld[19] = edid->prod_code[1];
3066
3067 if (cea_revision(cea) >= 3) {
3068 int i, start, end;
3069
3070 if (cea_db_offsets(cea, &start, &end)) {
3071 start = 0;
3072 end = 0;
3073 }
3074
3075 for_each_cea_db(cea, i, start, end) {
3076 db = &cea[i];
3077 dbl = cea_db_payload_len(db);
3078
3079 switch (cea_db_tag(db)) {
3080 case AUDIO_BLOCK:
3081 /* Audio Data Block, contains SADs */
3082 sad_count = dbl / 3;
3083 if (dbl >= 1)
3084 memcpy(eld + 20 + mnl, &db[1], dbl);
3085 break;
3086 case SPEAKER_BLOCK:
3087 /* Speaker Allocation Data Block */
3088 if (dbl >= 1)
3089 eld[7] = db[1];
3090 break;
3091 case VENDOR_BLOCK:
3092 /* HDMI Vendor-Specific Data Block */
3093 if (cea_db_is_hdmi_vsdb(db))
3094 parse_hdmi_vsdb(connector, db);
3095 break;
3096 default:
3097 break;
3098 }
3099 }
3100 }
3101 eld[5] |= sad_count << 4;
3102 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
3103
3104 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
3105}
3106EXPORT_SYMBOL(drm_edid_to_eld);
3107
3108/**
3109 * drm_edid_to_sad - extracts SADs from EDID
3110 * @edid: EDID to parse
3111 * @sads: pointer that will be set to the extracted SADs
3112 *
3113 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3114 * Note: returned pointer needs to be kfreed
3115 *
3116 * Return number of found SADs or negative number on error.
3117 */
3118int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3119{
3120 int count = 0;
3121 int i, start, end, dbl;
3122 u8 *cea;
3123
3124 cea = drm_find_cea_extension(edid);
3125 if (!cea) {
3126 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3127 return -ENOENT;
3128 }
3129
3130 if (cea_revision(cea) < 3) {
3131 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3132 return -ENOTSUPP;
3133 }
3134
3135 if (cea_db_offsets(cea, &start, &end)) {
3136 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3137 return -EPROTO;
3138 }
3139
3140 for_each_cea_db(cea, i, start, end) {
3141 u8 *db = &cea[i];
3142
3143 if (cea_db_tag(db) == AUDIO_BLOCK) {
3144 int j;
3145 dbl = cea_db_payload_len(db);
3146
3147 count = dbl / 3; /* SAD is 3B */
3148 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3149 if (!*sads)
3150 return -ENOMEM;
3151 for (j = 0; j < count; j++) {
3152 u8 *sad = &db[1 + j * 3];
3153
3154 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3155 (*sads)[j].channels = sad[0] & 0x7;
3156 (*sads)[j].freq = sad[1] & 0x7F;
3157 (*sads)[j].byte2 = sad[2];
3158 }
3159 break;
3160 }
3161 }
3162
3163 return count;
3164}
3165EXPORT_SYMBOL(drm_edid_to_sad);
3166
3167/**
3168 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3169 * @edid: EDID to parse
3170 * @sadb: pointer to the speaker block
3171 *
3172 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3173 * Note: returned pointer needs to be kfreed
3174 *
3175 * Return number of found Speaker Allocation Blocks or negative number on error.
3176 */
3177int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3178{
3179 int count = 0;
3180 int i, start, end, dbl;
3181 const u8 *cea;
3182
3183 cea = drm_find_cea_extension(edid);
3184 if (!cea) {
3185 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3186 return -ENOENT;
3187 }
3188
3189 if (cea_revision(cea) < 3) {
3190 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3191 return -ENOTSUPP;
3192 }
3193
3194 if (cea_db_offsets(cea, &start, &end)) {
3195 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3196 return -EPROTO;
3197 }
3198
3199 for_each_cea_db(cea, i, start, end) {
3200 const u8 *db = &cea[i];
3201
3202 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3203 dbl = cea_db_payload_len(db);
3204
3205 /* Speaker Allocation Data Block */
3206 if (dbl == 3) {
3207 *sadb = kmalloc(dbl, GFP_KERNEL);
3208 if (!*sadb)
3209 return -ENOMEM;
3210 memcpy(*sadb, &db[1], dbl);
3211 count = dbl;
3212 break;
3213 }
3214 }
3215 }
3216
3217 return count;
3218}
3219EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3220
3221/**
3222 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond
3223 * @connector: connector associated with the HDMI/DP sink
3224 * @mode: the display mode
3225 */
3226int drm_av_sync_delay(struct drm_connector *connector,
3227 struct drm_display_mode *mode)
3228{
3229 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3230 int a, v;
3231
3232 if (!connector->latency_present[0])
3233 return 0;
3234 if (!connector->latency_present[1])
3235 i = 0;
3236
3237 a = connector->audio_latency[i];
3238 v = connector->video_latency[i];
3239
3240 /*
3241 * HDMI/DP sink doesn't support audio or video?
3242 */
3243 if (a == 255 || v == 255)
3244 return 0;
3245
3246 /*
3247 * Convert raw EDID values to millisecond.
3248 * Treat unknown latency as 0ms.
3249 */
3250 if (a)
3251 a = min(2 * (a - 1), 500);
3252 if (v)
3253 v = min(2 * (v - 1), 500);
3254
3255 return max(v - a, 0);
3256}
3257EXPORT_SYMBOL(drm_av_sync_delay);
3258
3259/**
3260 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3261 * @encoder: the encoder just changed display mode
3262 * @mode: the adjusted display mode
3263 *
3264 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3265 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3266 */
3267struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3268 struct drm_display_mode *mode)
3269{
3270 struct drm_connector *connector;
3271 struct drm_device *dev = encoder->dev;
3272
3273 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3274 if (connector->encoder == encoder && connector->eld[0])
3275 return connector;
3276
3277 return NULL;
3278}
3279EXPORT_SYMBOL(drm_select_eld);
3280
3281/**
3282 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
3283 * @edid: monitor EDID information
3284 *
3285 * Parse the CEA extension according to CEA-861-B.
3286 * Return true if HDMI, false if not or unknown.
3287 */
3288bool drm_detect_hdmi_monitor(struct edid *edid)
3289{
3290 u8 *edid_ext;
3291 int i;
3292 int start_offset, end_offset;
3293
3294 edid_ext = drm_find_cea_extension(edid);
3295 if (!edid_ext)
3296 return false;
3297
3298 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3299 return false;
3300
3301 /*
3302 * Because HDMI identifier is in Vendor Specific Block,
3303 * search it from all data blocks of CEA extension.
3304 */
3305 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3306 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3307 return true;
3308 }
3309
3310 return false;
3311}
3312EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3313
3314/**
3315 * drm_detect_monitor_audio - check monitor audio capability
3316 * @edid: EDID block to scan
3317 *
3318 * Monitor should have CEA extension block.
3319 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3320 * audio' only. If there is any audio extension block and supported
3321 * audio format, assume at least 'basic audio' support, even if 'basic
3322 * audio' is not defined in EDID.
3323 *
3324 */
3325bool drm_detect_monitor_audio(struct edid *edid)
3326{
3327 u8 *edid_ext;
3328 int i, j;
3329 bool has_audio = false;
3330 int start_offset, end_offset;
3331
3332 edid_ext = drm_find_cea_extension(edid);
3333 if (!edid_ext)
3334 goto end;
3335
3336 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3337
3338 if (has_audio) {
3339 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3340 goto end;
3341 }
3342
3343 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3344 goto end;
3345
3346 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3347 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3348 has_audio = true;
3349 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3350 DRM_DEBUG_KMS("CEA audio format %d\n",
3351 (edid_ext[i + j] >> 3) & 0xf);
3352 goto end;
3353 }
3354 }
3355end:
3356 return has_audio;
3357}
3358EXPORT_SYMBOL(drm_detect_monitor_audio);
3359
3360/**
3361 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3362 * @edid: EDID block to scan
3363 *
3364 * Check whether the monitor reports the RGB quantization range selection
3365 * as supported. The AVI infoframe can then be used to inform the monitor
3366 * which quantization range (full or limited) is used.
3367 */
3368bool drm_rgb_quant_range_selectable(struct edid *edid)
3369{
3370 u8 *edid_ext;
3371 int i, start, end;
3372
3373 edid_ext = drm_find_cea_extension(edid);
3374 if (!edid_ext)
3375 return false;
3376
3377 if (cea_db_offsets(edid_ext, &start, &end))
3378 return false;
3379
3380 for_each_cea_db(edid_ext, i, start, end) {
3381 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3382 cea_db_payload_len(&edid_ext[i]) == 2) {
3383 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3384 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3385 }
3386 }
3387
3388 return false;
3389}
3390EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3391
3392/**
3393 * drm_add_display_info - pull display info out if present
3394 * @edid: EDID data
3395 * @info: display info (attached to connector)
3396 *
3397 * Grab any available display info and stuff it into the drm_display_info
3398 * structure that's part of the connector. Useful for tracking bpp and
3399 * color spaces.
3400 */
3401static void drm_add_display_info(struct edid *edid,
3402 struct drm_display_info *info)
3403{
3404 u8 *edid_ext;
3405
3406 info->width_mm = edid->width_cm * 10;
3407 info->height_mm = edid->height_cm * 10;
3408
3409 /* driver figures it out in this case */
3410 info->bpc = 0;
3411 info->color_formats = 0;
3412
3413 if (edid->revision < 3)
3414 return;
3415
3416 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3417 return;
3418
3419 /* Get data from CEA blocks if present */
3420 edid_ext = drm_find_cea_extension(edid);
3421 if (edid_ext) {
3422 info->cea_rev = edid_ext[1];
3423
3424 /* The existence of a CEA block should imply RGB support */
3425 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3426 if (edid_ext[3] & EDID_CEA_YCRCB444)
3427 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3428 if (edid_ext[3] & EDID_CEA_YCRCB422)
3429 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3430 }
3431
3432 /* Only defined for 1.4 with digital displays */
3433 if (edid->revision < 4)
3434 return;
3435
3436 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3437 case DRM_EDID_DIGITAL_DEPTH_6:
3438 info->bpc = 6;
3439 break;
3440 case DRM_EDID_DIGITAL_DEPTH_8:
3441 info->bpc = 8;
3442 break;
3443 case DRM_EDID_DIGITAL_DEPTH_10:
3444 info->bpc = 10;
3445 break;
3446 case DRM_EDID_DIGITAL_DEPTH_12:
3447 info->bpc = 12;
3448 break;
3449 case DRM_EDID_DIGITAL_DEPTH_14:
3450 info->bpc = 14;
3451 break;
3452 case DRM_EDID_DIGITAL_DEPTH_16:
3453 info->bpc = 16;
3454 break;
3455 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3456 default:
3457 info->bpc = 0;
3458 break;
3459 }
3460
3461 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3462 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3463 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3464 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3465 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3466}
3467
3468/**
3469 * drm_add_edid_modes - add modes from EDID data, if available
3470 * @connector: connector we're probing
3471 * @edid: edid data
3472 *
3473 * Add the specified modes to the connector's mode list.
3474 *
3475 * Return number of modes added or 0 if we couldn't find any.
3476 */
3477int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3478{
3479 int num_modes = 0;
3480 u32 quirks;
3481
3482 if (edid == NULL) {
3483 return 0;
3484 }
3485 if (!drm_edid_is_valid(edid)) {
3486 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
3487 drm_get_connector_name(connector));
3488 return 0;
3489 }
3490
3491 quirks = edid_get_quirks(edid);
3492
3493 /*
3494 * EDID spec says modes should be preferred in this order:
3495 * - preferred detailed mode
3496 * - other detailed modes from base block
3497 * - detailed modes from extension blocks
3498 * - CVT 3-byte code modes
3499 * - standard timing codes
3500 * - established timing codes
3501 * - modes inferred from GTF or CVT range information
3502 *
3503 * We get this pretty much right.
3504 *
3505 * XXX order for additional mode types in extension blocks?
3506 */
3507 num_modes += add_detailed_modes(connector, edid, quirks);
3508 num_modes += add_cvt_modes(connector, edid);
3509 num_modes += add_standard_modes(connector, edid);
3510 num_modes += add_established_modes(connector, edid);
3511 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3512 num_modes += add_inferred_modes(connector, edid);
3513 num_modes += add_cea_modes(connector, edid);
3514 num_modes += add_alternate_cea_modes(connector, edid);
3515
3516 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3517 edid_fixup_preferred(connector, quirks);
3518
3519 drm_add_display_info(edid, &connector->display_info);
3520
3521 if (quirks & EDID_QUIRK_FORCE_8BPC)
3522 connector->display_info.bpc = 8;
3523
3524 return num_modes;
3525}
3526EXPORT_SYMBOL(drm_add_edid_modes);
3527
3528/**
3529 * drm_add_modes_noedid - add modes for the connectors without EDID
3530 * @connector: connector we're probing
3531 * @hdisplay: the horizontal display limit
3532 * @vdisplay: the vertical display limit
3533 *
3534 * Add the specified modes to the connector's mode list. Only when the
3535 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3536 *
3537 * Return number of modes added or 0 if we couldn't find any.
3538 */
3539int drm_add_modes_noedid(struct drm_connector *connector,
3540 int hdisplay, int vdisplay)
3541{
3542 int i, count, num_modes = 0;
3543 struct drm_display_mode *mode;
3544 struct drm_device *dev = connector->dev;
3545
3546 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3547 if (hdisplay < 0)
3548 hdisplay = 0;
3549 if (vdisplay < 0)
3550 vdisplay = 0;
3551
3552 for (i = 0; i < count; i++) {
3553 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3554 if (hdisplay && vdisplay) {
3555 /*
3556 * Only when two are valid, they will be used to check
3557 * whether the mode should be added to the mode list of
3558 * the connector.
3559 */
3560 if (ptr->hdisplay > hdisplay ||
3561 ptr->vdisplay > vdisplay)
3562 continue;
3563 }
3564 if (drm_mode_vrefresh(ptr) > 61)
3565 continue;
3566 mode = drm_mode_duplicate(dev, ptr);
3567 if (mode) {
3568 drm_mode_probed_add(connector, mode);
3569 num_modes++;
3570 }
3571 }
3572 return num_modes;
3573}
3574EXPORT_SYMBOL(drm_add_modes_noedid);
3575
3576void drm_set_preferred_mode(struct drm_connector *connector,
3577 int hpref, int vpref)
3578{
3579 struct drm_display_mode *mode;
3580
3581 list_for_each_entry(mode, &connector->probed_modes, head) {
3582 if (mode->hdisplay == hpref &&
3583 mode->vdisplay == vpref)
3584 mode->type |= DRM_MODE_TYPE_PREFERRED;
3585 }
3586}
3587EXPORT_SYMBOL(drm_set_preferred_mode);
3588
3589/**
3590 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3591 * data from a DRM display mode
3592 * @frame: HDMI AVI infoframe
3593 * @mode: DRM display mode
3594 *
3595 * Returns 0 on success or a negative error code on failure.
3596 */
3597int
3598drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3599 const struct drm_display_mode *mode)
3600{
3601 int err;
3602
3603 if (!frame || !mode)
3604 return -EINVAL;
3605
3606 err = hdmi_avi_infoframe_init(frame);
3607 if (err < 0)
3608 return err;
3609
3610 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3611 frame->pixel_repeat = 1;
3612
3613 frame->video_code = drm_match_cea_mode(mode);
3614
3615 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
3616 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
3617 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
3618
3619 return 0;
3620}
3621EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
3622
3623static enum hdmi_3d_structure
3624s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3625{
3626 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3627
3628 switch (layout) {
3629 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3630 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3631 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3632 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3633 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3634 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3635 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3636 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3637 case DRM_MODE_FLAG_3D_L_DEPTH:
3638 return HDMI_3D_STRUCTURE_L_DEPTH;
3639 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3640 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3641 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3642 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3643 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3644 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3645 default:
3646 return HDMI_3D_STRUCTURE_INVALID;
3647 }
3648}
3649
3650/**
3651 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3652 * data from a DRM display mode
3653 * @frame: HDMI vendor infoframe
3654 * @mode: DRM display mode
3655 *
3656 * Note that there's is a need to send HDMI vendor infoframes only when using a
3657 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3658 * function will return -EINVAL, error that can be safely ignored.
3659 *
3660 * Returns 0 on success or a negative error code on failure.
3661 */
3662int
3663drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3664 const struct drm_display_mode *mode)
3665{
3666 int err;
3667 u32 s3d_flags;
3668 u8 vic;
3669
3670 if (!frame || !mode)
3671 return -EINVAL;
3672
3673 vic = drm_match_hdmi_mode(mode);
3674 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3675
3676 if (!vic && !s3d_flags)
3677 return -EINVAL;
3678
3679 if (vic && s3d_flags)
3680 return -EINVAL;
3681
3682 err = hdmi_vendor_infoframe_init(frame);
3683 if (err < 0)
3684 return err;
3685
3686 if (vic)
3687 frame->vic = vic;
3688 else
3689 frame->s3d_struct = s3d_structure_from_display_mode(mode);
3690
3691 return 0;
3692}
3693EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);