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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
7 */
8
9#include <linux/types.h>
10
11#include "omap_hwmod.h"
12#include "omap_hwmod_common_data.h"
13#include "cm-regbits-24xx.h"
14#include "prm-regbits-24xx.h"
15#include "wd_timer.h"
16
17/*
18 * 'dispc' class
19 * display controller
20 */
21
22static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
23 .rev_offs = 0x0000,
24 .sysc_offs = 0x0010,
25 .syss_offs = 0x0014,
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
31};
32
33static struct omap_hwmod_class omap2_dispc_hwmod_class = {
34 .name = "dispc",
35 .sysc = &omap2_dispc_sysc,
36};
37
38/* OMAP2xxx Timer Common */
39static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
40 .rev_offs = 0x0000,
41 .sysc_offs = 0x0010,
42 .syss_offs = 0x0014,
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
51 .name = "timer",
52 .sysc = &omap2xxx_timer_sysc,
53};
54
55/*
56 * 'wd_timer' class
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
58 * overflow condition
59 */
60
61static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
62 .rev_offs = 0x0000,
63 .sysc_offs = 0x0010,
64 .syss_offs = 0x0014,
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
68};
69
70static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
71 .name = "wd_timer",
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
75};
76
77/*
78 * 'gpio' class
79 * general purpose io module
80 */
81static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
90};
91
92struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
93 .name = "gpio",
94 .sysc = &omap2xxx_gpio_sysc,
95};
96
97/*
98 * 'mailbox' class
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
101 */
102
103static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
104 .rev_offs = 0x000,
105 .sysc_offs = 0x010,
106 .syss_offs = 0x014,
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
111};
112
113struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
114 .name = "mailbox",
115 .sysc = &omap2xxx_mailbox_sysc,
116};
117
118/*
119 * 'mcspi' class
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
121 * bus
122 */
123
124static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
125 .rev_offs = 0x0000,
126 .sysc_offs = 0x0010,
127 .syss_offs = 0x0014,
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
133};
134
135struct omap_hwmod_class omap2xxx_mcspi_class = {
136 .name = "mcspi",
137 .sysc = &omap2xxx_mcspi_sysc,
138};
139
140/*
141 * 'gpmc' class
142 * general purpose memory controller
143 */
144
145static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
146 .rev_offs = 0x0000,
147 .sysc_offs = 0x0010,
148 .syss_offs = 0x0014,
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
153};
154
155static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
156 .name = "gpmc",
157 .sysc = &omap2xxx_gpmc_sysc,
158};
159
160/*
161 * IP blocks
162 */
163
164/* L3 */
165struct omap_hwmod omap2xxx_l3_main_hwmod = {
166 .name = "l3_main",
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
169};
170
171/* L4 CORE */
172struct omap_hwmod omap2xxx_l4_core_hwmod = {
173 .name = "l4_core",
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
176};
177
178/* L4 WKUP */
179struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
180 .name = "l4_wkup",
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
183};
184
185/* MPU */
186struct omap_hwmod omap2xxx_mpu_hwmod = {
187 .name = "mpu",
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
190};
191
192/* timer3 */
193struct omap_hwmod omap2xxx_timer3_hwmod = {
194 .name = "timer3",
195 .main_clk = "gpt3_fck",
196 .prcm = {
197 .omap2 = {
198 .module_offs = CORE_MOD,
199 .idlest_reg_id = 1,
200 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
201 },
202 },
203 .class = &omap2xxx_timer_hwmod_class,
204 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
205};
206
207/* timer4 */
208struct omap_hwmod omap2xxx_timer4_hwmod = {
209 .name = "timer4",
210 .main_clk = "gpt4_fck",
211 .prcm = {
212 .omap2 = {
213 .module_offs = CORE_MOD,
214 .idlest_reg_id = 1,
215 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
216 },
217 },
218 .class = &omap2xxx_timer_hwmod_class,
219 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
220};
221
222/* timer5 */
223struct omap_hwmod omap2xxx_timer5_hwmod = {
224 .name = "timer5",
225 .main_clk = "gpt5_fck",
226 .prcm = {
227 .omap2 = {
228 .module_offs = CORE_MOD,
229 .idlest_reg_id = 1,
230 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
231 },
232 },
233 .class = &omap2xxx_timer_hwmod_class,
234 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
235};
236
237/* timer6 */
238struct omap_hwmod omap2xxx_timer6_hwmod = {
239 .name = "timer6",
240 .main_clk = "gpt6_fck",
241 .prcm = {
242 .omap2 = {
243 .module_offs = CORE_MOD,
244 .idlest_reg_id = 1,
245 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
246 },
247 },
248 .class = &omap2xxx_timer_hwmod_class,
249 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
250};
251
252/* timer7 */
253struct omap_hwmod omap2xxx_timer7_hwmod = {
254 .name = "timer7",
255 .main_clk = "gpt7_fck",
256 .prcm = {
257 .omap2 = {
258 .module_offs = CORE_MOD,
259 .idlest_reg_id = 1,
260 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
261 },
262 },
263 .class = &omap2xxx_timer_hwmod_class,
264 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
265};
266
267/* timer8 */
268struct omap_hwmod omap2xxx_timer8_hwmod = {
269 .name = "timer8",
270 .main_clk = "gpt8_fck",
271 .prcm = {
272 .omap2 = {
273 .module_offs = CORE_MOD,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
276 },
277 },
278 .class = &omap2xxx_timer_hwmod_class,
279 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
280};
281
282/* timer9 */
283struct omap_hwmod omap2xxx_timer9_hwmod = {
284 .name = "timer9",
285 .main_clk = "gpt9_fck",
286 .prcm = {
287 .omap2 = {
288 .module_offs = CORE_MOD,
289 .idlest_reg_id = 1,
290 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
291 },
292 },
293 .class = &omap2xxx_timer_hwmod_class,
294 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
295};
296
297/* timer10 */
298struct omap_hwmod omap2xxx_timer10_hwmod = {
299 .name = "timer10",
300 .main_clk = "gpt10_fck",
301 .prcm = {
302 .omap2 = {
303 .module_offs = CORE_MOD,
304 .idlest_reg_id = 1,
305 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
306 },
307 },
308 .class = &omap2xxx_timer_hwmod_class,
309 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
310};
311
312/* timer11 */
313struct omap_hwmod omap2xxx_timer11_hwmod = {
314 .name = "timer11",
315 .main_clk = "gpt11_fck",
316 .prcm = {
317 .omap2 = {
318 .module_offs = CORE_MOD,
319 .idlest_reg_id = 1,
320 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
321 },
322 },
323 .class = &omap2xxx_timer_hwmod_class,
324 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325};
326
327/* timer12 */
328struct omap_hwmod omap2xxx_timer12_hwmod = {
329 .name = "timer12",
330 .main_clk = "gpt12_fck",
331 .prcm = {
332 .omap2 = {
333 .module_offs = CORE_MOD,
334 .idlest_reg_id = 1,
335 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
336 },
337 },
338 .class = &omap2xxx_timer_hwmod_class,
339 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
340};
341
342/* wd_timer2 */
343struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
344 .name = "wd_timer2",
345 .class = &omap2xxx_wd_timer_hwmod_class,
346 .main_clk = "mpu_wdt_fck",
347 .prcm = {
348 .omap2 = {
349 .module_offs = WKUP_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
352 },
353 },
354};
355
356/* UART1 */
357
358struct omap_hwmod omap2xxx_uart1_hwmod = {
359 .name = "uart1",
360 .main_clk = "uart1_fck",
361 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
362 .prcm = {
363 .omap2 = {
364 .module_offs = CORE_MOD,
365 .idlest_reg_id = 1,
366 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
367 },
368 },
369 .class = &omap2_uart_class,
370};
371
372/* UART2 */
373
374struct omap_hwmod omap2xxx_uart2_hwmod = {
375 .name = "uart2",
376 .main_clk = "uart2_fck",
377 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
378 .prcm = {
379 .omap2 = {
380 .module_offs = CORE_MOD,
381 .idlest_reg_id = 1,
382 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
383 },
384 },
385 .class = &omap2_uart_class,
386};
387
388/* UART3 */
389
390struct omap_hwmod omap2xxx_uart3_hwmod = {
391 .name = "uart3",
392 .main_clk = "uart3_fck",
393 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
394 .prcm = {
395 .omap2 = {
396 .module_offs = CORE_MOD,
397 .idlest_reg_id = 2,
398 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
399 },
400 },
401 .class = &omap2_uart_class,
402};
403
404/* dss */
405
406static struct omap_hwmod_opt_clk dss_opt_clks[] = {
407 /*
408 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
409 * driver does not use these clocks.
410 */
411 { .role = "tv_clk", .clk = "dss_54m_fck" },
412 { .role = "sys_clk", .clk = "dss2_fck" },
413};
414
415struct omap_hwmod omap2xxx_dss_core_hwmod = {
416 .name = "dss_core",
417 .class = &omap2_dss_hwmod_class,
418 .main_clk = "dss1_fck", /* instead of dss_fck */
419 .prcm = {
420 .omap2 = {
421 .module_offs = CORE_MOD,
422 .idlest_reg_id = 1,
423 },
424 },
425 .opt_clks = dss_opt_clks,
426 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
427 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
428};
429
430struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
431 .name = "dss_dispc",
432 .class = &omap2_dispc_hwmod_class,
433 .main_clk = "dss1_fck",
434 .prcm = {
435 .omap2 = {
436 .module_offs = CORE_MOD,
437 .idlest_reg_id = 1,
438 },
439 },
440 .flags = HWMOD_NO_IDLEST,
441 .dev_attr = &omap2_3_dss_dispc_dev_attr,
442};
443
444static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
445 { .role = "ick", .clk = "dss_ick" },
446};
447
448struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
449 .name = "dss_rfbi",
450 .class = &omap2_rfbi_hwmod_class,
451 .main_clk = "dss1_fck",
452 .prcm = {
453 .omap2 = {
454 .module_offs = CORE_MOD,
455 },
456 },
457 .opt_clks = dss_rfbi_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
459 .flags = HWMOD_NO_IDLEST,
460};
461
462struct omap_hwmod omap2xxx_dss_venc_hwmod = {
463 .name = "dss_venc",
464 .class = &omap2_venc_hwmod_class,
465 .main_clk = "dss_54m_fck",
466 .prcm = {
467 .omap2 = {
468 .module_offs = CORE_MOD,
469 },
470 },
471 .flags = HWMOD_NO_IDLEST,
472};
473
474/* gpio1 */
475struct omap_hwmod omap2xxx_gpio1_hwmod = {
476 .name = "gpio1",
477 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
478 .main_clk = "gpios_fck",
479 .prcm = {
480 .omap2 = {
481 .module_offs = WKUP_MOD,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
484 },
485 },
486 .class = &omap2xxx_gpio_hwmod_class,
487};
488
489/* gpio2 */
490struct omap_hwmod omap2xxx_gpio2_hwmod = {
491 .name = "gpio2",
492 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
493 .main_clk = "gpios_fck",
494 .prcm = {
495 .omap2 = {
496 .module_offs = WKUP_MOD,
497 .idlest_reg_id = 1,
498 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
499 },
500 },
501 .class = &omap2xxx_gpio_hwmod_class,
502};
503
504/* gpio3 */
505struct omap_hwmod omap2xxx_gpio3_hwmod = {
506 .name = "gpio3",
507 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
508 .main_clk = "gpios_fck",
509 .prcm = {
510 .omap2 = {
511 .module_offs = WKUP_MOD,
512 .idlest_reg_id = 1,
513 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
514 },
515 },
516 .class = &omap2xxx_gpio_hwmod_class,
517};
518
519/* gpio4 */
520struct omap_hwmod omap2xxx_gpio4_hwmod = {
521 .name = "gpio4",
522 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
523 .main_clk = "gpios_fck",
524 .prcm = {
525 .omap2 = {
526 .module_offs = WKUP_MOD,
527 .idlest_reg_id = 1,
528 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
529 },
530 },
531 .class = &omap2xxx_gpio_hwmod_class,
532};
533
534/* mcspi1 */
535struct omap_hwmod omap2xxx_mcspi1_hwmod = {
536 .name = "mcspi1",
537 .main_clk = "mcspi1_fck",
538 .prcm = {
539 .omap2 = {
540 .module_offs = CORE_MOD,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
543 },
544 },
545 .class = &omap2xxx_mcspi_class,
546};
547
548/* mcspi2 */
549struct omap_hwmod omap2xxx_mcspi2_hwmod = {
550 .name = "mcspi2",
551 .main_clk = "mcspi2_fck",
552 .prcm = {
553 .omap2 = {
554 .module_offs = CORE_MOD,
555 .idlest_reg_id = 1,
556 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
557 },
558 },
559 .class = &omap2xxx_mcspi_class,
560};
561
562/* gpmc */
563struct omap_hwmod omap2xxx_gpmc_hwmod = {
564 .name = "gpmc",
565 .class = &omap2xxx_gpmc_hwmod_class,
566 .main_clk = "gpmc_fck",
567 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
568 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
569 .prcm = {
570 .omap2 = {
571 .module_offs = CORE_MOD,
572 },
573 },
574};
575
576/* RNG */
577
578static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
579 .rev_offs = 0x3c,
580 .sysc_offs = 0x40,
581 .syss_offs = 0x44,
582 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
583 SYSS_HAS_RESET_STATUS),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585};
586
587static struct omap_hwmod_class omap2_rng_hwmod_class = {
588 .name = "rng",
589 .sysc = &omap2_rng_sysc,
590};
591
592struct omap_hwmod omap2xxx_rng_hwmod = {
593 .name = "rng",
594 .main_clk = "l4_ck",
595 .prcm = {
596 .omap2 = {
597 .module_offs = CORE_MOD,
598 .idlest_reg_id = 4,
599 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
600 },
601 },
602 /*
603 * XXX The first read from the SYSSTATUS register of the RNG
604 * after the SYSCONFIG SOFTRESET bit is set triggers an
605 * imprecise external abort. It's unclear why this happens.
606 * Until this is analyzed, skip the IP block reset.
607 */
608 .flags = HWMOD_INIT_NO_RESET,
609 .class = &omap2_rng_hwmod_class,
610};
611
612/* SHAM */
613
614static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
615 .rev_offs = 0x5c,
616 .sysc_offs = 0x60,
617 .syss_offs = 0x64,
618 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
619 SYSS_HAS_RESET_STATUS),
620 .sysc_fields = &omap_hwmod_sysc_type1,
621};
622
623static struct omap_hwmod_class omap2xxx_sham_class = {
624 .name = "sham",
625 .sysc = &omap2_sham_sysc,
626};
627
628struct omap_hwmod omap2xxx_sham_hwmod = {
629 .name = "sham",
630 .main_clk = "l4_ck",
631 .prcm = {
632 .omap2 = {
633 .module_offs = CORE_MOD,
634 .idlest_reg_id = 4,
635 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
636 },
637 },
638 .class = &omap2xxx_sham_class,
639};
640
641/* AES */
642
643static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
644 .rev_offs = 0x44,
645 .sysc_offs = 0x48,
646 .syss_offs = 0x4c,
647 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
648 SYSS_HAS_RESET_STATUS),
649 .sysc_fields = &omap_hwmod_sysc_type1,
650};
651
652static struct omap_hwmod_class omap2xxx_aes_class = {
653 .name = "aes",
654 .sysc = &omap2_aes_sysc,
655};
656
657struct omap_hwmod omap2xxx_aes_hwmod = {
658 .name = "aes",
659 .main_clk = "l4_ck",
660 .prcm = {
661 .omap2 = {
662 .module_offs = CORE_MOD,
663 .idlest_reg_id = 4,
664 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
665 },
666 },
667 .class = &omap2xxx_aes_class,
668};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
7 */
8
9#include <linux/types.h>
10
11#include "omap_hwmod.h"
12#include "omap_hwmod_common_data.h"
13#include "cm-regbits-24xx.h"
14#include "prm-regbits-24xx.h"
15#include "wd_timer.h"
16
17/*
18 * 'dispc' class
19 * display controller
20 */
21
22static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
23 .rev_offs = 0x0000,
24 .sysc_offs = 0x0010,
25 .syss_offs = 0x0014,
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
31};
32
33static struct omap_hwmod_class omap2_dispc_hwmod_class = {
34 .name = "dispc",
35 .sysc = &omap2_dispc_sysc,
36};
37
38/* OMAP2xxx Timer Common */
39static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
40 .rev_offs = 0x0000,
41 .sysc_offs = 0x0010,
42 .syss_offs = 0x0014,
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
51 .name = "timer",
52 .sysc = &omap2xxx_timer_sysc,
53};
54
55/*
56 * 'wd_timer' class
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
58 * overflow condition
59 */
60
61static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
62 .rev_offs = 0x0000,
63 .sysc_offs = 0x0010,
64 .syss_offs = 0x0014,
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
68};
69
70static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
71 .name = "wd_timer",
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
75};
76
77/*
78 * 'gpio' class
79 * general purpose io module
80 */
81static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
90};
91
92struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
93 .name = "gpio",
94 .sysc = &omap2xxx_gpio_sysc,
95};
96
97/*
98 * 'mailbox' class
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
101 */
102
103static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
104 .rev_offs = 0x000,
105 .sysc_offs = 0x010,
106 .syss_offs = 0x014,
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
111};
112
113struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
114 .name = "mailbox",
115 .sysc = &omap2xxx_mailbox_sysc,
116};
117
118/*
119 * 'mcspi' class
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
121 * bus
122 */
123
124static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
125 .rev_offs = 0x0000,
126 .sysc_offs = 0x0010,
127 .syss_offs = 0x0014,
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
133};
134
135struct omap_hwmod_class omap2xxx_mcspi_class = {
136 .name = "mcspi",
137 .sysc = &omap2xxx_mcspi_sysc,
138};
139
140/*
141 * 'gpmc' class
142 * general purpose memory controller
143 */
144
145static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
146 .rev_offs = 0x0000,
147 .sysc_offs = 0x0010,
148 .syss_offs = 0x0014,
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
153};
154
155static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
156 .name = "gpmc",
157 .sysc = &omap2xxx_gpmc_sysc,
158};
159
160/*
161 * IP blocks
162 */
163
164/* L3 */
165struct omap_hwmod omap2xxx_l3_main_hwmod = {
166 .name = "l3_main",
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
169};
170
171/* L4 CORE */
172struct omap_hwmod omap2xxx_l4_core_hwmod = {
173 .name = "l4_core",
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
176};
177
178/* L4 WKUP */
179struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
180 .name = "l4_wkup",
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
183};
184
185/* MPU */
186struct omap_hwmod omap2xxx_mpu_hwmod = {
187 .name = "mpu",
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
190};
191
192/* timer3 */
193struct omap_hwmod omap2xxx_timer3_hwmod = {
194 .name = "timer3",
195 .main_clk = "gpt3_fck",
196 .prcm = {
197 .omap2 = {
198 .module_offs = CORE_MOD,
199 .idlest_reg_id = 1,
200 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
201 },
202 },
203 .class = &omap2xxx_timer_hwmod_class,
204 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
205};
206
207/* timer4 */
208struct omap_hwmod omap2xxx_timer4_hwmod = {
209 .name = "timer4",
210 .main_clk = "gpt4_fck",
211 .prcm = {
212 .omap2 = {
213 .module_offs = CORE_MOD,
214 .idlest_reg_id = 1,
215 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
216 },
217 },
218 .class = &omap2xxx_timer_hwmod_class,
219 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
220};
221
222/* timer5 */
223struct omap_hwmod omap2xxx_timer5_hwmod = {
224 .name = "timer5",
225 .main_clk = "gpt5_fck",
226 .prcm = {
227 .omap2 = {
228 .module_offs = CORE_MOD,
229 .idlest_reg_id = 1,
230 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
231 },
232 },
233 .class = &omap2xxx_timer_hwmod_class,
234 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
235};
236
237/* timer6 */
238struct omap_hwmod omap2xxx_timer6_hwmod = {
239 .name = "timer6",
240 .main_clk = "gpt6_fck",
241 .prcm = {
242 .omap2 = {
243 .module_offs = CORE_MOD,
244 .idlest_reg_id = 1,
245 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
246 },
247 },
248 .class = &omap2xxx_timer_hwmod_class,
249 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
250};
251
252/* timer7 */
253struct omap_hwmod omap2xxx_timer7_hwmod = {
254 .name = "timer7",
255 .main_clk = "gpt7_fck",
256 .prcm = {
257 .omap2 = {
258 .module_offs = CORE_MOD,
259 .idlest_reg_id = 1,
260 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
261 },
262 },
263 .class = &omap2xxx_timer_hwmod_class,
264 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
265};
266
267/* timer8 */
268struct omap_hwmod omap2xxx_timer8_hwmod = {
269 .name = "timer8",
270 .main_clk = "gpt8_fck",
271 .prcm = {
272 .omap2 = {
273 .module_offs = CORE_MOD,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
276 },
277 },
278 .class = &omap2xxx_timer_hwmod_class,
279 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
280};
281
282/* timer9 */
283struct omap_hwmod omap2xxx_timer9_hwmod = {
284 .name = "timer9",
285 .main_clk = "gpt9_fck",
286 .prcm = {
287 .omap2 = {
288 .module_offs = CORE_MOD,
289 .idlest_reg_id = 1,
290 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
291 },
292 },
293 .class = &omap2xxx_timer_hwmod_class,
294 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
295};
296
297/* timer10 */
298struct omap_hwmod omap2xxx_timer10_hwmod = {
299 .name = "timer10",
300 .main_clk = "gpt10_fck",
301 .prcm = {
302 .omap2 = {
303 .module_offs = CORE_MOD,
304 .idlest_reg_id = 1,
305 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
306 },
307 },
308 .class = &omap2xxx_timer_hwmod_class,
309 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
310};
311
312/* timer11 */
313struct omap_hwmod omap2xxx_timer11_hwmod = {
314 .name = "timer11",
315 .main_clk = "gpt11_fck",
316 .prcm = {
317 .omap2 = {
318 .module_offs = CORE_MOD,
319 .idlest_reg_id = 1,
320 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
321 },
322 },
323 .class = &omap2xxx_timer_hwmod_class,
324 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325};
326
327/* timer12 */
328struct omap_hwmod omap2xxx_timer12_hwmod = {
329 .name = "timer12",
330 .main_clk = "gpt12_fck",
331 .prcm = {
332 .omap2 = {
333 .module_offs = CORE_MOD,
334 .idlest_reg_id = 1,
335 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
336 },
337 },
338 .class = &omap2xxx_timer_hwmod_class,
339 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
340};
341
342/* wd_timer2 */
343struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
344 .name = "wd_timer2",
345 .class = &omap2xxx_wd_timer_hwmod_class,
346 .main_clk = "mpu_wdt_fck",
347 .prcm = {
348 .omap2 = {
349 .module_offs = WKUP_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
352 },
353 },
354};
355
356/* UART1 */
357
358struct omap_hwmod omap2xxx_uart1_hwmod = {
359 .name = "uart1",
360 .main_clk = "uart1_fck",
361 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
362 .prcm = {
363 .omap2 = {
364 .module_offs = CORE_MOD,
365 .idlest_reg_id = 1,
366 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
367 },
368 },
369 .class = &omap2_uart_class,
370};
371
372/* UART2 */
373
374struct omap_hwmod omap2xxx_uart2_hwmod = {
375 .name = "uart2",
376 .main_clk = "uart2_fck",
377 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
378 .prcm = {
379 .omap2 = {
380 .module_offs = CORE_MOD,
381 .idlest_reg_id = 1,
382 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
383 },
384 },
385 .class = &omap2_uart_class,
386};
387
388/* UART3 */
389
390struct omap_hwmod omap2xxx_uart3_hwmod = {
391 .name = "uart3",
392 .main_clk = "uart3_fck",
393 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
394 .prcm = {
395 .omap2 = {
396 .module_offs = CORE_MOD,
397 .idlest_reg_id = 2,
398 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
399 },
400 },
401 .class = &omap2_uart_class,
402};
403
404/* dss */
405
406static struct omap_hwmod_opt_clk dss_opt_clks[] = {
407 /*
408 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
409 * driver does not use these clocks.
410 */
411 { .role = "tv_clk", .clk = "dss_54m_fck" },
412 { .role = "sys_clk", .clk = "dss2_fck" },
413};
414
415struct omap_hwmod omap2xxx_dss_core_hwmod = {
416 .name = "dss_core",
417 .class = &omap2_dss_hwmod_class,
418 .main_clk = "dss1_fck", /* instead of dss_fck */
419 .prcm = {
420 .omap2 = {
421 .module_offs = CORE_MOD,
422 .idlest_reg_id = 1,
423 },
424 },
425 .opt_clks = dss_opt_clks,
426 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
427 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
428};
429
430struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
431 .name = "dss_dispc",
432 .class = &omap2_dispc_hwmod_class,
433 .main_clk = "dss1_fck",
434 .prcm = {
435 .omap2 = {
436 .module_offs = CORE_MOD,
437 .idlest_reg_id = 1,
438 },
439 },
440 .flags = HWMOD_NO_IDLEST,
441 .dev_attr = &omap2_3_dss_dispc_dev_attr,
442};
443
444static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
445 { .role = "ick", .clk = "dss_ick" },
446};
447
448struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
449 .name = "dss_rfbi",
450 .class = &omap2_rfbi_hwmod_class,
451 .main_clk = "dss1_fck",
452 .prcm = {
453 .omap2 = {
454 .module_offs = CORE_MOD,
455 },
456 },
457 .opt_clks = dss_rfbi_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
459 .flags = HWMOD_NO_IDLEST,
460};
461
462struct omap_hwmod omap2xxx_dss_venc_hwmod = {
463 .name = "dss_venc",
464 .class = &omap2_venc_hwmod_class,
465 .main_clk = "dss_54m_fck",
466 .prcm = {
467 .omap2 = {
468 .module_offs = CORE_MOD,
469 },
470 },
471 .flags = HWMOD_NO_IDLEST,
472};
473
474/* gpio1 */
475struct omap_hwmod omap2xxx_gpio1_hwmod = {
476 .name = "gpio1",
477 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
478 .main_clk = "gpios_fck",
479 .prcm = {
480 .omap2 = {
481 .module_offs = WKUP_MOD,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
484 },
485 },
486 .class = &omap2xxx_gpio_hwmod_class,
487};
488
489/* gpio2 */
490struct omap_hwmod omap2xxx_gpio2_hwmod = {
491 .name = "gpio2",
492 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
493 .main_clk = "gpios_fck",
494 .prcm = {
495 .omap2 = {
496 .module_offs = WKUP_MOD,
497 .idlest_reg_id = 1,
498 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
499 },
500 },
501 .class = &omap2xxx_gpio_hwmod_class,
502};
503
504/* gpio3 */
505struct omap_hwmod omap2xxx_gpio3_hwmod = {
506 .name = "gpio3",
507 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
508 .main_clk = "gpios_fck",
509 .prcm = {
510 .omap2 = {
511 .module_offs = WKUP_MOD,
512 .idlest_reg_id = 1,
513 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
514 },
515 },
516 .class = &omap2xxx_gpio_hwmod_class,
517};
518
519/* gpio4 */
520struct omap_hwmod omap2xxx_gpio4_hwmod = {
521 .name = "gpio4",
522 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
523 .main_clk = "gpios_fck",
524 .prcm = {
525 .omap2 = {
526 .module_offs = WKUP_MOD,
527 .idlest_reg_id = 1,
528 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
529 },
530 },
531 .class = &omap2xxx_gpio_hwmod_class,
532};
533
534/* mcspi1 */
535struct omap_hwmod omap2xxx_mcspi1_hwmod = {
536 .name = "mcspi1",
537 .main_clk = "mcspi1_fck",
538 .prcm = {
539 .omap2 = {
540 .module_offs = CORE_MOD,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
543 },
544 },
545 .class = &omap2xxx_mcspi_class,
546};
547
548/* mcspi2 */
549struct omap_hwmod omap2xxx_mcspi2_hwmod = {
550 .name = "mcspi2",
551 .main_clk = "mcspi2_fck",
552 .prcm = {
553 .omap2 = {
554 .module_offs = CORE_MOD,
555 .idlest_reg_id = 1,
556 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
557 },
558 },
559 .class = &omap2xxx_mcspi_class,
560};
561
562/* gpmc */
563struct omap_hwmod omap2xxx_gpmc_hwmod = {
564 .name = "gpmc",
565 .class = &omap2xxx_gpmc_hwmod_class,
566 .main_clk = "gpmc_fck",
567 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
568 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
569 .prcm = {
570 .omap2 = {
571 .module_offs = CORE_MOD,
572 },
573 },
574};
575
576/* RNG */
577
578static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
579 .rev_offs = 0x3c,
580 .sysc_offs = 0x40,
581 .syss_offs = 0x44,
582 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
583 SYSS_HAS_RESET_STATUS),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585};
586
587static struct omap_hwmod_class omap2_rng_hwmod_class = {
588 .name = "rng",
589 .sysc = &omap2_rng_sysc,
590};
591
592struct omap_hwmod omap2xxx_rng_hwmod = {
593 .name = "rng",
594 .main_clk = "l4_ck",
595 .prcm = {
596 .omap2 = {
597 .module_offs = CORE_MOD,
598 .idlest_reg_id = 4,
599 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
600 },
601 },
602 /*
603 * XXX The first read from the SYSSTATUS register of the RNG
604 * after the SYSCONFIG SOFTRESET bit is set triggers an
605 * imprecise external abort. It's unclear why this happens.
606 * Until this is analyzed, skip the IP block reset.
607 */
608 .flags = HWMOD_INIT_NO_RESET,
609 .class = &omap2_rng_hwmod_class,
610};
611
612/* SHAM */
613
614static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
615 .rev_offs = 0x5c,
616 .sysc_offs = 0x60,
617 .syss_offs = 0x64,
618 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
619 SYSS_HAS_RESET_STATUS),
620 .sysc_fields = &omap_hwmod_sysc_type1,
621};
622
623static struct omap_hwmod_class omap2xxx_sham_class = {
624 .name = "sham",
625 .sysc = &omap2_sham_sysc,
626};
627
628struct omap_hwmod omap2xxx_sham_hwmod = {
629 .name = "sham",
630 .main_clk = "l4_ck",
631 .prcm = {
632 .omap2 = {
633 .module_offs = CORE_MOD,
634 .idlest_reg_id = 4,
635 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
636 },
637 },
638 .class = &omap2xxx_sham_class,
639};
640
641/* AES */
642
643static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
644 .rev_offs = 0x44,
645 .sysc_offs = 0x48,
646 .syss_offs = 0x4c,
647 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
648 SYSS_HAS_RESET_STATUS),
649 .sysc_fields = &omap_hwmod_sysc_type1,
650};
651
652static struct omap_hwmod_class omap2xxx_aes_class = {
653 .name = "aes",
654 .sysc = &omap2_aes_sysc,
655};
656
657struct omap_hwmod omap2xxx_aes_hwmod = {
658 .name = "aes",
659 .main_clk = "l4_ck",
660 .prcm = {
661 .omap2 = {
662 .module_offs = CORE_MOD,
663 .idlest_reg_id = 4,
664 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
665 },
666 },
667 .class = &omap2xxx_aes_class,
668};