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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
7 */
8
9#include <linux/types.h>
10
11#include "omap_hwmod.h"
12#include "omap_hwmod_common_data.h"
13#include "cm-regbits-24xx.h"
14#include "prm-regbits-24xx.h"
15#include "wd_timer.h"
16
17/*
18 * 'dispc' class
19 * display controller
20 */
21
22static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
23 .rev_offs = 0x0000,
24 .sysc_offs = 0x0010,
25 .syss_offs = 0x0014,
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
31};
32
33static struct omap_hwmod_class omap2_dispc_hwmod_class = {
34 .name = "dispc",
35 .sysc = &omap2_dispc_sysc,
36};
37
38/* OMAP2xxx Timer Common */
39static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
40 .rev_offs = 0x0000,
41 .sysc_offs = 0x0010,
42 .syss_offs = 0x0014,
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
51 .name = "timer",
52 .sysc = &omap2xxx_timer_sysc,
53};
54
55/*
56 * 'wd_timer' class
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
58 * overflow condition
59 */
60
61static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
62 .rev_offs = 0x0000,
63 .sysc_offs = 0x0010,
64 .syss_offs = 0x0014,
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
68};
69
70static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
71 .name = "wd_timer",
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
75};
76
77/*
78 * 'gpio' class
79 * general purpose io module
80 */
81static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
90};
91
92struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
93 .name = "gpio",
94 .sysc = &omap2xxx_gpio_sysc,
95};
96
97/*
98 * 'mailbox' class
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
101 */
102
103static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
104 .rev_offs = 0x000,
105 .sysc_offs = 0x010,
106 .syss_offs = 0x014,
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
111};
112
113struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
114 .name = "mailbox",
115 .sysc = &omap2xxx_mailbox_sysc,
116};
117
118/*
119 * 'mcspi' class
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
121 * bus
122 */
123
124static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
125 .rev_offs = 0x0000,
126 .sysc_offs = 0x0010,
127 .syss_offs = 0x0014,
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
133};
134
135struct omap_hwmod_class omap2xxx_mcspi_class = {
136 .name = "mcspi",
137 .sysc = &omap2xxx_mcspi_sysc,
138};
139
140/*
141 * 'gpmc' class
142 * general purpose memory controller
143 */
144
145static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
146 .rev_offs = 0x0000,
147 .sysc_offs = 0x0010,
148 .syss_offs = 0x0014,
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
153};
154
155static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
156 .name = "gpmc",
157 .sysc = &omap2xxx_gpmc_sysc,
158};
159
160/*
161 * IP blocks
162 */
163
164/* L3 */
165struct omap_hwmod omap2xxx_l3_main_hwmod = {
166 .name = "l3_main",
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
169};
170
171/* L4 CORE */
172struct omap_hwmod omap2xxx_l4_core_hwmod = {
173 .name = "l4_core",
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
176};
177
178/* L4 WKUP */
179struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
180 .name = "l4_wkup",
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
183};
184
185/* MPU */
186struct omap_hwmod omap2xxx_mpu_hwmod = {
187 .name = "mpu",
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
190};
191
192/* timer3 */
193struct omap_hwmod omap2xxx_timer3_hwmod = {
194 .name = "timer3",
195 .main_clk = "gpt3_fck",
196 .prcm = {
197 .omap2 = {
198 .module_offs = CORE_MOD,
199 .idlest_reg_id = 1,
200 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
201 },
202 },
203 .class = &omap2xxx_timer_hwmod_class,
204 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
205};
206
207/* timer4 */
208struct omap_hwmod omap2xxx_timer4_hwmod = {
209 .name = "timer4",
210 .main_clk = "gpt4_fck",
211 .prcm = {
212 .omap2 = {
213 .module_offs = CORE_MOD,
214 .idlest_reg_id = 1,
215 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
216 },
217 },
218 .class = &omap2xxx_timer_hwmod_class,
219 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
220};
221
222/* timer5 */
223struct omap_hwmod omap2xxx_timer5_hwmod = {
224 .name = "timer5",
225 .main_clk = "gpt5_fck",
226 .prcm = {
227 .omap2 = {
228 .module_offs = CORE_MOD,
229 .idlest_reg_id = 1,
230 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
231 },
232 },
233 .class = &omap2xxx_timer_hwmod_class,
234 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
235};
236
237/* timer6 */
238struct omap_hwmod omap2xxx_timer6_hwmod = {
239 .name = "timer6",
240 .main_clk = "gpt6_fck",
241 .prcm = {
242 .omap2 = {
243 .module_offs = CORE_MOD,
244 .idlest_reg_id = 1,
245 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
246 },
247 },
248 .class = &omap2xxx_timer_hwmod_class,
249 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
250};
251
252/* timer7 */
253struct omap_hwmod omap2xxx_timer7_hwmod = {
254 .name = "timer7",
255 .main_clk = "gpt7_fck",
256 .prcm = {
257 .omap2 = {
258 .module_offs = CORE_MOD,
259 .idlest_reg_id = 1,
260 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
261 },
262 },
263 .class = &omap2xxx_timer_hwmod_class,
264 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
265};
266
267/* timer8 */
268struct omap_hwmod omap2xxx_timer8_hwmod = {
269 .name = "timer8",
270 .main_clk = "gpt8_fck",
271 .prcm = {
272 .omap2 = {
273 .module_offs = CORE_MOD,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
276 },
277 },
278 .class = &omap2xxx_timer_hwmod_class,
279 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
280};
281
282/* timer9 */
283struct omap_hwmod omap2xxx_timer9_hwmod = {
284 .name = "timer9",
285 .main_clk = "gpt9_fck",
286 .prcm = {
287 .omap2 = {
288 .module_offs = CORE_MOD,
289 .idlest_reg_id = 1,
290 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
291 },
292 },
293 .class = &omap2xxx_timer_hwmod_class,
294 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
295};
296
297/* timer10 */
298struct omap_hwmod omap2xxx_timer10_hwmod = {
299 .name = "timer10",
300 .main_clk = "gpt10_fck",
301 .prcm = {
302 .omap2 = {
303 .module_offs = CORE_MOD,
304 .idlest_reg_id = 1,
305 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
306 },
307 },
308 .class = &omap2xxx_timer_hwmod_class,
309 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
310};
311
312/* timer11 */
313struct omap_hwmod omap2xxx_timer11_hwmod = {
314 .name = "timer11",
315 .main_clk = "gpt11_fck",
316 .prcm = {
317 .omap2 = {
318 .module_offs = CORE_MOD,
319 .idlest_reg_id = 1,
320 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
321 },
322 },
323 .class = &omap2xxx_timer_hwmod_class,
324 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325};
326
327/* timer12 */
328struct omap_hwmod omap2xxx_timer12_hwmod = {
329 .name = "timer12",
330 .main_clk = "gpt12_fck",
331 .prcm = {
332 .omap2 = {
333 .module_offs = CORE_MOD,
334 .idlest_reg_id = 1,
335 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
336 },
337 },
338 .class = &omap2xxx_timer_hwmod_class,
339 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
340};
341
342/* wd_timer2 */
343struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
344 .name = "wd_timer2",
345 .class = &omap2xxx_wd_timer_hwmod_class,
346 .main_clk = "mpu_wdt_fck",
347 .prcm = {
348 .omap2 = {
349 .module_offs = WKUP_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
352 },
353 },
354};
355
356/* UART1 */
357
358struct omap_hwmod omap2xxx_uart1_hwmod = {
359 .name = "uart1",
360 .main_clk = "uart1_fck",
361 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
362 .prcm = {
363 .omap2 = {
364 .module_offs = CORE_MOD,
365 .idlest_reg_id = 1,
366 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
367 },
368 },
369 .class = &omap2_uart_class,
370};
371
372/* UART2 */
373
374struct omap_hwmod omap2xxx_uart2_hwmod = {
375 .name = "uart2",
376 .main_clk = "uart2_fck",
377 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
378 .prcm = {
379 .omap2 = {
380 .module_offs = CORE_MOD,
381 .idlest_reg_id = 1,
382 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
383 },
384 },
385 .class = &omap2_uart_class,
386};
387
388/* UART3 */
389
390struct omap_hwmod omap2xxx_uart3_hwmod = {
391 .name = "uart3",
392 .main_clk = "uart3_fck",
393 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
394 .prcm = {
395 .omap2 = {
396 .module_offs = CORE_MOD,
397 .idlest_reg_id = 2,
398 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
399 },
400 },
401 .class = &omap2_uart_class,
402};
403
404/* dss */
405
406static struct omap_hwmod_opt_clk dss_opt_clks[] = {
407 /*
408 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
409 * driver does not use these clocks.
410 */
411 { .role = "tv_clk", .clk = "dss_54m_fck" },
412 { .role = "sys_clk", .clk = "dss2_fck" },
413};
414
415struct omap_hwmod omap2xxx_dss_core_hwmod = {
416 .name = "dss_core",
417 .class = &omap2_dss_hwmod_class,
418 .main_clk = "dss1_fck", /* instead of dss_fck */
419 .prcm = {
420 .omap2 = {
421 .module_offs = CORE_MOD,
422 .idlest_reg_id = 1,
423 },
424 },
425 .opt_clks = dss_opt_clks,
426 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
427 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
428};
429
430struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
431 .name = "dss_dispc",
432 .class = &omap2_dispc_hwmod_class,
433 .main_clk = "dss1_fck",
434 .prcm = {
435 .omap2 = {
436 .module_offs = CORE_MOD,
437 .idlest_reg_id = 1,
438 },
439 },
440 .flags = HWMOD_NO_IDLEST,
441 .dev_attr = &omap2_3_dss_dispc_dev_attr,
442};
443
444static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
445 { .role = "ick", .clk = "dss_ick" },
446};
447
448struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
449 .name = "dss_rfbi",
450 .class = &omap2_rfbi_hwmod_class,
451 .main_clk = "dss1_fck",
452 .prcm = {
453 .omap2 = {
454 .module_offs = CORE_MOD,
455 },
456 },
457 .opt_clks = dss_rfbi_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
459 .flags = HWMOD_NO_IDLEST,
460};
461
462struct omap_hwmod omap2xxx_dss_venc_hwmod = {
463 .name = "dss_venc",
464 .class = &omap2_venc_hwmod_class,
465 .main_clk = "dss_54m_fck",
466 .prcm = {
467 .omap2 = {
468 .module_offs = CORE_MOD,
469 },
470 },
471 .flags = HWMOD_NO_IDLEST,
472};
473
474/* gpio1 */
475struct omap_hwmod omap2xxx_gpio1_hwmod = {
476 .name = "gpio1",
477 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
478 .main_clk = "gpios_fck",
479 .prcm = {
480 .omap2 = {
481 .module_offs = WKUP_MOD,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
484 },
485 },
486 .class = &omap2xxx_gpio_hwmod_class,
487};
488
489/* gpio2 */
490struct omap_hwmod omap2xxx_gpio2_hwmod = {
491 .name = "gpio2",
492 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
493 .main_clk = "gpios_fck",
494 .prcm = {
495 .omap2 = {
496 .module_offs = WKUP_MOD,
497 .idlest_reg_id = 1,
498 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
499 },
500 },
501 .class = &omap2xxx_gpio_hwmod_class,
502};
503
504/* gpio3 */
505struct omap_hwmod omap2xxx_gpio3_hwmod = {
506 .name = "gpio3",
507 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
508 .main_clk = "gpios_fck",
509 .prcm = {
510 .omap2 = {
511 .module_offs = WKUP_MOD,
512 .idlest_reg_id = 1,
513 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
514 },
515 },
516 .class = &omap2xxx_gpio_hwmod_class,
517};
518
519/* gpio4 */
520struct omap_hwmod omap2xxx_gpio4_hwmod = {
521 .name = "gpio4",
522 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
523 .main_clk = "gpios_fck",
524 .prcm = {
525 .omap2 = {
526 .module_offs = WKUP_MOD,
527 .idlest_reg_id = 1,
528 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
529 },
530 },
531 .class = &omap2xxx_gpio_hwmod_class,
532};
533
534/* mcspi1 */
535struct omap_hwmod omap2xxx_mcspi1_hwmod = {
536 .name = "mcspi1",
537 .main_clk = "mcspi1_fck",
538 .prcm = {
539 .omap2 = {
540 .module_offs = CORE_MOD,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
543 },
544 },
545 .class = &omap2xxx_mcspi_class,
546};
547
548/* mcspi2 */
549struct omap_hwmod omap2xxx_mcspi2_hwmod = {
550 .name = "mcspi2",
551 .main_clk = "mcspi2_fck",
552 .prcm = {
553 .omap2 = {
554 .module_offs = CORE_MOD,
555 .idlest_reg_id = 1,
556 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
557 },
558 },
559 .class = &omap2xxx_mcspi_class,
560};
561
562/* gpmc */
563struct omap_hwmod omap2xxx_gpmc_hwmod = {
564 .name = "gpmc",
565 .class = &omap2xxx_gpmc_hwmod_class,
566 .main_clk = "gpmc_fck",
567 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
568 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
569 .prcm = {
570 .omap2 = {
571 .module_offs = CORE_MOD,
572 },
573 },
574};
575
576/* RNG */
577
578static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
579 .rev_offs = 0x3c,
580 .sysc_offs = 0x40,
581 .syss_offs = 0x44,
582 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
583 SYSS_HAS_RESET_STATUS),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585};
586
587static struct omap_hwmod_class omap2_rng_hwmod_class = {
588 .name = "rng",
589 .sysc = &omap2_rng_sysc,
590};
591
592struct omap_hwmod omap2xxx_rng_hwmod = {
593 .name = "rng",
594 .main_clk = "l4_ck",
595 .prcm = {
596 .omap2 = {
597 .module_offs = CORE_MOD,
598 .idlest_reg_id = 4,
599 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
600 },
601 },
602 /*
603 * XXX The first read from the SYSSTATUS register of the RNG
604 * after the SYSCONFIG SOFTRESET bit is set triggers an
605 * imprecise external abort. It's unclear why this happens.
606 * Until this is analyzed, skip the IP block reset.
607 */
608 .flags = HWMOD_INIT_NO_RESET,
609 .class = &omap2_rng_hwmod_class,
610};
611
612/* SHAM */
613
614static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
615 .rev_offs = 0x5c,
616 .sysc_offs = 0x60,
617 .syss_offs = 0x64,
618 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
619 SYSS_HAS_RESET_STATUS),
620 .sysc_fields = &omap_hwmod_sysc_type1,
621};
622
623static struct omap_hwmod_class omap2xxx_sham_class = {
624 .name = "sham",
625 .sysc = &omap2_sham_sysc,
626};
627
628struct omap_hwmod omap2xxx_sham_hwmod = {
629 .name = "sham",
630 .main_clk = "l4_ck",
631 .prcm = {
632 .omap2 = {
633 .module_offs = CORE_MOD,
634 .idlest_reg_id = 4,
635 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
636 },
637 },
638 .class = &omap2xxx_sham_class,
639};
640
641/* AES */
642
643static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
644 .rev_offs = 0x44,
645 .sysc_offs = 0x48,
646 .syss_offs = 0x4c,
647 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
648 SYSS_HAS_RESET_STATUS),
649 .sysc_fields = &omap_hwmod_sysc_type1,
650};
651
652static struct omap_hwmod_class omap2xxx_aes_class = {
653 .name = "aes",
654 .sysc = &omap2_aes_sysc,
655};
656
657struct omap_hwmod omap2xxx_aes_hwmod = {
658 .name = "aes",
659 .main_clk = "l4_ck",
660 .prcm = {
661 .omap2 = {
662 .module_offs = CORE_MOD,
663 .idlest_reg_id = 4,
664 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
665 },
666 },
667 .class = &omap2xxx_aes_class,
668};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
7 */
8
9#include <linux/types.h>
10#include <linux/omap-dma.h>
11
12#include "omap_hwmod.h"
13#include "omap_hwmod_common_data.h"
14#include "cm-regbits-24xx.h"
15#include "prm-regbits-24xx.h"
16#include "wd_timer.h"
17
18/*
19 * 'dispc' class
20 * display controller
21 */
22
23static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
24 .rev_offs = 0x0000,
25 .sysc_offs = 0x0010,
26 .syss_offs = 0x0014,
27 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
28 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
29 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
30 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
31 .sysc_fields = &omap_hwmod_sysc_type1,
32};
33
34struct omap_hwmod_class omap2_dispc_hwmod_class = {
35 .name = "dispc",
36 .sysc = &omap2_dispc_sysc,
37};
38
39/* OMAP2xxx Timer Common */
40static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
41 .rev_offs = 0x0000,
42 .sysc_offs = 0x0010,
43 .syss_offs = 0x0014,
44 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
45 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
46 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
47 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
49};
50
51struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
52 .name = "timer",
53 .sysc = &omap2xxx_timer_sysc,
54};
55
56/*
57 * 'wd_timer' class
58 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
59 * overflow condition
60 */
61
62static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
63 .rev_offs = 0x0000,
64 .sysc_offs = 0x0010,
65 .syss_offs = 0x0014,
66 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
67 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
68 .sysc_fields = &omap_hwmod_sysc_type1,
69};
70
71struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
72 .name = "wd_timer",
73 .sysc = &omap2xxx_wd_timer_sysc,
74 .pre_shutdown = &omap2_wd_timer_disable,
75 .reset = &omap2_wd_timer_reset,
76};
77
78/*
79 * 'gpio' class
80 * general purpose io module
81 */
82static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
83 .rev_offs = 0x0000,
84 .sysc_offs = 0x0010,
85 .syss_offs = 0x0014,
86 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
87 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
88 SYSS_HAS_RESET_STATUS),
89 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90 .sysc_fields = &omap_hwmod_sysc_type1,
91};
92
93struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
94 .name = "gpio",
95 .sysc = &omap2xxx_gpio_sysc,
96};
97
98/* system dma */
99static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
100 .rev_offs = 0x0000,
101 .sysc_offs = 0x002c,
102 .syss_offs = 0x0028,
103 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
104 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
105 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
106 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
107 .sysc_fields = &omap_hwmod_sysc_type1,
108};
109
110struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
111 .name = "dma",
112 .sysc = &omap2xxx_dma_sysc,
113};
114
115/*
116 * 'mailbox' class
117 * mailbox module allowing communication between the on-chip processors
118 * using a queued mailbox-interrupt mechanism.
119 */
120
121static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
122 .rev_offs = 0x000,
123 .sysc_offs = 0x010,
124 .syss_offs = 0x014,
125 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
126 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
128 .sysc_fields = &omap_hwmod_sysc_type1,
129};
130
131struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
132 .name = "mailbox",
133 .sysc = &omap2xxx_mailbox_sysc,
134};
135
136/*
137 * 'mcspi' class
138 * multichannel serial port interface (mcspi) / master/slave synchronous serial
139 * bus
140 */
141
142static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
143 .rev_offs = 0x0000,
144 .sysc_offs = 0x0010,
145 .syss_offs = 0x0014,
146 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
147 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
148 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
150 .sysc_fields = &omap_hwmod_sysc_type1,
151};
152
153struct omap_hwmod_class omap2xxx_mcspi_class = {
154 .name = "mcspi",
155 .sysc = &omap2xxx_mcspi_sysc,
156};
157
158/*
159 * 'gpmc' class
160 * general purpose memory controller
161 */
162
163static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
164 .rev_offs = 0x0000,
165 .sysc_offs = 0x0010,
166 .syss_offs = 0x0014,
167 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
168 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
169 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
170 .sysc_fields = &omap_hwmod_sysc_type1,
171};
172
173static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
174 .name = "gpmc",
175 .sysc = &omap2xxx_gpmc_sysc,
176};
177
178/*
179 * IP blocks
180 */
181
182/* L3 */
183struct omap_hwmod omap2xxx_l3_main_hwmod = {
184 .name = "l3_main",
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
187};
188
189/* L4 CORE */
190struct omap_hwmod omap2xxx_l4_core_hwmod = {
191 .name = "l4_core",
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
194};
195
196/* L4 WKUP */
197struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
198 .name = "l4_wkup",
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
201};
202
203/* MPU */
204struct omap_hwmod omap2xxx_mpu_hwmod = {
205 .name = "mpu",
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
208};
209
210/* IVA2 */
211struct omap_hwmod omap2xxx_iva_hwmod = {
212 .name = "iva",
213 .class = &iva_hwmod_class,
214};
215
216/* timer1 */
217struct omap_hwmod omap2xxx_timer1_hwmod = {
218 .name = "timer1",
219 .main_clk = "gpt1_fck",
220 .prcm = {
221 .omap2 = {
222 .module_offs = WKUP_MOD,
223 .idlest_reg_id = 1,
224 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
225 },
226 },
227 .class = &omap2xxx_timer_hwmod_class,
228 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
229};
230
231/* timer2 */
232struct omap_hwmod omap2xxx_timer2_hwmod = {
233 .name = "timer2",
234 .main_clk = "gpt2_fck",
235 .prcm = {
236 .omap2 = {
237 .module_offs = CORE_MOD,
238 .idlest_reg_id = 1,
239 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
240 },
241 },
242 .class = &omap2xxx_timer_hwmod_class,
243 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
244};
245
246/* timer3 */
247struct omap_hwmod omap2xxx_timer3_hwmod = {
248 .name = "timer3",
249 .main_clk = "gpt3_fck",
250 .prcm = {
251 .omap2 = {
252 .module_offs = CORE_MOD,
253 .idlest_reg_id = 1,
254 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
255 },
256 },
257 .class = &omap2xxx_timer_hwmod_class,
258 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
259};
260
261/* timer4 */
262struct omap_hwmod omap2xxx_timer4_hwmod = {
263 .name = "timer4",
264 .main_clk = "gpt4_fck",
265 .prcm = {
266 .omap2 = {
267 .module_offs = CORE_MOD,
268 .idlest_reg_id = 1,
269 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
270 },
271 },
272 .class = &omap2xxx_timer_hwmod_class,
273 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
274};
275
276/* timer5 */
277struct omap_hwmod omap2xxx_timer5_hwmod = {
278 .name = "timer5",
279 .main_clk = "gpt5_fck",
280 .prcm = {
281 .omap2 = {
282 .module_offs = CORE_MOD,
283 .idlest_reg_id = 1,
284 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
285 },
286 },
287 .class = &omap2xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289};
290
291/* timer6 */
292struct omap_hwmod omap2xxx_timer6_hwmod = {
293 .name = "timer6",
294 .main_clk = "gpt6_fck",
295 .prcm = {
296 .omap2 = {
297 .module_offs = CORE_MOD,
298 .idlest_reg_id = 1,
299 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
300 },
301 },
302 .class = &omap2xxx_timer_hwmod_class,
303 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
304};
305
306/* timer7 */
307struct omap_hwmod omap2xxx_timer7_hwmod = {
308 .name = "timer7",
309 .main_clk = "gpt7_fck",
310 .prcm = {
311 .omap2 = {
312 .module_offs = CORE_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
315 },
316 },
317 .class = &omap2xxx_timer_hwmod_class,
318 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
319};
320
321/* timer8 */
322struct omap_hwmod omap2xxx_timer8_hwmod = {
323 .name = "timer8",
324 .main_clk = "gpt8_fck",
325 .prcm = {
326 .omap2 = {
327 .module_offs = CORE_MOD,
328 .idlest_reg_id = 1,
329 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
330 },
331 },
332 .class = &omap2xxx_timer_hwmod_class,
333 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
334};
335
336/* timer9 */
337struct omap_hwmod omap2xxx_timer9_hwmod = {
338 .name = "timer9",
339 .main_clk = "gpt9_fck",
340 .prcm = {
341 .omap2 = {
342 .module_offs = CORE_MOD,
343 .idlest_reg_id = 1,
344 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
345 },
346 },
347 .class = &omap2xxx_timer_hwmod_class,
348 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
349};
350
351/* timer10 */
352struct omap_hwmod omap2xxx_timer10_hwmod = {
353 .name = "timer10",
354 .main_clk = "gpt10_fck",
355 .prcm = {
356 .omap2 = {
357 .module_offs = CORE_MOD,
358 .idlest_reg_id = 1,
359 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
360 },
361 },
362 .class = &omap2xxx_timer_hwmod_class,
363 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
364};
365
366/* timer11 */
367struct omap_hwmod omap2xxx_timer11_hwmod = {
368 .name = "timer11",
369 .main_clk = "gpt11_fck",
370 .prcm = {
371 .omap2 = {
372 .module_offs = CORE_MOD,
373 .idlest_reg_id = 1,
374 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
375 },
376 },
377 .class = &omap2xxx_timer_hwmod_class,
378 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
379};
380
381/* timer12 */
382struct omap_hwmod omap2xxx_timer12_hwmod = {
383 .name = "timer12",
384 .main_clk = "gpt12_fck",
385 .prcm = {
386 .omap2 = {
387 .module_offs = CORE_MOD,
388 .idlest_reg_id = 1,
389 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
390 },
391 },
392 .class = &omap2xxx_timer_hwmod_class,
393 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
394};
395
396/* wd_timer2 */
397struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
398 .name = "wd_timer2",
399 .class = &omap2xxx_wd_timer_hwmod_class,
400 .main_clk = "mpu_wdt_fck",
401 .prcm = {
402 .omap2 = {
403 .module_offs = WKUP_MOD,
404 .idlest_reg_id = 1,
405 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
406 },
407 },
408};
409
410/* UART1 */
411
412struct omap_hwmod omap2xxx_uart1_hwmod = {
413 .name = "uart1",
414 .main_clk = "uart1_fck",
415 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
416 .prcm = {
417 .omap2 = {
418 .module_offs = CORE_MOD,
419 .idlest_reg_id = 1,
420 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
421 },
422 },
423 .class = &omap2_uart_class,
424};
425
426/* UART2 */
427
428struct omap_hwmod omap2xxx_uart2_hwmod = {
429 .name = "uart2",
430 .main_clk = "uart2_fck",
431 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
432 .prcm = {
433 .omap2 = {
434 .module_offs = CORE_MOD,
435 .idlest_reg_id = 1,
436 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
437 },
438 },
439 .class = &omap2_uart_class,
440};
441
442/* UART3 */
443
444struct omap_hwmod omap2xxx_uart3_hwmod = {
445 .name = "uart3",
446 .main_clk = "uart3_fck",
447 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
448 .prcm = {
449 .omap2 = {
450 .module_offs = CORE_MOD,
451 .idlest_reg_id = 2,
452 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
453 },
454 },
455 .class = &omap2_uart_class,
456};
457
458/* dss */
459
460static struct omap_hwmod_opt_clk dss_opt_clks[] = {
461 /*
462 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
463 * driver does not use these clocks.
464 */
465 { .role = "tv_clk", .clk = "dss_54m_fck" },
466 { .role = "sys_clk", .clk = "dss2_fck" },
467};
468
469struct omap_hwmod omap2xxx_dss_core_hwmod = {
470 .name = "dss_core",
471 .class = &omap2_dss_hwmod_class,
472 .main_clk = "dss1_fck", /* instead of dss_fck */
473 .prcm = {
474 .omap2 = {
475 .module_offs = CORE_MOD,
476 .idlest_reg_id = 1,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
482};
483
484struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
485 .name = "dss_dispc",
486 .class = &omap2_dispc_hwmod_class,
487 .main_clk = "dss1_fck",
488 .prcm = {
489 .omap2 = {
490 .module_offs = CORE_MOD,
491 .idlest_reg_id = 1,
492 },
493 },
494 .flags = HWMOD_NO_IDLEST,
495 .dev_attr = &omap2_3_dss_dispc_dev_attr,
496};
497
498static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
499 { .role = "ick", .clk = "dss_ick" },
500};
501
502struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
503 .name = "dss_rfbi",
504 .class = &omap2_rfbi_hwmod_class,
505 .main_clk = "dss1_fck",
506 .prcm = {
507 .omap2 = {
508 .module_offs = CORE_MOD,
509 },
510 },
511 .opt_clks = dss_rfbi_opt_clks,
512 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
513 .flags = HWMOD_NO_IDLEST,
514};
515
516struct omap_hwmod omap2xxx_dss_venc_hwmod = {
517 .name = "dss_venc",
518 .class = &omap2_venc_hwmod_class,
519 .main_clk = "dss_54m_fck",
520 .prcm = {
521 .omap2 = {
522 .module_offs = CORE_MOD,
523 },
524 },
525 .flags = HWMOD_NO_IDLEST,
526};
527
528/* gpio1 */
529struct omap_hwmod omap2xxx_gpio1_hwmod = {
530 .name = "gpio1",
531 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
532 .main_clk = "gpios_fck",
533 .prcm = {
534 .omap2 = {
535 .module_offs = WKUP_MOD,
536 .idlest_reg_id = 1,
537 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
538 },
539 },
540 .class = &omap2xxx_gpio_hwmod_class,
541};
542
543/* gpio2 */
544struct omap_hwmod omap2xxx_gpio2_hwmod = {
545 .name = "gpio2",
546 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
547 .main_clk = "gpios_fck",
548 .prcm = {
549 .omap2 = {
550 .module_offs = WKUP_MOD,
551 .idlest_reg_id = 1,
552 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
553 },
554 },
555 .class = &omap2xxx_gpio_hwmod_class,
556};
557
558/* gpio3 */
559struct omap_hwmod omap2xxx_gpio3_hwmod = {
560 .name = "gpio3",
561 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
562 .main_clk = "gpios_fck",
563 .prcm = {
564 .omap2 = {
565 .module_offs = WKUP_MOD,
566 .idlest_reg_id = 1,
567 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
568 },
569 },
570 .class = &omap2xxx_gpio_hwmod_class,
571};
572
573/* gpio4 */
574struct omap_hwmod omap2xxx_gpio4_hwmod = {
575 .name = "gpio4",
576 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
577 .main_clk = "gpios_fck",
578 .prcm = {
579 .omap2 = {
580 .module_offs = WKUP_MOD,
581 .idlest_reg_id = 1,
582 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
583 },
584 },
585 .class = &omap2xxx_gpio_hwmod_class,
586};
587
588/* mcspi1 */
589struct omap_hwmod omap2xxx_mcspi1_hwmod = {
590 .name = "mcspi1",
591 .main_clk = "mcspi1_fck",
592 .prcm = {
593 .omap2 = {
594 .module_offs = CORE_MOD,
595 .idlest_reg_id = 1,
596 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
597 },
598 },
599 .class = &omap2xxx_mcspi_class,
600};
601
602/* mcspi2 */
603struct omap_hwmod omap2xxx_mcspi2_hwmod = {
604 .name = "mcspi2",
605 .main_clk = "mcspi2_fck",
606 .prcm = {
607 .omap2 = {
608 .module_offs = CORE_MOD,
609 .idlest_reg_id = 1,
610 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
611 },
612 },
613 .class = &omap2xxx_mcspi_class,
614};
615
616static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
617 .name = "counter",
618};
619
620struct omap_hwmod omap2xxx_counter_32k_hwmod = {
621 .name = "counter_32k",
622 .main_clk = "func_32k_ck",
623 .prcm = {
624 .omap2 = {
625 .module_offs = WKUP_MOD,
626 .idlest_reg_id = 1,
627 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
628 },
629 },
630 .class = &omap2xxx_counter_hwmod_class,
631};
632
633/* gpmc */
634struct omap_hwmod omap2xxx_gpmc_hwmod = {
635 .name = "gpmc",
636 .class = &omap2xxx_gpmc_hwmod_class,
637 .main_clk = "gpmc_fck",
638 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
639 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
640 .prcm = {
641 .omap2 = {
642 .module_offs = CORE_MOD,
643 },
644 },
645};
646
647/* RNG */
648
649static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
650 .rev_offs = 0x3c,
651 .sysc_offs = 0x40,
652 .syss_offs = 0x44,
653 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
654 SYSS_HAS_RESET_STATUS),
655 .sysc_fields = &omap_hwmod_sysc_type1,
656};
657
658static struct omap_hwmod_class omap2_rng_hwmod_class = {
659 .name = "rng",
660 .sysc = &omap2_rng_sysc,
661};
662
663struct omap_hwmod omap2xxx_rng_hwmod = {
664 .name = "rng",
665 .main_clk = "l4_ck",
666 .prcm = {
667 .omap2 = {
668 .module_offs = CORE_MOD,
669 .idlest_reg_id = 4,
670 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
671 },
672 },
673 /*
674 * XXX The first read from the SYSSTATUS register of the RNG
675 * after the SYSCONFIG SOFTRESET bit is set triggers an
676 * imprecise external abort. It's unclear why this happens.
677 * Until this is analyzed, skip the IP block reset.
678 */
679 .flags = HWMOD_INIT_NO_RESET,
680 .class = &omap2_rng_hwmod_class,
681};
682
683/* SHAM */
684
685static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
686 .rev_offs = 0x5c,
687 .sysc_offs = 0x60,
688 .syss_offs = 0x64,
689 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
690 SYSS_HAS_RESET_STATUS),
691 .sysc_fields = &omap_hwmod_sysc_type1,
692};
693
694static struct omap_hwmod_class omap2xxx_sham_class = {
695 .name = "sham",
696 .sysc = &omap2_sham_sysc,
697};
698
699struct omap_hwmod omap2xxx_sham_hwmod = {
700 .name = "sham",
701 .main_clk = "l4_ck",
702 .prcm = {
703 .omap2 = {
704 .module_offs = CORE_MOD,
705 .idlest_reg_id = 4,
706 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
707 },
708 },
709 .class = &omap2xxx_sham_class,
710};
711
712/* AES */
713
714static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
715 .rev_offs = 0x44,
716 .sysc_offs = 0x48,
717 .syss_offs = 0x4c,
718 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
719 SYSS_HAS_RESET_STATUS),
720 .sysc_fields = &omap_hwmod_sysc_type1,
721};
722
723static struct omap_hwmod_class omap2xxx_aes_class = {
724 .name = "aes",
725 .sysc = &omap2_aes_sysc,
726};
727
728struct omap_hwmod omap2xxx_aes_hwmod = {
729 .name = "aes",
730 .main_clk = "l4_ck",
731 .prcm = {
732 .omap2 = {
733 .module_offs = CORE_MOD,
734 .idlest_reg_id = 4,
735 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
736 },
737 },
738 .class = &omap2xxx_aes_class,
739};