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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G2L WDT Watchdog Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 */
7#include <linux/bitops.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pm_domain.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18#include <linux/units.h>
19#include <linux/watchdog.h>
20
21#define WDTCNT 0x00
22#define WDTSET 0x04
23#define WDTTIM 0x08
24#define WDTINT 0x0C
25#define PECR 0x10
26#define PEEN 0x14
27#define WDTCNT_WDTEN BIT(0)
28#define WDTINT_INTDISP BIT(0)
29#define PEEN_FORCE BIT(0)
30
31#define WDT_DEFAULT_TIMEOUT 60U
32
33/* Setting period time register only 12 bit set in WDTSET[31:20] */
34#define WDTSET_COUNTER_MASK (0xFFF00000)
35#define WDTSET_COUNTER_VAL(f) ((f) << 20)
36
37#define F2CYCLE_NSEC(f) (1000000000 / (f))
38
39#define RZV2M_A_NSEC 730
40
41static bool nowayout = WATCHDOG_NOWAYOUT;
42module_param(nowayout, bool, 0);
43MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
44 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
45
46enum rz_wdt_type {
47 WDT_RZG2L,
48 WDT_RZV2M,
49};
50
51struct rzg2l_wdt_priv {
52 void __iomem *base;
53 struct watchdog_device wdev;
54 struct reset_control *rstc;
55 unsigned long osc_clk_rate;
56 unsigned long delay;
57 struct clk *pclk;
58 struct clk *osc_clk;
59 enum rz_wdt_type devtype;
60};
61
62static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
63{
64 /* delay timer when change the setting register */
65 ndelay(priv->delay);
66}
67
68static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
69{
70 u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
71
72 return div64_ul(timer_cycle_us, cycle);
73}
74
75static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
76{
77 if (reg == WDTSET)
78 val &= WDTSET_COUNTER_MASK;
79
80 writel_relaxed(val, priv->base + reg);
81 /* Registers other than the WDTINT is always synchronized with WDT_CLK */
82 if (reg != WDTINT)
83 rzg2l_wdt_wait_delay(priv);
84}
85
86static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
87{
88 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
89 u32 time_out;
90
91 /* Clear Lapsed Time Register and clear Interrupt */
92 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
93 /* 2 consecutive overflow cycle needed to trigger reset */
94 time_out = (wdev->timeout * (MICRO / 2)) /
95 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
96 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
97}
98
99static int rzg2l_wdt_start(struct watchdog_device *wdev)
100{
101 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
102 int ret;
103
104 ret = pm_runtime_resume_and_get(wdev->parent);
105 if (ret)
106 return ret;
107
108 ret = reset_control_deassert(priv->rstc);
109 if (ret) {
110 pm_runtime_put(wdev->parent);
111 return ret;
112 }
113
114 /* Initialize time out */
115 rzg2l_wdt_init_timeout(wdev);
116
117 /* Initialize watchdog counter register */
118 rzg2l_wdt_write(priv, 0, WDTTIM);
119
120 /* Enable watchdog timer*/
121 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
122
123 return 0;
124}
125
126static int rzg2l_wdt_stop(struct watchdog_device *wdev)
127{
128 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
129 int ret;
130
131 ret = reset_control_assert(priv->rstc);
132 if (ret)
133 return ret;
134
135 ret = pm_runtime_put(wdev->parent);
136 if (ret < 0)
137 return ret;
138
139 return 0;
140}
141
142static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
143{
144 int ret = 0;
145
146 wdev->timeout = timeout;
147
148 /*
149 * If the watchdog is active, reset the module for updating the WDTSET
150 * register by calling rzg2l_wdt_stop() (which internally calls reset_control_reset()
151 * to reset the module) so that it is updated with new timeout values.
152 */
153 if (watchdog_active(wdev)) {
154 ret = rzg2l_wdt_stop(wdev);
155 if (ret)
156 return ret;
157
158 ret = rzg2l_wdt_start(wdev);
159 }
160
161 return ret;
162}
163
164static int rzg2l_wdt_restart(struct watchdog_device *wdev,
165 unsigned long action, void *data)
166{
167 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
168 int ret;
169
170 /*
171 * In case of RZ/G3S the watchdog device may be part of an IRQ safe power
172 * domain that is currently powered off. In this case we need to power
173 * it on before accessing registers. Along with this the clocks will be
174 * enabled. We don't undo the pm_runtime_resume_and_get() as the device
175 * need to be on for the reboot to happen.
176 *
177 * For the rest of SoCs not registering a watchdog IRQ safe power
178 * domain it is safe to call pm_runtime_resume_and_get() as the
179 * irq_safe_dev_in_sleep_domain() call in genpd_runtime_resume()
180 * returns non zero value and the genpd_lock() is avoided, thus, there
181 * will be no invalid wait context reported by lockdep.
182 */
183 ret = pm_runtime_resume_and_get(wdev->parent);
184 if (ret)
185 return ret;
186
187 if (priv->devtype == WDT_RZG2L) {
188 ret = reset_control_deassert(priv->rstc);
189 if (ret)
190 return ret;
191
192 /* Generate Reset (WDTRSTB) Signal on parity error */
193 rzg2l_wdt_write(priv, 0, PECR);
194
195 /* Force parity error */
196 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
197 } else {
198 /* RZ/V2M doesn't have parity error registers */
199 ret = reset_control_reset(priv->rstc);
200 if (ret)
201 return ret;
202
203 wdev->timeout = 0;
204
205 /* Initialize time out */
206 rzg2l_wdt_init_timeout(wdev);
207
208 /* Initialize watchdog counter register */
209 rzg2l_wdt_write(priv, 0, WDTTIM);
210
211 /* Enable watchdog timer*/
212 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
213
214 /* Wait 2 consecutive overflow cycles for reset */
215 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
216 }
217
218 return 0;
219}
220
221static const struct watchdog_info rzg2l_wdt_ident = {
222 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
223 .identity = "Renesas RZ/G2L WDT Watchdog",
224};
225
226static int rzg2l_wdt_ping(struct watchdog_device *wdev)
227{
228 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
229
230 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
231
232 return 0;
233}
234
235static const struct watchdog_ops rzg2l_wdt_ops = {
236 .owner = THIS_MODULE,
237 .start = rzg2l_wdt_start,
238 .stop = rzg2l_wdt_stop,
239 .ping = rzg2l_wdt_ping,
240 .set_timeout = rzg2l_wdt_set_timeout,
241 .restart = rzg2l_wdt_restart,
242};
243
244static void rzg2l_wdt_pm_disable(void *data)
245{
246 struct watchdog_device *wdev = data;
247
248 pm_runtime_disable(wdev->parent);
249}
250
251static int rzg2l_wdt_probe(struct platform_device *pdev)
252{
253 struct device *dev = &pdev->dev;
254 struct rzg2l_wdt_priv *priv;
255 unsigned long pclk_rate;
256 int ret;
257
258 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
259 if (!priv)
260 return -ENOMEM;
261
262 priv->base = devm_platform_ioremap_resource(pdev, 0);
263 if (IS_ERR(priv->base))
264 return PTR_ERR(priv->base);
265
266 /* Get watchdog main clock */
267 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
268 if (IS_ERR(priv->osc_clk))
269 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
270
271 priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
272 if (!priv->osc_clk_rate)
273 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
274
275 /* Get Peripheral clock */
276 priv->pclk = devm_clk_get(&pdev->dev, "pclk");
277 if (IS_ERR(priv->pclk))
278 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
279
280 pclk_rate = clk_get_rate(priv->pclk);
281 if (!pclk_rate)
282 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
283
284 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
285
286 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
287 if (IS_ERR(priv->rstc))
288 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
289 "failed to get cpg reset");
290
291 priv->devtype = (uintptr_t)of_device_get_match_data(dev);
292
293 pm_runtime_irq_safe(&pdev->dev);
294 pm_runtime_enable(&pdev->dev);
295
296 priv->wdev.info = &rzg2l_wdt_ident;
297 priv->wdev.ops = &rzg2l_wdt_ops;
298 priv->wdev.parent = dev;
299 priv->wdev.min_timeout = 1;
300 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
301 USEC_PER_SEC;
302 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
303
304 watchdog_set_drvdata(&priv->wdev, priv);
305 dev_set_drvdata(dev, priv);
306 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_wdt_pm_disable, &priv->wdev);
307 if (ret)
308 return ret;
309
310 watchdog_set_nowayout(&priv->wdev, nowayout);
311 watchdog_stop_on_unregister(&priv->wdev);
312
313 ret = watchdog_init_timeout(&priv->wdev, 0, dev);
314 if (ret)
315 dev_warn(dev, "Specified timeout invalid, using default");
316
317 return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
318}
319
320static const struct of_device_id rzg2l_wdt_ids[] = {
321 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
322 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
323 { /* sentinel */ }
324};
325MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
326
327static int rzg2l_wdt_suspend_late(struct device *dev)
328{
329 struct rzg2l_wdt_priv *priv = dev_get_drvdata(dev);
330
331 if (!watchdog_active(&priv->wdev))
332 return 0;
333
334 return rzg2l_wdt_stop(&priv->wdev);
335}
336
337static int rzg2l_wdt_resume_early(struct device *dev)
338{
339 struct rzg2l_wdt_priv *priv = dev_get_drvdata(dev);
340
341 if (!watchdog_active(&priv->wdev))
342 return 0;
343
344 return rzg2l_wdt_start(&priv->wdev);
345}
346
347static const struct dev_pm_ops rzg2l_wdt_pm_ops = {
348 LATE_SYSTEM_SLEEP_PM_OPS(rzg2l_wdt_suspend_late, rzg2l_wdt_resume_early)
349};
350
351static struct platform_driver rzg2l_wdt_driver = {
352 .driver = {
353 .name = "rzg2l_wdt",
354 .of_match_table = rzg2l_wdt_ids,
355 .pm = &rzg2l_wdt_pm_ops,
356 },
357 .probe = rzg2l_wdt_probe,
358};
359module_platform_driver(rzg2l_wdt_driver);
360
361MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
362MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
363MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G2L WDT Watchdog Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 */
7#include <linux/bitops.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/reset.h>
17#include <linux/units.h>
18#include <linux/watchdog.h>
19
20#define WDTCNT 0x00
21#define WDTSET 0x04
22#define WDTTIM 0x08
23#define WDTINT 0x0C
24#define PECR 0x10
25#define PEEN 0x14
26#define WDTCNT_WDTEN BIT(0)
27#define WDTINT_INTDISP BIT(0)
28#define PEEN_FORCE BIT(0)
29
30#define WDT_DEFAULT_TIMEOUT 60U
31
32/* Setting period time register only 12 bit set in WDTSET[31:20] */
33#define WDTSET_COUNTER_MASK (0xFFF00000)
34#define WDTSET_COUNTER_VAL(f) ((f) << 20)
35
36#define F2CYCLE_NSEC(f) (1000000000 / (f))
37
38static bool nowayout = WATCHDOG_NOWAYOUT;
39module_param(nowayout, bool, 0);
40MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
42
43enum rz_wdt_type {
44 WDT_RZG2L,
45 WDT_RZV2M,
46};
47
48struct rzg2l_wdt_priv {
49 void __iomem *base;
50 struct watchdog_device wdev;
51 struct reset_control *rstc;
52 unsigned long osc_clk_rate;
53 unsigned long delay;
54 struct clk *pclk;
55 struct clk *osc_clk;
56 enum rz_wdt_type devtype;
57};
58
59static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
60{
61 /* delay timer when change the setting register */
62 ndelay(priv->delay);
63}
64
65static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
66{
67 u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
68
69 return div64_ul(timer_cycle_us, cycle);
70}
71
72static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
73{
74 if (reg == WDTSET)
75 val &= WDTSET_COUNTER_MASK;
76
77 writel_relaxed(val, priv->base + reg);
78 /* Registers other than the WDTINT is always synchronized with WDT_CLK */
79 if (reg != WDTINT)
80 rzg2l_wdt_wait_delay(priv);
81}
82
83static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
84{
85 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
86 u32 time_out;
87
88 /* Clear Lapsed Time Register and clear Interrupt */
89 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
90 /* 2 consecutive overflow cycle needed to trigger reset */
91 time_out = (wdev->timeout * (MICRO / 2)) /
92 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
93 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
94}
95
96static int rzg2l_wdt_start(struct watchdog_device *wdev)
97{
98 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
99
100 pm_runtime_get_sync(wdev->parent);
101
102 /* Initialize time out */
103 rzg2l_wdt_init_timeout(wdev);
104
105 /* Initialize watchdog counter register */
106 rzg2l_wdt_write(priv, 0, WDTTIM);
107
108 /* Enable watchdog timer*/
109 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
110
111 return 0;
112}
113
114static int rzg2l_wdt_stop(struct watchdog_device *wdev)
115{
116 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
117
118 pm_runtime_put(wdev->parent);
119 reset_control_reset(priv->rstc);
120
121 return 0;
122}
123
124static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
125{
126 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
127
128 wdev->timeout = timeout;
129
130 /*
131 * If the watchdog is active, reset the module for updating the WDTSET
132 * register so that it is updated with new timeout values.
133 */
134 if (watchdog_active(wdev)) {
135 pm_runtime_put(wdev->parent);
136 reset_control_reset(priv->rstc);
137 rzg2l_wdt_start(wdev);
138 }
139
140 return 0;
141}
142
143static int rzg2l_wdt_restart(struct watchdog_device *wdev,
144 unsigned long action, void *data)
145{
146 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
147
148 clk_prepare_enable(priv->pclk);
149 clk_prepare_enable(priv->osc_clk);
150
151 if (priv->devtype == WDT_RZG2L) {
152 /* Generate Reset (WDTRSTB) Signal on parity error */
153 rzg2l_wdt_write(priv, 0, PECR);
154
155 /* Force parity error */
156 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
157 } else {
158 /* RZ/V2M doesn't have parity error registers */
159
160 wdev->timeout = 0;
161
162 /* Initialize time out */
163 rzg2l_wdt_init_timeout(wdev);
164
165 /* Initialize watchdog counter register */
166 rzg2l_wdt_write(priv, 0, WDTTIM);
167
168 /* Enable watchdog timer*/
169 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
170
171 /* Wait 2 consecutive overflow cycles for reset */
172 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
173 }
174
175 return 0;
176}
177
178static const struct watchdog_info rzg2l_wdt_ident = {
179 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
180 .identity = "Renesas RZ/G2L WDT Watchdog",
181};
182
183static int rzg2l_wdt_ping(struct watchdog_device *wdev)
184{
185 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
186
187 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
188
189 return 0;
190}
191
192static const struct watchdog_ops rzg2l_wdt_ops = {
193 .owner = THIS_MODULE,
194 .start = rzg2l_wdt_start,
195 .stop = rzg2l_wdt_stop,
196 .ping = rzg2l_wdt_ping,
197 .set_timeout = rzg2l_wdt_set_timeout,
198 .restart = rzg2l_wdt_restart,
199};
200
201static void rzg2l_wdt_reset_assert_pm_disable(void *data)
202{
203 struct watchdog_device *wdev = data;
204 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
205
206 pm_runtime_disable(wdev->parent);
207 reset_control_assert(priv->rstc);
208}
209
210static int rzg2l_wdt_probe(struct platform_device *pdev)
211{
212 struct device *dev = &pdev->dev;
213 struct rzg2l_wdt_priv *priv;
214 unsigned long pclk_rate;
215 int ret;
216
217 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
218 if (!priv)
219 return -ENOMEM;
220
221 priv->base = devm_platform_ioremap_resource(pdev, 0);
222 if (IS_ERR(priv->base))
223 return PTR_ERR(priv->base);
224
225 /* Get watchdog main clock */
226 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
227 if (IS_ERR(priv->osc_clk))
228 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
229
230 priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
231 if (!priv->osc_clk_rate)
232 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
233
234 /* Get Peripheral clock */
235 priv->pclk = devm_clk_get(&pdev->dev, "pclk");
236 if (IS_ERR(priv->pclk))
237 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
238
239 pclk_rate = clk_get_rate(priv->pclk);
240 if (!pclk_rate)
241 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
242
243 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
244
245 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
246 if (IS_ERR(priv->rstc))
247 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
248 "failed to get cpg reset");
249
250 ret = reset_control_deassert(priv->rstc);
251 if (ret)
252 return dev_err_probe(dev, ret, "failed to deassert");
253
254 priv->devtype = (uintptr_t)of_device_get_match_data(dev);
255
256 pm_runtime_enable(&pdev->dev);
257
258 priv->wdev.info = &rzg2l_wdt_ident;
259 priv->wdev.ops = &rzg2l_wdt_ops;
260 priv->wdev.parent = dev;
261 priv->wdev.min_timeout = 1;
262 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
263 USEC_PER_SEC;
264 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
265
266 watchdog_set_drvdata(&priv->wdev, priv);
267 ret = devm_add_action_or_reset(&pdev->dev,
268 rzg2l_wdt_reset_assert_pm_disable,
269 &priv->wdev);
270 if (ret < 0)
271 return ret;
272
273 watchdog_set_nowayout(&priv->wdev, nowayout);
274 watchdog_stop_on_unregister(&priv->wdev);
275
276 ret = watchdog_init_timeout(&priv->wdev, 0, dev);
277 if (ret)
278 dev_warn(dev, "Specified timeout invalid, using default");
279
280 return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
281}
282
283static const struct of_device_id rzg2l_wdt_ids[] = {
284 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
285 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
286 { /* sentinel */ }
287};
288MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
289
290static struct platform_driver rzg2l_wdt_driver = {
291 .driver = {
292 .name = "rzg2l_wdt",
293 .of_match_table = rzg2l_wdt_ids,
294 },
295 .probe = rzg2l_wdt_probe,
296};
297module_platform_driver(rzg2l_wdt_driver);
298
299MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
300MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
301MODULE_LICENSE("GPL v2");