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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (host and target mode)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22#include <linux/spi/spi.h>
23
24/* Name of this driver */
25#define CDNS_SPI_NAME "cdns-spi"
26
27/* Register offset definitions */
28#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
29#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
30#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
31#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
32#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
33#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
34#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
35#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
36#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
37#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
38#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
39
40#define SPI_AUTOSUSPEND_TIMEOUT 3000
41/*
42 * SPI Configuration Register bit Masks
43 *
44 * This register contains various control bits that affect the operation
45 * of the SPI controller
46 */
47#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
48#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
49#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
50#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
51#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
52#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
53#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
54#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
55#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
56#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
57#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
58 CDNS_SPI_CR_SSCTRL | \
59 CDNS_SPI_CR_SSFORCE | \
60 CDNS_SPI_CR_BAUD_DIV_4)
61
62/*
63 * SPI Configuration Register - Baud rate and target select
64 *
65 * These are the values used in the calculation of baud rate divisor and
66 * setting the target select.
67 */
68
69#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
70#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
71#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
72#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
73#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
74#define CDNS_SPI_NOSS 0xF /* No Slave select */
75
76/*
77 * SPI Interrupt Registers bit Masks
78 *
79 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
80 * bit definitions.
81 */
82#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
84#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
85#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
86 CDNS_SPI_IXR_MODF)
87#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
88#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
89
90/*
91 * SPI Enable Register bit Masks
92 *
93 * This register is used to enable or disable the SPI controller
94 */
95#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
96#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
97
98/* Default number of chip select lines */
99#define CDNS_SPI_DEFAULT_NUM_CS 4
100
101/**
102 * struct cdns_spi - This definition defines spi driver instance
103 * @regs: Virtual address of the SPI controller registers
104 * @ref_clk: Pointer to the peripheral clock
105 * @pclk: Pointer to the APB clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
107 * @speed_hz: Current SPI bus clock speed in Hz
108 * @txbuf: Pointer to the TX buffer
109 * @rxbuf: Pointer to the RX buffer
110 * @tx_bytes: Number of bytes left to transfer
111 * @rx_bytes: Number of bytes requested
112 * @dev_busy: Device busy flag
113 * @is_decoded_cs: Flag for decoder property set or not
114 * @tx_fifo_depth: Depth of the TX FIFO
115 * @rstc: Optional reset control for SPI controller
116 */
117struct cdns_spi {
118 void __iomem *regs;
119 struct clk *ref_clk;
120 struct clk *pclk;
121 unsigned int clk_rate;
122 u32 speed_hz;
123 const u8 *txbuf;
124 u8 *rxbuf;
125 int tx_bytes;
126 int rx_bytes;
127 u8 dev_busy;
128 u32 is_decoded_cs;
129 unsigned int tx_fifo_depth;
130 struct reset_control *rstc;
131};
132
133/* Macros for the SPI controller read/write */
134static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
135{
136 return readl_relaxed(xspi->regs + offset);
137}
138
139static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
140{
141 writel_relaxed(val, xspi->regs + offset);
142}
143
144/**
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
146 * @xspi: Pointer to the cdns_spi structure
147 * @is_target: Flag to indicate target or host mode
148 * * On reset the SPI controller is configured to target or host mode.
149 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
150 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
151 *
152 * This function initializes the SPI controller to disable and clear all the
153 * interrupts, enable manual target select and manual start, deselect all the
154 * chip select lines, and enable the SPI controller.
155 */
156static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
157{
158 u32 ctrl_reg = 0;
159
160 if (!is_target)
161 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
162
163 if (xspi->is_decoded_cs)
164 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
165
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
167 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
168
169 /* Clear the RX FIFO */
170 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
171 cdns_spi_read(xspi, CDNS_SPI_RXD);
172
173 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
174 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
175 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
176}
177
178/**
179 * cdns_spi_chipselect - Select or deselect the chip select line
180 * @spi: Pointer to the spi_device structure
181 * @is_high: Select(0) or deselect (1) the chip select line
182 */
183static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
184{
185 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
186 u32 ctrl_reg;
187
188 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
189
190 if (is_high) {
191 /* Deselect the target */
192 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
193 } else {
194 /* Select the target */
195 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
196 if (!(xspi->is_decoded_cs))
197 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
198 CDNS_SPI_SS_SHIFT) &
199 CDNS_SPI_CR_SSCTRL;
200 else
201 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
202 CDNS_SPI_CR_SSCTRL;
203 }
204
205 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
206}
207
208/**
209 * cdns_spi_config_clock_mode - Sets clock polarity and phase
210 * @spi: Pointer to the spi_device structure
211 *
212 * Sets the requested clock polarity and phase.
213 */
214static void cdns_spi_config_clock_mode(struct spi_device *spi)
215{
216 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
217 u32 ctrl_reg, new_ctrl_reg;
218
219 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
220 ctrl_reg = new_ctrl_reg;
221
222 /* Set the SPI clock phase and clock polarity */
223 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
224 if (spi->mode & SPI_CPHA)
225 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
226 if (spi->mode & SPI_CPOL)
227 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
228
229 if (new_ctrl_reg != ctrl_reg) {
230 /*
231 * Just writing the CR register does not seem to apply the clock
232 * setting changes. This is problematic when changing the clock
233 * polarity as it will cause the SPI target to see spurious clock
234 * transitions. To workaround the issue toggle the ER register.
235 */
236 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
237 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
238 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
239 }
240}
241
242/**
243 * cdns_spi_config_clock_freq - Sets clock frequency
244 * @spi: Pointer to the spi_device structure
245 * @transfer: Pointer to the spi_transfer structure which provides
246 * information about next transfer setup parameters
247 *
248 * Sets the requested clock frequency.
249 * Note: If the requested frequency is not an exact match with what can be
250 * obtained using the prescalar value the driver sets the clock frequency which
251 * is lower than the requested frequency (maximum lower) for the transfer. If
252 * the requested frequency is higher or lower than that is supported by the SPI
253 * controller the driver will set the highest or lowest frequency supported by
254 * controller.
255 */
256static void cdns_spi_config_clock_freq(struct spi_device *spi,
257 struct spi_transfer *transfer)
258{
259 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
260 u32 ctrl_reg, baud_rate_val;
261 unsigned long frequency;
262
263 frequency = xspi->clk_rate;
264
265 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
266
267 /* Set the clock frequency */
268 if (xspi->speed_hz != transfer->speed_hz) {
269 /* first valid value is 1 */
270 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
271 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
272 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
273 baud_rate_val++;
274
275 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
276 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
277
278 xspi->speed_hz = frequency / (2 << baud_rate_val);
279 }
280 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
281}
282
283/**
284 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
285 * @spi: Pointer to the spi_device structure
286 * @transfer: Pointer to the spi_transfer structure which provides
287 * information about next transfer setup parameters
288 *
289 * Sets the operational mode of SPI controller for the next SPI transfer and
290 * sets the requested clock frequency.
291 *
292 * Return: Always 0
293 */
294static int cdns_spi_setup_transfer(struct spi_device *spi,
295 struct spi_transfer *transfer)
296{
297 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
298
299 cdns_spi_config_clock_freq(spi, transfer);
300
301 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
302 __func__, spi->mode, spi->bits_per_word,
303 xspi->speed_hz);
304
305 return 0;
306}
307
308/**
309 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
310 * @xspi: Pointer to the cdns_spi structure
311 * @ntx: Number of bytes to pack into the TX FIFO
312 * @nrx: Number of bytes to drain from the RX FIFO
313 */
314static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
315{
316 ntx = clamp(ntx, 0, xspi->tx_bytes);
317 nrx = clamp(nrx, 0, xspi->rx_bytes);
318
319 xspi->tx_bytes -= ntx;
320 xspi->rx_bytes -= nrx;
321
322 while (ntx || nrx) {
323 if (nrx) {
324 u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
325
326 if (xspi->rxbuf)
327 *xspi->rxbuf++ = data;
328
329 nrx--;
330 }
331
332 if (ntx) {
333 if (xspi->txbuf)
334 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
335 else
336 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
337
338 ntx--;
339 }
340
341 }
342}
343
344/**
345 * cdns_spi_irq - Interrupt service routine of the SPI controller
346 * @irq: IRQ number
347 * @dev_id: Pointer to the xspi structure
348 *
349 * This function handles TX empty and Mode Fault interrupts only.
350 * On TX empty interrupt this function reads the received data from RX FIFO and
351 * fills the TX FIFO if there is any data remaining to be transferred.
352 * On Mode Fault interrupt this function indicates that transfer is completed,
353 * the SPI subsystem will identify the error as the remaining bytes to be
354 * transferred is non-zero.
355 *
356 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
357 */
358static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
359{
360 struct spi_controller *ctlr = dev_id;
361 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
362 irqreturn_t status;
363 u32 intr_status;
364
365 status = IRQ_NONE;
366 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
367 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
368
369 if (intr_status & CDNS_SPI_IXR_MODF) {
370 /* Indicate that transfer is completed, the SPI subsystem will
371 * identify the error as the remaining bytes to be
372 * transferred is non-zero
373 */
374 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
375 spi_finalize_current_transfer(ctlr);
376 status = IRQ_HANDLED;
377 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
378 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
379 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
380
381 if (threshold > 1)
382 trans_cnt -= threshold;
383
384 /* Set threshold to one if number of pending are
385 * less than half fifo
386 */
387 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
388 cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
389
390 if (xspi->tx_bytes) {
391 cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
392 } else {
393 /* Fixed delay due to controller limitation with
394 * RX_NEMPTY incorrect status
395 * Xilinx AR:65885 contains more details
396 */
397 udelay(10);
398 cdns_spi_process_fifo(xspi, 0, trans_cnt);
399 cdns_spi_write(xspi, CDNS_SPI_IDR,
400 CDNS_SPI_IXR_DEFAULT);
401 spi_finalize_current_transfer(ctlr);
402 }
403 status = IRQ_HANDLED;
404 }
405
406 return status;
407}
408
409static int cdns_prepare_message(struct spi_controller *ctlr,
410 struct spi_message *msg)
411{
412 if (!spi_controller_is_target(ctlr))
413 cdns_spi_config_clock_mode(msg->spi);
414 return 0;
415}
416
417/**
418 * cdns_transfer_one - Initiates the SPI transfer
419 * @ctlr: Pointer to spi_controller structure
420 * @spi: Pointer to the spi_device structure
421 * @transfer: Pointer to the spi_transfer structure which provides
422 * information about next transfer parameters
423 *
424 * This function in host mode fills the TX FIFO, starts the SPI transfer and
425 * returns a positive transfer count so that core will wait for completion.
426 * This function in target mode fills the TX FIFO and wait for transfer trigger.
427 *
428 * Return: Number of bytes transferred in the last transfer
429 */
430static int cdns_transfer_one(struct spi_controller *ctlr,
431 struct spi_device *spi,
432 struct spi_transfer *transfer)
433{
434 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
435
436 xspi->txbuf = transfer->tx_buf;
437 xspi->rxbuf = transfer->rx_buf;
438 xspi->tx_bytes = transfer->len;
439 xspi->rx_bytes = transfer->len;
440
441 if (!spi_controller_is_target(ctlr)) {
442 cdns_spi_setup_transfer(spi, transfer);
443 } else {
444 /* Set TX empty threshold to half of FIFO depth
445 * only if TX bytes are more than FIFO depth.
446 */
447 if (xspi->tx_bytes > xspi->tx_fifo_depth)
448 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
449 }
450
451 /* When xspi in busy condition, bytes may send failed,
452 * then spi control didn't work thoroughly, add one byte delay
453 */
454 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
455 udelay(10);
456
457 cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
458
459 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
460 return transfer->len;
461}
462
463/**
464 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
465 * @ctlr: Pointer to the spi_controller structure which provides
466 * information about the controller.
467 *
468 * This function enables SPI host controller.
469 *
470 * Return: 0 always
471 */
472static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
473{
474 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
475
476 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
477
478 return 0;
479}
480
481/**
482 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
483 * @ctlr: Pointer to the spi_controller structure which provides
484 * information about the controller.
485 *
486 * This function disables the SPI host controller when no target selected.
487 * This function flush out if any pending data in FIFO.
488 *
489 * Return: 0 always
490 */
491static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
492{
493 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
494 u32 ctrl_reg;
495 unsigned int cnt = xspi->tx_fifo_depth;
496
497 if (spi_controller_is_target(ctlr)) {
498 while (cnt--)
499 cdns_spi_read(xspi, CDNS_SPI_RXD);
500 }
501
502 /* Disable the SPI if target is deselected */
503 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
504 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
505 if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
506 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
507
508 /* Reset to default */
509 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
510 return 0;
511}
512
513/**
514 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
515 * @xspi: Pointer to the cdns_spi structure
516 *
517 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
518 * IP. The FIFO threshold register is sized so that its maximum value can be the
519 * FIFO size - 1. This is used to detect the size of the FIFO.
520 */
521static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
522{
523 /* The MSBs will get truncated giving us the size of the FIFO */
524 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
525 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
526
527 /* Reset to default */
528 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
529}
530
531/**
532 * cdns_target_abort - Abort target transfer
533 * @ctlr: Pointer to the spi_controller structure
534 *
535 * This function abort target transfer if there any transfer timeout.
536 *
537 * Return: 0 always
538 */
539static int cdns_target_abort(struct spi_controller *ctlr)
540{
541 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
542 u32 intr_status;
543
544 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
545 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
546 cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
547 spi_finalize_current_transfer(ctlr);
548
549 return 0;
550}
551
552/**
553 * cdns_spi_probe - Probe method for the SPI driver
554 * @pdev: Pointer to the platform_device structure
555 *
556 * This function initializes the driver data structures and the hardware.
557 *
558 * Return: 0 on success and error value on error
559 */
560static int cdns_spi_probe(struct platform_device *pdev)
561{
562 int ret = 0, irq;
563 struct spi_controller *ctlr;
564 struct cdns_spi *xspi;
565 u32 num_cs;
566 bool target;
567
568 target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
569 if (target)
570 ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
571 else
572 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
573
574 if (!ctlr)
575 return -ENOMEM;
576
577 xspi = spi_controller_get_devdata(ctlr);
578 ctlr->dev.of_node = pdev->dev.of_node;
579 platform_set_drvdata(pdev, ctlr);
580
581 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
582 if (IS_ERR(xspi->regs)) {
583 ret = PTR_ERR(xspi->regs);
584 goto remove_ctlr;
585 }
586
587 xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
588 if (IS_ERR(xspi->pclk)) {
589 dev_err(&pdev->dev, "pclk clock not found.\n");
590 ret = PTR_ERR(xspi->pclk);
591 goto remove_ctlr;
592 }
593
594 xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
595 if (IS_ERR(xspi->rstc)) {
596 ret = dev_err_probe(&pdev->dev, PTR_ERR(xspi->rstc),
597 "Cannot get SPI reset.\n");
598 goto remove_ctlr;
599 }
600
601 reset_control_assert(xspi->rstc);
602 reset_control_deassert(xspi->rstc);
603
604 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
605 if (IS_ERR(xspi->ref_clk)) {
606 dev_err(&pdev->dev, "ref_clk clock not found.\n");
607 ret = PTR_ERR(xspi->ref_clk);
608 goto remove_ctlr;
609 }
610
611 if (!spi_controller_is_target(ctlr)) {
612 pm_runtime_use_autosuspend(&pdev->dev);
613 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
614 pm_runtime_get_noresume(&pdev->dev);
615 pm_runtime_set_active(&pdev->dev);
616 pm_runtime_enable(&pdev->dev);
617
618 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
619 if (ret < 0)
620 ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
621 else
622 ctlr->num_chipselect = num_cs;
623
624 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
625 &xspi->is_decoded_cs);
626 if (ret < 0)
627 xspi->is_decoded_cs = 0;
628 }
629
630 cdns_spi_detect_fifo_depth(xspi);
631
632 /* SPI controller initializations */
633 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
634
635 irq = platform_get_irq(pdev, 0);
636 if (irq < 0) {
637 ret = irq;
638 goto clk_dis_all;
639 }
640
641 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
642 0, pdev->name, ctlr);
643 if (ret != 0) {
644 ret = -ENXIO;
645 dev_err(&pdev->dev, "request_irq failed\n");
646 goto clk_dis_all;
647 }
648
649 ctlr->use_gpio_descriptors = true;
650 ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
651 ctlr->prepare_message = cdns_prepare_message;
652 ctlr->transfer_one = cdns_transfer_one;
653 ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
654 ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
655 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
656
657 if (!spi_controller_is_target(ctlr)) {
658 ctlr->mode_bits |= SPI_CS_HIGH;
659 ctlr->set_cs = cdns_spi_chipselect;
660 ctlr->auto_runtime_pm = true;
661 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
662 /* Set to default valid value */
663 ctlr->max_speed_hz = xspi->clk_rate / 4;
664 xspi->speed_hz = ctlr->max_speed_hz;
665 pm_runtime_mark_last_busy(&pdev->dev);
666 pm_runtime_put_autosuspend(&pdev->dev);
667 } else {
668 ctlr->mode_bits |= SPI_NO_CS;
669 ctlr->target_abort = cdns_target_abort;
670 }
671 ret = spi_register_controller(ctlr);
672 if (ret) {
673 dev_err(&pdev->dev, "spi_register_controller failed\n");
674 goto clk_dis_all;
675 }
676
677 return ret;
678
679clk_dis_all:
680 if (!spi_controller_is_target(ctlr)) {
681 pm_runtime_disable(&pdev->dev);
682 pm_runtime_set_suspended(&pdev->dev);
683 }
684remove_ctlr:
685 spi_controller_put(ctlr);
686 return ret;
687}
688
689/**
690 * cdns_spi_remove - Remove method for the SPI driver
691 * @pdev: Pointer to the platform_device structure
692 *
693 * This function is called if a device is physically removed from the system or
694 * if the driver module is being unloaded. It frees all resources allocated to
695 * the device.
696 */
697static void cdns_spi_remove(struct platform_device *pdev)
698{
699 struct spi_controller *ctlr = platform_get_drvdata(pdev);
700 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
701
702 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
703
704 if (!spi_controller_is_target(ctlr)) {
705 pm_runtime_disable(&pdev->dev);
706 pm_runtime_set_suspended(&pdev->dev);
707 }
708
709 spi_unregister_controller(ctlr);
710}
711
712/**
713 * cdns_spi_suspend - Suspend method for the SPI driver
714 * @dev: Address of the platform_device structure
715 *
716 * This function disables the SPI controller and
717 * changes the driver state to "suspend"
718 *
719 * Return: 0 on success and error value on error
720 */
721static int __maybe_unused cdns_spi_suspend(struct device *dev)
722{
723 struct spi_controller *ctlr = dev_get_drvdata(dev);
724
725 return spi_controller_suspend(ctlr);
726}
727
728/**
729 * cdns_spi_resume - Resume method for the SPI driver
730 * @dev: Address of the platform_device structure
731 *
732 * This function changes the driver state to "ready"
733 *
734 * Return: 0 on success and error value on error
735 */
736static int __maybe_unused cdns_spi_resume(struct device *dev)
737{
738 struct spi_controller *ctlr = dev_get_drvdata(dev);
739 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
740
741 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
742 return spi_controller_resume(ctlr);
743}
744
745/**
746 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
747 * @dev: Address of the platform_device structure
748 *
749 * This function enables the clocks
750 *
751 * Return: 0 on success and error value on error
752 */
753static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
754{
755 struct spi_controller *ctlr = dev_get_drvdata(dev);
756 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
757 int ret;
758
759 ret = clk_prepare_enable(xspi->pclk);
760 if (ret) {
761 dev_err(dev, "Cannot enable APB clock.\n");
762 return ret;
763 }
764
765 ret = clk_prepare_enable(xspi->ref_clk);
766 if (ret) {
767 dev_err(dev, "Cannot enable device clock.\n");
768 clk_disable_unprepare(xspi->pclk);
769 return ret;
770 }
771 return 0;
772}
773
774/**
775 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
776 * @dev: Address of the platform_device structure
777 *
778 * This function disables the clocks
779 *
780 * Return: Always 0
781 */
782static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
783{
784 struct spi_controller *ctlr = dev_get_drvdata(dev);
785 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
786
787 clk_disable_unprepare(xspi->ref_clk);
788 clk_disable_unprepare(xspi->pclk);
789
790 return 0;
791}
792
793static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
794 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
795 cdns_spi_runtime_resume, NULL)
796 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
797};
798
799static const struct of_device_id cdns_spi_of_match[] = {
800 { .compatible = "xlnx,zynq-spi-r1p6" },
801 { .compatible = "cdns,spi-r1p6" },
802 { /* end of table */ }
803};
804MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
805
806/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
807static struct platform_driver cdns_spi_driver = {
808 .probe = cdns_spi_probe,
809 .remove = cdns_spi_remove,
810 .driver = {
811 .name = CDNS_SPI_NAME,
812 .of_match_table = cdns_spi_of_match,
813 .pm = &cdns_spi_dev_pm_ops,
814 },
815};
816
817module_platform_driver(cdns_spi_driver);
818
819MODULE_AUTHOR("Xilinx, Inc.");
820MODULE_DESCRIPTION("Cadence SPI driver");
821MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (master mode only)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21
22/* Name of this driver */
23#define CDNS_SPI_NAME "cdns-spi"
24
25/* Register offset definitions */
26#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
27#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
28#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
29#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
30#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
31#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
32#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
33#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
34#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
35#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
36#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
37
38#define SPI_AUTOSUSPEND_TIMEOUT 3000
39/*
40 * SPI Configuration Register bit Masks
41 *
42 * This register contains various control bits that affect the operation
43 * of the SPI controller
44 */
45#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
46#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
47#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
48#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
49#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
50#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
51#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
52#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
53#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
54#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
55#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
56 CDNS_SPI_CR_SSCTRL | \
57 CDNS_SPI_CR_SSFORCE | \
58 CDNS_SPI_CR_BAUD_DIV_4)
59
60/*
61 * SPI Configuration Register - Baud rate and slave select
62 *
63 * These are the values used in the calculation of baud rate divisor and
64 * setting the slave select.
65 */
66
67#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
68#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
69#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
70#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
71#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
72#define CDNS_SPI_NOSS 0xF /* No Slave select */
73
74/*
75 * SPI Interrupt Registers bit Masks
76 *
77 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
78 * bit definitions.
79 */
80#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
81#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
82#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
83#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
84 CDNS_SPI_IXR_MODF)
85#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
86#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
87
88/*
89 * SPI Enable Register bit Masks
90 *
91 * This register is used to enable or disable the SPI controller
92 */
93#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
94#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
95
96/* Default number of chip select lines */
97#define CDNS_SPI_DEFAULT_NUM_CS 4
98
99/**
100 * struct cdns_spi - This definition defines spi driver instance
101 * @regs: Virtual address of the SPI controller registers
102 * @ref_clk: Pointer to the peripheral clock
103 * @pclk: Pointer to the APB clock
104 * @speed_hz: Current SPI bus clock speed in Hz
105 * @txbuf: Pointer to the TX buffer
106 * @rxbuf: Pointer to the RX buffer
107 * @tx_bytes: Number of bytes left to transfer
108 * @rx_bytes: Number of bytes requested
109 * @dev_busy: Device busy flag
110 * @is_decoded_cs: Flag for decoder property set or not
111 * @tx_fifo_depth: Depth of the TX FIFO
112 */
113struct cdns_spi {
114 void __iomem *regs;
115 struct clk *ref_clk;
116 struct clk *pclk;
117 unsigned int clk_rate;
118 u32 speed_hz;
119 const u8 *txbuf;
120 u8 *rxbuf;
121 int tx_bytes;
122 int rx_bytes;
123 u8 dev_busy;
124 u32 is_decoded_cs;
125 unsigned int tx_fifo_depth;
126};
127
128/* Macros for the SPI controller read/write */
129static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
130{
131 return readl_relaxed(xspi->regs + offset);
132}
133
134static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
135{
136 writel_relaxed(val, xspi->regs + offset);
137}
138
139/**
140 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
141 * @xspi: Pointer to the cdns_spi structure
142 *
143 * On reset the SPI controller is configured to be in master mode, baud rate
144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
145 * to 1 and size of the word to be transferred as 8 bit.
146 * This function initializes the SPI controller to disable and clear all the
147 * interrupts, enable manual slave select and manual start, deselect all the
148 * chip select lines, and enable the SPI controller.
149 */
150static void cdns_spi_init_hw(struct cdns_spi *xspi)
151{
152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
153
154 if (xspi->is_decoded_cs)
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
156
157 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
158 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
159
160 /* Clear the RX FIFO */
161 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
162 cdns_spi_read(xspi, CDNS_SPI_RXD);
163
164 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
167}
168
169/**
170 * cdns_spi_chipselect - Select or deselect the chip select line
171 * @spi: Pointer to the spi_device structure
172 * @is_high: Select(0) or deselect (1) the chip select line
173 */
174static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
175{
176 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
177 u32 ctrl_reg;
178
179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
180
181 if (is_high) {
182 /* Deselect the slave */
183 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
184 } else {
185 /* Select the slave */
186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
187 if (!(xspi->is_decoded_cs))
188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
189 CDNS_SPI_SS_SHIFT) &
190 CDNS_SPI_CR_SSCTRL;
191 else
192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
193 CDNS_SPI_CR_SSCTRL;
194 }
195
196 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
197}
198
199/**
200 * cdns_spi_config_clock_mode - Sets clock polarity and phase
201 * @spi: Pointer to the spi_device structure
202 *
203 * Sets the requested clock polarity and phase.
204 */
205static void cdns_spi_config_clock_mode(struct spi_device *spi)
206{
207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
208 u32 ctrl_reg, new_ctrl_reg;
209
210 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
211 ctrl_reg = new_ctrl_reg;
212
213 /* Set the SPI clock phase and clock polarity */
214 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
215 if (spi->mode & SPI_CPHA)
216 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
217 if (spi->mode & SPI_CPOL)
218 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
219
220 if (new_ctrl_reg != ctrl_reg) {
221 /*
222 * Just writing the CR register does not seem to apply the clock
223 * setting changes. This is problematic when changing the clock
224 * polarity as it will cause the SPI slave to see spurious clock
225 * transitions. To workaround the issue toggle the ER register.
226 */
227 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
228 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
229 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
230 }
231}
232
233/**
234 * cdns_spi_config_clock_freq - Sets clock frequency
235 * @spi: Pointer to the spi_device structure
236 * @transfer: Pointer to the spi_transfer structure which provides
237 * information about next transfer setup parameters
238 *
239 * Sets the requested clock frequency.
240 * Note: If the requested frequency is not an exact match with what can be
241 * obtained using the prescalar value the driver sets the clock frequency which
242 * is lower than the requested frequency (maximum lower) for the transfer. If
243 * the requested frequency is higher or lower than that is supported by the SPI
244 * controller the driver will set the highest or lowest frequency supported by
245 * controller.
246 */
247static void cdns_spi_config_clock_freq(struct spi_device *spi,
248 struct spi_transfer *transfer)
249{
250 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
251 u32 ctrl_reg, baud_rate_val;
252 unsigned long frequency;
253
254 frequency = xspi->clk_rate;
255
256 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
257
258 /* Set the clock frequency */
259 if (xspi->speed_hz != transfer->speed_hz) {
260 /* first valid value is 1 */
261 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
262 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
263 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
264 baud_rate_val++;
265
266 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
267 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
268
269 xspi->speed_hz = frequency / (2 << baud_rate_val);
270 }
271 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
272}
273
274/**
275 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
276 * @spi: Pointer to the spi_device structure
277 * @transfer: Pointer to the spi_transfer structure which provides
278 * information about next transfer setup parameters
279 *
280 * Sets the operational mode of SPI controller for the next SPI transfer and
281 * sets the requested clock frequency.
282 *
283 * Return: Always 0
284 */
285static int cdns_spi_setup_transfer(struct spi_device *spi,
286 struct spi_transfer *transfer)
287{
288 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
289
290 cdns_spi_config_clock_freq(spi, transfer);
291
292 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
293 __func__, spi->mode, spi->bits_per_word,
294 xspi->speed_hz);
295
296 return 0;
297}
298
299/**
300 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
301 * @xspi: Pointer to the cdns_spi structure
302 */
303static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
304{
305 unsigned long trans_cnt = 0;
306
307 while ((trans_cnt < xspi->tx_fifo_depth) &&
308 (xspi->tx_bytes > 0)) {
309
310 /* When xspi in busy condition, bytes may send failed,
311 * then spi control did't work thoroughly, add one byte delay
312 */
313 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
314 CDNS_SPI_IXR_TXFULL)
315 udelay(10);
316
317 if (xspi->txbuf)
318 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
319 else
320 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
321
322 xspi->tx_bytes--;
323 trans_cnt++;
324 }
325}
326
327/**
328 * cdns_spi_irq - Interrupt service routine of the SPI controller
329 * @irq: IRQ number
330 * @dev_id: Pointer to the xspi structure
331 *
332 * This function handles TX empty and Mode Fault interrupts only.
333 * On TX empty interrupt this function reads the received data from RX FIFO and
334 * fills the TX FIFO if there is any data remaining to be transferred.
335 * On Mode Fault interrupt this function indicates that transfer is completed,
336 * the SPI subsystem will identify the error as the remaining bytes to be
337 * transferred is non-zero.
338 *
339 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
340 */
341static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
342{
343 struct spi_master *master = dev_id;
344 struct cdns_spi *xspi = spi_master_get_devdata(master);
345 irqreturn_t status;
346 u32 intr_status;
347
348 status = IRQ_NONE;
349 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
350 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
351
352 if (intr_status & CDNS_SPI_IXR_MODF) {
353 /* Indicate that transfer is completed, the SPI subsystem will
354 * identify the error as the remaining bytes to be
355 * transferred is non-zero
356 */
357 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
358 spi_finalize_current_transfer(master);
359 status = IRQ_HANDLED;
360 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
361 unsigned long trans_cnt;
362
363 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
364
365 /* Read out the data from the RX FIFO */
366 while (trans_cnt) {
367 u8 data;
368
369 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
370 if (xspi->rxbuf)
371 *xspi->rxbuf++ = data;
372
373 xspi->rx_bytes--;
374 trans_cnt--;
375 }
376
377 if (xspi->tx_bytes) {
378 /* There is more data to send */
379 cdns_spi_fill_tx_fifo(xspi);
380 } else {
381 /* Transfer is completed */
382 cdns_spi_write(xspi, CDNS_SPI_IDR,
383 CDNS_SPI_IXR_DEFAULT);
384 spi_finalize_current_transfer(master);
385 }
386 status = IRQ_HANDLED;
387 }
388
389 return status;
390}
391
392static int cdns_prepare_message(struct spi_master *master,
393 struct spi_message *msg)
394{
395 cdns_spi_config_clock_mode(msg->spi);
396 return 0;
397}
398
399/**
400 * cdns_transfer_one - Initiates the SPI transfer
401 * @master: Pointer to spi_master structure
402 * @spi: Pointer to the spi_device structure
403 * @transfer: Pointer to the spi_transfer structure which provides
404 * information about next transfer parameters
405 *
406 * This function fills the TX FIFO, starts the SPI transfer and
407 * returns a positive transfer count so that core will wait for completion.
408 *
409 * Return: Number of bytes transferred in the last transfer
410 */
411static int cdns_transfer_one(struct spi_master *master,
412 struct spi_device *spi,
413 struct spi_transfer *transfer)
414{
415 struct cdns_spi *xspi = spi_master_get_devdata(master);
416
417 xspi->txbuf = transfer->tx_buf;
418 xspi->rxbuf = transfer->rx_buf;
419 xspi->tx_bytes = transfer->len;
420 xspi->rx_bytes = transfer->len;
421
422 cdns_spi_setup_transfer(spi, transfer);
423 cdns_spi_fill_tx_fifo(xspi);
424 spi_transfer_delay_exec(transfer);
425
426 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
427 return transfer->len;
428}
429
430/**
431 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
432 * @master: Pointer to the spi_master structure which provides
433 * information about the controller.
434 *
435 * This function enables SPI master controller.
436 *
437 * Return: 0 always
438 */
439static int cdns_prepare_transfer_hardware(struct spi_master *master)
440{
441 struct cdns_spi *xspi = spi_master_get_devdata(master);
442
443 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
444
445 return 0;
446}
447
448/**
449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
450 * @master: Pointer to the spi_master structure which provides
451 * information about the controller.
452 *
453 * This function disables the SPI master controller when no slave selected.
454 *
455 * Return: 0 always
456 */
457static int cdns_unprepare_transfer_hardware(struct spi_master *master)
458{
459 struct cdns_spi *xspi = spi_master_get_devdata(master);
460 u32 ctrl_reg;
461
462 /* Disable the SPI if slave is deselected */
463 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
464 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
465 if (ctrl_reg == CDNS_SPI_NOSS)
466 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
467
468 return 0;
469}
470
471/**
472 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
473 * @xspi: Pointer to the cdns_spi structure
474 *
475 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
476 * IP. The FIFO threshold register is sized so that its maximum value can be the
477 * FIFO size - 1. This is used to detect the size of the FIFO.
478 */
479static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
480{
481 /* The MSBs will get truncated giving us the size of the FIFO */
482 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
483 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
484
485 /* Reset to default */
486 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
487}
488
489/**
490 * cdns_spi_probe - Probe method for the SPI driver
491 * @pdev: Pointer to the platform_device structure
492 *
493 * This function initializes the driver data structures and the hardware.
494 *
495 * Return: 0 on success and error value on error
496 */
497static int cdns_spi_probe(struct platform_device *pdev)
498{
499 int ret = 0, irq;
500 struct spi_master *master;
501 struct cdns_spi *xspi;
502 u32 num_cs;
503
504 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
505 if (!master)
506 return -ENOMEM;
507
508 xspi = spi_master_get_devdata(master);
509 master->dev.of_node = pdev->dev.of_node;
510 platform_set_drvdata(pdev, master);
511
512 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
513 if (IS_ERR(xspi->regs)) {
514 ret = PTR_ERR(xspi->regs);
515 goto remove_master;
516 }
517
518 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
519 if (IS_ERR(xspi->pclk)) {
520 dev_err(&pdev->dev, "pclk clock not found.\n");
521 ret = PTR_ERR(xspi->pclk);
522 goto remove_master;
523 }
524
525 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
526 if (IS_ERR(xspi->ref_clk)) {
527 dev_err(&pdev->dev, "ref_clk clock not found.\n");
528 ret = PTR_ERR(xspi->ref_clk);
529 goto remove_master;
530 }
531
532 ret = clk_prepare_enable(xspi->pclk);
533 if (ret) {
534 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
535 goto remove_master;
536 }
537
538 ret = clk_prepare_enable(xspi->ref_clk);
539 if (ret) {
540 dev_err(&pdev->dev, "Unable to enable device clock.\n");
541 goto clk_dis_apb;
542 }
543
544 pm_runtime_use_autosuspend(&pdev->dev);
545 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
546 pm_runtime_get_noresume(&pdev->dev);
547 pm_runtime_set_active(&pdev->dev);
548 pm_runtime_enable(&pdev->dev);
549
550 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
551 if (ret < 0)
552 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
553 else
554 master->num_chipselect = num_cs;
555
556 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
557 &xspi->is_decoded_cs);
558 if (ret < 0)
559 xspi->is_decoded_cs = 0;
560
561 cdns_spi_detect_fifo_depth(xspi);
562
563 /* SPI controller initializations */
564 cdns_spi_init_hw(xspi);
565
566 irq = platform_get_irq(pdev, 0);
567 if (irq <= 0) {
568 ret = -ENXIO;
569 goto clk_dis_all;
570 }
571
572 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
573 0, pdev->name, master);
574 if (ret != 0) {
575 ret = -ENXIO;
576 dev_err(&pdev->dev, "request_irq failed\n");
577 goto clk_dis_all;
578 }
579
580 master->use_gpio_descriptors = true;
581 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
582 master->prepare_message = cdns_prepare_message;
583 master->transfer_one = cdns_transfer_one;
584 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
585 master->set_cs = cdns_spi_chipselect;
586 master->auto_runtime_pm = true;
587 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
588
589 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
590 /* Set to default valid value */
591 master->max_speed_hz = xspi->clk_rate / 4;
592 xspi->speed_hz = master->max_speed_hz;
593
594 master->bits_per_word_mask = SPI_BPW_MASK(8);
595
596 pm_runtime_mark_last_busy(&pdev->dev);
597 pm_runtime_put_autosuspend(&pdev->dev);
598
599 ret = spi_register_master(master);
600 if (ret) {
601 dev_err(&pdev->dev, "spi_register_master failed\n");
602 goto clk_dis_all;
603 }
604
605 return ret;
606
607clk_dis_all:
608 pm_runtime_set_suspended(&pdev->dev);
609 pm_runtime_disable(&pdev->dev);
610 clk_disable_unprepare(xspi->ref_clk);
611clk_dis_apb:
612 clk_disable_unprepare(xspi->pclk);
613remove_master:
614 spi_master_put(master);
615 return ret;
616}
617
618/**
619 * cdns_spi_remove - Remove method for the SPI driver
620 * @pdev: Pointer to the platform_device structure
621 *
622 * This function is called if a device is physically removed from the system or
623 * if the driver module is being unloaded. It frees all resources allocated to
624 * the device.
625 *
626 * Return: 0 on success and error value on error
627 */
628static int cdns_spi_remove(struct platform_device *pdev)
629{
630 struct spi_master *master = platform_get_drvdata(pdev);
631 struct cdns_spi *xspi = spi_master_get_devdata(master);
632
633 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
634
635 clk_disable_unprepare(xspi->ref_clk);
636 clk_disable_unprepare(xspi->pclk);
637 pm_runtime_set_suspended(&pdev->dev);
638 pm_runtime_disable(&pdev->dev);
639
640 spi_unregister_master(master);
641
642 return 0;
643}
644
645/**
646 * cdns_spi_suspend - Suspend method for the SPI driver
647 * @dev: Address of the platform_device structure
648 *
649 * This function disables the SPI controller and
650 * changes the driver state to "suspend"
651 *
652 * Return: 0 on success and error value on error
653 */
654static int __maybe_unused cdns_spi_suspend(struct device *dev)
655{
656 struct spi_master *master = dev_get_drvdata(dev);
657
658 return spi_master_suspend(master);
659}
660
661/**
662 * cdns_spi_resume - Resume method for the SPI driver
663 * @dev: Address of the platform_device structure
664 *
665 * This function changes the driver state to "ready"
666 *
667 * Return: 0 on success and error value on error
668 */
669static int __maybe_unused cdns_spi_resume(struct device *dev)
670{
671 struct spi_master *master = dev_get_drvdata(dev);
672 struct cdns_spi *xspi = spi_master_get_devdata(master);
673
674 cdns_spi_init_hw(xspi);
675 return spi_master_resume(master);
676}
677
678/**
679 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
680 * @dev: Address of the platform_device structure
681 *
682 * This function enables the clocks
683 *
684 * Return: 0 on success and error value on error
685 */
686static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
687{
688 struct spi_master *master = dev_get_drvdata(dev);
689 struct cdns_spi *xspi = spi_master_get_devdata(master);
690 int ret;
691
692 ret = clk_prepare_enable(xspi->pclk);
693 if (ret) {
694 dev_err(dev, "Cannot enable APB clock.\n");
695 return ret;
696 }
697
698 ret = clk_prepare_enable(xspi->ref_clk);
699 if (ret) {
700 dev_err(dev, "Cannot enable device clock.\n");
701 clk_disable_unprepare(xspi->pclk);
702 return ret;
703 }
704 return 0;
705}
706
707/**
708 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
709 * @dev: Address of the platform_device structure
710 *
711 * This function disables the clocks
712 *
713 * Return: Always 0
714 */
715static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
716{
717 struct spi_master *master = dev_get_drvdata(dev);
718 struct cdns_spi *xspi = spi_master_get_devdata(master);
719
720 clk_disable_unprepare(xspi->ref_clk);
721 clk_disable_unprepare(xspi->pclk);
722
723 return 0;
724}
725
726static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
727 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
728 cdns_spi_runtime_resume, NULL)
729 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
730};
731
732static const struct of_device_id cdns_spi_of_match[] = {
733 { .compatible = "xlnx,zynq-spi-r1p6" },
734 { .compatible = "cdns,spi-r1p6" },
735 { /* end of table */ }
736};
737MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
738
739/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
740static struct platform_driver cdns_spi_driver = {
741 .probe = cdns_spi_probe,
742 .remove = cdns_spi_remove,
743 .driver = {
744 .name = CDNS_SPI_NAME,
745 .of_match_table = cdns_spi_of_match,
746 .pm = &cdns_spi_dev_pm_ops,
747 },
748};
749
750module_platform_driver(cdns_spi_driver);
751
752MODULE_AUTHOR("Xilinx, Inc.");
753MODULE_DESCRIPTION("Cadence SPI driver");
754MODULE_LICENSE("GPL");