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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (host and target mode)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22#include <linux/spi/spi.h>
23
24/* Name of this driver */
25#define CDNS_SPI_NAME "cdns-spi"
26
27/* Register offset definitions */
28#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
29#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
30#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
31#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
32#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
33#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
34#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
35#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
36#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
37#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
38#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
39
40#define SPI_AUTOSUSPEND_TIMEOUT 3000
41/*
42 * SPI Configuration Register bit Masks
43 *
44 * This register contains various control bits that affect the operation
45 * of the SPI controller
46 */
47#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
48#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
49#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
50#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
51#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
52#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
53#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
54#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
55#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
56#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
57#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
58 CDNS_SPI_CR_SSCTRL | \
59 CDNS_SPI_CR_SSFORCE | \
60 CDNS_SPI_CR_BAUD_DIV_4)
61
62/*
63 * SPI Configuration Register - Baud rate and target select
64 *
65 * These are the values used in the calculation of baud rate divisor and
66 * setting the target select.
67 */
68
69#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
70#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
71#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
72#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
73#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
74#define CDNS_SPI_NOSS 0xF /* No Slave select */
75
76/*
77 * SPI Interrupt Registers bit Masks
78 *
79 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
80 * bit definitions.
81 */
82#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
84#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
85#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
86 CDNS_SPI_IXR_MODF)
87#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
88#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
89
90/*
91 * SPI Enable Register bit Masks
92 *
93 * This register is used to enable or disable the SPI controller
94 */
95#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
96#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
97
98/* Default number of chip select lines */
99#define CDNS_SPI_DEFAULT_NUM_CS 4
100
101/**
102 * struct cdns_spi - This definition defines spi driver instance
103 * @regs: Virtual address of the SPI controller registers
104 * @ref_clk: Pointer to the peripheral clock
105 * @pclk: Pointer to the APB clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
107 * @speed_hz: Current SPI bus clock speed in Hz
108 * @txbuf: Pointer to the TX buffer
109 * @rxbuf: Pointer to the RX buffer
110 * @tx_bytes: Number of bytes left to transfer
111 * @rx_bytes: Number of bytes requested
112 * @dev_busy: Device busy flag
113 * @is_decoded_cs: Flag for decoder property set or not
114 * @tx_fifo_depth: Depth of the TX FIFO
115 * @rstc: Optional reset control for SPI controller
116 */
117struct cdns_spi {
118 void __iomem *regs;
119 struct clk *ref_clk;
120 struct clk *pclk;
121 unsigned int clk_rate;
122 u32 speed_hz;
123 const u8 *txbuf;
124 u8 *rxbuf;
125 int tx_bytes;
126 int rx_bytes;
127 u8 dev_busy;
128 u32 is_decoded_cs;
129 unsigned int tx_fifo_depth;
130 struct reset_control *rstc;
131};
132
133/* Macros for the SPI controller read/write */
134static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
135{
136 return readl_relaxed(xspi->regs + offset);
137}
138
139static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
140{
141 writel_relaxed(val, xspi->regs + offset);
142}
143
144/**
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
146 * @xspi: Pointer to the cdns_spi structure
147 * @is_target: Flag to indicate target or host mode
148 * * On reset the SPI controller is configured to target or host mode.
149 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
150 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
151 *
152 * This function initializes the SPI controller to disable and clear all the
153 * interrupts, enable manual target select and manual start, deselect all the
154 * chip select lines, and enable the SPI controller.
155 */
156static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
157{
158 u32 ctrl_reg = 0;
159
160 if (!is_target)
161 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
162
163 if (xspi->is_decoded_cs)
164 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
165
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
167 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
168
169 /* Clear the RX FIFO */
170 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
171 cdns_spi_read(xspi, CDNS_SPI_RXD);
172
173 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
174 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
175 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
176}
177
178/**
179 * cdns_spi_chipselect - Select or deselect the chip select line
180 * @spi: Pointer to the spi_device structure
181 * @is_high: Select(0) or deselect (1) the chip select line
182 */
183static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
184{
185 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
186 u32 ctrl_reg;
187
188 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
189
190 if (is_high) {
191 /* Deselect the target */
192 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
193 } else {
194 /* Select the target */
195 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
196 if (!(xspi->is_decoded_cs))
197 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
198 CDNS_SPI_SS_SHIFT) &
199 CDNS_SPI_CR_SSCTRL;
200 else
201 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
202 CDNS_SPI_CR_SSCTRL;
203 }
204
205 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
206}
207
208/**
209 * cdns_spi_config_clock_mode - Sets clock polarity and phase
210 * @spi: Pointer to the spi_device structure
211 *
212 * Sets the requested clock polarity and phase.
213 */
214static void cdns_spi_config_clock_mode(struct spi_device *spi)
215{
216 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
217 u32 ctrl_reg, new_ctrl_reg;
218
219 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
220 ctrl_reg = new_ctrl_reg;
221
222 /* Set the SPI clock phase and clock polarity */
223 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
224 if (spi->mode & SPI_CPHA)
225 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
226 if (spi->mode & SPI_CPOL)
227 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
228
229 if (new_ctrl_reg != ctrl_reg) {
230 /*
231 * Just writing the CR register does not seem to apply the clock
232 * setting changes. This is problematic when changing the clock
233 * polarity as it will cause the SPI target to see spurious clock
234 * transitions. To workaround the issue toggle the ER register.
235 */
236 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
237 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
238 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
239 }
240}
241
242/**
243 * cdns_spi_config_clock_freq - Sets clock frequency
244 * @spi: Pointer to the spi_device structure
245 * @transfer: Pointer to the spi_transfer structure which provides
246 * information about next transfer setup parameters
247 *
248 * Sets the requested clock frequency.
249 * Note: If the requested frequency is not an exact match with what can be
250 * obtained using the prescalar value the driver sets the clock frequency which
251 * is lower than the requested frequency (maximum lower) for the transfer. If
252 * the requested frequency is higher or lower than that is supported by the SPI
253 * controller the driver will set the highest or lowest frequency supported by
254 * controller.
255 */
256static void cdns_spi_config_clock_freq(struct spi_device *spi,
257 struct spi_transfer *transfer)
258{
259 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
260 u32 ctrl_reg, baud_rate_val;
261 unsigned long frequency;
262
263 frequency = xspi->clk_rate;
264
265 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
266
267 /* Set the clock frequency */
268 if (xspi->speed_hz != transfer->speed_hz) {
269 /* first valid value is 1 */
270 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
271 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
272 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
273 baud_rate_val++;
274
275 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
276 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
277
278 xspi->speed_hz = frequency / (2 << baud_rate_val);
279 }
280 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
281}
282
283/**
284 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
285 * @spi: Pointer to the spi_device structure
286 * @transfer: Pointer to the spi_transfer structure which provides
287 * information about next transfer setup parameters
288 *
289 * Sets the operational mode of SPI controller for the next SPI transfer and
290 * sets the requested clock frequency.
291 *
292 * Return: Always 0
293 */
294static int cdns_spi_setup_transfer(struct spi_device *spi,
295 struct spi_transfer *transfer)
296{
297 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
298
299 cdns_spi_config_clock_freq(spi, transfer);
300
301 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
302 __func__, spi->mode, spi->bits_per_word,
303 xspi->speed_hz);
304
305 return 0;
306}
307
308/**
309 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
310 * @xspi: Pointer to the cdns_spi structure
311 * @ntx: Number of bytes to pack into the TX FIFO
312 * @nrx: Number of bytes to drain from the RX FIFO
313 */
314static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
315{
316 ntx = clamp(ntx, 0, xspi->tx_bytes);
317 nrx = clamp(nrx, 0, xspi->rx_bytes);
318
319 xspi->tx_bytes -= ntx;
320 xspi->rx_bytes -= nrx;
321
322 while (ntx || nrx) {
323 if (nrx) {
324 u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
325
326 if (xspi->rxbuf)
327 *xspi->rxbuf++ = data;
328
329 nrx--;
330 }
331
332 if (ntx) {
333 if (xspi->txbuf)
334 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
335 else
336 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
337
338 ntx--;
339 }
340
341 }
342}
343
344/**
345 * cdns_spi_irq - Interrupt service routine of the SPI controller
346 * @irq: IRQ number
347 * @dev_id: Pointer to the xspi structure
348 *
349 * This function handles TX empty and Mode Fault interrupts only.
350 * On TX empty interrupt this function reads the received data from RX FIFO and
351 * fills the TX FIFO if there is any data remaining to be transferred.
352 * On Mode Fault interrupt this function indicates that transfer is completed,
353 * the SPI subsystem will identify the error as the remaining bytes to be
354 * transferred is non-zero.
355 *
356 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
357 */
358static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
359{
360 struct spi_controller *ctlr = dev_id;
361 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
362 irqreturn_t status;
363 u32 intr_status;
364
365 status = IRQ_NONE;
366 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
367 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
368
369 if (intr_status & CDNS_SPI_IXR_MODF) {
370 /* Indicate that transfer is completed, the SPI subsystem will
371 * identify the error as the remaining bytes to be
372 * transferred is non-zero
373 */
374 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
375 spi_finalize_current_transfer(ctlr);
376 status = IRQ_HANDLED;
377 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
378 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
379 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
380
381 if (threshold > 1)
382 trans_cnt -= threshold;
383
384 /* Set threshold to one if number of pending are
385 * less than half fifo
386 */
387 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
388 cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
389
390 if (xspi->tx_bytes) {
391 cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
392 } else {
393 /* Fixed delay due to controller limitation with
394 * RX_NEMPTY incorrect status
395 * Xilinx AR:65885 contains more details
396 */
397 udelay(10);
398 cdns_spi_process_fifo(xspi, 0, trans_cnt);
399 cdns_spi_write(xspi, CDNS_SPI_IDR,
400 CDNS_SPI_IXR_DEFAULT);
401 spi_finalize_current_transfer(ctlr);
402 }
403 status = IRQ_HANDLED;
404 }
405
406 return status;
407}
408
409static int cdns_prepare_message(struct spi_controller *ctlr,
410 struct spi_message *msg)
411{
412 if (!spi_controller_is_target(ctlr))
413 cdns_spi_config_clock_mode(msg->spi);
414 return 0;
415}
416
417/**
418 * cdns_transfer_one - Initiates the SPI transfer
419 * @ctlr: Pointer to spi_controller structure
420 * @spi: Pointer to the spi_device structure
421 * @transfer: Pointer to the spi_transfer structure which provides
422 * information about next transfer parameters
423 *
424 * This function in host mode fills the TX FIFO, starts the SPI transfer and
425 * returns a positive transfer count so that core will wait for completion.
426 * This function in target mode fills the TX FIFO and wait for transfer trigger.
427 *
428 * Return: Number of bytes transferred in the last transfer
429 */
430static int cdns_transfer_one(struct spi_controller *ctlr,
431 struct spi_device *spi,
432 struct spi_transfer *transfer)
433{
434 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
435
436 xspi->txbuf = transfer->tx_buf;
437 xspi->rxbuf = transfer->rx_buf;
438 xspi->tx_bytes = transfer->len;
439 xspi->rx_bytes = transfer->len;
440
441 if (!spi_controller_is_target(ctlr)) {
442 cdns_spi_setup_transfer(spi, transfer);
443 } else {
444 /* Set TX empty threshold to half of FIFO depth
445 * only if TX bytes are more than FIFO depth.
446 */
447 if (xspi->tx_bytes > xspi->tx_fifo_depth)
448 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
449 }
450
451 /* When xspi in busy condition, bytes may send failed,
452 * then spi control didn't work thoroughly, add one byte delay
453 */
454 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
455 udelay(10);
456
457 cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
458
459 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
460 return transfer->len;
461}
462
463/**
464 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
465 * @ctlr: Pointer to the spi_controller structure which provides
466 * information about the controller.
467 *
468 * This function enables SPI host controller.
469 *
470 * Return: 0 always
471 */
472static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
473{
474 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
475
476 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
477
478 return 0;
479}
480
481/**
482 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
483 * @ctlr: Pointer to the spi_controller structure which provides
484 * information about the controller.
485 *
486 * This function disables the SPI host controller when no target selected.
487 * This function flush out if any pending data in FIFO.
488 *
489 * Return: 0 always
490 */
491static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
492{
493 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
494 u32 ctrl_reg;
495 unsigned int cnt = xspi->tx_fifo_depth;
496
497 if (spi_controller_is_target(ctlr)) {
498 while (cnt--)
499 cdns_spi_read(xspi, CDNS_SPI_RXD);
500 }
501
502 /* Disable the SPI if target is deselected */
503 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
504 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
505 if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
506 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
507
508 /* Reset to default */
509 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
510 return 0;
511}
512
513/**
514 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
515 * @xspi: Pointer to the cdns_spi structure
516 *
517 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
518 * IP. The FIFO threshold register is sized so that its maximum value can be the
519 * FIFO size - 1. This is used to detect the size of the FIFO.
520 */
521static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
522{
523 /* The MSBs will get truncated giving us the size of the FIFO */
524 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
525 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
526
527 /* Reset to default */
528 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
529}
530
531/**
532 * cdns_target_abort - Abort target transfer
533 * @ctlr: Pointer to the spi_controller structure
534 *
535 * This function abort target transfer if there any transfer timeout.
536 *
537 * Return: 0 always
538 */
539static int cdns_target_abort(struct spi_controller *ctlr)
540{
541 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
542 u32 intr_status;
543
544 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
545 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
546 cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
547 spi_finalize_current_transfer(ctlr);
548
549 return 0;
550}
551
552/**
553 * cdns_spi_probe - Probe method for the SPI driver
554 * @pdev: Pointer to the platform_device structure
555 *
556 * This function initializes the driver data structures and the hardware.
557 *
558 * Return: 0 on success and error value on error
559 */
560static int cdns_spi_probe(struct platform_device *pdev)
561{
562 int ret = 0, irq;
563 struct spi_controller *ctlr;
564 struct cdns_spi *xspi;
565 u32 num_cs;
566 bool target;
567
568 target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
569 if (target)
570 ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
571 else
572 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
573
574 if (!ctlr)
575 return -ENOMEM;
576
577 xspi = spi_controller_get_devdata(ctlr);
578 ctlr->dev.of_node = pdev->dev.of_node;
579 platform_set_drvdata(pdev, ctlr);
580
581 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
582 if (IS_ERR(xspi->regs)) {
583 ret = PTR_ERR(xspi->regs);
584 goto remove_ctlr;
585 }
586
587 xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
588 if (IS_ERR(xspi->pclk)) {
589 dev_err(&pdev->dev, "pclk clock not found.\n");
590 ret = PTR_ERR(xspi->pclk);
591 goto remove_ctlr;
592 }
593
594 xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
595 if (IS_ERR(xspi->rstc)) {
596 ret = dev_err_probe(&pdev->dev, PTR_ERR(xspi->rstc),
597 "Cannot get SPI reset.\n");
598 goto remove_ctlr;
599 }
600
601 reset_control_assert(xspi->rstc);
602 reset_control_deassert(xspi->rstc);
603
604 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
605 if (IS_ERR(xspi->ref_clk)) {
606 dev_err(&pdev->dev, "ref_clk clock not found.\n");
607 ret = PTR_ERR(xspi->ref_clk);
608 goto remove_ctlr;
609 }
610
611 if (!spi_controller_is_target(ctlr)) {
612 pm_runtime_use_autosuspend(&pdev->dev);
613 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
614 pm_runtime_get_noresume(&pdev->dev);
615 pm_runtime_set_active(&pdev->dev);
616 pm_runtime_enable(&pdev->dev);
617
618 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
619 if (ret < 0)
620 ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
621 else
622 ctlr->num_chipselect = num_cs;
623
624 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
625 &xspi->is_decoded_cs);
626 if (ret < 0)
627 xspi->is_decoded_cs = 0;
628 }
629
630 cdns_spi_detect_fifo_depth(xspi);
631
632 /* SPI controller initializations */
633 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
634
635 irq = platform_get_irq(pdev, 0);
636 if (irq < 0) {
637 ret = irq;
638 goto clk_dis_all;
639 }
640
641 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
642 0, pdev->name, ctlr);
643 if (ret != 0) {
644 ret = -ENXIO;
645 dev_err(&pdev->dev, "request_irq failed\n");
646 goto clk_dis_all;
647 }
648
649 ctlr->use_gpio_descriptors = true;
650 ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
651 ctlr->prepare_message = cdns_prepare_message;
652 ctlr->transfer_one = cdns_transfer_one;
653 ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
654 ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
655 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
656
657 if (!spi_controller_is_target(ctlr)) {
658 ctlr->mode_bits |= SPI_CS_HIGH;
659 ctlr->set_cs = cdns_spi_chipselect;
660 ctlr->auto_runtime_pm = true;
661 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
662 /* Set to default valid value */
663 ctlr->max_speed_hz = xspi->clk_rate / 4;
664 xspi->speed_hz = ctlr->max_speed_hz;
665 pm_runtime_mark_last_busy(&pdev->dev);
666 pm_runtime_put_autosuspend(&pdev->dev);
667 } else {
668 ctlr->mode_bits |= SPI_NO_CS;
669 ctlr->target_abort = cdns_target_abort;
670 }
671 ret = spi_register_controller(ctlr);
672 if (ret) {
673 dev_err(&pdev->dev, "spi_register_controller failed\n");
674 goto clk_dis_all;
675 }
676
677 return ret;
678
679clk_dis_all:
680 if (!spi_controller_is_target(ctlr)) {
681 pm_runtime_disable(&pdev->dev);
682 pm_runtime_set_suspended(&pdev->dev);
683 }
684remove_ctlr:
685 spi_controller_put(ctlr);
686 return ret;
687}
688
689/**
690 * cdns_spi_remove - Remove method for the SPI driver
691 * @pdev: Pointer to the platform_device structure
692 *
693 * This function is called if a device is physically removed from the system or
694 * if the driver module is being unloaded. It frees all resources allocated to
695 * the device.
696 */
697static void cdns_spi_remove(struct platform_device *pdev)
698{
699 struct spi_controller *ctlr = platform_get_drvdata(pdev);
700 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
701
702 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
703
704 if (!spi_controller_is_target(ctlr)) {
705 pm_runtime_disable(&pdev->dev);
706 pm_runtime_set_suspended(&pdev->dev);
707 }
708
709 spi_unregister_controller(ctlr);
710}
711
712/**
713 * cdns_spi_suspend - Suspend method for the SPI driver
714 * @dev: Address of the platform_device structure
715 *
716 * This function disables the SPI controller and
717 * changes the driver state to "suspend"
718 *
719 * Return: 0 on success and error value on error
720 */
721static int __maybe_unused cdns_spi_suspend(struct device *dev)
722{
723 struct spi_controller *ctlr = dev_get_drvdata(dev);
724
725 return spi_controller_suspend(ctlr);
726}
727
728/**
729 * cdns_spi_resume - Resume method for the SPI driver
730 * @dev: Address of the platform_device structure
731 *
732 * This function changes the driver state to "ready"
733 *
734 * Return: 0 on success and error value on error
735 */
736static int __maybe_unused cdns_spi_resume(struct device *dev)
737{
738 struct spi_controller *ctlr = dev_get_drvdata(dev);
739 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
740
741 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
742 return spi_controller_resume(ctlr);
743}
744
745/**
746 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
747 * @dev: Address of the platform_device structure
748 *
749 * This function enables the clocks
750 *
751 * Return: 0 on success and error value on error
752 */
753static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
754{
755 struct spi_controller *ctlr = dev_get_drvdata(dev);
756 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
757 int ret;
758
759 ret = clk_prepare_enable(xspi->pclk);
760 if (ret) {
761 dev_err(dev, "Cannot enable APB clock.\n");
762 return ret;
763 }
764
765 ret = clk_prepare_enable(xspi->ref_clk);
766 if (ret) {
767 dev_err(dev, "Cannot enable device clock.\n");
768 clk_disable_unprepare(xspi->pclk);
769 return ret;
770 }
771 return 0;
772}
773
774/**
775 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
776 * @dev: Address of the platform_device structure
777 *
778 * This function disables the clocks
779 *
780 * Return: Always 0
781 */
782static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
783{
784 struct spi_controller *ctlr = dev_get_drvdata(dev);
785 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
786
787 clk_disable_unprepare(xspi->ref_clk);
788 clk_disable_unprepare(xspi->pclk);
789
790 return 0;
791}
792
793static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
794 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
795 cdns_spi_runtime_resume, NULL)
796 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
797};
798
799static const struct of_device_id cdns_spi_of_match[] = {
800 { .compatible = "xlnx,zynq-spi-r1p6" },
801 { .compatible = "cdns,spi-r1p6" },
802 { /* end of table */ }
803};
804MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
805
806/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
807static struct platform_driver cdns_spi_driver = {
808 .probe = cdns_spi_probe,
809 .remove = cdns_spi_remove,
810 .driver = {
811 .name = CDNS_SPI_NAME,
812 .of_match_table = cdns_spi_of_match,
813 .pm = &cdns_spi_dev_pm_ops,
814 },
815};
816
817module_platform_driver(cdns_spi_driver);
818
819MODULE_AUTHOR("Xilinx, Inc.");
820MODULE_DESCRIPTION("Cadence SPI driver");
821MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (host and target mode)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/spi/spi.h>
22
23/* Name of this driver */
24#define CDNS_SPI_NAME "cdns-spi"
25
26/* Register offset definitions */
27#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
28#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
29#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
30#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
31#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
32#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
33#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
34#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
35#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
36#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
37#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
38
39#define SPI_AUTOSUSPEND_TIMEOUT 3000
40/*
41 * SPI Configuration Register bit Masks
42 *
43 * This register contains various control bits that affect the operation
44 * of the SPI controller
45 */
46#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
47#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
48#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
49#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
50#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
51#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
52#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
53#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
54#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
55#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
56#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
57 CDNS_SPI_CR_SSCTRL | \
58 CDNS_SPI_CR_SSFORCE | \
59 CDNS_SPI_CR_BAUD_DIV_4)
60
61/*
62 * SPI Configuration Register - Baud rate and target select
63 *
64 * These are the values used in the calculation of baud rate divisor and
65 * setting the target select.
66 */
67
68#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
69#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
70#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
71#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
72#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
73#define CDNS_SPI_NOSS 0xF /* No Slave select */
74
75/*
76 * SPI Interrupt Registers bit Masks
77 *
78 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
79 * bit definitions.
80 */
81#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
82#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
83#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
84#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
85 CDNS_SPI_IXR_MODF)
86#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
87#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
88
89/*
90 * SPI Enable Register bit Masks
91 *
92 * This register is used to enable or disable the SPI controller
93 */
94#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
95#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
96
97/* Default number of chip select lines */
98#define CDNS_SPI_DEFAULT_NUM_CS 4
99
100/**
101 * struct cdns_spi - This definition defines spi driver instance
102 * @regs: Virtual address of the SPI controller registers
103 * @ref_clk: Pointer to the peripheral clock
104 * @pclk: Pointer to the APB clock
105 * @clk_rate: Reference clock frequency, taken from @ref_clk
106 * @speed_hz: Current SPI bus clock speed in Hz
107 * @txbuf: Pointer to the TX buffer
108 * @rxbuf: Pointer to the RX buffer
109 * @tx_bytes: Number of bytes left to transfer
110 * @rx_bytes: Number of bytes requested
111 * @dev_busy: Device busy flag
112 * @is_decoded_cs: Flag for decoder property set or not
113 * @tx_fifo_depth: Depth of the TX FIFO
114 */
115struct cdns_spi {
116 void __iomem *regs;
117 struct clk *ref_clk;
118 struct clk *pclk;
119 unsigned int clk_rate;
120 u32 speed_hz;
121 const u8 *txbuf;
122 u8 *rxbuf;
123 int tx_bytes;
124 int rx_bytes;
125 u8 dev_busy;
126 u32 is_decoded_cs;
127 unsigned int tx_fifo_depth;
128};
129
130/* Macros for the SPI controller read/write */
131static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
132{
133 return readl_relaxed(xspi->regs + offset);
134}
135
136static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
137{
138 writel_relaxed(val, xspi->regs + offset);
139}
140
141/**
142 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
143 * @xspi: Pointer to the cdns_spi structure
144 * @is_target: Flag to indicate target or host mode
145 * * On reset the SPI controller is configured to target or host mode.
146 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
147 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
148 *
149 * This function initializes the SPI controller to disable and clear all the
150 * interrupts, enable manual target select and manual start, deselect all the
151 * chip select lines, and enable the SPI controller.
152 */
153static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
154{
155 u32 ctrl_reg = 0;
156
157 if (!is_target)
158 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
159
160 if (xspi->is_decoded_cs)
161 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
162
163 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
164 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
165
166 /* Clear the RX FIFO */
167 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
168 cdns_spi_read(xspi, CDNS_SPI_RXD);
169
170 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
171 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
172 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
173}
174
175/**
176 * cdns_spi_chipselect - Select or deselect the chip select line
177 * @spi: Pointer to the spi_device structure
178 * @is_high: Select(0) or deselect (1) the chip select line
179 */
180static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
181{
182 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
183 u32 ctrl_reg;
184
185 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
186
187 if (is_high) {
188 /* Deselect the target */
189 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
190 } else {
191 /* Select the target */
192 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
193 if (!(xspi->is_decoded_cs))
194 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
195 CDNS_SPI_SS_SHIFT) &
196 CDNS_SPI_CR_SSCTRL;
197 else
198 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
199 CDNS_SPI_CR_SSCTRL;
200 }
201
202 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
203}
204
205/**
206 * cdns_spi_config_clock_mode - Sets clock polarity and phase
207 * @spi: Pointer to the spi_device structure
208 *
209 * Sets the requested clock polarity and phase.
210 */
211static void cdns_spi_config_clock_mode(struct spi_device *spi)
212{
213 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
214 u32 ctrl_reg, new_ctrl_reg;
215
216 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
217 ctrl_reg = new_ctrl_reg;
218
219 /* Set the SPI clock phase and clock polarity */
220 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
221 if (spi->mode & SPI_CPHA)
222 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
223 if (spi->mode & SPI_CPOL)
224 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
225
226 if (new_ctrl_reg != ctrl_reg) {
227 /*
228 * Just writing the CR register does not seem to apply the clock
229 * setting changes. This is problematic when changing the clock
230 * polarity as it will cause the SPI target to see spurious clock
231 * transitions. To workaround the issue toggle the ER register.
232 */
233 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
234 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
235 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
236 }
237}
238
239/**
240 * cdns_spi_config_clock_freq - Sets clock frequency
241 * @spi: Pointer to the spi_device structure
242 * @transfer: Pointer to the spi_transfer structure which provides
243 * information about next transfer setup parameters
244 *
245 * Sets the requested clock frequency.
246 * Note: If the requested frequency is not an exact match with what can be
247 * obtained using the prescalar value the driver sets the clock frequency which
248 * is lower than the requested frequency (maximum lower) for the transfer. If
249 * the requested frequency is higher or lower than that is supported by the SPI
250 * controller the driver will set the highest or lowest frequency supported by
251 * controller.
252 */
253static void cdns_spi_config_clock_freq(struct spi_device *spi,
254 struct spi_transfer *transfer)
255{
256 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
257 u32 ctrl_reg, baud_rate_val;
258 unsigned long frequency;
259
260 frequency = xspi->clk_rate;
261
262 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
263
264 /* Set the clock frequency */
265 if (xspi->speed_hz != transfer->speed_hz) {
266 /* first valid value is 1 */
267 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
268 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
270 baud_rate_val++;
271
272 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
273 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
274
275 xspi->speed_hz = frequency / (2 << baud_rate_val);
276 }
277 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
278}
279
280/**
281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
282 * @spi: Pointer to the spi_device structure
283 * @transfer: Pointer to the spi_transfer structure which provides
284 * information about next transfer setup parameters
285 *
286 * Sets the operational mode of SPI controller for the next SPI transfer and
287 * sets the requested clock frequency.
288 *
289 * Return: Always 0
290 */
291static int cdns_spi_setup_transfer(struct spi_device *spi,
292 struct spi_transfer *transfer)
293{
294 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
295
296 cdns_spi_config_clock_freq(spi, transfer);
297
298 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
299 __func__, spi->mode, spi->bits_per_word,
300 xspi->speed_hz);
301
302 return 0;
303}
304
305/**
306 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
307 * @xspi: Pointer to the cdns_spi structure
308 * @ntx: Number of bytes to pack into the TX FIFO
309 * @nrx: Number of bytes to drain from the RX FIFO
310 */
311static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
312{
313 ntx = clamp(ntx, 0, xspi->tx_bytes);
314 nrx = clamp(nrx, 0, xspi->rx_bytes);
315
316 xspi->tx_bytes -= ntx;
317 xspi->rx_bytes -= nrx;
318
319 while (ntx || nrx) {
320 if (nrx) {
321 u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
322
323 if (xspi->rxbuf)
324 *xspi->rxbuf++ = data;
325
326 nrx--;
327 }
328
329 if (ntx) {
330 if (xspi->txbuf)
331 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
332 else
333 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
334
335 ntx--;
336 }
337
338 }
339}
340
341/**
342 * cdns_spi_irq - Interrupt service routine of the SPI controller
343 * @irq: IRQ number
344 * @dev_id: Pointer to the xspi structure
345 *
346 * This function handles TX empty and Mode Fault interrupts only.
347 * On TX empty interrupt this function reads the received data from RX FIFO and
348 * fills the TX FIFO if there is any data remaining to be transferred.
349 * On Mode Fault interrupt this function indicates that transfer is completed,
350 * the SPI subsystem will identify the error as the remaining bytes to be
351 * transferred is non-zero.
352 *
353 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
354 */
355static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
356{
357 struct spi_controller *ctlr = dev_id;
358 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
359 irqreturn_t status;
360 u32 intr_status;
361
362 status = IRQ_NONE;
363 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
364 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
365
366 if (intr_status & CDNS_SPI_IXR_MODF) {
367 /* Indicate that transfer is completed, the SPI subsystem will
368 * identify the error as the remaining bytes to be
369 * transferred is non-zero
370 */
371 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
372 spi_finalize_current_transfer(ctlr);
373 status = IRQ_HANDLED;
374 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
375 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
376 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
377
378 if (threshold > 1)
379 trans_cnt -= threshold;
380
381 /* Set threshold to one if number of pending are
382 * less than half fifo
383 */
384 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
385 cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
386
387 if (xspi->tx_bytes) {
388 cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
389 } else {
390 /* Fixed delay due to controller limitation with
391 * RX_NEMPTY incorrect status
392 * Xilinx AR:65885 contains more details
393 */
394 udelay(10);
395 cdns_spi_process_fifo(xspi, 0, trans_cnt);
396 cdns_spi_write(xspi, CDNS_SPI_IDR,
397 CDNS_SPI_IXR_DEFAULT);
398 spi_finalize_current_transfer(ctlr);
399 }
400 status = IRQ_HANDLED;
401 }
402
403 return status;
404}
405
406static int cdns_prepare_message(struct spi_controller *ctlr,
407 struct spi_message *msg)
408{
409 if (!spi_controller_is_target(ctlr))
410 cdns_spi_config_clock_mode(msg->spi);
411 return 0;
412}
413
414/**
415 * cdns_transfer_one - Initiates the SPI transfer
416 * @ctlr: Pointer to spi_controller structure
417 * @spi: Pointer to the spi_device structure
418 * @transfer: Pointer to the spi_transfer structure which provides
419 * information about next transfer parameters
420 *
421 * This function in host mode fills the TX FIFO, starts the SPI transfer and
422 * returns a positive transfer count so that core will wait for completion.
423 * This function in target mode fills the TX FIFO and wait for transfer trigger.
424 *
425 * Return: Number of bytes transferred in the last transfer
426 */
427static int cdns_transfer_one(struct spi_controller *ctlr,
428 struct spi_device *spi,
429 struct spi_transfer *transfer)
430{
431 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
432
433 xspi->txbuf = transfer->tx_buf;
434 xspi->rxbuf = transfer->rx_buf;
435 xspi->tx_bytes = transfer->len;
436 xspi->rx_bytes = transfer->len;
437
438 if (!spi_controller_is_target(ctlr)) {
439 cdns_spi_setup_transfer(spi, transfer);
440 } else {
441 /* Set TX empty threshold to half of FIFO depth
442 * only if TX bytes are more than FIFO depth.
443 */
444 if (xspi->tx_bytes > xspi->tx_fifo_depth)
445 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
446 }
447
448 /* When xspi in busy condition, bytes may send failed,
449 * then spi control didn't work thoroughly, add one byte delay
450 */
451 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
452 udelay(10);
453
454 cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
455
456 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
457 return transfer->len;
458}
459
460/**
461 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
462 * @ctlr: Pointer to the spi_controller structure which provides
463 * information about the controller.
464 *
465 * This function enables SPI host controller.
466 *
467 * Return: 0 always
468 */
469static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
470{
471 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
472
473 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
474
475 return 0;
476}
477
478/**
479 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
480 * @ctlr: Pointer to the spi_controller structure which provides
481 * information about the controller.
482 *
483 * This function disables the SPI host controller when no target selected.
484 * This function flush out if any pending data in FIFO.
485 *
486 * Return: 0 always
487 */
488static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
489{
490 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
491 u32 ctrl_reg;
492 unsigned int cnt = xspi->tx_fifo_depth;
493
494 if (spi_controller_is_target(ctlr)) {
495 while (cnt--)
496 cdns_spi_read(xspi, CDNS_SPI_RXD);
497 }
498
499 /* Disable the SPI if target is deselected */
500 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
501 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
502 if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
503 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
504
505 /* Reset to default */
506 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
507 return 0;
508}
509
510/**
511 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
512 * @xspi: Pointer to the cdns_spi structure
513 *
514 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
515 * IP. The FIFO threshold register is sized so that its maximum value can be the
516 * FIFO size - 1. This is used to detect the size of the FIFO.
517 */
518static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
519{
520 /* The MSBs will get truncated giving us the size of the FIFO */
521 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
522 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
523
524 /* Reset to default */
525 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
526}
527
528/**
529 * cdns_target_abort - Abort target transfer
530 * @ctlr: Pointer to the spi_controller structure
531 *
532 * This function abort target transfer if there any transfer timeout.
533 *
534 * Return: 0 always
535 */
536static int cdns_target_abort(struct spi_controller *ctlr)
537{
538 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
539 u32 intr_status;
540
541 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
542 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
543 cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
544 spi_finalize_current_transfer(ctlr);
545
546 return 0;
547}
548
549/**
550 * cdns_spi_probe - Probe method for the SPI driver
551 * @pdev: Pointer to the platform_device structure
552 *
553 * This function initializes the driver data structures and the hardware.
554 *
555 * Return: 0 on success and error value on error
556 */
557static int cdns_spi_probe(struct platform_device *pdev)
558{
559 int ret = 0, irq;
560 struct spi_controller *ctlr;
561 struct cdns_spi *xspi;
562 u32 num_cs;
563 bool target;
564
565 target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
566 if (target)
567 ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
568 else
569 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
570
571 if (!ctlr)
572 return -ENOMEM;
573
574 xspi = spi_controller_get_devdata(ctlr);
575 ctlr->dev.of_node = pdev->dev.of_node;
576 platform_set_drvdata(pdev, ctlr);
577
578 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
579 if (IS_ERR(xspi->regs)) {
580 ret = PTR_ERR(xspi->regs);
581 goto remove_ctlr;
582 }
583
584 xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
585 if (IS_ERR(xspi->pclk)) {
586 dev_err(&pdev->dev, "pclk clock not found.\n");
587 ret = PTR_ERR(xspi->pclk);
588 goto remove_ctlr;
589 }
590
591 if (!spi_controller_is_target(ctlr)) {
592 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
593 if (IS_ERR(xspi->ref_clk)) {
594 dev_err(&pdev->dev, "ref_clk clock not found.\n");
595 ret = PTR_ERR(xspi->ref_clk);
596 goto remove_ctlr;
597 }
598
599 pm_runtime_use_autosuspend(&pdev->dev);
600 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
601 pm_runtime_get_noresume(&pdev->dev);
602 pm_runtime_set_active(&pdev->dev);
603 pm_runtime_enable(&pdev->dev);
604
605 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
606 if (ret < 0)
607 ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
608 else
609 ctlr->num_chipselect = num_cs;
610
611 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
612 &xspi->is_decoded_cs);
613 if (ret < 0)
614 xspi->is_decoded_cs = 0;
615 }
616
617 cdns_spi_detect_fifo_depth(xspi);
618
619 /* SPI controller initializations */
620 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
621
622 irq = platform_get_irq(pdev, 0);
623 if (irq < 0) {
624 ret = irq;
625 goto clk_dis_all;
626 }
627
628 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
629 0, pdev->name, ctlr);
630 if (ret != 0) {
631 ret = -ENXIO;
632 dev_err(&pdev->dev, "request_irq failed\n");
633 goto clk_dis_all;
634 }
635
636 ctlr->use_gpio_descriptors = true;
637 ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
638 ctlr->prepare_message = cdns_prepare_message;
639 ctlr->transfer_one = cdns_transfer_one;
640 ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
641 ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
642 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
643
644 if (!spi_controller_is_target(ctlr)) {
645 ctlr->mode_bits |= SPI_CS_HIGH;
646 ctlr->set_cs = cdns_spi_chipselect;
647 ctlr->auto_runtime_pm = true;
648 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
649 /* Set to default valid value */
650 ctlr->max_speed_hz = xspi->clk_rate / 4;
651 xspi->speed_hz = ctlr->max_speed_hz;
652 pm_runtime_mark_last_busy(&pdev->dev);
653 pm_runtime_put_autosuspend(&pdev->dev);
654 } else {
655 ctlr->mode_bits |= SPI_NO_CS;
656 ctlr->target_abort = cdns_target_abort;
657 }
658 ret = spi_register_controller(ctlr);
659 if (ret) {
660 dev_err(&pdev->dev, "spi_register_controller failed\n");
661 goto clk_dis_all;
662 }
663
664 return ret;
665
666clk_dis_all:
667 if (!spi_controller_is_target(ctlr)) {
668 pm_runtime_set_suspended(&pdev->dev);
669 pm_runtime_disable(&pdev->dev);
670 }
671remove_ctlr:
672 spi_controller_put(ctlr);
673 return ret;
674}
675
676/**
677 * cdns_spi_remove - Remove method for the SPI driver
678 * @pdev: Pointer to the platform_device structure
679 *
680 * This function is called if a device is physically removed from the system or
681 * if the driver module is being unloaded. It frees all resources allocated to
682 * the device.
683 */
684static void cdns_spi_remove(struct platform_device *pdev)
685{
686 struct spi_controller *ctlr = platform_get_drvdata(pdev);
687 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
688
689 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
690
691 pm_runtime_set_suspended(&pdev->dev);
692 pm_runtime_disable(&pdev->dev);
693
694 spi_unregister_controller(ctlr);
695}
696
697/**
698 * cdns_spi_suspend - Suspend method for the SPI driver
699 * @dev: Address of the platform_device structure
700 *
701 * This function disables the SPI controller and
702 * changes the driver state to "suspend"
703 *
704 * Return: 0 on success and error value on error
705 */
706static int __maybe_unused cdns_spi_suspend(struct device *dev)
707{
708 struct spi_controller *ctlr = dev_get_drvdata(dev);
709
710 return spi_controller_suspend(ctlr);
711}
712
713/**
714 * cdns_spi_resume - Resume method for the SPI driver
715 * @dev: Address of the platform_device structure
716 *
717 * This function changes the driver state to "ready"
718 *
719 * Return: 0 on success and error value on error
720 */
721static int __maybe_unused cdns_spi_resume(struct device *dev)
722{
723 struct spi_controller *ctlr = dev_get_drvdata(dev);
724 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
725
726 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
727 return spi_controller_resume(ctlr);
728}
729
730/**
731 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
732 * @dev: Address of the platform_device structure
733 *
734 * This function enables the clocks
735 *
736 * Return: 0 on success and error value on error
737 */
738static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
739{
740 struct spi_controller *ctlr = dev_get_drvdata(dev);
741 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
742 int ret;
743
744 ret = clk_prepare_enable(xspi->pclk);
745 if (ret) {
746 dev_err(dev, "Cannot enable APB clock.\n");
747 return ret;
748 }
749
750 ret = clk_prepare_enable(xspi->ref_clk);
751 if (ret) {
752 dev_err(dev, "Cannot enable device clock.\n");
753 clk_disable_unprepare(xspi->pclk);
754 return ret;
755 }
756 return 0;
757}
758
759/**
760 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
761 * @dev: Address of the platform_device structure
762 *
763 * This function disables the clocks
764 *
765 * Return: Always 0
766 */
767static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
768{
769 struct spi_controller *ctlr = dev_get_drvdata(dev);
770 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
771
772 clk_disable_unprepare(xspi->ref_clk);
773 clk_disable_unprepare(xspi->pclk);
774
775 return 0;
776}
777
778static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
779 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
780 cdns_spi_runtime_resume, NULL)
781 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
782};
783
784static const struct of_device_id cdns_spi_of_match[] = {
785 { .compatible = "xlnx,zynq-spi-r1p6" },
786 { .compatible = "cdns,spi-r1p6" },
787 { /* end of table */ }
788};
789MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
790
791/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
792static struct platform_driver cdns_spi_driver = {
793 .probe = cdns_spi_probe,
794 .remove_new = cdns_spi_remove,
795 .driver = {
796 .name = CDNS_SPI_NAME,
797 .of_match_table = cdns_spi_of_match,
798 .pm = &cdns_spi_dev_pm_ops,
799 },
800};
801
802module_platform_driver(cdns_spi_driver);
803
804MODULE_AUTHOR("Xilinx, Inc.");
805MODULE_DESCRIPTION("Cadence SPI driver");
806MODULE_LICENSE("GPL");