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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Core PHY library, taken from phy.c
4 */
5#include <linux/export.h>
6#include <linux/phy.h>
7#include <linux/of.h>
8
9/**
10 * phy_speed_to_str - Return a string representing the PHY link speed
11 *
12 * @speed: Speed of the link
13 */
14const char *phy_speed_to_str(int speed)
15{
16 BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103,
17 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
18 "If a speed or mode has been added please update phy_speed_to_str "
19 "and the PHY settings array.\n");
20
21 switch (speed) {
22 case SPEED_10:
23 return "10Mbps";
24 case SPEED_100:
25 return "100Mbps";
26 case SPEED_1000:
27 return "1Gbps";
28 case SPEED_2500:
29 return "2.5Gbps";
30 case SPEED_5000:
31 return "5Gbps";
32 case SPEED_10000:
33 return "10Gbps";
34 case SPEED_14000:
35 return "14Gbps";
36 case SPEED_20000:
37 return "20Gbps";
38 case SPEED_25000:
39 return "25Gbps";
40 case SPEED_40000:
41 return "40Gbps";
42 case SPEED_50000:
43 return "50Gbps";
44 case SPEED_56000:
45 return "56Gbps";
46 case SPEED_100000:
47 return "100Gbps";
48 case SPEED_200000:
49 return "200Gbps";
50 case SPEED_400000:
51 return "400Gbps";
52 case SPEED_800000:
53 return "800Gbps";
54 case SPEED_UNKNOWN:
55 return "Unknown";
56 default:
57 return "Unsupported (update phy-core.c)";
58 }
59}
60EXPORT_SYMBOL_GPL(phy_speed_to_str);
61
62/**
63 * phy_duplex_to_str - Return string describing the duplex
64 *
65 * @duplex: Duplex setting to describe
66 */
67const char *phy_duplex_to_str(unsigned int duplex)
68{
69 if (duplex == DUPLEX_HALF)
70 return "Half";
71 if (duplex == DUPLEX_FULL)
72 return "Full";
73 if (duplex == DUPLEX_UNKNOWN)
74 return "Unknown";
75 return "Unsupported (update phy-core.c)";
76}
77EXPORT_SYMBOL_GPL(phy_duplex_to_str);
78
79/**
80 * phy_rate_matching_to_str - Return a string describing the rate matching
81 *
82 * @rate_matching: Type of rate matching to describe
83 */
84const char *phy_rate_matching_to_str(int rate_matching)
85{
86 switch (rate_matching) {
87 case RATE_MATCH_NONE:
88 return "none";
89 case RATE_MATCH_PAUSE:
90 return "pause";
91 case RATE_MATCH_CRS:
92 return "crs";
93 case RATE_MATCH_OPEN_LOOP:
94 return "open-loop";
95 }
96 return "Unsupported (update phy-core.c)";
97}
98EXPORT_SYMBOL_GPL(phy_rate_matching_to_str);
99
100/**
101 * phy_interface_num_ports - Return the number of links that can be carried by
102 * a given MAC-PHY physical link. Returns 0 if this is
103 * unknown, the number of links else.
104 *
105 * @interface: The interface mode we want to get the number of ports
106 */
107int phy_interface_num_ports(phy_interface_t interface)
108{
109 switch (interface) {
110 case PHY_INTERFACE_MODE_NA:
111 return 0;
112 case PHY_INTERFACE_MODE_INTERNAL:
113 case PHY_INTERFACE_MODE_MII:
114 case PHY_INTERFACE_MODE_GMII:
115 case PHY_INTERFACE_MODE_TBI:
116 case PHY_INTERFACE_MODE_REVMII:
117 case PHY_INTERFACE_MODE_RMII:
118 case PHY_INTERFACE_MODE_REVRMII:
119 case PHY_INTERFACE_MODE_RGMII:
120 case PHY_INTERFACE_MODE_RGMII_ID:
121 case PHY_INTERFACE_MODE_RGMII_RXID:
122 case PHY_INTERFACE_MODE_RGMII_TXID:
123 case PHY_INTERFACE_MODE_RTBI:
124 case PHY_INTERFACE_MODE_XGMII:
125 case PHY_INTERFACE_MODE_XLGMII:
126 case PHY_INTERFACE_MODE_MOCA:
127 case PHY_INTERFACE_MODE_TRGMII:
128 case PHY_INTERFACE_MODE_USXGMII:
129 case PHY_INTERFACE_MODE_SGMII:
130 case PHY_INTERFACE_MODE_SMII:
131 case PHY_INTERFACE_MODE_1000BASEX:
132 case PHY_INTERFACE_MODE_2500BASEX:
133 case PHY_INTERFACE_MODE_5GBASER:
134 case PHY_INTERFACE_MODE_10GBASER:
135 case PHY_INTERFACE_MODE_25GBASER:
136 case PHY_INTERFACE_MODE_10GKR:
137 case PHY_INTERFACE_MODE_100BASEX:
138 case PHY_INTERFACE_MODE_RXAUI:
139 case PHY_INTERFACE_MODE_XAUI:
140 case PHY_INTERFACE_MODE_1000BASEKX:
141 return 1;
142 case PHY_INTERFACE_MODE_QSGMII:
143 case PHY_INTERFACE_MODE_QUSGMII:
144 case PHY_INTERFACE_MODE_10G_QXGMII:
145 return 4;
146 case PHY_INTERFACE_MODE_PSGMII:
147 return 5;
148 case PHY_INTERFACE_MODE_MAX:
149 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
150 return 0;
151 }
152 return 0;
153}
154EXPORT_SYMBOL_GPL(phy_interface_num_ports);
155
156/* A mapping of all SUPPORTED settings to speed/duplex. This table
157 * must be grouped by speed and sorted in descending match priority
158 * - iow, descending speed.
159 */
160
161#define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \
162 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
163
164static const struct phy_setting settings[] = {
165 /* 800G */
166 PHY_SETTING( 800000, FULL, 800000baseCR8_Full ),
167 PHY_SETTING( 800000, FULL, 800000baseKR8_Full ),
168 PHY_SETTING( 800000, FULL, 800000baseDR8_Full ),
169 PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ),
170 PHY_SETTING( 800000, FULL, 800000baseSR8_Full ),
171 PHY_SETTING( 800000, FULL, 800000baseVR8_Full ),
172 /* 400G */
173 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
174 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
175 PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
176 PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
177 PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
178 PHY_SETTING( 400000, FULL, 400000baseCR4_Full ),
179 PHY_SETTING( 400000, FULL, 400000baseKR4_Full ),
180 PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ),
181 PHY_SETTING( 400000, FULL, 400000baseDR4_Full ),
182 PHY_SETTING( 400000, FULL, 400000baseSR4_Full ),
183 /* 200G */
184 PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
185 PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
186 PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ),
187 PHY_SETTING( 200000, FULL, 200000baseDR4_Full ),
188 PHY_SETTING( 200000, FULL, 200000baseSR4_Full ),
189 PHY_SETTING( 200000, FULL, 200000baseCR2_Full ),
190 PHY_SETTING( 200000, FULL, 200000baseKR2_Full ),
191 PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ),
192 PHY_SETTING( 200000, FULL, 200000baseDR2_Full ),
193 PHY_SETTING( 200000, FULL, 200000baseSR2_Full ),
194 /* 100G */
195 PHY_SETTING( 100000, FULL, 100000baseCR4_Full ),
196 PHY_SETTING( 100000, FULL, 100000baseKR4_Full ),
197 PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ),
198 PHY_SETTING( 100000, FULL, 100000baseSR4_Full ),
199 PHY_SETTING( 100000, FULL, 100000baseCR2_Full ),
200 PHY_SETTING( 100000, FULL, 100000baseKR2_Full ),
201 PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ),
202 PHY_SETTING( 100000, FULL, 100000baseDR2_Full ),
203 PHY_SETTING( 100000, FULL, 100000baseSR2_Full ),
204 PHY_SETTING( 100000, FULL, 100000baseCR_Full ),
205 PHY_SETTING( 100000, FULL, 100000baseKR_Full ),
206 PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ),
207 PHY_SETTING( 100000, FULL, 100000baseDR_Full ),
208 PHY_SETTING( 100000, FULL, 100000baseSR_Full ),
209 /* 56G */
210 PHY_SETTING( 56000, FULL, 56000baseCR4_Full ),
211 PHY_SETTING( 56000, FULL, 56000baseKR4_Full ),
212 PHY_SETTING( 56000, FULL, 56000baseLR4_Full ),
213 PHY_SETTING( 56000, FULL, 56000baseSR4_Full ),
214 /* 50G */
215 PHY_SETTING( 50000, FULL, 50000baseCR2_Full ),
216 PHY_SETTING( 50000, FULL, 50000baseKR2_Full ),
217 PHY_SETTING( 50000, FULL, 50000baseSR2_Full ),
218 PHY_SETTING( 50000, FULL, 50000baseCR_Full ),
219 PHY_SETTING( 50000, FULL, 50000baseKR_Full ),
220 PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ),
221 PHY_SETTING( 50000, FULL, 50000baseDR_Full ),
222 PHY_SETTING( 50000, FULL, 50000baseSR_Full ),
223 /* 40G */
224 PHY_SETTING( 40000, FULL, 40000baseCR4_Full ),
225 PHY_SETTING( 40000, FULL, 40000baseKR4_Full ),
226 PHY_SETTING( 40000, FULL, 40000baseLR4_Full ),
227 PHY_SETTING( 40000, FULL, 40000baseSR4_Full ),
228 /* 25G */
229 PHY_SETTING( 25000, FULL, 25000baseCR_Full ),
230 PHY_SETTING( 25000, FULL, 25000baseKR_Full ),
231 PHY_SETTING( 25000, FULL, 25000baseSR_Full ),
232 /* 20G */
233 PHY_SETTING( 20000, FULL, 20000baseKR2_Full ),
234 PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ),
235 /* 10G */
236 PHY_SETTING( 10000, FULL, 10000baseCR_Full ),
237 PHY_SETTING( 10000, FULL, 10000baseER_Full ),
238 PHY_SETTING( 10000, FULL, 10000baseKR_Full ),
239 PHY_SETTING( 10000, FULL, 10000baseKX4_Full ),
240 PHY_SETTING( 10000, FULL, 10000baseLR_Full ),
241 PHY_SETTING( 10000, FULL, 10000baseLRM_Full ),
242 PHY_SETTING( 10000, FULL, 10000baseR_FEC ),
243 PHY_SETTING( 10000, FULL, 10000baseSR_Full ),
244 PHY_SETTING( 10000, FULL, 10000baseT_Full ),
245 /* 5G */
246 PHY_SETTING( 5000, FULL, 5000baseT_Full ),
247 /* 2.5G */
248 PHY_SETTING( 2500, FULL, 2500baseT_Full ),
249 PHY_SETTING( 2500, FULL, 2500baseX_Full ),
250 /* 1G */
251 PHY_SETTING( 1000, FULL, 1000baseT_Full ),
252 PHY_SETTING( 1000, HALF, 1000baseT_Half ),
253 PHY_SETTING( 1000, FULL, 1000baseT1_Full ),
254 PHY_SETTING( 1000, FULL, 1000baseX_Full ),
255 PHY_SETTING( 1000, FULL, 1000baseKX_Full ),
256 /* 100M */
257 PHY_SETTING( 100, FULL, 100baseT_Full ),
258 PHY_SETTING( 100, FULL, 100baseT1_Full ),
259 PHY_SETTING( 100, HALF, 100baseT_Half ),
260 PHY_SETTING( 100, HALF, 100baseFX_Half ),
261 PHY_SETTING( 100, FULL, 100baseFX_Full ),
262 /* 10M */
263 PHY_SETTING( 10, FULL, 10baseT_Full ),
264 PHY_SETTING( 10, HALF, 10baseT_Half ),
265 PHY_SETTING( 10, FULL, 10baseT1L_Full ),
266 PHY_SETTING( 10, FULL, 10baseT1S_Full ),
267 PHY_SETTING( 10, HALF, 10baseT1S_Half ),
268 PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ),
269 PHY_SETTING( 10, FULL, 10baseT1BRR_Full ),
270};
271#undef PHY_SETTING
272
273/**
274 * phy_lookup_setting - lookup a PHY setting
275 * @speed: speed to match
276 * @duplex: duplex to match
277 * @mask: allowed link modes
278 * @exact: an exact match is required
279 *
280 * Search the settings array for a setting that matches the speed and
281 * duplex, and which is supported.
282 *
283 * If @exact is unset, either an exact match or %NULL for no match will
284 * be returned.
285 *
286 * If @exact is set, an exact match, the fastest supported setting at
287 * or below the specified speed, the slowest supported setting, or if
288 * they all fail, %NULL will be returned.
289 */
290const struct phy_setting *
291phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact)
292{
293 const struct phy_setting *p, *match = NULL, *last = NULL;
294 int i;
295
296 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
297 if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&
298 test_bit(p->bit, mask)) {
299 last = p;
300 if (p->speed == speed && p->duplex == duplex) {
301 /* Exact match for speed and duplex */
302 match = p;
303 break;
304 } else if (!exact) {
305 if (!match && p->speed <= speed)
306 /* Candidate */
307 match = p;
308
309 if (p->speed < speed)
310 break;
311 }
312 }
313 }
314
315 if (!match && !exact)
316 match = last;
317
318 return match;
319}
320EXPORT_SYMBOL_GPL(phy_lookup_setting);
321
322size_t phy_speeds(unsigned int *speeds, size_t size,
323 unsigned long *mask)
324{
325 size_t count;
326 int i;
327
328 for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++)
329 if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&
330 test_bit(settings[i].bit, mask) &&
331 (count == 0 || speeds[count - 1] != settings[i].speed))
332 speeds[count++] = settings[i].speed;
333
334 return count;
335}
336
337static void __set_linkmode_max_speed(u32 max_speed, unsigned long *addr)
338{
339 const struct phy_setting *p;
340 int i;
341
342 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
343 if (p->speed > max_speed)
344 linkmode_clear_bit(p->bit, addr);
345 else
346 break;
347 }
348}
349
350static void __set_phy_supported(struct phy_device *phydev, u32 max_speed)
351{
352 __set_linkmode_max_speed(max_speed, phydev->supported);
353}
354
355/**
356 * phy_set_max_speed - Set the maximum speed the PHY should support
357 *
358 * @phydev: The phy_device struct
359 * @max_speed: Maximum speed
360 *
361 * The PHY might be more capable than the MAC. For example a Fast Ethernet
362 * is connected to a 1G PHY. This function allows the MAC to indicate its
363 * maximum speed, and so limit what the PHY will advertise.
364 */
365void phy_set_max_speed(struct phy_device *phydev, u32 max_speed)
366{
367 __set_phy_supported(phydev, max_speed);
368
369 phy_advertise_supported(phydev);
370}
371EXPORT_SYMBOL(phy_set_max_speed);
372
373void of_set_phy_supported(struct phy_device *phydev)
374{
375 struct device_node *node = phydev->mdio.dev.of_node;
376 u32 max_speed;
377
378 if (!IS_ENABLED(CONFIG_OF_MDIO))
379 return;
380
381 if (!node)
382 return;
383
384 if (!of_property_read_u32(node, "max-speed", &max_speed))
385 __set_phy_supported(phydev, max_speed);
386}
387
388void of_set_phy_eee_broken(struct phy_device *phydev)
389{
390 struct device_node *node = phydev->mdio.dev.of_node;
391 unsigned long *modes = phydev->eee_broken_modes;
392
393 if (!IS_ENABLED(CONFIG_OF_MDIO) || !node)
394 return;
395
396 linkmode_zero(modes);
397
398 if (of_property_read_bool(node, "eee-broken-100tx"))
399 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, modes);
400 if (of_property_read_bool(node, "eee-broken-1000t"))
401 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, modes);
402 if (of_property_read_bool(node, "eee-broken-10gt"))
403 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, modes);
404 if (of_property_read_bool(node, "eee-broken-1000kx"))
405 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, modes);
406 if (of_property_read_bool(node, "eee-broken-10gkx4"))
407 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, modes);
408 if (of_property_read_bool(node, "eee-broken-10gkr"))
409 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, modes);
410}
411
412/**
413 * of_set_phy_timing_role - Set the master/slave mode of the PHY
414 *
415 * @phydev: The phy_device struct
416 *
417 * Set master/slave configuration of the PHY based on the device tree.
418 */
419void of_set_phy_timing_role(struct phy_device *phydev)
420{
421 struct device_node *node = phydev->mdio.dev.of_node;
422 const char *master;
423
424 if (!IS_ENABLED(CONFIG_OF_MDIO))
425 return;
426
427 if (!node)
428 return;
429
430 if (of_property_read_string(node, "timing-role", &master))
431 return;
432
433 if (strcmp(master, "forced-master") == 0)
434 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE;
435 else if (strcmp(master, "forced-slave") == 0)
436 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE;
437 else if (strcmp(master, "preferred-master") == 0)
438 phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED;
439 else if (strcmp(master, "preferred-slave") == 0)
440 phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
441 else
442 phydev_warn(phydev, "Unknown master-slave mode %s\n", master);
443}
444
445/**
446 * phy_resolve_aneg_pause - Determine pause autoneg results
447 *
448 * @phydev: The phy_device struct
449 *
450 * Once autoneg has completed the local pause settings can be
451 * resolved. Determine if pause and asymmetric pause should be used
452 * by the MAC.
453 */
454
455void phy_resolve_aneg_pause(struct phy_device *phydev)
456{
457 if (phydev->duplex == DUPLEX_FULL) {
458 phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
459 phydev->lp_advertising);
460 phydev->asym_pause = linkmode_test_bit(
461 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
462 phydev->lp_advertising);
463 }
464}
465EXPORT_SYMBOL_GPL(phy_resolve_aneg_pause);
466
467/**
468 * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings
469 * @phydev: The phy_device struct
470 *
471 * Resolve our and the link partner advertisements into their corresponding
472 * speed and duplex. If full duplex was negotiated, extract the pause mode
473 * from the link partner mask.
474 */
475void phy_resolve_aneg_linkmode(struct phy_device *phydev)
476{
477 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
478 int i;
479
480 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
481
482 for (i = 0; i < ARRAY_SIZE(settings); i++)
483 if (test_bit(settings[i].bit, common)) {
484 phydev->speed = settings[i].speed;
485 phydev->duplex = settings[i].duplex;
486 break;
487 }
488
489 phy_resolve_aneg_pause(phydev);
490}
491EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode);
492
493/**
494 * phy_check_downshift - check whether downshift occurred
495 * @phydev: The phy_device struct
496 *
497 * Check whether a downshift to a lower speed occurred. If this should be the
498 * case warn the user.
499 * Prerequisite for detecting downshift is that PHY driver implements the
500 * read_status callback and sets phydev->speed to the actual link speed.
501 */
502void phy_check_downshift(struct phy_device *phydev)
503{
504 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
505 int i, speed = SPEED_UNKNOWN;
506
507 phydev->downshifted_rate = 0;
508
509 if (phydev->autoneg == AUTONEG_DISABLE ||
510 phydev->speed == SPEED_UNKNOWN)
511 return;
512
513 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
514
515 for (i = 0; i < ARRAY_SIZE(settings); i++)
516 if (test_bit(settings[i].bit, common)) {
517 speed = settings[i].speed;
518 break;
519 }
520
521 if (speed == SPEED_UNKNOWN || phydev->speed >= speed)
522 return;
523
524 phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n",
525 phy_speed_to_str(speed), phy_speed_to_str(phydev->speed));
526
527 phydev->downshifted_rate = 1;
528}
529EXPORT_SYMBOL_GPL(phy_check_downshift);
530
531static int phy_resolve_min_speed(struct phy_device *phydev, bool fdx_only)
532{
533 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
534 int i = ARRAY_SIZE(settings);
535
536 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
537
538 while (--i >= 0) {
539 if (test_bit(settings[i].bit, common)) {
540 if (fdx_only && settings[i].duplex != DUPLEX_FULL)
541 continue;
542 return settings[i].speed;
543 }
544 }
545
546 return SPEED_UNKNOWN;
547}
548
549int phy_speed_down_core(struct phy_device *phydev)
550{
551 int min_common_speed = phy_resolve_min_speed(phydev, true);
552
553 if (min_common_speed == SPEED_UNKNOWN)
554 return -EINVAL;
555
556 __set_linkmode_max_speed(min_common_speed, phydev->advertising);
557
558 return 0;
559}
560
561static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
562 u16 regnum)
563{
564 /* Write the desired MMD Devad */
565 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
566
567 /* Write the desired MMD register address */
568 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
569
570 /* Select the Function : DATA with no post increment */
571 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
572 devad | MII_MMD_CTRL_NOINCR);
573}
574
575static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
576 int devad, u32 regnum)
577{
578 if (is_c45)
579 return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
580
581 mmd_phy_indirect(bus, phy_addr, devad, regnum);
582 /* Read the content of the MMD's selected register */
583 return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
584}
585
586static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
587 int devad, u32 regnum, u16 val)
588{
589 if (is_c45)
590 return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
591
592 mmd_phy_indirect(bus, phy_addr, devad, regnum);
593 /* Write the data into MMD's selected register */
594 return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
595}
596
597/**
598 * __phy_read_mmd - Convenience function for reading a register
599 * from an MMD on a given PHY.
600 * @phydev: The phy_device struct
601 * @devad: The MMD to read from (0..31)
602 * @regnum: The register on the MMD to read (0..65535)
603 *
604 * Same rules as for __phy_read();
605 */
606int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
607{
608 if (regnum > (u16)~0 || devad > 32)
609 return -EINVAL;
610
611 if (phydev->drv && phydev->drv->read_mmd)
612 return phydev->drv->read_mmd(phydev, devad, regnum);
613
614 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr,
615 phydev->is_c45, devad, regnum);
616}
617EXPORT_SYMBOL(__phy_read_mmd);
618
619/**
620 * phy_read_mmd - Convenience function for reading a register
621 * from an MMD on a given PHY.
622 * @phydev: The phy_device struct
623 * @devad: The MMD to read from
624 * @regnum: The register on the MMD to read
625 *
626 * Same rules as for phy_read();
627 */
628int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
629{
630 int ret;
631
632 phy_lock_mdio_bus(phydev);
633 ret = __phy_read_mmd(phydev, devad, regnum);
634 phy_unlock_mdio_bus(phydev);
635
636 return ret;
637}
638EXPORT_SYMBOL(phy_read_mmd);
639
640/**
641 * __phy_write_mmd - Convenience function for writing a register
642 * on an MMD on a given PHY.
643 * @phydev: The phy_device struct
644 * @devad: The MMD to read from
645 * @regnum: The register on the MMD to read
646 * @val: value to write to @regnum
647 *
648 * Same rules as for __phy_write();
649 */
650int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
651{
652 if (regnum > (u16)~0 || devad > 32)
653 return -EINVAL;
654
655 if (phydev->drv && phydev->drv->write_mmd)
656 return phydev->drv->write_mmd(phydev, devad, regnum, val);
657
658 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr,
659 phydev->is_c45, devad, regnum, val);
660}
661EXPORT_SYMBOL(__phy_write_mmd);
662
663/**
664 * phy_write_mmd - Convenience function for writing a register
665 * on an MMD on a given PHY.
666 * @phydev: The phy_device struct
667 * @devad: The MMD to read from
668 * @regnum: The register on the MMD to read
669 * @val: value to write to @regnum
670 *
671 * Same rules as for phy_write();
672 */
673int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
674{
675 int ret;
676
677 phy_lock_mdio_bus(phydev);
678 ret = __phy_write_mmd(phydev, devad, regnum, val);
679 phy_unlock_mdio_bus(phydev);
680
681 return ret;
682}
683EXPORT_SYMBOL(phy_write_mmd);
684
685/**
686 * __phy_package_read_mmd - read MMD reg relative to PHY package base addr
687 * @phydev: The phy_device struct
688 * @addr_offset: The offset to be added to PHY package base_addr
689 * @devad: The MMD to read from
690 * @regnum: The register on the MMD to read
691 *
692 * Convenience helper for reading a register of an MMD on a given PHY
693 * using the PHY package base address. The base address is added to
694 * the addr_offset value.
695 *
696 * Same calling rules as for __phy_read();
697 *
698 * NOTE: It's assumed that the entire PHY package is either C22 or C45.
699 */
700int __phy_package_read_mmd(struct phy_device *phydev,
701 unsigned int addr_offset, int devad,
702 u32 regnum)
703{
704 int addr = phy_package_address(phydev, addr_offset);
705
706 if (addr < 0)
707 return addr;
708
709 if (regnum > (u16)~0 || devad > 32)
710 return -EINVAL;
711
712 return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
713 regnum);
714}
715EXPORT_SYMBOL(__phy_package_read_mmd);
716
717/**
718 * phy_package_read_mmd - read MMD reg relative to PHY package base addr
719 * @phydev: The phy_device struct
720 * @addr_offset: The offset to be added to PHY package base_addr
721 * @devad: The MMD to read from
722 * @regnum: The register on the MMD to read
723 *
724 * Convenience helper for reading a register of an MMD on a given PHY
725 * using the PHY package base address. The base address is added to
726 * the addr_offset value.
727 *
728 * Same calling rules as for phy_read();
729 *
730 * NOTE: It's assumed that the entire PHY package is either C22 or C45.
731 */
732int phy_package_read_mmd(struct phy_device *phydev,
733 unsigned int addr_offset, int devad,
734 u32 regnum)
735{
736 int addr = phy_package_address(phydev, addr_offset);
737 int val;
738
739 if (addr < 0)
740 return addr;
741
742 if (regnum > (u16)~0 || devad > 32)
743 return -EINVAL;
744
745 phy_lock_mdio_bus(phydev);
746 val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
747 regnum);
748 phy_unlock_mdio_bus(phydev);
749
750 return val;
751}
752EXPORT_SYMBOL(phy_package_read_mmd);
753
754/**
755 * __phy_package_write_mmd - write MMD reg relative to PHY package base addr
756 * @phydev: The phy_device struct
757 * @addr_offset: The offset to be added to PHY package base_addr
758 * @devad: The MMD to write to
759 * @regnum: The register on the MMD to write
760 * @val: value to write to @regnum
761 *
762 * Convenience helper for writing a register of an MMD on a given PHY
763 * using the PHY package base address. The base address is added to
764 * the addr_offset value.
765 *
766 * Same calling rules as for __phy_write();
767 *
768 * NOTE: It's assumed that the entire PHY package is either C22 or C45.
769 */
770int __phy_package_write_mmd(struct phy_device *phydev,
771 unsigned int addr_offset, int devad,
772 u32 regnum, u16 val)
773{
774 int addr = phy_package_address(phydev, addr_offset);
775
776 if (addr < 0)
777 return addr;
778
779 if (regnum > (u16)~0 || devad > 32)
780 return -EINVAL;
781
782 return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
783 regnum, val);
784}
785EXPORT_SYMBOL(__phy_package_write_mmd);
786
787/**
788 * phy_package_write_mmd - write MMD reg relative to PHY package base addr
789 * @phydev: The phy_device struct
790 * @addr_offset: The offset to be added to PHY package base_addr
791 * @devad: The MMD to write to
792 * @regnum: The register on the MMD to write
793 * @val: value to write to @regnum
794 *
795 * Convenience helper for writing a register of an MMD on a given PHY
796 * using the PHY package base address. The base address is added to
797 * the addr_offset value.
798 *
799 * Same calling rules as for phy_write();
800 *
801 * NOTE: It's assumed that the entire PHY package is either C22 or C45.
802 */
803int phy_package_write_mmd(struct phy_device *phydev,
804 unsigned int addr_offset, int devad,
805 u32 regnum, u16 val)
806{
807 int addr = phy_package_address(phydev, addr_offset);
808 int ret;
809
810 if (addr < 0)
811 return addr;
812
813 if (regnum > (u16)~0 || devad > 32)
814 return -EINVAL;
815
816 phy_lock_mdio_bus(phydev);
817 ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
818 regnum, val);
819 phy_unlock_mdio_bus(phydev);
820
821 return ret;
822}
823EXPORT_SYMBOL(phy_package_write_mmd);
824
825/**
826 * phy_modify_changed - Function for modifying a PHY register
827 * @phydev: the phy_device struct
828 * @regnum: register number to modify
829 * @mask: bit mask of bits to clear
830 * @set: new value of bits set in mask to write to @regnum
831 *
832 * NOTE: MUST NOT be called from interrupt context,
833 * because the bus read/write functions may wait for an interrupt
834 * to conclude the operation.
835 *
836 * Returns negative errno, 0 if there was no change, and 1 in case of change
837 */
838int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
839{
840 int ret;
841
842 phy_lock_mdio_bus(phydev);
843 ret = __phy_modify_changed(phydev, regnum, mask, set);
844 phy_unlock_mdio_bus(phydev);
845
846 return ret;
847}
848EXPORT_SYMBOL_GPL(phy_modify_changed);
849
850/**
851 * __phy_modify - Convenience function for modifying a PHY register
852 * @phydev: the phy_device struct
853 * @regnum: register number to modify
854 * @mask: bit mask of bits to clear
855 * @set: new value of bits set in mask to write to @regnum
856 *
857 * NOTE: MUST NOT be called from interrupt context,
858 * because the bus read/write functions may wait for an interrupt
859 * to conclude the operation.
860 */
861int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
862{
863 int ret;
864
865 ret = __phy_modify_changed(phydev, regnum, mask, set);
866
867 return ret < 0 ? ret : 0;
868}
869EXPORT_SYMBOL_GPL(__phy_modify);
870
871/**
872 * phy_modify - Convenience function for modifying a given PHY register
873 * @phydev: the phy_device struct
874 * @regnum: register number to write
875 * @mask: bit mask of bits to clear
876 * @set: new value of bits set in mask to write to @regnum
877 *
878 * NOTE: MUST NOT be called from interrupt context,
879 * because the bus read/write functions may wait for an interrupt
880 * to conclude the operation.
881 */
882int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
883{
884 int ret;
885
886 phy_lock_mdio_bus(phydev);
887 ret = __phy_modify(phydev, regnum, mask, set);
888 phy_unlock_mdio_bus(phydev);
889
890 return ret;
891}
892EXPORT_SYMBOL_GPL(phy_modify);
893
894/**
895 * __phy_modify_mmd_changed - Function for modifying a register on MMD
896 * @phydev: the phy_device struct
897 * @devad: the MMD containing register to modify
898 * @regnum: register number to modify
899 * @mask: bit mask of bits to clear
900 * @set: new value of bits set in mask to write to @regnum
901 *
902 * Unlocked helper function which allows a MMD register to be modified as
903 * new register value = (old register value & ~mask) | set
904 *
905 * Returns negative errno, 0 if there was no change, and 1 in case of change
906 */
907int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
908 u16 mask, u16 set)
909{
910 int new, ret;
911
912 ret = __phy_read_mmd(phydev, devad, regnum);
913 if (ret < 0)
914 return ret;
915
916 new = (ret & ~mask) | set;
917 if (new == ret)
918 return 0;
919
920 ret = __phy_write_mmd(phydev, devad, regnum, new);
921
922 return ret < 0 ? ret : 1;
923}
924EXPORT_SYMBOL_GPL(__phy_modify_mmd_changed);
925
926/**
927 * phy_modify_mmd_changed - Function for modifying a register on MMD
928 * @phydev: the phy_device struct
929 * @devad: the MMD containing register to modify
930 * @regnum: register number to modify
931 * @mask: bit mask of bits to clear
932 * @set: new value of bits set in mask to write to @regnum
933 *
934 * NOTE: MUST NOT be called from interrupt context,
935 * because the bus read/write functions may wait for an interrupt
936 * to conclude the operation.
937 *
938 * Returns negative errno, 0 if there was no change, and 1 in case of change
939 */
940int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
941 u16 mask, u16 set)
942{
943 int ret;
944
945 phy_lock_mdio_bus(phydev);
946 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
947 phy_unlock_mdio_bus(phydev);
948
949 return ret;
950}
951EXPORT_SYMBOL_GPL(phy_modify_mmd_changed);
952
953/**
954 * __phy_modify_mmd - Convenience function for modifying a register on MMD
955 * @phydev: the phy_device struct
956 * @devad: the MMD containing register to modify
957 * @regnum: register number to modify
958 * @mask: bit mask of bits to clear
959 * @set: new value of bits set in mask to write to @regnum
960 *
961 * NOTE: MUST NOT be called from interrupt context,
962 * because the bus read/write functions may wait for an interrupt
963 * to conclude the operation.
964 */
965int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
966 u16 mask, u16 set)
967{
968 int ret;
969
970 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
971
972 return ret < 0 ? ret : 0;
973}
974EXPORT_SYMBOL_GPL(__phy_modify_mmd);
975
976/**
977 * phy_modify_mmd - Convenience function for modifying a register on MMD
978 * @phydev: the phy_device struct
979 * @devad: the MMD containing register to modify
980 * @regnum: register number to modify
981 * @mask: bit mask of bits to clear
982 * @set: new value of bits set in mask to write to @regnum
983 *
984 * NOTE: MUST NOT be called from interrupt context,
985 * because the bus read/write functions may wait for an interrupt
986 * to conclude the operation.
987 */
988int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
989 u16 mask, u16 set)
990{
991 int ret;
992
993 phy_lock_mdio_bus(phydev);
994 ret = __phy_modify_mmd(phydev, devad, regnum, mask, set);
995 phy_unlock_mdio_bus(phydev);
996
997 return ret;
998}
999EXPORT_SYMBOL_GPL(phy_modify_mmd);
1000
1001static int __phy_read_page(struct phy_device *phydev)
1002{
1003 if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n"))
1004 return -EOPNOTSUPP;
1005
1006 return phydev->drv->read_page(phydev);
1007}
1008
1009static int __phy_write_page(struct phy_device *phydev, int page)
1010{
1011 if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n"))
1012 return -EOPNOTSUPP;
1013
1014 return phydev->drv->write_page(phydev, page);
1015}
1016
1017/**
1018 * phy_save_page() - take the bus lock and save the current page
1019 * @phydev: a pointer to a &struct phy_device
1020 *
1021 * Take the MDIO bus lock, and return the current page number. On error,
1022 * returns a negative errno. phy_restore_page() must always be called
1023 * after this, irrespective of success or failure of this call.
1024 */
1025int phy_save_page(struct phy_device *phydev)
1026{
1027 phy_lock_mdio_bus(phydev);
1028 return __phy_read_page(phydev);
1029}
1030EXPORT_SYMBOL_GPL(phy_save_page);
1031
1032/**
1033 * phy_select_page() - take the bus lock, save the current page, and set a page
1034 * @phydev: a pointer to a &struct phy_device
1035 * @page: desired page
1036 *
1037 * Take the MDIO bus lock to protect against concurrent access, save the
1038 * current PHY page, and set the current page. On error, returns a
1039 * negative errno, otherwise returns the previous page number.
1040 * phy_restore_page() must always be called after this, irrespective
1041 * of success or failure of this call.
1042 */
1043int phy_select_page(struct phy_device *phydev, int page)
1044{
1045 int ret, oldpage;
1046
1047 oldpage = ret = phy_save_page(phydev);
1048 if (ret < 0)
1049 return ret;
1050
1051 if (oldpage != page) {
1052 ret = __phy_write_page(phydev, page);
1053 if (ret < 0)
1054 return ret;
1055 }
1056
1057 return oldpage;
1058}
1059EXPORT_SYMBOL_GPL(phy_select_page);
1060
1061/**
1062 * phy_restore_page() - restore the page register and release the bus lock
1063 * @phydev: a pointer to a &struct phy_device
1064 * @oldpage: the old page, return value from phy_save_page() or phy_select_page()
1065 * @ret: operation's return code
1066 *
1067 * Release the MDIO bus lock, restoring @oldpage if it is a valid page.
1068 * This function propagates the earliest error code from the group of
1069 * operations.
1070 *
1071 * Returns:
1072 * @oldpage if it was a negative value, otherwise
1073 * @ret if it was a negative errno value, otherwise
1074 * phy_write_page()'s negative value if it were in error, otherwise
1075 * @ret.
1076 */
1077int phy_restore_page(struct phy_device *phydev, int oldpage, int ret)
1078{
1079 int r;
1080
1081 if (oldpage >= 0) {
1082 r = __phy_write_page(phydev, oldpage);
1083
1084 /* Propagate the operation return code if the page write
1085 * was successful.
1086 */
1087 if (ret >= 0 && r < 0)
1088 ret = r;
1089 } else {
1090 /* Propagate the phy page selection error code */
1091 ret = oldpage;
1092 }
1093
1094 phy_unlock_mdio_bus(phydev);
1095
1096 return ret;
1097}
1098EXPORT_SYMBOL_GPL(phy_restore_page);
1099
1100/**
1101 * phy_read_paged() - Convenience function for reading a paged register
1102 * @phydev: a pointer to a &struct phy_device
1103 * @page: the page for the phy
1104 * @regnum: register number
1105 *
1106 * Same rules as for phy_read().
1107 */
1108int phy_read_paged(struct phy_device *phydev, int page, u32 regnum)
1109{
1110 int ret = 0, oldpage;
1111
1112 oldpage = phy_select_page(phydev, page);
1113 if (oldpage >= 0)
1114 ret = __phy_read(phydev, regnum);
1115
1116 return phy_restore_page(phydev, oldpage, ret);
1117}
1118EXPORT_SYMBOL(phy_read_paged);
1119
1120/**
1121 * phy_write_paged() - Convenience function for writing a paged register
1122 * @phydev: a pointer to a &struct phy_device
1123 * @page: the page for the phy
1124 * @regnum: register number
1125 * @val: value to write
1126 *
1127 * Same rules as for phy_write().
1128 */
1129int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
1130{
1131 int ret = 0, oldpage;
1132
1133 oldpage = phy_select_page(phydev, page);
1134 if (oldpage >= 0)
1135 ret = __phy_write(phydev, regnum, val);
1136
1137 return phy_restore_page(phydev, oldpage, ret);
1138}
1139EXPORT_SYMBOL(phy_write_paged);
1140
1141/**
1142 * phy_modify_paged_changed() - Function for modifying a paged register
1143 * @phydev: a pointer to a &struct phy_device
1144 * @page: the page for the phy
1145 * @regnum: register number
1146 * @mask: bit mask of bits to clear
1147 * @set: bit mask of bits to set
1148 *
1149 * Returns negative errno, 0 if there was no change, and 1 in case of change
1150 */
1151int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
1152 u16 mask, u16 set)
1153{
1154 int ret = 0, oldpage;
1155
1156 oldpage = phy_select_page(phydev, page);
1157 if (oldpage >= 0)
1158 ret = __phy_modify_changed(phydev, regnum, mask, set);
1159
1160 return phy_restore_page(phydev, oldpage, ret);
1161}
1162EXPORT_SYMBOL(phy_modify_paged_changed);
1163
1164/**
1165 * phy_modify_paged() - Convenience function for modifying a paged register
1166 * @phydev: a pointer to a &struct phy_device
1167 * @page: the page for the phy
1168 * @regnum: register number
1169 * @mask: bit mask of bits to clear
1170 * @set: bit mask of bits to set
1171 *
1172 * Same rules as for phy_read() and phy_write().
1173 */
1174int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
1175 u16 mask, u16 set)
1176{
1177 int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set);
1178
1179 return ret < 0 ? ret : 0;
1180}
1181EXPORT_SYMBOL(phy_modify_paged);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Core PHY library, taken from phy.c
4 */
5#include <linux/export.h>
6#include <linux/phy.h>
7#include <linux/of.h>
8
9/**
10 * phy_speed_to_str - Return a string representing the PHY link speed
11 *
12 * @speed: Speed of the link
13 */
14const char *phy_speed_to_str(int speed)
15{
16 BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,
17 "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
18 "If a speed or mode has been added please update phy_speed_to_str "
19 "and the PHY settings array.\n");
20
21 switch (speed) {
22 case SPEED_10:
23 return "10Mbps";
24 case SPEED_100:
25 return "100Mbps";
26 case SPEED_1000:
27 return "1Gbps";
28 case SPEED_2500:
29 return "2.5Gbps";
30 case SPEED_5000:
31 return "5Gbps";
32 case SPEED_10000:
33 return "10Gbps";
34 case SPEED_14000:
35 return "14Gbps";
36 case SPEED_20000:
37 return "20Gbps";
38 case SPEED_25000:
39 return "25Gbps";
40 case SPEED_40000:
41 return "40Gbps";
42 case SPEED_50000:
43 return "50Gbps";
44 case SPEED_56000:
45 return "56Gbps";
46 case SPEED_100000:
47 return "100Gbps";
48 case SPEED_200000:
49 return "200Gbps";
50 case SPEED_400000:
51 return "400Gbps";
52 case SPEED_800000:
53 return "800Gbps";
54 case SPEED_UNKNOWN:
55 return "Unknown";
56 default:
57 return "Unsupported (update phy-core.c)";
58 }
59}
60EXPORT_SYMBOL_GPL(phy_speed_to_str);
61
62/**
63 * phy_duplex_to_str - Return string describing the duplex
64 *
65 * @duplex: Duplex setting to describe
66 */
67const char *phy_duplex_to_str(unsigned int duplex)
68{
69 if (duplex == DUPLEX_HALF)
70 return "Half";
71 if (duplex == DUPLEX_FULL)
72 return "Full";
73 if (duplex == DUPLEX_UNKNOWN)
74 return "Unknown";
75 return "Unsupported (update phy-core.c)";
76}
77EXPORT_SYMBOL_GPL(phy_duplex_to_str);
78
79/**
80 * phy_rate_matching_to_str - Return a string describing the rate matching
81 *
82 * @rate_matching: Type of rate matching to describe
83 */
84const char *phy_rate_matching_to_str(int rate_matching)
85{
86 switch (rate_matching) {
87 case RATE_MATCH_NONE:
88 return "none";
89 case RATE_MATCH_PAUSE:
90 return "pause";
91 case RATE_MATCH_CRS:
92 return "crs";
93 case RATE_MATCH_OPEN_LOOP:
94 return "open-loop";
95 }
96 return "Unsupported (update phy-core.c)";
97}
98EXPORT_SYMBOL_GPL(phy_rate_matching_to_str);
99
100/**
101 * phy_interface_num_ports - Return the number of links that can be carried by
102 * a given MAC-PHY physical link. Returns 0 if this is
103 * unknown, the number of links else.
104 *
105 * @interface: The interface mode we want to get the number of ports
106 */
107int phy_interface_num_ports(phy_interface_t interface)
108{
109 switch (interface) {
110 case PHY_INTERFACE_MODE_NA:
111 return 0;
112 case PHY_INTERFACE_MODE_INTERNAL:
113 case PHY_INTERFACE_MODE_MII:
114 case PHY_INTERFACE_MODE_GMII:
115 case PHY_INTERFACE_MODE_TBI:
116 case PHY_INTERFACE_MODE_REVMII:
117 case PHY_INTERFACE_MODE_RMII:
118 case PHY_INTERFACE_MODE_REVRMII:
119 case PHY_INTERFACE_MODE_RGMII:
120 case PHY_INTERFACE_MODE_RGMII_ID:
121 case PHY_INTERFACE_MODE_RGMII_RXID:
122 case PHY_INTERFACE_MODE_RGMII_TXID:
123 case PHY_INTERFACE_MODE_RTBI:
124 case PHY_INTERFACE_MODE_XGMII:
125 case PHY_INTERFACE_MODE_XLGMII:
126 case PHY_INTERFACE_MODE_MOCA:
127 case PHY_INTERFACE_MODE_TRGMII:
128 case PHY_INTERFACE_MODE_USXGMII:
129 case PHY_INTERFACE_MODE_SGMII:
130 case PHY_INTERFACE_MODE_SMII:
131 case PHY_INTERFACE_MODE_1000BASEX:
132 case PHY_INTERFACE_MODE_2500BASEX:
133 case PHY_INTERFACE_MODE_5GBASER:
134 case PHY_INTERFACE_MODE_10GBASER:
135 case PHY_INTERFACE_MODE_25GBASER:
136 case PHY_INTERFACE_MODE_10GKR:
137 case PHY_INTERFACE_MODE_100BASEX:
138 case PHY_INTERFACE_MODE_RXAUI:
139 case PHY_INTERFACE_MODE_XAUI:
140 case PHY_INTERFACE_MODE_1000BASEKX:
141 return 1;
142 case PHY_INTERFACE_MODE_QSGMII:
143 case PHY_INTERFACE_MODE_QUSGMII:
144 return 4;
145 case PHY_INTERFACE_MODE_MAX:
146 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
147 return 0;
148 }
149 return 0;
150}
151EXPORT_SYMBOL_GPL(phy_interface_num_ports);
152
153/* A mapping of all SUPPORTED settings to speed/duplex. This table
154 * must be grouped by speed and sorted in descending match priority
155 * - iow, descending speed.
156 */
157
158#define PHY_SETTING(s, d, b) { .speed = SPEED_ ## s, .duplex = DUPLEX_ ## d, \
159 .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
160
161static const struct phy_setting settings[] = {
162 /* 800G */
163 PHY_SETTING( 800000, FULL, 800000baseCR8_Full ),
164 PHY_SETTING( 800000, FULL, 800000baseKR8_Full ),
165 PHY_SETTING( 800000, FULL, 800000baseDR8_Full ),
166 PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ),
167 PHY_SETTING( 800000, FULL, 800000baseSR8_Full ),
168 PHY_SETTING( 800000, FULL, 800000baseVR8_Full ),
169 /* 400G */
170 PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
171 PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
172 PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
173 PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
174 PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
175 PHY_SETTING( 400000, FULL, 400000baseCR4_Full ),
176 PHY_SETTING( 400000, FULL, 400000baseKR4_Full ),
177 PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ),
178 PHY_SETTING( 400000, FULL, 400000baseDR4_Full ),
179 PHY_SETTING( 400000, FULL, 400000baseSR4_Full ),
180 /* 200G */
181 PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
182 PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
183 PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ),
184 PHY_SETTING( 200000, FULL, 200000baseDR4_Full ),
185 PHY_SETTING( 200000, FULL, 200000baseSR4_Full ),
186 PHY_SETTING( 200000, FULL, 200000baseCR2_Full ),
187 PHY_SETTING( 200000, FULL, 200000baseKR2_Full ),
188 PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ),
189 PHY_SETTING( 200000, FULL, 200000baseDR2_Full ),
190 PHY_SETTING( 200000, FULL, 200000baseSR2_Full ),
191 /* 100G */
192 PHY_SETTING( 100000, FULL, 100000baseCR4_Full ),
193 PHY_SETTING( 100000, FULL, 100000baseKR4_Full ),
194 PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ),
195 PHY_SETTING( 100000, FULL, 100000baseSR4_Full ),
196 PHY_SETTING( 100000, FULL, 100000baseCR2_Full ),
197 PHY_SETTING( 100000, FULL, 100000baseKR2_Full ),
198 PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ),
199 PHY_SETTING( 100000, FULL, 100000baseDR2_Full ),
200 PHY_SETTING( 100000, FULL, 100000baseSR2_Full ),
201 PHY_SETTING( 100000, FULL, 100000baseCR_Full ),
202 PHY_SETTING( 100000, FULL, 100000baseKR_Full ),
203 PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ),
204 PHY_SETTING( 100000, FULL, 100000baseDR_Full ),
205 PHY_SETTING( 100000, FULL, 100000baseSR_Full ),
206 /* 56G */
207 PHY_SETTING( 56000, FULL, 56000baseCR4_Full ),
208 PHY_SETTING( 56000, FULL, 56000baseKR4_Full ),
209 PHY_SETTING( 56000, FULL, 56000baseLR4_Full ),
210 PHY_SETTING( 56000, FULL, 56000baseSR4_Full ),
211 /* 50G */
212 PHY_SETTING( 50000, FULL, 50000baseCR2_Full ),
213 PHY_SETTING( 50000, FULL, 50000baseKR2_Full ),
214 PHY_SETTING( 50000, FULL, 50000baseSR2_Full ),
215 PHY_SETTING( 50000, FULL, 50000baseCR_Full ),
216 PHY_SETTING( 50000, FULL, 50000baseKR_Full ),
217 PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ),
218 PHY_SETTING( 50000, FULL, 50000baseDR_Full ),
219 PHY_SETTING( 50000, FULL, 50000baseSR_Full ),
220 /* 40G */
221 PHY_SETTING( 40000, FULL, 40000baseCR4_Full ),
222 PHY_SETTING( 40000, FULL, 40000baseKR4_Full ),
223 PHY_SETTING( 40000, FULL, 40000baseLR4_Full ),
224 PHY_SETTING( 40000, FULL, 40000baseSR4_Full ),
225 /* 25G */
226 PHY_SETTING( 25000, FULL, 25000baseCR_Full ),
227 PHY_SETTING( 25000, FULL, 25000baseKR_Full ),
228 PHY_SETTING( 25000, FULL, 25000baseSR_Full ),
229 /* 20G */
230 PHY_SETTING( 20000, FULL, 20000baseKR2_Full ),
231 PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ),
232 /* 10G */
233 PHY_SETTING( 10000, FULL, 10000baseCR_Full ),
234 PHY_SETTING( 10000, FULL, 10000baseER_Full ),
235 PHY_SETTING( 10000, FULL, 10000baseKR_Full ),
236 PHY_SETTING( 10000, FULL, 10000baseKX4_Full ),
237 PHY_SETTING( 10000, FULL, 10000baseLR_Full ),
238 PHY_SETTING( 10000, FULL, 10000baseLRM_Full ),
239 PHY_SETTING( 10000, FULL, 10000baseR_FEC ),
240 PHY_SETTING( 10000, FULL, 10000baseSR_Full ),
241 PHY_SETTING( 10000, FULL, 10000baseT_Full ),
242 /* 5G */
243 PHY_SETTING( 5000, FULL, 5000baseT_Full ),
244 /* 2.5G */
245 PHY_SETTING( 2500, FULL, 2500baseT_Full ),
246 PHY_SETTING( 2500, FULL, 2500baseX_Full ),
247 /* 1G */
248 PHY_SETTING( 1000, FULL, 1000baseT_Full ),
249 PHY_SETTING( 1000, HALF, 1000baseT_Half ),
250 PHY_SETTING( 1000, FULL, 1000baseT1_Full ),
251 PHY_SETTING( 1000, FULL, 1000baseX_Full ),
252 PHY_SETTING( 1000, FULL, 1000baseKX_Full ),
253 /* 100M */
254 PHY_SETTING( 100, FULL, 100baseT_Full ),
255 PHY_SETTING( 100, FULL, 100baseT1_Full ),
256 PHY_SETTING( 100, HALF, 100baseT_Half ),
257 PHY_SETTING( 100, HALF, 100baseFX_Half ),
258 PHY_SETTING( 100, FULL, 100baseFX_Full ),
259 /* 10M */
260 PHY_SETTING( 10, FULL, 10baseT_Full ),
261 PHY_SETTING( 10, HALF, 10baseT_Half ),
262 PHY_SETTING( 10, FULL, 10baseT1L_Full ),
263};
264#undef PHY_SETTING
265
266/**
267 * phy_lookup_setting - lookup a PHY setting
268 * @speed: speed to match
269 * @duplex: duplex to match
270 * @mask: allowed link modes
271 * @exact: an exact match is required
272 *
273 * Search the settings array for a setting that matches the speed and
274 * duplex, and which is supported.
275 *
276 * If @exact is unset, either an exact match or %NULL for no match will
277 * be returned.
278 *
279 * If @exact is set, an exact match, the fastest supported setting at
280 * or below the specified speed, the slowest supported setting, or if
281 * they all fail, %NULL will be returned.
282 */
283const struct phy_setting *
284phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact)
285{
286 const struct phy_setting *p, *match = NULL, *last = NULL;
287 int i;
288
289 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
290 if (p->bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&
291 test_bit(p->bit, mask)) {
292 last = p;
293 if (p->speed == speed && p->duplex == duplex) {
294 /* Exact match for speed and duplex */
295 match = p;
296 break;
297 } else if (!exact) {
298 if (!match && p->speed <= speed)
299 /* Candidate */
300 match = p;
301
302 if (p->speed < speed)
303 break;
304 }
305 }
306 }
307
308 if (!match && !exact)
309 match = last;
310
311 return match;
312}
313EXPORT_SYMBOL_GPL(phy_lookup_setting);
314
315size_t phy_speeds(unsigned int *speeds, size_t size,
316 unsigned long *mask)
317{
318 size_t count;
319 int i;
320
321 for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++)
322 if (settings[i].bit < __ETHTOOL_LINK_MODE_MASK_NBITS &&
323 test_bit(settings[i].bit, mask) &&
324 (count == 0 || speeds[count - 1] != settings[i].speed))
325 speeds[count++] = settings[i].speed;
326
327 return count;
328}
329
330static void __set_linkmode_max_speed(u32 max_speed, unsigned long *addr)
331{
332 const struct phy_setting *p;
333 int i;
334
335 for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
336 if (p->speed > max_speed)
337 linkmode_clear_bit(p->bit, addr);
338 else
339 break;
340 }
341}
342
343static void __set_phy_supported(struct phy_device *phydev, u32 max_speed)
344{
345 __set_linkmode_max_speed(max_speed, phydev->supported);
346}
347
348/**
349 * phy_set_max_speed - Set the maximum speed the PHY should support
350 *
351 * @phydev: The phy_device struct
352 * @max_speed: Maximum speed
353 *
354 * The PHY might be more capable than the MAC. For example a Fast Ethernet
355 * is connected to a 1G PHY. This function allows the MAC to indicate its
356 * maximum speed, and so limit what the PHY will advertise.
357 */
358void phy_set_max_speed(struct phy_device *phydev, u32 max_speed)
359{
360 __set_phy_supported(phydev, max_speed);
361
362 phy_advertise_supported(phydev);
363}
364EXPORT_SYMBOL(phy_set_max_speed);
365
366void of_set_phy_supported(struct phy_device *phydev)
367{
368 struct device_node *node = phydev->mdio.dev.of_node;
369 u32 max_speed;
370
371 if (!IS_ENABLED(CONFIG_OF_MDIO))
372 return;
373
374 if (!node)
375 return;
376
377 if (!of_property_read_u32(node, "max-speed", &max_speed))
378 __set_phy_supported(phydev, max_speed);
379}
380
381void of_set_phy_eee_broken(struct phy_device *phydev)
382{
383 struct device_node *node = phydev->mdio.dev.of_node;
384 u32 broken = 0;
385
386 if (!IS_ENABLED(CONFIG_OF_MDIO))
387 return;
388
389 if (!node)
390 return;
391
392 if (of_property_read_bool(node, "eee-broken-100tx"))
393 broken |= MDIO_EEE_100TX;
394 if (of_property_read_bool(node, "eee-broken-1000t"))
395 broken |= MDIO_EEE_1000T;
396 if (of_property_read_bool(node, "eee-broken-10gt"))
397 broken |= MDIO_EEE_10GT;
398 if (of_property_read_bool(node, "eee-broken-1000kx"))
399 broken |= MDIO_EEE_1000KX;
400 if (of_property_read_bool(node, "eee-broken-10gkx4"))
401 broken |= MDIO_EEE_10GKX4;
402 if (of_property_read_bool(node, "eee-broken-10gkr"))
403 broken |= MDIO_EEE_10GKR;
404
405 phydev->eee_broken_modes = broken;
406}
407
408/**
409 * phy_resolve_aneg_pause - Determine pause autoneg results
410 *
411 * @phydev: The phy_device struct
412 *
413 * Once autoneg has completed the local pause settings can be
414 * resolved. Determine if pause and asymmetric pause should be used
415 * by the MAC.
416 */
417
418void phy_resolve_aneg_pause(struct phy_device *phydev)
419{
420 if (phydev->duplex == DUPLEX_FULL) {
421 phydev->pause = linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
422 phydev->lp_advertising);
423 phydev->asym_pause = linkmode_test_bit(
424 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
425 phydev->lp_advertising);
426 }
427}
428EXPORT_SYMBOL_GPL(phy_resolve_aneg_pause);
429
430/**
431 * phy_resolve_aneg_linkmode - resolve the advertisements into PHY settings
432 * @phydev: The phy_device struct
433 *
434 * Resolve our and the link partner advertisements into their corresponding
435 * speed and duplex. If full duplex was negotiated, extract the pause mode
436 * from the link partner mask.
437 */
438void phy_resolve_aneg_linkmode(struct phy_device *phydev)
439{
440 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
441 int i;
442
443 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
444
445 for (i = 0; i < ARRAY_SIZE(settings); i++)
446 if (test_bit(settings[i].bit, common)) {
447 phydev->speed = settings[i].speed;
448 phydev->duplex = settings[i].duplex;
449 break;
450 }
451
452 phy_resolve_aneg_pause(phydev);
453}
454EXPORT_SYMBOL_GPL(phy_resolve_aneg_linkmode);
455
456/**
457 * phy_check_downshift - check whether downshift occurred
458 * @phydev: The phy_device struct
459 *
460 * Check whether a downshift to a lower speed occurred. If this should be the
461 * case warn the user.
462 * Prerequisite for detecting downshift is that PHY driver implements the
463 * read_status callback and sets phydev->speed to the actual link speed.
464 */
465void phy_check_downshift(struct phy_device *phydev)
466{
467 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
468 int i, speed = SPEED_UNKNOWN;
469
470 phydev->downshifted_rate = 0;
471
472 if (phydev->autoneg == AUTONEG_DISABLE ||
473 phydev->speed == SPEED_UNKNOWN)
474 return;
475
476 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
477
478 for (i = 0; i < ARRAY_SIZE(settings); i++)
479 if (test_bit(settings[i].bit, common)) {
480 speed = settings[i].speed;
481 break;
482 }
483
484 if (speed == SPEED_UNKNOWN || phydev->speed >= speed)
485 return;
486
487 phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n",
488 phy_speed_to_str(speed), phy_speed_to_str(phydev->speed));
489
490 phydev->downshifted_rate = 1;
491}
492EXPORT_SYMBOL_GPL(phy_check_downshift);
493
494static int phy_resolve_min_speed(struct phy_device *phydev, bool fdx_only)
495{
496 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
497 int i = ARRAY_SIZE(settings);
498
499 linkmode_and(common, phydev->lp_advertising, phydev->advertising);
500
501 while (--i >= 0) {
502 if (test_bit(settings[i].bit, common)) {
503 if (fdx_only && settings[i].duplex != DUPLEX_FULL)
504 continue;
505 return settings[i].speed;
506 }
507 }
508
509 return SPEED_UNKNOWN;
510}
511
512int phy_speed_down_core(struct phy_device *phydev)
513{
514 int min_common_speed = phy_resolve_min_speed(phydev, true);
515
516 if (min_common_speed == SPEED_UNKNOWN)
517 return -EINVAL;
518
519 __set_linkmode_max_speed(min_common_speed, phydev->advertising);
520
521 return 0;
522}
523
524static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
525 u16 regnum)
526{
527 /* Write the desired MMD Devad */
528 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
529
530 /* Write the desired MMD register address */
531 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
532
533 /* Select the Function : DATA with no post increment */
534 __mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
535 devad | MII_MMD_CTRL_NOINCR);
536}
537
538/**
539 * __phy_read_mmd - Convenience function for reading a register
540 * from an MMD on a given PHY.
541 * @phydev: The phy_device struct
542 * @devad: The MMD to read from (0..31)
543 * @regnum: The register on the MMD to read (0..65535)
544 *
545 * Same rules as for __phy_read();
546 */
547int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
548{
549 int val;
550
551 if (regnum > (u16)~0 || devad > 32)
552 return -EINVAL;
553
554 if (phydev->drv && phydev->drv->read_mmd) {
555 val = phydev->drv->read_mmd(phydev, devad, regnum);
556 } else if (phydev->is_c45) {
557 val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr,
558 devad, regnum);
559 } else {
560 struct mii_bus *bus = phydev->mdio.bus;
561 int phy_addr = phydev->mdio.addr;
562
563 mmd_phy_indirect(bus, phy_addr, devad, regnum);
564
565 /* Read the content of the MMD's selected register */
566 val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
567 }
568 return val;
569}
570EXPORT_SYMBOL(__phy_read_mmd);
571
572/**
573 * phy_read_mmd - Convenience function for reading a register
574 * from an MMD on a given PHY.
575 * @phydev: The phy_device struct
576 * @devad: The MMD to read from
577 * @regnum: The register on the MMD to read
578 *
579 * Same rules as for phy_read();
580 */
581int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
582{
583 int ret;
584
585 phy_lock_mdio_bus(phydev);
586 ret = __phy_read_mmd(phydev, devad, regnum);
587 phy_unlock_mdio_bus(phydev);
588
589 return ret;
590}
591EXPORT_SYMBOL(phy_read_mmd);
592
593/**
594 * __phy_write_mmd - Convenience function for writing a register
595 * on an MMD on a given PHY.
596 * @phydev: The phy_device struct
597 * @devad: The MMD to read from
598 * @regnum: The register on the MMD to read
599 * @val: value to write to @regnum
600 *
601 * Same rules as for __phy_write();
602 */
603int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
604{
605 int ret;
606
607 if (regnum > (u16)~0 || devad > 32)
608 return -EINVAL;
609
610 if (phydev->drv && phydev->drv->write_mmd) {
611 ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
612 } else if (phydev->is_c45) {
613 ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr,
614 devad, regnum, val);
615 } else {
616 struct mii_bus *bus = phydev->mdio.bus;
617 int phy_addr = phydev->mdio.addr;
618
619 mmd_phy_indirect(bus, phy_addr, devad, regnum);
620
621 /* Write the data into MMD's selected register */
622 __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
623
624 ret = 0;
625 }
626 return ret;
627}
628EXPORT_SYMBOL(__phy_write_mmd);
629
630/**
631 * phy_write_mmd - Convenience function for writing a register
632 * on an MMD on a given PHY.
633 * @phydev: The phy_device struct
634 * @devad: The MMD to read from
635 * @regnum: The register on the MMD to read
636 * @val: value to write to @regnum
637 *
638 * Same rules as for phy_write();
639 */
640int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
641{
642 int ret;
643
644 phy_lock_mdio_bus(phydev);
645 ret = __phy_write_mmd(phydev, devad, regnum, val);
646 phy_unlock_mdio_bus(phydev);
647
648 return ret;
649}
650EXPORT_SYMBOL(phy_write_mmd);
651
652/**
653 * phy_modify_changed - Function for modifying a PHY register
654 * @phydev: the phy_device struct
655 * @regnum: register number to modify
656 * @mask: bit mask of bits to clear
657 * @set: new value of bits set in mask to write to @regnum
658 *
659 * NOTE: MUST NOT be called from interrupt context,
660 * because the bus read/write functions may wait for an interrupt
661 * to conclude the operation.
662 *
663 * Returns negative errno, 0 if there was no change, and 1 in case of change
664 */
665int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
666{
667 int ret;
668
669 phy_lock_mdio_bus(phydev);
670 ret = __phy_modify_changed(phydev, regnum, mask, set);
671 phy_unlock_mdio_bus(phydev);
672
673 return ret;
674}
675EXPORT_SYMBOL_GPL(phy_modify_changed);
676
677/**
678 * __phy_modify - Convenience function for modifying a PHY register
679 * @phydev: the phy_device struct
680 * @regnum: register number to modify
681 * @mask: bit mask of bits to clear
682 * @set: new value of bits set in mask to write to @regnum
683 *
684 * NOTE: MUST NOT be called from interrupt context,
685 * because the bus read/write functions may wait for an interrupt
686 * to conclude the operation.
687 */
688int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
689{
690 int ret;
691
692 ret = __phy_modify_changed(phydev, regnum, mask, set);
693
694 return ret < 0 ? ret : 0;
695}
696EXPORT_SYMBOL_GPL(__phy_modify);
697
698/**
699 * phy_modify - Convenience function for modifying a given PHY register
700 * @phydev: the phy_device struct
701 * @regnum: register number to write
702 * @mask: bit mask of bits to clear
703 * @set: new value of bits set in mask to write to @regnum
704 *
705 * NOTE: MUST NOT be called from interrupt context,
706 * because the bus read/write functions may wait for an interrupt
707 * to conclude the operation.
708 */
709int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
710{
711 int ret;
712
713 phy_lock_mdio_bus(phydev);
714 ret = __phy_modify(phydev, regnum, mask, set);
715 phy_unlock_mdio_bus(phydev);
716
717 return ret;
718}
719EXPORT_SYMBOL_GPL(phy_modify);
720
721/**
722 * __phy_modify_mmd_changed - Function for modifying a register on MMD
723 * @phydev: the phy_device struct
724 * @devad: the MMD containing register to modify
725 * @regnum: register number to modify
726 * @mask: bit mask of bits to clear
727 * @set: new value of bits set in mask to write to @regnum
728 *
729 * Unlocked helper function which allows a MMD register to be modified as
730 * new register value = (old register value & ~mask) | set
731 *
732 * Returns negative errno, 0 if there was no change, and 1 in case of change
733 */
734int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
735 u16 mask, u16 set)
736{
737 int new, ret;
738
739 ret = __phy_read_mmd(phydev, devad, regnum);
740 if (ret < 0)
741 return ret;
742
743 new = (ret & ~mask) | set;
744 if (new == ret)
745 return 0;
746
747 ret = __phy_write_mmd(phydev, devad, regnum, new);
748
749 return ret < 0 ? ret : 1;
750}
751EXPORT_SYMBOL_GPL(__phy_modify_mmd_changed);
752
753/**
754 * phy_modify_mmd_changed - Function for modifying a register on MMD
755 * @phydev: the phy_device struct
756 * @devad: the MMD containing register to modify
757 * @regnum: register number to modify
758 * @mask: bit mask of bits to clear
759 * @set: new value of bits set in mask to write to @regnum
760 *
761 * NOTE: MUST NOT be called from interrupt context,
762 * because the bus read/write functions may wait for an interrupt
763 * to conclude the operation.
764 *
765 * Returns negative errno, 0 if there was no change, and 1 in case of change
766 */
767int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
768 u16 mask, u16 set)
769{
770 int ret;
771
772 phy_lock_mdio_bus(phydev);
773 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
774 phy_unlock_mdio_bus(phydev);
775
776 return ret;
777}
778EXPORT_SYMBOL_GPL(phy_modify_mmd_changed);
779
780/**
781 * __phy_modify_mmd - Convenience function for modifying a register on MMD
782 * @phydev: the phy_device struct
783 * @devad: the MMD containing register to modify
784 * @regnum: register number to modify
785 * @mask: bit mask of bits to clear
786 * @set: new value of bits set in mask to write to @regnum
787 *
788 * NOTE: MUST NOT be called from interrupt context,
789 * because the bus read/write functions may wait for an interrupt
790 * to conclude the operation.
791 */
792int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
793 u16 mask, u16 set)
794{
795 int ret;
796
797 ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
798
799 return ret < 0 ? ret : 0;
800}
801EXPORT_SYMBOL_GPL(__phy_modify_mmd);
802
803/**
804 * phy_modify_mmd - Convenience function for modifying a register on MMD
805 * @phydev: the phy_device struct
806 * @devad: the MMD containing register to modify
807 * @regnum: register number to modify
808 * @mask: bit mask of bits to clear
809 * @set: new value of bits set in mask to write to @regnum
810 *
811 * NOTE: MUST NOT be called from interrupt context,
812 * because the bus read/write functions may wait for an interrupt
813 * to conclude the operation.
814 */
815int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
816 u16 mask, u16 set)
817{
818 int ret;
819
820 phy_lock_mdio_bus(phydev);
821 ret = __phy_modify_mmd(phydev, devad, regnum, mask, set);
822 phy_unlock_mdio_bus(phydev);
823
824 return ret;
825}
826EXPORT_SYMBOL_GPL(phy_modify_mmd);
827
828static int __phy_read_page(struct phy_device *phydev)
829{
830 if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n"))
831 return -EOPNOTSUPP;
832
833 return phydev->drv->read_page(phydev);
834}
835
836static int __phy_write_page(struct phy_device *phydev, int page)
837{
838 if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n"))
839 return -EOPNOTSUPP;
840
841 return phydev->drv->write_page(phydev, page);
842}
843
844/**
845 * phy_save_page() - take the bus lock and save the current page
846 * @phydev: a pointer to a &struct phy_device
847 *
848 * Take the MDIO bus lock, and return the current page number. On error,
849 * returns a negative errno. phy_restore_page() must always be called
850 * after this, irrespective of success or failure of this call.
851 */
852int phy_save_page(struct phy_device *phydev)
853{
854 phy_lock_mdio_bus(phydev);
855 return __phy_read_page(phydev);
856}
857EXPORT_SYMBOL_GPL(phy_save_page);
858
859/**
860 * phy_select_page() - take the bus lock, save the current page, and set a page
861 * @phydev: a pointer to a &struct phy_device
862 * @page: desired page
863 *
864 * Take the MDIO bus lock to protect against concurrent access, save the
865 * current PHY page, and set the current page. On error, returns a
866 * negative errno, otherwise returns the previous page number.
867 * phy_restore_page() must always be called after this, irrespective
868 * of success or failure of this call.
869 */
870int phy_select_page(struct phy_device *phydev, int page)
871{
872 int ret, oldpage;
873
874 oldpage = ret = phy_save_page(phydev);
875 if (ret < 0)
876 return ret;
877
878 if (oldpage != page) {
879 ret = __phy_write_page(phydev, page);
880 if (ret < 0)
881 return ret;
882 }
883
884 return oldpage;
885}
886EXPORT_SYMBOL_GPL(phy_select_page);
887
888/**
889 * phy_restore_page() - restore the page register and release the bus lock
890 * @phydev: a pointer to a &struct phy_device
891 * @oldpage: the old page, return value from phy_save_page() or phy_select_page()
892 * @ret: operation's return code
893 *
894 * Release the MDIO bus lock, restoring @oldpage if it is a valid page.
895 * This function propagates the earliest error code from the group of
896 * operations.
897 *
898 * Returns:
899 * @oldpage if it was a negative value, otherwise
900 * @ret if it was a negative errno value, otherwise
901 * phy_write_page()'s negative value if it were in error, otherwise
902 * @ret.
903 */
904int phy_restore_page(struct phy_device *phydev, int oldpage, int ret)
905{
906 int r;
907
908 if (oldpage >= 0) {
909 r = __phy_write_page(phydev, oldpage);
910
911 /* Propagate the operation return code if the page write
912 * was successful.
913 */
914 if (ret >= 0 && r < 0)
915 ret = r;
916 } else {
917 /* Propagate the phy page selection error code */
918 ret = oldpage;
919 }
920
921 phy_unlock_mdio_bus(phydev);
922
923 return ret;
924}
925EXPORT_SYMBOL_GPL(phy_restore_page);
926
927/**
928 * phy_read_paged() - Convenience function for reading a paged register
929 * @phydev: a pointer to a &struct phy_device
930 * @page: the page for the phy
931 * @regnum: register number
932 *
933 * Same rules as for phy_read().
934 */
935int phy_read_paged(struct phy_device *phydev, int page, u32 regnum)
936{
937 int ret = 0, oldpage;
938
939 oldpage = phy_select_page(phydev, page);
940 if (oldpage >= 0)
941 ret = __phy_read(phydev, regnum);
942
943 return phy_restore_page(phydev, oldpage, ret);
944}
945EXPORT_SYMBOL(phy_read_paged);
946
947/**
948 * phy_write_paged() - Convenience function for writing a paged register
949 * @phydev: a pointer to a &struct phy_device
950 * @page: the page for the phy
951 * @regnum: register number
952 * @val: value to write
953 *
954 * Same rules as for phy_write().
955 */
956int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
957{
958 int ret = 0, oldpage;
959
960 oldpage = phy_select_page(phydev, page);
961 if (oldpage >= 0)
962 ret = __phy_write(phydev, regnum, val);
963
964 return phy_restore_page(phydev, oldpage, ret);
965}
966EXPORT_SYMBOL(phy_write_paged);
967
968/**
969 * phy_modify_paged_changed() - Function for modifying a paged register
970 * @phydev: a pointer to a &struct phy_device
971 * @page: the page for the phy
972 * @regnum: register number
973 * @mask: bit mask of bits to clear
974 * @set: bit mask of bits to set
975 *
976 * Returns negative errno, 0 if there was no change, and 1 in case of change
977 */
978int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
979 u16 mask, u16 set)
980{
981 int ret = 0, oldpage;
982
983 oldpage = phy_select_page(phydev, page);
984 if (oldpage >= 0)
985 ret = __phy_modify_changed(phydev, regnum, mask, set);
986
987 return phy_restore_page(phydev, oldpage, ret);
988}
989EXPORT_SYMBOL(phy_modify_paged_changed);
990
991/**
992 * phy_modify_paged() - Convenience function for modifying a paged register
993 * @phydev: a pointer to a &struct phy_device
994 * @page: the page for the phy
995 * @regnum: register number
996 * @mask: bit mask of bits to clear
997 * @set: bit mask of bits to set
998 *
999 * Same rules as for phy_read() and phy_write().
1000 */
1001int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
1002 u16 mask, u16 set)
1003{
1004 int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set);
1005
1006 return ret < 0 ? ret : 0;
1007}
1008EXPORT_SYMBOL(phy_modify_paged);