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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5#include <linux/ethtool.h>
6
7static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14/* Cable length tables */
15static const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17};
18
19#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 ARRAY_SIZE(e1000_m88_cable_length_table)
21
22static const u16 e1000_igp_2_cable_length_table[] = {
23 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 124
31};
32
33#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 ARRAY_SIZE(e1000_igp_2_cable_length_table)
35
36/**
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
39 *
40 * Read the PHY management control register and check whether a PHY reset
41 * is blocked. If a reset is not blocked return 0, otherwise
42 * return E1000_BLK_PHY_RESET (12).
43 **/
44s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45{
46 u32 manc;
47
48 manc = er32(MANC);
49
50 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51}
52
53/**
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
56 *
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
58 * revision in the hardware structure.
59 **/
60s32 e1000e_get_phy_id(struct e1000_hw *hw)
61{
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = 0;
64 u16 phy_id;
65 u16 retry_count = 0;
66
67 if (!phy->ops.read_reg)
68 return 0;
69
70 while (retry_count < 2) {
71 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 if (ret_val)
73 return ret_val;
74
75 phy->id = (u32)(phy_id << 16);
76 usleep_range(20, 40);
77 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 if (ret_val)
79 return ret_val;
80
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 return 0;
86
87 retry_count++;
88 }
89
90 return 0;
91}
92
93/**
94 * e1000e_phy_reset_dsp - Reset PHY DSP
95 * @hw: pointer to the HW structure
96 *
97 * Reset the digital signal processor.
98 **/
99s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100{
101 s32 ret_val;
102
103 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 if (ret_val)
105 return ret_val;
106
107 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108}
109
110void e1000e_disable_phy_retry(struct e1000_hw *hw)
111{
112 hw->phy.retry_enabled = false;
113}
114
115void e1000e_enable_phy_retry(struct e1000_hw *hw)
116{
117 hw->phy.retry_enabled = true;
118}
119
120/**
121 * e1000e_read_phy_reg_mdic - Read MDI control register
122 * @hw: pointer to the HW structure
123 * @offset: register offset to be read
124 * @data: pointer to the read data
125 *
126 * Reads the MDI control register in the PHY at offset and stores the
127 * information read to data.
128 **/
129s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
130{
131 u32 i, mdic = 0, retry_counter, retry_max;
132 struct e1000_phy_info *phy = &hw->phy;
133 bool success;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 e_dbg("PHY Address %d is out of range\n", offset);
137 return -E1000_ERR_PARAM;
138 }
139
140 retry_max = phy->retry_enabled ? phy->retry_count : 0;
141
142 /* Set up Op-code, Phy Address, and register offset in the MDI
143 * Control register. The MAC will take care of interfacing with the
144 * PHY to retrieve the desired data.
145 */
146 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
147 success = true;
148
149 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
150 (phy->addr << E1000_MDIC_PHY_SHIFT) |
151 (E1000_MDIC_OP_READ));
152
153 ew32(MDIC, mdic);
154
155 /* Poll the ready bit to see if the MDI read completed
156 * Increasing the time out as testing showed failures with
157 * the lower time out
158 */
159 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
160 udelay(50);
161 mdic = er32(MDIC);
162 if (mdic & E1000_MDIC_READY)
163 break;
164 }
165 if (!(mdic & E1000_MDIC_READY)) {
166 e_dbg("MDI Read PHY Reg Address %d did not complete\n",
167 offset);
168 success = false;
169 }
170 if (mdic & E1000_MDIC_ERROR) {
171 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
172 success = false;
173 }
174 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
175 e_dbg("MDI Read offset error - requested %d, returned %d\n",
176 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
177 success = false;
178 }
179
180 /* Allow some time after each MDIC transaction to avoid
181 * reading duplicate data in the next MDIC transaction.
182 */
183 if (hw->mac.type == e1000_pch2lan)
184 udelay(100);
185
186 if (success) {
187 *data = (u16)mdic;
188 return 0;
189 }
190
191 if (retry_counter != retry_max) {
192 e_dbg("Perform retry on PHY transaction...\n");
193 mdelay(10);
194 }
195 }
196
197 return -E1000_ERR_PHY;
198}
199
200/**
201 * e1000e_write_phy_reg_mdic - Write MDI control register
202 * @hw: pointer to the HW structure
203 * @offset: register offset to write to
204 * @data: data to write to register at offset
205 *
206 * Writes data to MDI control register in the PHY at offset.
207 **/
208s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
209{
210 u32 i, mdic = 0, retry_counter, retry_max;
211 struct e1000_phy_info *phy = &hw->phy;
212 bool success;
213
214 if (offset > MAX_PHY_REG_ADDRESS) {
215 e_dbg("PHY Address %d is out of range\n", offset);
216 return -E1000_ERR_PARAM;
217 }
218
219 retry_max = phy->retry_enabled ? phy->retry_count : 0;
220
221 /* Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
224 */
225 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
226 success = true;
227
228 mdic = (((u32)data) |
229 (offset << E1000_MDIC_REG_SHIFT) |
230 (phy->addr << E1000_MDIC_PHY_SHIFT) |
231 (E1000_MDIC_OP_WRITE));
232
233 ew32(MDIC, mdic);
234
235 /* Poll the ready bit to see if the MDI read completed
236 * Increasing the time out as testing showed failures with
237 * the lower time out
238 */
239 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
240 udelay(50);
241 mdic = er32(MDIC);
242 if (mdic & E1000_MDIC_READY)
243 break;
244 }
245 if (!(mdic & E1000_MDIC_READY)) {
246 e_dbg("MDI Write PHY Reg Address %d did not complete\n",
247 offset);
248 success = false;
249 }
250 if (mdic & E1000_MDIC_ERROR) {
251 e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
252 success = false;
253 }
254 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
255 e_dbg("MDI Write offset error - requested %d, returned %d\n",
256 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
257 success = false;
258 }
259
260 /* Allow some time after each MDIC transaction to avoid
261 * reading duplicate data in the next MDIC transaction.
262 */
263 if (hw->mac.type == e1000_pch2lan)
264 udelay(100);
265
266 if (success)
267 return 0;
268
269 if (retry_counter != retry_max) {
270 e_dbg("Perform retry on PHY transaction...\n");
271 mdelay(10);
272 }
273 }
274
275 return -E1000_ERR_PHY;
276}
277
278/**
279 * e1000e_read_phy_reg_m88 - Read m88 PHY register
280 * @hw: pointer to the HW structure
281 * @offset: register offset to be read
282 * @data: pointer to the read data
283 *
284 * Acquires semaphore, if necessary, then reads the PHY register at offset
285 * and storing the retrieved information in data. Release any acquired
286 * semaphores before exiting.
287 **/
288s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
289{
290 s32 ret_val;
291
292 ret_val = hw->phy.ops.acquire(hw);
293 if (ret_val)
294 return ret_val;
295
296 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
297 data);
298
299 hw->phy.ops.release(hw);
300
301 return ret_val;
302}
303
304/**
305 * e1000e_write_phy_reg_m88 - Write m88 PHY register
306 * @hw: pointer to the HW structure
307 * @offset: register offset to write to
308 * @data: data to write at register offset
309 *
310 * Acquires semaphore, if necessary, then writes the data to PHY register
311 * at the offset. Release any acquired semaphores before exiting.
312 **/
313s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
314{
315 s32 ret_val;
316
317 ret_val = hw->phy.ops.acquire(hw);
318 if (ret_val)
319 return ret_val;
320
321 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
322 data);
323
324 hw->phy.ops.release(hw);
325
326 return ret_val;
327}
328
329/**
330 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
331 * @hw: pointer to the HW structure
332 * @page: page to set (shifted left when necessary)
333 *
334 * Sets PHY page required for PHY register access. Assumes semaphore is
335 * already acquired. Note, this function sets phy.addr to 1 so the caller
336 * must set it appropriately (if necessary) after this function returns.
337 **/
338s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
339{
340 e_dbg("Setting page 0x%x\n", page);
341
342 hw->phy.addr = 1;
343
344 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
345}
346
347/**
348 * __e1000e_read_phy_reg_igp - Read igp PHY register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to be read
351 * @data: pointer to the read data
352 * @locked: semaphore has already been acquired or not
353 *
354 * Acquires semaphore, if necessary, then reads the PHY register at offset
355 * and stores the retrieved information in data. Release any acquired
356 * semaphores before exiting.
357 **/
358static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
359 bool locked)
360{
361 s32 ret_val = 0;
362
363 if (!locked) {
364 if (!hw->phy.ops.acquire)
365 return 0;
366
367 ret_val = hw->phy.ops.acquire(hw);
368 if (ret_val)
369 return ret_val;
370 }
371
372 if (offset > MAX_PHY_MULTI_PAGE_REG)
373 ret_val = e1000e_write_phy_reg_mdic(hw,
374 IGP01E1000_PHY_PAGE_SELECT,
375 (u16)offset);
376 if (!ret_val)
377 ret_val = e1000e_read_phy_reg_mdic(hw,
378 MAX_PHY_REG_ADDRESS & offset,
379 data);
380 if (!locked)
381 hw->phy.ops.release(hw);
382
383 return ret_val;
384}
385
386/**
387 * e1000e_read_phy_reg_igp - Read igp PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
391 *
392 * Acquires semaphore then reads the PHY register at offset and stores the
393 * retrieved information in data.
394 * Release the acquired semaphore before exiting.
395 **/
396s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
397{
398 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
399}
400
401/**
402 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
403 * @hw: pointer to the HW structure
404 * @offset: register offset to be read
405 * @data: pointer to the read data
406 *
407 * Reads the PHY register at offset and stores the retrieved information
408 * in data. Assumes semaphore already acquired.
409 **/
410s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
411{
412 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
413}
414
415/**
416 * __e1000e_write_phy_reg_igp - Write igp PHY register
417 * @hw: pointer to the HW structure
418 * @offset: register offset to write to
419 * @data: data to write at register offset
420 * @locked: semaphore has already been acquired or not
421 *
422 * Acquires semaphore, if necessary, then writes the data to PHY register
423 * at the offset. Release any acquired semaphores before exiting.
424 **/
425static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
426 bool locked)
427{
428 s32 ret_val = 0;
429
430 if (!locked) {
431 if (!hw->phy.ops.acquire)
432 return 0;
433
434 ret_val = hw->phy.ops.acquire(hw);
435 if (ret_val)
436 return ret_val;
437 }
438
439 if (offset > MAX_PHY_MULTI_PAGE_REG)
440 ret_val = e1000e_write_phy_reg_mdic(hw,
441 IGP01E1000_PHY_PAGE_SELECT,
442 (u16)offset);
443 if (!ret_val)
444 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
445 offset, data);
446 if (!locked)
447 hw->phy.ops.release(hw);
448
449 return ret_val;
450}
451
452/**
453 * e1000e_write_phy_reg_igp - Write igp PHY register
454 * @hw: pointer to the HW structure
455 * @offset: register offset to write to
456 * @data: data to write at register offset
457 *
458 * Acquires semaphore then writes the data to PHY register
459 * at the offset. Release any acquired semaphores before exiting.
460 **/
461s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
462{
463 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
464}
465
466/**
467 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
468 * @hw: pointer to the HW structure
469 * @offset: register offset to write to
470 * @data: data to write at register offset
471 *
472 * Writes the data to PHY register at the offset.
473 * Assumes semaphore already acquired.
474 **/
475s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
476{
477 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
478}
479
480/**
481 * __e1000_read_kmrn_reg - Read kumeran register
482 * @hw: pointer to the HW structure
483 * @offset: register offset to be read
484 * @data: pointer to the read data
485 * @locked: semaphore has already been acquired or not
486 *
487 * Acquires semaphore, if necessary. Then reads the PHY register at offset
488 * using the kumeran interface. The information retrieved is stored in data.
489 * Release any acquired semaphores before exiting.
490 **/
491static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
492 bool locked)
493{
494 u32 kmrnctrlsta;
495
496 if (!locked) {
497 s32 ret_val = 0;
498
499 if (!hw->phy.ops.acquire)
500 return 0;
501
502 ret_val = hw->phy.ops.acquire(hw);
503 if (ret_val)
504 return ret_val;
505 }
506
507 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
508 E1000_KMRNCTRLSTA_REN;
509 ew32(KMRNCTRLSTA, kmrnctrlsta);
510 e1e_flush();
511
512 udelay(2);
513
514 kmrnctrlsta = er32(KMRNCTRLSTA);
515 *data = (u16)kmrnctrlsta;
516
517 if (!locked)
518 hw->phy.ops.release(hw);
519
520 return 0;
521}
522
523/**
524 * e1000e_read_kmrn_reg - Read kumeran register
525 * @hw: pointer to the HW structure
526 * @offset: register offset to be read
527 * @data: pointer to the read data
528 *
529 * Acquires semaphore then reads the PHY register at offset using the
530 * kumeran interface. The information retrieved is stored in data.
531 * Release the acquired semaphore before exiting.
532 **/
533s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
534{
535 return __e1000_read_kmrn_reg(hw, offset, data, false);
536}
537
538/**
539 * e1000e_read_kmrn_reg_locked - Read kumeran register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be read
542 * @data: pointer to the read data
543 *
544 * Reads the PHY register at offset using the kumeran interface. The
545 * information retrieved is stored in data.
546 * Assumes semaphore already acquired.
547 **/
548s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
549{
550 return __e1000_read_kmrn_reg(hw, offset, data, true);
551}
552
553/**
554 * __e1000_write_kmrn_reg - Write kumeran register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to write to
557 * @data: data to write at register offset
558 * @locked: semaphore has already been acquired or not
559 *
560 * Acquires semaphore, if necessary. Then write the data to PHY register
561 * at the offset using the kumeran interface. Release any acquired semaphores
562 * before exiting.
563 **/
564static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
565 bool locked)
566{
567 u32 kmrnctrlsta;
568
569 if (!locked) {
570 s32 ret_val = 0;
571
572 if (!hw->phy.ops.acquire)
573 return 0;
574
575 ret_val = hw->phy.ops.acquire(hw);
576 if (ret_val)
577 return ret_val;
578 }
579
580 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
581 ew32(KMRNCTRLSTA, kmrnctrlsta);
582 e1e_flush();
583
584 udelay(2);
585
586 if (!locked)
587 hw->phy.ops.release(hw);
588
589 return 0;
590}
591
592/**
593 * e1000e_write_kmrn_reg - Write kumeran register
594 * @hw: pointer to the HW structure
595 * @offset: register offset to write to
596 * @data: data to write at register offset
597 *
598 * Acquires semaphore then writes the data to the PHY register at the offset
599 * using the kumeran interface. Release the acquired semaphore before exiting.
600 **/
601s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
602{
603 return __e1000_write_kmrn_reg(hw, offset, data, false);
604}
605
606/**
607 * e1000e_write_kmrn_reg_locked - Write kumeran register
608 * @hw: pointer to the HW structure
609 * @offset: register offset to write to
610 * @data: data to write at register offset
611 *
612 * Write the data to PHY register at the offset using the kumeran interface.
613 * Assumes semaphore already acquired.
614 **/
615s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
616{
617 return __e1000_write_kmrn_reg(hw, offset, data, true);
618}
619
620/**
621 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
622 * @hw: pointer to the HW structure
623 *
624 * Sets up Master/slave mode
625 **/
626static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
627{
628 s32 ret_val;
629 u16 phy_data;
630
631 /* Resolve Master/Slave mode */
632 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
633 if (ret_val)
634 return ret_val;
635
636 /* load defaults for future use */
637 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
638 ((phy_data & CTL1000_AS_MASTER) ?
639 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
640
641 switch (hw->phy.ms_type) {
642 case e1000_ms_force_master:
643 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
644 break;
645 case e1000_ms_force_slave:
646 phy_data |= CTL1000_ENABLE_MASTER;
647 phy_data &= ~(CTL1000_AS_MASTER);
648 break;
649 case e1000_ms_auto:
650 phy_data &= ~CTL1000_ENABLE_MASTER;
651 fallthrough;
652 default:
653 break;
654 }
655
656 return e1e_wphy(hw, MII_CTRL1000, phy_data);
657}
658
659/**
660 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
661 * @hw: pointer to the HW structure
662 *
663 * Sets up Carrier-sense on Transmit and downshift values.
664 **/
665s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
666{
667 s32 ret_val;
668 u16 phy_data;
669
670 /* Enable CRS on Tx. This must be set for half-duplex operation. */
671 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
672 if (ret_val)
673 return ret_val;
674
675 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
676
677 /* Enable downshift */
678 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
679
680 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
681 if (ret_val)
682 return ret_val;
683
684 /* Set MDI/MDIX mode */
685 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
686 if (ret_val)
687 return ret_val;
688 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
689 /* Options:
690 * 0 - Auto (default)
691 * 1 - MDI mode
692 * 2 - MDI-X mode
693 */
694 switch (hw->phy.mdix) {
695 case 1:
696 break;
697 case 2:
698 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
699 break;
700 case 0:
701 default:
702 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
703 break;
704 }
705 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
706 if (ret_val)
707 return ret_val;
708
709 return e1000_set_master_slave_mode(hw);
710}
711
712/**
713 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
714 * @hw: pointer to the HW structure
715 *
716 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
717 * and downshift values are set also.
718 **/
719s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
720{
721 struct e1000_phy_info *phy = &hw->phy;
722 s32 ret_val;
723 u16 phy_data;
724
725 /* Enable CRS on Tx. This must be set for half-duplex operation. */
726 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
727 if (ret_val)
728 return ret_val;
729
730 /* For BM PHY this bit is downshift enable */
731 if (phy->type != e1000_phy_bm)
732 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
733
734 /* Options:
735 * MDI/MDI-X = 0 (default)
736 * 0 - Auto for all speeds
737 * 1 - MDI mode
738 * 2 - MDI-X mode
739 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
740 */
741 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
742
743 switch (phy->mdix) {
744 case 1:
745 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
746 break;
747 case 2:
748 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
749 break;
750 case 3:
751 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
752 break;
753 case 0:
754 default:
755 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
756 break;
757 }
758
759 /* Options:
760 * disable_polarity_correction = 0 (default)
761 * Automatic Correction for Reversed Cable Polarity
762 * 0 - Disabled
763 * 1 - Enabled
764 */
765 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
766 if (phy->disable_polarity_correction)
767 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
768
769 /* Enable downshift on BM (disabled by default) */
770 if (phy->type == e1000_phy_bm) {
771 /* For 82574/82583, first disable then enable downshift */
772 if (phy->id == BME1000_E_PHY_ID_R2) {
773 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
774 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
775 phy_data);
776 if (ret_val)
777 return ret_val;
778 /* Commit the changes. */
779 ret_val = phy->ops.commit(hw);
780 if (ret_val) {
781 e_dbg("Error committing the PHY changes\n");
782 return ret_val;
783 }
784 }
785
786 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
787 }
788
789 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
790 if (ret_val)
791 return ret_val;
792
793 if ((phy->type == e1000_phy_m88) &&
794 (phy->revision < E1000_REVISION_4) &&
795 (phy->id != BME1000_E_PHY_ID_R2)) {
796 /* Force TX_CLK in the Extended PHY Specific Control Register
797 * to 25MHz clock.
798 */
799 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
800 if (ret_val)
801 return ret_val;
802
803 phy_data |= M88E1000_EPSCR_TX_CLK_25;
804
805 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
806 /* 82573L PHY - set the downshift counter to 5x. */
807 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
808 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
809 } else {
810 /* Configure Master and Slave downshift values */
811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
812 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
814 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
815 }
816 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
817 if (ret_val)
818 return ret_val;
819 }
820
821 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
822 /* Set PHY page 0, register 29 to 0x0003 */
823 ret_val = e1e_wphy(hw, 29, 0x0003);
824 if (ret_val)
825 return ret_val;
826
827 /* Set PHY page 0, register 30 to 0x0000 */
828 ret_val = e1e_wphy(hw, 30, 0x0000);
829 if (ret_val)
830 return ret_val;
831 }
832
833 /* Commit the changes. */
834 if (phy->ops.commit) {
835 ret_val = phy->ops.commit(hw);
836 if (ret_val) {
837 e_dbg("Error committing the PHY changes\n");
838 return ret_val;
839 }
840 }
841
842 if (phy->type == e1000_phy_82578) {
843 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
844 if (ret_val)
845 return ret_val;
846
847 /* 82578 PHY - set the downshift count to 1x. */
848 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
849 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
850 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
851 if (ret_val)
852 return ret_val;
853 }
854
855 return 0;
856}
857
858/**
859 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
860 * @hw: pointer to the HW structure
861 *
862 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
863 * igp PHY's.
864 **/
865s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
866{
867 struct e1000_phy_info *phy = &hw->phy;
868 s32 ret_val;
869 u16 data;
870
871 ret_val = e1000_phy_hw_reset(hw);
872 if (ret_val) {
873 e_dbg("Error resetting the PHY.\n");
874 return ret_val;
875 }
876
877 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
878 * timeout issues when LFS is enabled.
879 */
880 msleep(100);
881
882 /* disable lplu d0 during driver init */
883 if (hw->phy.ops.set_d0_lplu_state) {
884 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
885 if (ret_val) {
886 e_dbg("Error Disabling LPLU D0\n");
887 return ret_val;
888 }
889 }
890 /* Configure mdi-mdix settings */
891 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
892 if (ret_val)
893 return ret_val;
894
895 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
896
897 switch (phy->mdix) {
898 case 1:
899 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
900 break;
901 case 2:
902 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
903 break;
904 case 0:
905 default:
906 data |= IGP01E1000_PSCR_AUTO_MDIX;
907 break;
908 }
909 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
910 if (ret_val)
911 return ret_val;
912
913 /* set auto-master slave resolution settings */
914 if (hw->mac.autoneg) {
915 /* when autonegotiation advertisement is only 1000Mbps then we
916 * should disable SmartSpeed and enable Auto MasterSlave
917 * resolution as hardware default.
918 */
919 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
920 /* Disable SmartSpeed */
921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
922 &data);
923 if (ret_val)
924 return ret_val;
925
926 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
927 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
928 data);
929 if (ret_val)
930 return ret_val;
931
932 /* Set auto Master/Slave resolution process */
933 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
934 if (ret_val)
935 return ret_val;
936
937 data &= ~CTL1000_ENABLE_MASTER;
938 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
939 if (ret_val)
940 return ret_val;
941 }
942
943 ret_val = e1000_set_master_slave_mode(hw);
944 }
945
946 return ret_val;
947}
948
949/**
950 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
951 * @hw: pointer to the HW structure
952 *
953 * Reads the MII auto-neg advertisement register and/or the 1000T control
954 * register and if the PHY is already setup for auto-negotiation, then
955 * return successful. Otherwise, setup advertisement and flow control to
956 * the appropriate values for the wanted auto-negotiation.
957 **/
958static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
959{
960 struct e1000_phy_info *phy = &hw->phy;
961 s32 ret_val;
962 u16 mii_autoneg_adv_reg;
963 u16 mii_1000t_ctrl_reg = 0;
964
965 phy->autoneg_advertised &= phy->autoneg_mask;
966
967 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
968 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
969 if (ret_val)
970 return ret_val;
971
972 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
973 /* Read the MII 1000Base-T Control Register (Address 9). */
974 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
975 if (ret_val)
976 return ret_val;
977 }
978
979 /* Need to parse both autoneg_advertised and fc and set up
980 * the appropriate PHY registers. First we will parse for
981 * autoneg_advertised software override. Since we can advertise
982 * a plethora of combinations, we need to check each bit
983 * individually.
984 */
985
986 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
987 * Advertisement Register (Address 4) and the 1000 mb speed bits in
988 * the 1000Base-T Control Register (Address 9).
989 */
990 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
991 ADVERTISE_100HALF |
992 ADVERTISE_10FULL | ADVERTISE_10HALF);
993 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
994
995 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
996
997 /* Do we want to advertise 10 Mb Half Duplex? */
998 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
999 e_dbg("Advertise 10mb Half duplex\n");
1000 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
1001 }
1002
1003 /* Do we want to advertise 10 Mb Full Duplex? */
1004 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1005 e_dbg("Advertise 10mb Full duplex\n");
1006 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
1007 }
1008
1009 /* Do we want to advertise 100 Mb Half Duplex? */
1010 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1011 e_dbg("Advertise 100mb Half duplex\n");
1012 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
1013 }
1014
1015 /* Do we want to advertise 100 Mb Full Duplex? */
1016 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1017 e_dbg("Advertise 100mb Full duplex\n");
1018 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
1019 }
1020
1021 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1022 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1023 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1024
1025 /* Do we want to advertise 1000 Mb Full Duplex? */
1026 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1027 e_dbg("Advertise 1000mb Full duplex\n");
1028 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1029 }
1030
1031 /* Check for a software override of the flow control settings, and
1032 * setup the PHY advertisement registers accordingly. If
1033 * auto-negotiation is enabled, then software will have to set the
1034 * "PAUSE" bits to the correct value in the Auto-Negotiation
1035 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1036 * negotiation.
1037 *
1038 * The possible values of the "fc" parameter are:
1039 * 0: Flow control is completely disabled
1040 * 1: Rx flow control is enabled (we can receive pause frames
1041 * but not send pause frames).
1042 * 2: Tx flow control is enabled (we can send pause frames
1043 * but we do not support receiving pause frames).
1044 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1045 * other: No software override. The flow control configuration
1046 * in the EEPROM is used.
1047 */
1048 switch (hw->fc.current_mode) {
1049 case e1000_fc_none:
1050 /* Flow control (Rx & Tx) is completely disabled by a
1051 * software over-ride.
1052 */
1053 mii_autoneg_adv_reg &=
1054 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1055 phy->autoneg_advertised &=
1056 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1057 break;
1058 case e1000_fc_rx_pause:
1059 /* Rx Flow control is enabled, and Tx Flow control is
1060 * disabled, by a software over-ride.
1061 *
1062 * Since there really isn't a way to advertise that we are
1063 * capable of Rx Pause ONLY, we will advertise that we
1064 * support both symmetric and asymmetric Rx PAUSE. Later
1065 * (in e1000e_config_fc_after_link_up) we will disable the
1066 * hw's ability to send PAUSE frames.
1067 */
1068 mii_autoneg_adv_reg |=
1069 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1070 phy->autoneg_advertised |=
1071 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1072 break;
1073 case e1000_fc_tx_pause:
1074 /* Tx Flow control is enabled, and Rx Flow control is
1075 * disabled, by a software over-ride.
1076 */
1077 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1078 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1079 phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1080 phy->autoneg_advertised &= ~ADVERTISED_Pause;
1081 break;
1082 case e1000_fc_full:
1083 /* Flow control (both Rx and Tx) is enabled by a software
1084 * over-ride.
1085 */
1086 mii_autoneg_adv_reg |=
1087 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1088 phy->autoneg_advertised |=
1089 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1090 break;
1091 default:
1092 e_dbg("Flow control param set incorrectly\n");
1093 return -E1000_ERR_CONFIG;
1094 }
1095
1096 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1097 if (ret_val)
1098 return ret_val;
1099
1100 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1101
1102 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1103 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1104
1105 return ret_val;
1106}
1107
1108/**
1109 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1110 * @hw: pointer to the HW structure
1111 *
1112 * Performs initial bounds checking on autoneg advertisement parameter, then
1113 * configure to advertise the full capability. Setup the PHY to autoneg
1114 * and restart the negotiation process between the link partner. If
1115 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1116 **/
1117static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1118{
1119 struct e1000_phy_info *phy = &hw->phy;
1120 s32 ret_val;
1121 u16 phy_ctrl;
1122
1123 /* Perform some bounds checking on the autoneg advertisement
1124 * parameter.
1125 */
1126 phy->autoneg_advertised &= phy->autoneg_mask;
1127
1128 /* If autoneg_advertised is zero, we assume it was not defaulted
1129 * by the calling code so we set to advertise full capability.
1130 */
1131 if (!phy->autoneg_advertised)
1132 phy->autoneg_advertised = phy->autoneg_mask;
1133
1134 e_dbg("Reconfiguring auto-neg advertisement params\n");
1135 ret_val = e1000_phy_setup_autoneg(hw);
1136 if (ret_val) {
1137 e_dbg("Error Setting up Auto-Negotiation\n");
1138 return ret_val;
1139 }
1140 e_dbg("Restarting Auto-Neg\n");
1141
1142 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1143 * the Auto Neg Restart bit in the PHY control register.
1144 */
1145 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1146 if (ret_val)
1147 return ret_val;
1148
1149 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1150 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1151 if (ret_val)
1152 return ret_val;
1153
1154 /* Does the user want to wait for Auto-Neg to complete here, or
1155 * check at a later time (for example, callback routine).
1156 */
1157 if (phy->autoneg_wait_to_complete) {
1158 ret_val = e1000_wait_autoneg(hw);
1159 if (ret_val) {
1160 e_dbg("Error while waiting for autoneg to complete\n");
1161 return ret_val;
1162 }
1163 }
1164
1165 hw->mac.get_link_status = true;
1166
1167 return ret_val;
1168}
1169
1170/**
1171 * e1000e_setup_copper_link - Configure copper link settings
1172 * @hw: pointer to the HW structure
1173 *
1174 * Calls the appropriate function to configure the link for auto-neg or forced
1175 * speed and duplex. Then we check for link, once link is established calls
1176 * to configure collision distance and flow control are called. If link is
1177 * not established, we return -E1000_ERR_PHY (-2).
1178 **/
1179s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1180{
1181 s32 ret_val;
1182 bool link;
1183
1184 if (hw->mac.autoneg) {
1185 /* Setup autoneg and flow control advertisement and perform
1186 * autonegotiation.
1187 */
1188 ret_val = e1000_copper_link_autoneg(hw);
1189 if (ret_val)
1190 return ret_val;
1191 } else {
1192 /* PHY will be set to 10H, 10F, 100H or 100F
1193 * depending on user settings.
1194 */
1195 e_dbg("Forcing Speed and Duplex\n");
1196 ret_val = hw->phy.ops.force_speed_duplex(hw);
1197 if (ret_val) {
1198 e_dbg("Error Forcing Speed and Duplex\n");
1199 return ret_val;
1200 }
1201 }
1202
1203 /* Check link status. Wait up to 100 microseconds for link to become
1204 * valid.
1205 */
1206 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1207 &link);
1208 if (ret_val)
1209 return ret_val;
1210
1211 if (link) {
1212 e_dbg("Valid link established!!!\n");
1213 hw->mac.ops.config_collision_dist(hw);
1214 ret_val = e1000e_config_fc_after_link_up(hw);
1215 } else {
1216 e_dbg("Unable to establish link!!!\n");
1217 }
1218
1219 return ret_val;
1220}
1221
1222/**
1223 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1224 * @hw: pointer to the HW structure
1225 *
1226 * Calls the PHY setup function to force speed and duplex. Clears the
1227 * auto-crossover to force MDI manually. Waits for link and returns
1228 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1229 **/
1230s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1231{
1232 struct e1000_phy_info *phy = &hw->phy;
1233 s32 ret_val;
1234 u16 phy_data;
1235 bool link;
1236
1237 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1238 if (ret_val)
1239 return ret_val;
1240
1241 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1242
1243 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1244 if (ret_val)
1245 return ret_val;
1246
1247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1248 * forced whenever speed and duplex are forced.
1249 */
1250 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1251 if (ret_val)
1252 return ret_val;
1253
1254 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1255 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1256
1257 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1258 if (ret_val)
1259 return ret_val;
1260
1261 e_dbg("IGP PSCR: %X\n", phy_data);
1262
1263 udelay(1);
1264
1265 if (phy->autoneg_wait_to_complete) {
1266 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1267
1268 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1269 100000, &link);
1270 if (ret_val)
1271 return ret_val;
1272
1273 if (!link)
1274 e_dbg("Link taking longer than expected.\n");
1275
1276 /* Try once more */
1277 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1278 100000, &link);
1279 }
1280
1281 return ret_val;
1282}
1283
1284/**
1285 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1286 * @hw: pointer to the HW structure
1287 *
1288 * Calls the PHY setup function to force speed and duplex. Clears the
1289 * auto-crossover to force MDI manually. Resets the PHY to commit the
1290 * changes. If time expires while waiting for link up, we reset the DSP.
1291 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1292 * successful completion, else return corresponding error code.
1293 **/
1294s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1295{
1296 struct e1000_phy_info *phy = &hw->phy;
1297 s32 ret_val;
1298 u16 phy_data;
1299 bool link;
1300
1301 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1302 * forced whenever speed and duplex are forced.
1303 */
1304 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1305 if (ret_val)
1306 return ret_val;
1307
1308 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1309 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1310 if (ret_val)
1311 return ret_val;
1312
1313 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1314
1315 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1316 if (ret_val)
1317 return ret_val;
1318
1319 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1320
1321 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1322 if (ret_val)
1323 return ret_val;
1324
1325 /* Reset the phy to commit changes. */
1326 if (hw->phy.ops.commit) {
1327 ret_val = hw->phy.ops.commit(hw);
1328 if (ret_val)
1329 return ret_val;
1330 }
1331
1332 if (phy->autoneg_wait_to_complete) {
1333 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1334
1335 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1336 100000, &link);
1337 if (ret_val)
1338 return ret_val;
1339
1340 if (!link) {
1341 if (hw->phy.type != e1000_phy_m88) {
1342 e_dbg("Link taking longer than expected.\n");
1343 } else {
1344 /* We didn't get link.
1345 * Reset the DSP and cross our fingers.
1346 */
1347 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1348 0x001d);
1349 if (ret_val)
1350 return ret_val;
1351 ret_val = e1000e_phy_reset_dsp(hw);
1352 if (ret_val)
1353 return ret_val;
1354 }
1355 }
1356
1357 /* Try once more */
1358 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1359 100000, &link);
1360 if (ret_val)
1361 return ret_val;
1362 }
1363
1364 if (hw->phy.type != e1000_phy_m88)
1365 return 0;
1366
1367 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1368 if (ret_val)
1369 return ret_val;
1370
1371 /* Resetting the phy means we need to re-force TX_CLK in the
1372 * Extended PHY Specific Control Register to 25MHz clock from
1373 * the reset value of 2.5MHz.
1374 */
1375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1376 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1377 if (ret_val)
1378 return ret_val;
1379
1380 /* In addition, we must re-enable CRS on Tx for both half and full
1381 * duplex.
1382 */
1383 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1388 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1389
1390 return ret_val;
1391}
1392
1393/**
1394 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1395 * @hw: pointer to the HW structure
1396 *
1397 * Forces the speed and duplex settings of the PHY.
1398 * This is a function pointer entry point only called by
1399 * PHY setup routines.
1400 **/
1401s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1402{
1403 struct e1000_phy_info *phy = &hw->phy;
1404 s32 ret_val;
1405 u16 data;
1406 bool link;
1407
1408 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1409 if (ret_val)
1410 return ret_val;
1411
1412 e1000e_phy_force_speed_duplex_setup(hw, &data);
1413
1414 ret_val = e1e_wphy(hw, MII_BMCR, data);
1415 if (ret_val)
1416 return ret_val;
1417
1418 /* Disable MDI-X support for 10/100 */
1419 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1420 if (ret_val)
1421 return ret_val;
1422
1423 data &= ~IFE_PMC_AUTO_MDIX;
1424 data &= ~IFE_PMC_FORCE_MDIX;
1425
1426 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1427 if (ret_val)
1428 return ret_val;
1429
1430 e_dbg("IFE PMC: %X\n", data);
1431
1432 udelay(1);
1433
1434 if (phy->autoneg_wait_to_complete) {
1435 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1436
1437 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1438 100000, &link);
1439 if (ret_val)
1440 return ret_val;
1441
1442 if (!link)
1443 e_dbg("Link taking longer than expected.\n");
1444
1445 /* Try once more */
1446 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1447 100000, &link);
1448 if (ret_val)
1449 return ret_val;
1450 }
1451
1452 return 0;
1453}
1454
1455/**
1456 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1457 * @hw: pointer to the HW structure
1458 * @phy_ctrl: pointer to current value of MII_BMCR
1459 *
1460 * Forces speed and duplex on the PHY by doing the following: disable flow
1461 * control, force speed/duplex on the MAC, disable auto speed detection,
1462 * disable auto-negotiation, configure duplex, configure speed, configure
1463 * the collision distance, write configuration to CTRL register. The
1464 * caller must write to the MII_BMCR register for these settings to
1465 * take affect.
1466 **/
1467void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1470 u32 ctrl;
1471
1472 /* Turn off flow control when forcing speed/duplex */
1473 hw->fc.current_mode = e1000_fc_none;
1474
1475 /* Force speed/duplex on the mac */
1476 ctrl = er32(CTRL);
1477 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1478 ctrl &= ~E1000_CTRL_SPD_SEL;
1479
1480 /* Disable Auto Speed Detection */
1481 ctrl &= ~E1000_CTRL_ASDE;
1482
1483 /* Disable autoneg on the phy */
1484 *phy_ctrl &= ~BMCR_ANENABLE;
1485
1486 /* Forcing Full or Half Duplex? */
1487 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1488 ctrl &= ~E1000_CTRL_FD;
1489 *phy_ctrl &= ~BMCR_FULLDPLX;
1490 e_dbg("Half Duplex\n");
1491 } else {
1492 ctrl |= E1000_CTRL_FD;
1493 *phy_ctrl |= BMCR_FULLDPLX;
1494 e_dbg("Full Duplex\n");
1495 }
1496
1497 /* Forcing 10mb or 100mb? */
1498 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1499 ctrl |= E1000_CTRL_SPD_100;
1500 *phy_ctrl |= BMCR_SPEED100;
1501 *phy_ctrl &= ~BMCR_SPEED1000;
1502 e_dbg("Forcing 100mb\n");
1503 } else {
1504 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1505 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1506 e_dbg("Forcing 10mb\n");
1507 }
1508
1509 hw->mac.ops.config_collision_dist(hw);
1510
1511 ew32(CTRL, ctrl);
1512}
1513
1514/**
1515 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1516 * @hw: pointer to the HW structure
1517 * @active: boolean used to enable/disable lplu
1518 *
1519 * Success returns 0, Failure returns 1
1520 *
1521 * The low power link up (lplu) state is set to the power management level D3
1522 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1523 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1524 * is used during Dx states where the power conservation is most important.
1525 * During driver activity, SmartSpeed should be enabled so performance is
1526 * maintained.
1527 **/
1528s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1529{
1530 struct e1000_phy_info *phy = &hw->phy;
1531 s32 ret_val;
1532 u16 data;
1533
1534 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1535 if (ret_val)
1536 return ret_val;
1537
1538 if (!active) {
1539 data &= ~IGP02E1000_PM_D3_LPLU;
1540 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1541 if (ret_val)
1542 return ret_val;
1543 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1544 * during Dx states where the power conservation is most
1545 * important. During driver activity we should enable
1546 * SmartSpeed, so performance is maintained.
1547 */
1548 if (phy->smart_speed == e1000_smart_speed_on) {
1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1550 &data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 data |= IGP01E1000_PSCFR_SMART_SPEED;
1555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1556 data);
1557 if (ret_val)
1558 return ret_val;
1559 } else if (phy->smart_speed == e1000_smart_speed_off) {
1560 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1561 &data);
1562 if (ret_val)
1563 return ret_val;
1564
1565 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1566 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1567 data);
1568 if (ret_val)
1569 return ret_val;
1570 }
1571 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1572 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1573 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1574 data |= IGP02E1000_PM_D3_LPLU;
1575 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1576 if (ret_val)
1577 return ret_val;
1578
1579 /* When LPLU is enabled, we should disable SmartSpeed */
1580 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1581 if (ret_val)
1582 return ret_val;
1583
1584 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1585 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1586 }
1587
1588 return ret_val;
1589}
1590
1591/**
1592 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1593 * @hw: pointer to the HW structure
1594 *
1595 * Success returns 0, Failure returns 1
1596 *
1597 * A downshift is detected by querying the PHY link health.
1598 **/
1599s32 e1000e_check_downshift(struct e1000_hw *hw)
1600{
1601 struct e1000_phy_info *phy = &hw->phy;
1602 s32 ret_val;
1603 u16 phy_data, offset, mask;
1604
1605 switch (phy->type) {
1606 case e1000_phy_m88:
1607 case e1000_phy_gg82563:
1608 case e1000_phy_bm:
1609 case e1000_phy_82578:
1610 offset = M88E1000_PHY_SPEC_STATUS;
1611 mask = M88E1000_PSSR_DOWNSHIFT;
1612 break;
1613 case e1000_phy_igp_2:
1614 case e1000_phy_igp_3:
1615 offset = IGP01E1000_PHY_LINK_HEALTH;
1616 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1617 break;
1618 default:
1619 /* speed downshift not supported */
1620 phy->speed_downgraded = false;
1621 return 0;
1622 }
1623
1624 ret_val = e1e_rphy(hw, offset, &phy_data);
1625
1626 if (!ret_val)
1627 phy->speed_downgraded = !!(phy_data & mask);
1628
1629 return ret_val;
1630}
1631
1632/**
1633 * e1000_check_polarity_m88 - Checks the polarity.
1634 * @hw: pointer to the HW structure
1635 *
1636 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1637 *
1638 * Polarity is determined based on the PHY specific status register.
1639 **/
1640s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1641{
1642 struct e1000_phy_info *phy = &hw->phy;
1643 s32 ret_val;
1644 u16 data;
1645
1646 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1647
1648 if (!ret_val)
1649 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1650 ? e1000_rev_polarity_reversed
1651 : e1000_rev_polarity_normal);
1652
1653 return ret_val;
1654}
1655
1656/**
1657 * e1000_check_polarity_igp - Checks the polarity.
1658 * @hw: pointer to the HW structure
1659 *
1660 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1661 *
1662 * Polarity is determined based on the PHY port status register, and the
1663 * current speed (since there is no polarity at 100Mbps).
1664 **/
1665s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1666{
1667 struct e1000_phy_info *phy = &hw->phy;
1668 s32 ret_val;
1669 u16 data, offset, mask;
1670
1671 /* Polarity is determined based on the speed of
1672 * our connection.
1673 */
1674 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1675 if (ret_val)
1676 return ret_val;
1677
1678 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1679 IGP01E1000_PSSR_SPEED_1000MBPS) {
1680 offset = IGP01E1000_PHY_PCS_INIT_REG;
1681 mask = IGP01E1000_PHY_POLARITY_MASK;
1682 } else {
1683 /* This really only applies to 10Mbps since
1684 * there is no polarity for 100Mbps (always 0).
1685 */
1686 offset = IGP01E1000_PHY_PORT_STATUS;
1687 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1688 }
1689
1690 ret_val = e1e_rphy(hw, offset, &data);
1691
1692 if (!ret_val)
1693 phy->cable_polarity = ((data & mask)
1694 ? e1000_rev_polarity_reversed
1695 : e1000_rev_polarity_normal);
1696
1697 return ret_val;
1698}
1699
1700/**
1701 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1702 * @hw: pointer to the HW structure
1703 *
1704 * Polarity is determined on the polarity reversal feature being enabled.
1705 **/
1706s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1707{
1708 struct e1000_phy_info *phy = &hw->phy;
1709 s32 ret_val;
1710 u16 phy_data, offset, mask;
1711
1712 /* Polarity is determined based on the reversal feature being enabled.
1713 */
1714 if (phy->polarity_correction) {
1715 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1716 mask = IFE_PESC_POLARITY_REVERSED;
1717 } else {
1718 offset = IFE_PHY_SPECIAL_CONTROL;
1719 mask = IFE_PSC_FORCE_POLARITY;
1720 }
1721
1722 ret_val = e1e_rphy(hw, offset, &phy_data);
1723
1724 if (!ret_val)
1725 phy->cable_polarity = ((phy_data & mask)
1726 ? e1000_rev_polarity_reversed
1727 : e1000_rev_polarity_normal);
1728
1729 return ret_val;
1730}
1731
1732/**
1733 * e1000_wait_autoneg - Wait for auto-neg completion
1734 * @hw: pointer to the HW structure
1735 *
1736 * Waits for auto-negotiation to complete or for the auto-negotiation time
1737 * limit to expire, which ever happens first.
1738 **/
1739static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1740{
1741 s32 ret_val = 0;
1742 u16 i, phy_status;
1743
1744 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1745 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1746 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 if (ret_val)
1748 break;
1749 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1750 if (ret_val)
1751 break;
1752 if (phy_status & BMSR_ANEGCOMPLETE)
1753 break;
1754 msleep(100);
1755 }
1756
1757 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1758 * has completed.
1759 */
1760 return ret_val;
1761}
1762
1763/**
1764 * e1000e_phy_has_link_generic - Polls PHY for link
1765 * @hw: pointer to the HW structure
1766 * @iterations: number of times to poll for link
1767 * @usec_interval: delay between polling attempts
1768 * @success: pointer to whether polling was successful or not
1769 *
1770 * Polls the PHY status register for link, 'iterations' number of times.
1771 **/
1772s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1773 u32 usec_interval, bool *success)
1774{
1775 s32 ret_val = 0;
1776 u16 i, phy_status;
1777
1778 *success = false;
1779 for (i = 0; i < iterations; i++) {
1780 /* Some PHYs require the MII_BMSR register to be read
1781 * twice due to the link bit being sticky. No harm doing
1782 * it across the board.
1783 */
1784 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1785 if (ret_val) {
1786 /* If the first read fails, another entity may have
1787 * ownership of the resources, wait and try again to
1788 * see if they have relinquished the resources yet.
1789 */
1790 if (usec_interval >= 1000)
1791 msleep(usec_interval / 1000);
1792 else
1793 udelay(usec_interval);
1794 }
1795 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1796 if (ret_val)
1797 break;
1798 if (phy_status & BMSR_LSTATUS) {
1799 *success = true;
1800 break;
1801 }
1802 if (usec_interval >= 1000)
1803 msleep(usec_interval / 1000);
1804 else
1805 udelay(usec_interval);
1806 }
1807
1808 return ret_val;
1809}
1810
1811/**
1812 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1813 * @hw: pointer to the HW structure
1814 *
1815 * Reads the PHY specific status register to retrieve the cable length
1816 * information. The cable length is determined by averaging the minimum and
1817 * maximum values to get the "average" cable length. The m88 PHY has four
1818 * possible cable length values, which are:
1819 * Register Value Cable Length
1820 * 0 < 50 meters
1821 * 1 50 - 80 meters
1822 * 2 80 - 110 meters
1823 * 3 110 - 140 meters
1824 * 4 > 140 meters
1825 **/
1826s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1827{
1828 struct e1000_phy_info *phy = &hw->phy;
1829 s32 ret_val;
1830 u16 phy_data, index;
1831
1832 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1837
1838 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1839 return -E1000_ERR_PHY;
1840
1841 phy->min_cable_length = e1000_m88_cable_length_table[index];
1842 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1843
1844 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1845
1846 return 0;
1847}
1848
1849/**
1850 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1851 * @hw: pointer to the HW structure
1852 *
1853 * The automatic gain control (agc) normalizes the amplitude of the
1854 * received signal, adjusting for the attenuation produced by the
1855 * cable. By reading the AGC registers, which represent the
1856 * combination of coarse and fine gain value, the value can be put
1857 * into a lookup table to obtain the approximate cable length
1858 * for each channel.
1859 **/
1860s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1861{
1862 struct e1000_phy_info *phy = &hw->phy;
1863 s32 ret_val;
1864 u16 phy_data, i, agc_value = 0;
1865 u16 cur_agc_index, max_agc_index = 0;
1866 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1867 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1868 IGP02E1000_PHY_AGC_A,
1869 IGP02E1000_PHY_AGC_B,
1870 IGP02E1000_PHY_AGC_C,
1871 IGP02E1000_PHY_AGC_D
1872 };
1873
1874 /* Read the AGC registers for all channels */
1875 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1876 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1877 if (ret_val)
1878 return ret_val;
1879
1880 /* Getting bits 15:9, which represent the combination of
1881 * coarse and fine gain values. The result is a number
1882 * that can be put into the lookup table to obtain the
1883 * approximate cable length.
1884 */
1885 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1886 IGP02E1000_AGC_LENGTH_MASK);
1887
1888 /* Array index bound check. */
1889 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1890 (cur_agc_index == 0))
1891 return -E1000_ERR_PHY;
1892
1893 /* Remove min & max AGC values from calculation. */
1894 if (e1000_igp_2_cable_length_table[min_agc_index] >
1895 e1000_igp_2_cable_length_table[cur_agc_index])
1896 min_agc_index = cur_agc_index;
1897 if (e1000_igp_2_cable_length_table[max_agc_index] <
1898 e1000_igp_2_cable_length_table[cur_agc_index])
1899 max_agc_index = cur_agc_index;
1900
1901 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1902 }
1903
1904 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1905 e1000_igp_2_cable_length_table[max_agc_index]);
1906 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1907
1908 /* Calculate cable length with the error range of +/- 10 meters. */
1909 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1910 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1911 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1912
1913 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1914
1915 return 0;
1916}
1917
1918/**
1919 * e1000e_get_phy_info_m88 - Retrieve PHY information
1920 * @hw: pointer to the HW structure
1921 *
1922 * Valid for only copper links. Read the PHY status register (sticky read)
1923 * to verify that link is up. Read the PHY special control register to
1924 * determine the polarity and 10base-T extended distance. Read the PHY
1925 * special status register to determine MDI/MDIx and current speed. If
1926 * speed is 1000, then determine cable length, local and remote receiver.
1927 **/
1928s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1929{
1930 struct e1000_phy_info *phy = &hw->phy;
1931 s32 ret_val;
1932 u16 phy_data;
1933 bool link;
1934
1935 if (phy->media_type != e1000_media_type_copper) {
1936 e_dbg("Phy info is only valid for copper media\n");
1937 return -E1000_ERR_CONFIG;
1938 }
1939
1940 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1941 if (ret_val)
1942 return ret_val;
1943
1944 if (!link) {
1945 e_dbg("Phy info is only valid if link is up\n");
1946 return -E1000_ERR_CONFIG;
1947 }
1948
1949 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1950 if (ret_val)
1951 return ret_val;
1952
1953 phy->polarity_correction = !!(phy_data &
1954 M88E1000_PSCR_POLARITY_REVERSAL);
1955
1956 ret_val = e1000_check_polarity_m88(hw);
1957 if (ret_val)
1958 return ret_val;
1959
1960 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1961 if (ret_val)
1962 return ret_val;
1963
1964 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1965
1966 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1967 ret_val = hw->phy.ops.get_cable_length(hw);
1968 if (ret_val)
1969 return ret_val;
1970
1971 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1972 if (ret_val)
1973 return ret_val;
1974
1975 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1976 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1977
1978 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1979 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1980 } else {
1981 /* Set values to "undefined" */
1982 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1983 phy->local_rx = e1000_1000t_rx_status_undefined;
1984 phy->remote_rx = e1000_1000t_rx_status_undefined;
1985 }
1986
1987 return ret_val;
1988}
1989
1990/**
1991 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1992 * @hw: pointer to the HW structure
1993 *
1994 * Read PHY status to determine if link is up. If link is up, then
1995 * set/determine 10base-T extended distance and polarity correction. Read
1996 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1997 * determine on the cable length, local and remote receiver.
1998 **/
1999s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2000{
2001 struct e1000_phy_info *phy = &hw->phy;
2002 s32 ret_val;
2003 u16 data;
2004 bool link;
2005
2006 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2007 if (ret_val)
2008 return ret_val;
2009
2010 if (!link) {
2011 e_dbg("Phy info is only valid if link is up\n");
2012 return -E1000_ERR_CONFIG;
2013 }
2014
2015 phy->polarity_correction = true;
2016
2017 ret_val = e1000_check_polarity_igp(hw);
2018 if (ret_val)
2019 return ret_val;
2020
2021 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2022 if (ret_val)
2023 return ret_val;
2024
2025 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2026
2027 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2028 IGP01E1000_PSSR_SPEED_1000MBPS) {
2029 ret_val = phy->ops.get_cable_length(hw);
2030 if (ret_val)
2031 return ret_val;
2032
2033 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2034 if (ret_val)
2035 return ret_val;
2036
2037 phy->local_rx = (data & LPA_1000LOCALRXOK)
2038 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2039
2040 phy->remote_rx = (data & LPA_1000REMRXOK)
2041 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2042 } else {
2043 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2044 phy->local_rx = e1000_1000t_rx_status_undefined;
2045 phy->remote_rx = e1000_1000t_rx_status_undefined;
2046 }
2047
2048 return ret_val;
2049}
2050
2051/**
2052 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2053 * @hw: pointer to the HW structure
2054 *
2055 * Populates "phy" structure with various feature states.
2056 **/
2057s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2058{
2059 struct e1000_phy_info *phy = &hw->phy;
2060 s32 ret_val;
2061 u16 data;
2062 bool link;
2063
2064 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2065 if (ret_val)
2066 return ret_val;
2067
2068 if (!link) {
2069 e_dbg("Phy info is only valid if link is up\n");
2070 return -E1000_ERR_CONFIG;
2071 }
2072
2073 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2074 if (ret_val)
2075 return ret_val;
2076 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2077
2078 if (phy->polarity_correction) {
2079 ret_val = e1000_check_polarity_ife(hw);
2080 if (ret_val)
2081 return ret_val;
2082 } else {
2083 /* Polarity is forced */
2084 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2085 ? e1000_rev_polarity_reversed
2086 : e1000_rev_polarity_normal);
2087 }
2088
2089 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2090 if (ret_val)
2091 return ret_val;
2092
2093 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2094
2095 /* The following parameters are undefined for 10/100 operation. */
2096 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2097 phy->local_rx = e1000_1000t_rx_status_undefined;
2098 phy->remote_rx = e1000_1000t_rx_status_undefined;
2099
2100 return 0;
2101}
2102
2103/**
2104 * e1000e_phy_sw_reset - PHY software reset
2105 * @hw: pointer to the HW structure
2106 *
2107 * Does a software reset of the PHY by reading the PHY control register and
2108 * setting/write the control register reset bit to the PHY.
2109 **/
2110s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2111{
2112 s32 ret_val;
2113 u16 phy_ctrl;
2114
2115 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2116 if (ret_val)
2117 return ret_val;
2118
2119 phy_ctrl |= BMCR_RESET;
2120 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2121 if (ret_val)
2122 return ret_val;
2123
2124 udelay(1);
2125
2126 return ret_val;
2127}
2128
2129/**
2130 * e1000e_phy_hw_reset_generic - PHY hardware reset
2131 * @hw: pointer to the HW structure
2132 *
2133 * Verify the reset block is not blocking us from resetting. Acquire
2134 * semaphore (if necessary) and read/set/write the device control reset
2135 * bit in the PHY. Wait the appropriate delay time for the device to
2136 * reset and release the semaphore (if necessary).
2137 **/
2138s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2139{
2140 struct e1000_phy_info *phy = &hw->phy;
2141 s32 ret_val;
2142 u32 ctrl;
2143
2144 if (phy->ops.check_reset_block) {
2145 ret_val = phy->ops.check_reset_block(hw);
2146 if (ret_val)
2147 return 0;
2148 }
2149
2150 ret_val = phy->ops.acquire(hw);
2151 if (ret_val)
2152 return ret_val;
2153
2154 ctrl = er32(CTRL);
2155 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2156 e1e_flush();
2157
2158 udelay(phy->reset_delay_us);
2159
2160 ew32(CTRL, ctrl);
2161 e1e_flush();
2162
2163 usleep_range(150, 300);
2164
2165 phy->ops.release(hw);
2166
2167 return phy->ops.get_cfg_done(hw);
2168}
2169
2170/**
2171 * e1000e_get_cfg_done_generic - Generic configuration done
2172 * @hw: pointer to the HW structure
2173 *
2174 * Generic function to wait 10 milli-seconds for configuration to complete
2175 * and return success.
2176 **/
2177s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2178{
2179 mdelay(10);
2180
2181 return 0;
2182}
2183
2184/**
2185 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2186 * @hw: pointer to the HW structure
2187 *
2188 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2189 **/
2190s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2191{
2192 e_dbg("Running IGP 3 PHY init script\n");
2193
2194 /* PHY init IGP 3 */
2195 /* Enable rise/fall, 10-mode work in class-A */
2196 e1e_wphy(hw, 0x2F5B, 0x9018);
2197 /* Remove all caps from Replica path filter */
2198 e1e_wphy(hw, 0x2F52, 0x0000);
2199 /* Bias trimming for ADC, AFE and Driver (Default) */
2200 e1e_wphy(hw, 0x2FB1, 0x8B24);
2201 /* Increase Hybrid poly bias */
2202 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2203 /* Add 4% to Tx amplitude in Gig mode */
2204 e1e_wphy(hw, 0x2010, 0x10B0);
2205 /* Disable trimming (TTT) */
2206 e1e_wphy(hw, 0x2011, 0x0000);
2207 /* Poly DC correction to 94.6% + 2% for all channels */
2208 e1e_wphy(hw, 0x20DD, 0x249A);
2209 /* ABS DC correction to 95.9% */
2210 e1e_wphy(hw, 0x20DE, 0x00D3);
2211 /* BG temp curve trim */
2212 e1e_wphy(hw, 0x28B4, 0x04CE);
2213 /* Increasing ADC OPAMP stage 1 currents to max */
2214 e1e_wphy(hw, 0x2F70, 0x29E4);
2215 /* Force 1000 ( required for enabling PHY regs configuration) */
2216 e1e_wphy(hw, 0x0000, 0x0140);
2217 /* Set upd_freq to 6 */
2218 e1e_wphy(hw, 0x1F30, 0x1606);
2219 /* Disable NPDFE */
2220 e1e_wphy(hw, 0x1F31, 0xB814);
2221 /* Disable adaptive fixed FFE (Default) */
2222 e1e_wphy(hw, 0x1F35, 0x002A);
2223 /* Enable FFE hysteresis */
2224 e1e_wphy(hw, 0x1F3E, 0x0067);
2225 /* Fixed FFE for short cable lengths */
2226 e1e_wphy(hw, 0x1F54, 0x0065);
2227 /* Fixed FFE for medium cable lengths */
2228 e1e_wphy(hw, 0x1F55, 0x002A);
2229 /* Fixed FFE for long cable lengths */
2230 e1e_wphy(hw, 0x1F56, 0x002A);
2231 /* Enable Adaptive Clip Threshold */
2232 e1e_wphy(hw, 0x1F72, 0x3FB0);
2233 /* AHT reset limit to 1 */
2234 e1e_wphy(hw, 0x1F76, 0xC0FF);
2235 /* Set AHT master delay to 127 msec */
2236 e1e_wphy(hw, 0x1F77, 0x1DEC);
2237 /* Set scan bits for AHT */
2238 e1e_wphy(hw, 0x1F78, 0xF9EF);
2239 /* Set AHT Preset bits */
2240 e1e_wphy(hw, 0x1F79, 0x0210);
2241 /* Change integ_factor of channel A to 3 */
2242 e1e_wphy(hw, 0x1895, 0x0003);
2243 /* Change prop_factor of channels BCD to 8 */
2244 e1e_wphy(hw, 0x1796, 0x0008);
2245 /* Change cg_icount + enable integbp for channels BCD */
2246 e1e_wphy(hw, 0x1798, 0xD008);
2247 /* Change cg_icount + enable integbp + change prop_factor_master
2248 * to 8 for channel A
2249 */
2250 e1e_wphy(hw, 0x1898, 0xD918);
2251 /* Disable AHT in Slave mode on channel A */
2252 e1e_wphy(hw, 0x187A, 0x0800);
2253 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2254 * Enable SPD+B2B
2255 */
2256 e1e_wphy(hw, 0x0019, 0x008D);
2257 /* Enable restart AN on an1000_dis change */
2258 e1e_wphy(hw, 0x001B, 0x2080);
2259 /* Enable wh_fifo read clock in 10/100 modes */
2260 e1e_wphy(hw, 0x0014, 0x0045);
2261 /* Restart AN, Speed selection is 1000 */
2262 e1e_wphy(hw, 0x0000, 0x1340);
2263
2264 return 0;
2265}
2266
2267/**
2268 * e1000e_get_phy_type_from_id - Get PHY type from id
2269 * @phy_id: phy_id read from the phy
2270 *
2271 * Returns the phy type from the id.
2272 **/
2273enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2274{
2275 enum e1000_phy_type phy_type = e1000_phy_unknown;
2276
2277 switch (phy_id) {
2278 case M88E1000_I_PHY_ID:
2279 case M88E1000_E_PHY_ID:
2280 case M88E1111_I_PHY_ID:
2281 case M88E1011_I_PHY_ID:
2282 phy_type = e1000_phy_m88;
2283 break;
2284 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2285 phy_type = e1000_phy_igp_2;
2286 break;
2287 case GG82563_E_PHY_ID:
2288 phy_type = e1000_phy_gg82563;
2289 break;
2290 case IGP03E1000_E_PHY_ID:
2291 phy_type = e1000_phy_igp_3;
2292 break;
2293 case IFE_E_PHY_ID:
2294 case IFE_PLUS_E_PHY_ID:
2295 case IFE_C_E_PHY_ID:
2296 phy_type = e1000_phy_ife;
2297 break;
2298 case BME1000_E_PHY_ID:
2299 case BME1000_E_PHY_ID_R2:
2300 phy_type = e1000_phy_bm;
2301 break;
2302 case I82578_E_PHY_ID:
2303 phy_type = e1000_phy_82578;
2304 break;
2305 case I82577_E_PHY_ID:
2306 phy_type = e1000_phy_82577;
2307 break;
2308 case I82579_E_PHY_ID:
2309 phy_type = e1000_phy_82579;
2310 break;
2311 case I217_E_PHY_ID:
2312 phy_type = e1000_phy_i217;
2313 break;
2314 default:
2315 phy_type = e1000_phy_unknown;
2316 break;
2317 }
2318 return phy_type;
2319}
2320
2321/**
2322 * e1000e_determine_phy_address - Determines PHY address.
2323 * @hw: pointer to the HW structure
2324 *
2325 * This uses a trial and error method to loop through possible PHY
2326 * addresses. It tests each by reading the PHY ID registers and
2327 * checking for a match.
2328 **/
2329s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2330{
2331 u32 phy_addr = 0;
2332 u32 i;
2333 enum e1000_phy_type phy_type = e1000_phy_unknown;
2334
2335 hw->phy.id = phy_type;
2336
2337 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2338 hw->phy.addr = phy_addr;
2339 i = 0;
2340
2341 do {
2342 e1000e_get_phy_id(hw);
2343 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2344
2345 /* If phy_type is valid, break - we found our
2346 * PHY address
2347 */
2348 if (phy_type != e1000_phy_unknown)
2349 return 0;
2350
2351 usleep_range(1000, 2000);
2352 i++;
2353 } while (i < 10);
2354 }
2355
2356 return -E1000_ERR_PHY_TYPE;
2357}
2358
2359/**
2360 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2361 * @page: page to access
2362 * @reg: register to check
2363 *
2364 * Returns the phy address for the page requested.
2365 **/
2366static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2367{
2368 u32 phy_addr = 2;
2369
2370 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2371 phy_addr = 1;
2372
2373 return phy_addr;
2374}
2375
2376/**
2377 * e1000e_write_phy_reg_bm - Write BM PHY register
2378 * @hw: pointer to the HW structure
2379 * @offset: register offset to write to
2380 * @data: data to write at register offset
2381 *
2382 * Acquires semaphore, if necessary, then writes the data to PHY register
2383 * at the offset. Release any acquired semaphores before exiting.
2384 **/
2385s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2386{
2387 s32 ret_val;
2388 u32 page = offset >> IGP_PAGE_SHIFT;
2389
2390 ret_val = hw->phy.ops.acquire(hw);
2391 if (ret_val)
2392 return ret_val;
2393
2394 /* Page 800 works differently than the rest so it has its own func */
2395 if (page == BM_WUC_PAGE) {
2396 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2397 false, false);
2398 goto release;
2399 }
2400
2401 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2402
2403 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2404 u32 page_shift, page_select;
2405
2406 /* Page select is register 31 for phy address 1 and 22 for
2407 * phy address 2 and 3. Page select is shifted only for
2408 * phy address 1.
2409 */
2410 if (hw->phy.addr == 1) {
2411 page_shift = IGP_PAGE_SHIFT;
2412 page_select = IGP01E1000_PHY_PAGE_SELECT;
2413 } else {
2414 page_shift = 0;
2415 page_select = BM_PHY_PAGE_SELECT;
2416 }
2417
2418 /* Page is shifted left, PHY expects (page x 32) */
2419 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2420 (page << page_shift));
2421 if (ret_val)
2422 goto release;
2423 }
2424
2425 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2426 data);
2427
2428release:
2429 hw->phy.ops.release(hw);
2430 return ret_val;
2431}
2432
2433/**
2434 * e1000e_read_phy_reg_bm - Read BM PHY register
2435 * @hw: pointer to the HW structure
2436 * @offset: register offset to be read
2437 * @data: pointer to the read data
2438 *
2439 * Acquires semaphore, if necessary, then reads the PHY register at offset
2440 * and storing the retrieved information in data. Release any acquired
2441 * semaphores before exiting.
2442 **/
2443s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2444{
2445 s32 ret_val;
2446 u32 page = offset >> IGP_PAGE_SHIFT;
2447
2448 ret_val = hw->phy.ops.acquire(hw);
2449 if (ret_val)
2450 return ret_val;
2451
2452 /* Page 800 works differently than the rest so it has its own func */
2453 if (page == BM_WUC_PAGE) {
2454 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2455 true, false);
2456 goto release;
2457 }
2458
2459 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2460
2461 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2462 u32 page_shift, page_select;
2463
2464 /* Page select is register 31 for phy address 1 and 22 for
2465 * phy address 2 and 3. Page select is shifted only for
2466 * phy address 1.
2467 */
2468 if (hw->phy.addr == 1) {
2469 page_shift = IGP_PAGE_SHIFT;
2470 page_select = IGP01E1000_PHY_PAGE_SELECT;
2471 } else {
2472 page_shift = 0;
2473 page_select = BM_PHY_PAGE_SELECT;
2474 }
2475
2476 /* Page is shifted left, PHY expects (page x 32) */
2477 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2478 (page << page_shift));
2479 if (ret_val)
2480 goto release;
2481 }
2482
2483 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2484 data);
2485release:
2486 hw->phy.ops.release(hw);
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2492 * @hw: pointer to the HW structure
2493 * @offset: register offset to be read
2494 * @data: pointer to the read data
2495 *
2496 * Acquires semaphore, if necessary, then reads the PHY register at offset
2497 * and storing the retrieved information in data. Release any acquired
2498 * semaphores before exiting.
2499 **/
2500s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2501{
2502 s32 ret_val;
2503 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2504
2505 ret_val = hw->phy.ops.acquire(hw);
2506 if (ret_val)
2507 return ret_val;
2508
2509 /* Page 800 works differently than the rest so it has its own func */
2510 if (page == BM_WUC_PAGE) {
2511 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2512 true, false);
2513 goto release;
2514 }
2515
2516 hw->phy.addr = 1;
2517
2518 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2519 /* Page is shifted left, PHY expects (page x 32) */
2520 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2521 page);
2522
2523 if (ret_val)
2524 goto release;
2525 }
2526
2527 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2528 data);
2529release:
2530 hw->phy.ops.release(hw);
2531 return ret_val;
2532}
2533
2534/**
2535 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2536 * @hw: pointer to the HW structure
2537 * @offset: register offset to write to
2538 * @data: data to write at register offset
2539 *
2540 * Acquires semaphore, if necessary, then writes the data to PHY register
2541 * at the offset. Release any acquired semaphores before exiting.
2542 **/
2543s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2544{
2545 s32 ret_val;
2546 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2547
2548 ret_val = hw->phy.ops.acquire(hw);
2549 if (ret_val)
2550 return ret_val;
2551
2552 /* Page 800 works differently than the rest so it has its own func */
2553 if (page == BM_WUC_PAGE) {
2554 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2555 false, false);
2556 goto release;
2557 }
2558
2559 hw->phy.addr = 1;
2560
2561 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2562 /* Page is shifted left, PHY expects (page x 32) */
2563 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2564 page);
2565
2566 if (ret_val)
2567 goto release;
2568 }
2569
2570 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2571 data);
2572
2573release:
2574 hw->phy.ops.release(hw);
2575 return ret_val;
2576}
2577
2578/**
2579 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2580 * @hw: pointer to the HW structure
2581 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2582 *
2583 * Assumes semaphore already acquired and phy_reg points to a valid memory
2584 * address to store contents of the BM_WUC_ENABLE_REG register.
2585 **/
2586s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2587{
2588 s32 ret_val;
2589 u16 temp;
2590
2591 /* All page select, port ctrl and wakeup registers use phy address 1 */
2592 hw->phy.addr = 1;
2593
2594 /* Select Port Control Registers page */
2595 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2596 if (ret_val) {
2597 e_dbg("Could not set Port Control page\n");
2598 return ret_val;
2599 }
2600
2601 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2602 if (ret_val) {
2603 e_dbg("Could not read PHY register %d.%d\n",
2604 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2605 return ret_val;
2606 }
2607
2608 /* Enable both PHY wakeup mode and Wakeup register page writes.
2609 * Prevent a power state change by disabling ME and Host PHY wakeup.
2610 */
2611 temp = *phy_reg;
2612 temp |= BM_WUC_ENABLE_BIT;
2613 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2614
2615 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2616 if (ret_val) {
2617 e_dbg("Could not write PHY register %d.%d\n",
2618 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2619 return ret_val;
2620 }
2621
2622 /* Select Host Wakeup Registers page - caller now able to write
2623 * registers on the Wakeup registers page
2624 */
2625 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2626}
2627
2628/**
2629 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2630 * @hw: pointer to the HW structure
2631 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2632 *
2633 * Restore BM_WUC_ENABLE_REG to its original value.
2634 *
2635 * Assumes semaphore already acquired and *phy_reg is the contents of the
2636 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2637 * caller.
2638 **/
2639s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2640{
2641 s32 ret_val;
2642
2643 /* Select Port Control Registers page */
2644 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2645 if (ret_val) {
2646 e_dbg("Could not set Port Control page\n");
2647 return ret_val;
2648 }
2649
2650 /* Restore 769.17 to its original value */
2651 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2652 if (ret_val)
2653 e_dbg("Could not restore PHY register %d.%d\n",
2654 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2655
2656 return ret_val;
2657}
2658
2659/**
2660 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2661 * @hw: pointer to the HW structure
2662 * @offset: register offset to be read or written
2663 * @data: pointer to the data to read or write
2664 * @read: determines if operation is read or write
2665 * @page_set: BM_WUC_PAGE already set and access enabled
2666 *
2667 * Read the PHY register at offset and store the retrieved information in
2668 * data, or write data to PHY register at offset. Note the procedure to
2669 * access the PHY wakeup registers is different than reading the other PHY
2670 * registers. It works as such:
2671 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2672 * 2) Set page to 800 for host (801 if we were manageability)
2673 * 3) Write the address using the address opcode (0x11)
2674 * 4) Read or write the data using the data opcode (0x12)
2675 * 5) Restore 769.17.2 to its original value
2676 *
2677 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2678 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2679 *
2680 * Assumes semaphore is already acquired. When page_set==true, assumes
2681 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2682 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2683 **/
2684static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2685 u16 *data, bool read, bool page_set)
2686{
2687 s32 ret_val;
2688 u16 reg = BM_PHY_REG_NUM(offset);
2689 u16 page = BM_PHY_REG_PAGE(offset);
2690 u16 phy_reg = 0;
2691
2692 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2693 if ((hw->mac.type == e1000_pchlan) &&
2694 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2695 e_dbg("Attempting to access page %d while gig enabled.\n",
2696 page);
2697
2698 if (!page_set) {
2699 /* Enable access to PHY wakeup registers */
2700 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2701 if (ret_val) {
2702 e_dbg("Could not enable PHY wakeup reg access\n");
2703 return ret_val;
2704 }
2705 }
2706
2707 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2708
2709 /* Write the Wakeup register page offset value using opcode 0x11 */
2710 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2711 if (ret_val) {
2712 e_dbg("Could not write address opcode to page %d\n", page);
2713 return ret_val;
2714 }
2715
2716 if (read) {
2717 /* Read the Wakeup register page value using opcode 0x12 */
2718 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2719 data);
2720 } else {
2721 /* Write the Wakeup register page value using opcode 0x12 */
2722 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2723 *data);
2724 }
2725
2726 if (ret_val) {
2727 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2728 return ret_val;
2729 }
2730
2731 if (!page_set)
2732 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2733
2734 return ret_val;
2735}
2736
2737/**
2738 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2739 * @hw: pointer to the HW structure
2740 *
2741 * In the case of a PHY power down to save power, or to turn off link during a
2742 * driver unload, or wake on lan is not enabled, restore the link to previous
2743 * settings.
2744 **/
2745void e1000_power_up_phy_copper(struct e1000_hw *hw)
2746{
2747 u16 mii_reg = 0;
2748 int ret;
2749
2750 /* The PHY will retain its settings across a power down/up cycle */
2751 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2752 if (ret) {
2753 e_dbg("Error reading PHY register\n");
2754 return;
2755 }
2756 mii_reg &= ~BMCR_PDOWN;
2757 e1e_wphy(hw, MII_BMCR, mii_reg);
2758}
2759
2760/**
2761 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2762 * @hw: pointer to the HW structure
2763 *
2764 * In the case of a PHY power down to save power, or to turn off link during a
2765 * driver unload, or wake on lan is not enabled, restore the link to previous
2766 * settings.
2767 **/
2768void e1000_power_down_phy_copper(struct e1000_hw *hw)
2769{
2770 u16 mii_reg = 0;
2771 int ret;
2772
2773 /* The PHY will retain its settings across a power down/up cycle */
2774 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2775 if (ret) {
2776 e_dbg("Error reading PHY register\n");
2777 return;
2778 }
2779 mii_reg |= BMCR_PDOWN;
2780 e1e_wphy(hw, MII_BMCR, mii_reg);
2781 usleep_range(1000, 2000);
2782}
2783
2784/**
2785 * __e1000_read_phy_reg_hv - Read HV PHY register
2786 * @hw: pointer to the HW structure
2787 * @offset: register offset to be read
2788 * @data: pointer to the read data
2789 * @locked: semaphore has already been acquired or not
2790 * @page_set: BM_WUC_PAGE already set and access enabled
2791 *
2792 * Acquires semaphore, if necessary, then reads the PHY register at offset
2793 * and stores the retrieved information in data. Release any acquired
2794 * semaphore before exiting.
2795 **/
2796static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2797 bool locked, bool page_set)
2798{
2799 s32 ret_val;
2800 u16 page = BM_PHY_REG_PAGE(offset);
2801 u16 reg = BM_PHY_REG_NUM(offset);
2802 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2803
2804 if (!locked) {
2805 ret_val = hw->phy.ops.acquire(hw);
2806 if (ret_val)
2807 return ret_val;
2808 }
2809
2810 /* Page 800 works differently than the rest so it has its own func */
2811 if (page == BM_WUC_PAGE) {
2812 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2813 true, page_set);
2814 goto out;
2815 }
2816
2817 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2818 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2819 data, true);
2820 goto out;
2821 }
2822
2823 if (!page_set) {
2824 if (page == HV_INTC_FC_PAGE_START)
2825 page = 0;
2826
2827 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2828 /* Page is shifted left, PHY expects (page x 32) */
2829 ret_val = e1000_set_page_igp(hw,
2830 (page << IGP_PAGE_SHIFT));
2831
2832 hw->phy.addr = phy_addr;
2833
2834 if (ret_val)
2835 goto out;
2836 }
2837 }
2838
2839 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2840 page << IGP_PAGE_SHIFT, reg);
2841
2842 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2843out:
2844 if (!locked)
2845 hw->phy.ops.release(hw);
2846
2847 return ret_val;
2848}
2849
2850/**
2851 * e1000_read_phy_reg_hv - Read HV PHY register
2852 * @hw: pointer to the HW structure
2853 * @offset: register offset to be read
2854 * @data: pointer to the read data
2855 *
2856 * Acquires semaphore then reads the PHY register at offset and stores
2857 * the retrieved information in data. Release the acquired semaphore
2858 * before exiting.
2859 **/
2860s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2861{
2862 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2863}
2864
2865/**
2866 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2867 * @hw: pointer to the HW structure
2868 * @offset: register offset to be read
2869 * @data: pointer to the read data
2870 *
2871 * Reads the PHY register at offset and stores the retrieved information
2872 * in data. Assumes semaphore already acquired.
2873 **/
2874s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2875{
2876 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2877}
2878
2879/**
2880 * e1000_read_phy_reg_page_hv - Read HV PHY register
2881 * @hw: pointer to the HW structure
2882 * @offset: register offset to write to
2883 * @data: data to write at register offset
2884 *
2885 * Reads the PHY register at offset and stores the retrieved information
2886 * in data. Assumes semaphore already acquired and page already set.
2887 **/
2888s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2889{
2890 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2891}
2892
2893/**
2894 * __e1000_write_phy_reg_hv - Write HV PHY register
2895 * @hw: pointer to the HW structure
2896 * @offset: register offset to write to
2897 * @data: data to write at register offset
2898 * @locked: semaphore has already been acquired or not
2899 * @page_set: BM_WUC_PAGE already set and access enabled
2900 *
2901 * Acquires semaphore, if necessary, then writes the data to PHY register
2902 * at the offset. Release any acquired semaphores before exiting.
2903 **/
2904static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2905 bool locked, bool page_set)
2906{
2907 s32 ret_val;
2908 u16 page = BM_PHY_REG_PAGE(offset);
2909 u16 reg = BM_PHY_REG_NUM(offset);
2910 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2911
2912 if (!locked) {
2913 ret_val = hw->phy.ops.acquire(hw);
2914 if (ret_val)
2915 return ret_val;
2916 }
2917
2918 /* Page 800 works differently than the rest so it has its own func */
2919 if (page == BM_WUC_PAGE) {
2920 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2921 false, page_set);
2922 goto out;
2923 }
2924
2925 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2926 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2927 &data, false);
2928 goto out;
2929 }
2930
2931 if (!page_set) {
2932 if (page == HV_INTC_FC_PAGE_START)
2933 page = 0;
2934
2935 /* Workaround MDIO accesses being disabled after entering IEEE
2936 * Power Down (when bit 11 of the PHY Control register is set)
2937 */
2938 if ((hw->phy.type == e1000_phy_82578) &&
2939 (hw->phy.revision >= 1) &&
2940 (hw->phy.addr == 2) &&
2941 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2942 u16 data2 = 0x7EFF;
2943
2944 ret_val = e1000_access_phy_debug_regs_hv(hw,
2945 BIT(6) | 0x3,
2946 &data2, false);
2947 if (ret_val)
2948 goto out;
2949 }
2950
2951 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2952 /* Page is shifted left, PHY expects (page x 32) */
2953 ret_val = e1000_set_page_igp(hw,
2954 (page << IGP_PAGE_SHIFT));
2955
2956 hw->phy.addr = phy_addr;
2957
2958 if (ret_val)
2959 goto out;
2960 }
2961 }
2962
2963 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2964 page << IGP_PAGE_SHIFT, reg);
2965
2966 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2967 data);
2968
2969out:
2970 if (!locked)
2971 hw->phy.ops.release(hw);
2972
2973 return ret_val;
2974}
2975
2976/**
2977 * e1000_write_phy_reg_hv - Write HV PHY register
2978 * @hw: pointer to the HW structure
2979 * @offset: register offset to write to
2980 * @data: data to write at register offset
2981 *
2982 * Acquires semaphore then writes the data to PHY register at the offset.
2983 * Release the acquired semaphores before exiting.
2984 **/
2985s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2986{
2987 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2988}
2989
2990/**
2991 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2992 * @hw: pointer to the HW structure
2993 * @offset: register offset to write to
2994 * @data: data to write at register offset
2995 *
2996 * Writes the data to PHY register at the offset. Assumes semaphore
2997 * already acquired.
2998 **/
2999s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3000{
3001 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3002}
3003
3004/**
3005 * e1000_write_phy_reg_page_hv - Write HV PHY register
3006 * @hw: pointer to the HW structure
3007 * @offset: register offset to write to
3008 * @data: data to write at register offset
3009 *
3010 * Writes the data to PHY register at the offset. Assumes semaphore
3011 * already acquired and page already set.
3012 **/
3013s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3014{
3015 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3016}
3017
3018/**
3019 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3020 * @page: page to be accessed
3021 **/
3022static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3023{
3024 u32 phy_addr = 2;
3025
3026 if (page >= HV_INTC_FC_PAGE_START)
3027 phy_addr = 1;
3028
3029 return phy_addr;
3030}
3031
3032/**
3033 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3034 * @hw: pointer to the HW structure
3035 * @offset: register offset to be read or written
3036 * @data: pointer to the data to be read or written
3037 * @read: determines if operation is read or write
3038 *
3039 * Reads the PHY register at offset and stores the retrieved information
3040 * in data. Assumes semaphore already acquired. Note that the procedure
3041 * to access these regs uses the address port and data port to read/write.
3042 * These accesses done with PHY address 2 and without using pages.
3043 **/
3044static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3045 u16 *data, bool read)
3046{
3047 s32 ret_val;
3048 u32 addr_reg;
3049 u32 data_reg;
3050
3051 /* This takes care of the difference with desktop vs mobile phy */
3052 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3053 I82578_ADDR_REG : I82577_ADDR_REG);
3054 data_reg = addr_reg + 1;
3055
3056 /* All operations in this function are phy address 2 */
3057 hw->phy.addr = 2;
3058
3059 /* masking with 0x3F to remove the page from offset */
3060 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3061 if (ret_val) {
3062 e_dbg("Could not write the Address Offset port register\n");
3063 return ret_val;
3064 }
3065
3066 /* Read or write the data value next */
3067 if (read)
3068 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3069 else
3070 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3071
3072 if (ret_val)
3073 e_dbg("Could not access the Data port register\n");
3074
3075 return ret_val;
3076}
3077
3078/**
3079 * e1000_link_stall_workaround_hv - Si workaround
3080 * @hw: pointer to the HW structure
3081 *
3082 * This function works around a Si bug where the link partner can get
3083 * a link up indication before the PHY does. If small packets are sent
3084 * by the link partner they can be placed in the packet buffer without
3085 * being properly accounted for by the PHY and will stall preventing
3086 * further packets from being received. The workaround is to clear the
3087 * packet buffer after the PHY detects link up.
3088 **/
3089s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3090{
3091 s32 ret_val = 0;
3092 u16 data;
3093
3094 if (hw->phy.type != e1000_phy_82578)
3095 return 0;
3096
3097 /* Do not apply workaround if in PHY loopback bit 14 set */
3098 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3099 if (ret_val) {
3100 e_dbg("Error reading PHY register\n");
3101 return ret_val;
3102 }
3103 if (data & BMCR_LOOPBACK)
3104 return 0;
3105
3106 /* check if link is up and at 1Gbps */
3107 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3108 if (ret_val)
3109 return ret_val;
3110
3111 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3112 BM_CS_STATUS_SPEED_MASK);
3113
3114 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3115 BM_CS_STATUS_SPEED_1000))
3116 return 0;
3117
3118 msleep(200);
3119
3120 /* flush the packets in the fifo buffer */
3121 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3122 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3123 HV_MUX_DATA_CTRL_FORCE_SPEED));
3124 if (ret_val)
3125 return ret_val;
3126
3127 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3128}
3129
3130/**
3131 * e1000_check_polarity_82577 - Checks the polarity.
3132 * @hw: pointer to the HW structure
3133 *
3134 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3135 *
3136 * Polarity is determined based on the PHY specific status register.
3137 **/
3138s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3139{
3140 struct e1000_phy_info *phy = &hw->phy;
3141 s32 ret_val;
3142 u16 data;
3143
3144 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3145
3146 if (!ret_val)
3147 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3148 ? e1000_rev_polarity_reversed
3149 : e1000_rev_polarity_normal);
3150
3151 return ret_val;
3152}
3153
3154/**
3155 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3156 * @hw: pointer to the HW structure
3157 *
3158 * Calls the PHY setup function to force speed and duplex.
3159 **/
3160s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3161{
3162 struct e1000_phy_info *phy = &hw->phy;
3163 s32 ret_val;
3164 u16 phy_data;
3165 bool link;
3166
3167 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3168 if (ret_val)
3169 return ret_val;
3170
3171 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3172
3173 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3174 if (ret_val)
3175 return ret_val;
3176
3177 udelay(1);
3178
3179 if (phy->autoneg_wait_to_complete) {
3180 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3181
3182 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3183 100000, &link);
3184 if (ret_val)
3185 return ret_val;
3186
3187 if (!link)
3188 e_dbg("Link taking longer than expected.\n");
3189
3190 /* Try once more */
3191 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3192 100000, &link);
3193 }
3194
3195 return ret_val;
3196}
3197
3198/**
3199 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3200 * @hw: pointer to the HW structure
3201 *
3202 * Read PHY status to determine if link is up. If link is up, then
3203 * set/determine 10base-T extended distance and polarity correction. Read
3204 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3205 * determine on the cable length, local and remote receiver.
3206 **/
3207s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3208{
3209 struct e1000_phy_info *phy = &hw->phy;
3210 s32 ret_val;
3211 u16 data;
3212 bool link;
3213
3214 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3215 if (ret_val)
3216 return ret_val;
3217
3218 if (!link) {
3219 e_dbg("Phy info is only valid if link is up\n");
3220 return -E1000_ERR_CONFIG;
3221 }
3222
3223 phy->polarity_correction = true;
3224
3225 ret_val = e1000_check_polarity_82577(hw);
3226 if (ret_val)
3227 return ret_val;
3228
3229 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3230 if (ret_val)
3231 return ret_val;
3232
3233 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3234
3235 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3236 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3237 ret_val = hw->phy.ops.get_cable_length(hw);
3238 if (ret_val)
3239 return ret_val;
3240
3241 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3242 if (ret_val)
3243 return ret_val;
3244
3245 phy->local_rx = (data & LPA_1000LOCALRXOK)
3246 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3247
3248 phy->remote_rx = (data & LPA_1000REMRXOK)
3249 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3250 } else {
3251 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3252 phy->local_rx = e1000_1000t_rx_status_undefined;
3253 phy->remote_rx = e1000_1000t_rx_status_undefined;
3254 }
3255
3256 return 0;
3257}
3258
3259/**
3260 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3261 * @hw: pointer to the HW structure
3262 *
3263 * Reads the diagnostic status register and verifies result is valid before
3264 * placing it in the phy_cable_length field.
3265 **/
3266s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3267{
3268 struct e1000_phy_info *phy = &hw->phy;
3269 s32 ret_val;
3270 u16 phy_data, length;
3271
3272 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3273 if (ret_val)
3274 return ret_val;
3275
3276 length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);
3277
3278 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3279 return -E1000_ERR_PHY;
3280
3281 phy->cable_length = length;
3282
3283 return 0;
3284}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5
6static s32 e1000_wait_autoneg(struct e1000_hw *hw);
7static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
8 u16 *data, bool read, bool page_set);
9static u32 e1000_get_phy_addr_for_hv_page(u32 page);
10static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
11 u16 *data, bool read);
12
13/* Cable length tables */
14static const u16 e1000_m88_cable_length_table[] = {
15 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
16};
17
18#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_m88_cable_length_table)
20
21static const u16 e1000_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
29 124
30};
31
32#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
33 ARRAY_SIZE(e1000_igp_2_cable_length_table)
34
35/**
36 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
37 * @hw: pointer to the HW structure
38 *
39 * Read the PHY management control register and check whether a PHY reset
40 * is blocked. If a reset is not blocked return 0, otherwise
41 * return E1000_BLK_PHY_RESET (12).
42 **/
43s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
44{
45 u32 manc;
46
47 manc = er32(MANC);
48
49 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
50}
51
52/**
53 * e1000e_get_phy_id - Retrieve the PHY ID and revision
54 * @hw: pointer to the HW structure
55 *
56 * Reads the PHY registers and stores the PHY ID and possibly the PHY
57 * revision in the hardware structure.
58 **/
59s32 e1000e_get_phy_id(struct e1000_hw *hw)
60{
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val = 0;
63 u16 phy_id;
64 u16 retry_count = 0;
65
66 if (!phy->ops.read_reg)
67 return 0;
68
69 while (retry_count < 2) {
70 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
71 if (ret_val)
72 return ret_val;
73
74 phy->id = (u32)(phy_id << 16);
75 usleep_range(20, 40);
76 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
77 if (ret_val)
78 return ret_val;
79
80 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
81 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
82
83 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
84 return 0;
85
86 retry_count++;
87 }
88
89 return 0;
90}
91
92/**
93 * e1000e_phy_reset_dsp - Reset PHY DSP
94 * @hw: pointer to the HW structure
95 *
96 * Reset the digital signal processor.
97 **/
98s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
99{
100 s32 ret_val;
101
102 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
103 if (ret_val)
104 return ret_val;
105
106 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
107}
108
109/**
110 * e1000e_read_phy_reg_mdic - Read MDI control register
111 * @hw: pointer to the HW structure
112 * @offset: register offset to be read
113 * @data: pointer to the read data
114 *
115 * Reads the MDI control register in the PHY at offset and stores the
116 * information read to data.
117 **/
118s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 u32 i, mdic = 0;
122
123 if (offset > MAX_PHY_REG_ADDRESS) {
124 e_dbg("PHY Address %d is out of range\n", offset);
125 return -E1000_ERR_PARAM;
126 }
127
128 /* Set up Op-code, Phy Address, and register offset in the MDI
129 * Control register. The MAC will take care of interfacing with the
130 * PHY to retrieve the desired data.
131 */
132 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
133 (phy->addr << E1000_MDIC_PHY_SHIFT) |
134 (E1000_MDIC_OP_READ));
135
136 ew32(MDIC, mdic);
137
138 /* Poll the ready bit to see if the MDI read completed
139 * Increasing the time out as testing showed failures with
140 * the lower time out
141 */
142 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
143 udelay(50);
144 mdic = er32(MDIC);
145 if (mdic & E1000_MDIC_READY)
146 break;
147 }
148 if (!(mdic & E1000_MDIC_READY)) {
149 e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
150 return -E1000_ERR_PHY;
151 }
152 if (mdic & E1000_MDIC_ERROR) {
153 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
154 return -E1000_ERR_PHY;
155 }
156 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
157 e_dbg("MDI Read offset error - requested %d, returned %d\n",
158 offset,
159 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16)mdic;
163
164 /* Allow some time after each MDIC transaction to avoid
165 * reading duplicate data in the next MDIC transaction.
166 */
167 if (hw->mac.type == e1000_pch2lan)
168 udelay(100);
169
170 return 0;
171}
172
173/**
174 * e1000e_write_phy_reg_mdic - Write MDI control register
175 * @hw: pointer to the HW structure
176 * @offset: register offset to write to
177 * @data: data to write to register at offset
178 *
179 * Writes data to MDI control register in the PHY at offset.
180 **/
181s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
182{
183 struct e1000_phy_info *phy = &hw->phy;
184 u32 i, mdic = 0;
185
186 if (offset > MAX_PHY_REG_ADDRESS) {
187 e_dbg("PHY Address %d is out of range\n", offset);
188 return -E1000_ERR_PARAM;
189 }
190
191 /* Set up Op-code, Phy Address, and register offset in the MDI
192 * Control register. The MAC will take care of interfacing with the
193 * PHY to retrieve the desired data.
194 */
195 mdic = (((u32)data) |
196 (offset << E1000_MDIC_REG_SHIFT) |
197 (phy->addr << E1000_MDIC_PHY_SHIFT) |
198 (E1000_MDIC_OP_WRITE));
199
200 ew32(MDIC, mdic);
201
202 /* Poll the ready bit to see if the MDI read completed
203 * Increasing the time out as testing showed failures with
204 * the lower time out
205 */
206 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
207 udelay(50);
208 mdic = er32(MDIC);
209 if (mdic & E1000_MDIC_READY)
210 break;
211 }
212 if (!(mdic & E1000_MDIC_READY)) {
213 e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
214 return -E1000_ERR_PHY;
215 }
216 if (mdic & E1000_MDIC_ERROR) {
217 e_dbg("MDI Write PHY Red Address %d Error\n", offset);
218 return -E1000_ERR_PHY;
219 }
220 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
221 e_dbg("MDI Write offset error - requested %d, returned %d\n",
222 offset,
223 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
224 return -E1000_ERR_PHY;
225 }
226
227 /* Allow some time after each MDIC transaction to avoid
228 * reading duplicate data in the next MDIC transaction.
229 */
230 if (hw->mac.type == e1000_pch2lan)
231 udelay(100);
232
233 return 0;
234}
235
236/**
237 * e1000e_read_phy_reg_m88 - Read m88 PHY register
238 * @hw: pointer to the HW structure
239 * @offset: register offset to be read
240 * @data: pointer to the read data
241 *
242 * Acquires semaphore, if necessary, then reads the PHY register at offset
243 * and storing the retrieved information in data. Release any acquired
244 * semaphores before exiting.
245 **/
246s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
247{
248 s32 ret_val;
249
250 ret_val = hw->phy.ops.acquire(hw);
251 if (ret_val)
252 return ret_val;
253
254 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
255 data);
256
257 hw->phy.ops.release(hw);
258
259 return ret_val;
260}
261
262/**
263 * e1000e_write_phy_reg_m88 - Write m88 PHY register
264 * @hw: pointer to the HW structure
265 * @offset: register offset to write to
266 * @data: data to write at register offset
267 *
268 * Acquires semaphore, if necessary, then writes the data to PHY register
269 * at the offset. Release any acquired semaphores before exiting.
270 **/
271s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
272{
273 s32 ret_val;
274
275 ret_val = hw->phy.ops.acquire(hw);
276 if (ret_val)
277 return ret_val;
278
279 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
280 data);
281
282 hw->phy.ops.release(hw);
283
284 return ret_val;
285}
286
287/**
288 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
289 * @hw: pointer to the HW structure
290 * @page: page to set (shifted left when necessary)
291 *
292 * Sets PHY page required for PHY register access. Assumes semaphore is
293 * already acquired. Note, this function sets phy.addr to 1 so the caller
294 * must set it appropriately (if necessary) after this function returns.
295 **/
296s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
297{
298 e_dbg("Setting page 0x%x\n", page);
299
300 hw->phy.addr = 1;
301
302 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
303}
304
305/**
306 * __e1000e_read_phy_reg_igp - Read igp PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to be read
309 * @data: pointer to the read data
310 * @locked: semaphore has already been acquired or not
311 *
312 * Acquires semaphore, if necessary, then reads the PHY register at offset
313 * and stores the retrieved information in data. Release any acquired
314 * semaphores before exiting.
315 **/
316static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
317 bool locked)
318{
319 s32 ret_val = 0;
320
321 if (!locked) {
322 if (!hw->phy.ops.acquire)
323 return 0;
324
325 ret_val = hw->phy.ops.acquire(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330 if (offset > MAX_PHY_MULTI_PAGE_REG)
331 ret_val = e1000e_write_phy_reg_mdic(hw,
332 IGP01E1000_PHY_PAGE_SELECT,
333 (u16)offset);
334 if (!ret_val)
335 ret_val = e1000e_read_phy_reg_mdic(hw,
336 MAX_PHY_REG_ADDRESS & offset,
337 data);
338 if (!locked)
339 hw->phy.ops.release(hw);
340
341 return ret_val;
342}
343
344/**
345 * e1000e_read_phy_reg_igp - Read igp PHY register
346 * @hw: pointer to the HW structure
347 * @offset: register offset to be read
348 * @data: pointer to the read data
349 *
350 * Acquires semaphore then reads the PHY register at offset and stores the
351 * retrieved information in data.
352 * Release the acquired semaphore before exiting.
353 **/
354s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
355{
356 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
357}
358
359/**
360 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 *
365 * Reads the PHY register at offset and stores the retrieved information
366 * in data. Assumes semaphore already acquired.
367 **/
368s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
369{
370 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
371}
372
373/**
374 * __e1000e_write_phy_reg_igp - Write igp PHY register
375 * @hw: pointer to the HW structure
376 * @offset: register offset to write to
377 * @data: data to write at register offset
378 * @locked: semaphore has already been acquired or not
379 *
380 * Acquires semaphore, if necessary, then writes the data to PHY register
381 * at the offset. Release any acquired semaphores before exiting.
382 **/
383static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
384 bool locked)
385{
386 s32 ret_val = 0;
387
388 if (!locked) {
389 if (!hw->phy.ops.acquire)
390 return 0;
391
392 ret_val = hw->phy.ops.acquire(hw);
393 if (ret_val)
394 return ret_val;
395 }
396
397 if (offset > MAX_PHY_MULTI_PAGE_REG)
398 ret_val = e1000e_write_phy_reg_mdic(hw,
399 IGP01E1000_PHY_PAGE_SELECT,
400 (u16)offset);
401 if (!ret_val)
402 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
403 offset, data);
404 if (!locked)
405 hw->phy.ops.release(hw);
406
407 return ret_val;
408}
409
410/**
411 * e1000e_write_phy_reg_igp - Write igp PHY register
412 * @hw: pointer to the HW structure
413 * @offset: register offset to write to
414 * @data: data to write at register offset
415 *
416 * Acquires semaphore then writes the data to PHY register
417 * at the offset. Release any acquired semaphores before exiting.
418 **/
419s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
420{
421 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
422}
423
424/**
425 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
426 * @hw: pointer to the HW structure
427 * @offset: register offset to write to
428 * @data: data to write at register offset
429 *
430 * Writes the data to PHY register at the offset.
431 * Assumes semaphore already acquired.
432 **/
433s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
434{
435 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
436}
437
438/**
439 * __e1000_read_kmrn_reg - Read kumeran register
440 * @hw: pointer to the HW structure
441 * @offset: register offset to be read
442 * @data: pointer to the read data
443 * @locked: semaphore has already been acquired or not
444 *
445 * Acquires semaphore, if necessary. Then reads the PHY register at offset
446 * using the kumeran interface. The information retrieved is stored in data.
447 * Release any acquired semaphores before exiting.
448 **/
449static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
450 bool locked)
451{
452 u32 kmrnctrlsta;
453
454 if (!locked) {
455 s32 ret_val = 0;
456
457 if (!hw->phy.ops.acquire)
458 return 0;
459
460 ret_val = hw->phy.ops.acquire(hw);
461 if (ret_val)
462 return ret_val;
463 }
464
465 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
466 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
467 ew32(KMRNCTRLSTA, kmrnctrlsta);
468 e1e_flush();
469
470 udelay(2);
471
472 kmrnctrlsta = er32(KMRNCTRLSTA);
473 *data = (u16)kmrnctrlsta;
474
475 if (!locked)
476 hw->phy.ops.release(hw);
477
478 return 0;
479}
480
481/**
482 * e1000e_read_kmrn_reg - Read kumeran register
483 * @hw: pointer to the HW structure
484 * @offset: register offset to be read
485 * @data: pointer to the read data
486 *
487 * Acquires semaphore then reads the PHY register at offset using the
488 * kumeran interface. The information retrieved is stored in data.
489 * Release the acquired semaphore before exiting.
490 **/
491s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
492{
493 return __e1000_read_kmrn_reg(hw, offset, data, false);
494}
495
496/**
497 * e1000e_read_kmrn_reg_locked - Read kumeran register
498 * @hw: pointer to the HW structure
499 * @offset: register offset to be read
500 * @data: pointer to the read data
501 *
502 * Reads the PHY register at offset using the kumeran interface. The
503 * information retrieved is stored in data.
504 * Assumes semaphore already acquired.
505 **/
506s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
507{
508 return __e1000_read_kmrn_reg(hw, offset, data, true);
509}
510
511/**
512 * __e1000_write_kmrn_reg - Write kumeran register
513 * @hw: pointer to the HW structure
514 * @offset: register offset to write to
515 * @data: data to write at register offset
516 * @locked: semaphore has already been acquired or not
517 *
518 * Acquires semaphore, if necessary. Then write the data to PHY register
519 * at the offset using the kumeran interface. Release any acquired semaphores
520 * before exiting.
521 **/
522static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
523 bool locked)
524{
525 u32 kmrnctrlsta;
526
527 if (!locked) {
528 s32 ret_val = 0;
529
530 if (!hw->phy.ops.acquire)
531 return 0;
532
533 ret_val = hw->phy.ops.acquire(hw);
534 if (ret_val)
535 return ret_val;
536 }
537
538 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
539 E1000_KMRNCTRLSTA_OFFSET) | data;
540 ew32(KMRNCTRLSTA, kmrnctrlsta);
541 e1e_flush();
542
543 udelay(2);
544
545 if (!locked)
546 hw->phy.ops.release(hw);
547
548 return 0;
549}
550
551/**
552 * e1000e_write_kmrn_reg - Write kumeran register
553 * @hw: pointer to the HW structure
554 * @offset: register offset to write to
555 * @data: data to write at register offset
556 *
557 * Acquires semaphore then writes the data to the PHY register at the offset
558 * using the kumeran interface. Release the acquired semaphore before exiting.
559 **/
560s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
561{
562 return __e1000_write_kmrn_reg(hw, offset, data, false);
563}
564
565/**
566 * e1000e_write_kmrn_reg_locked - Write kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
570 *
571 * Write the data to PHY register at the offset using the kumeran interface.
572 * Assumes semaphore already acquired.
573 **/
574s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
575{
576 return __e1000_write_kmrn_reg(hw, offset, data, true);
577}
578
579/**
580 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
581 * @hw: pointer to the HW structure
582 *
583 * Sets up Master/slave mode
584 **/
585static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
586{
587 s32 ret_val;
588 u16 phy_data;
589
590 /* Resolve Master/Slave mode */
591 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
592 if (ret_val)
593 return ret_val;
594
595 /* load defaults for future use */
596 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
597 ((phy_data & CTL1000_AS_MASTER) ?
598 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
599
600 switch (hw->phy.ms_type) {
601 case e1000_ms_force_master:
602 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
603 break;
604 case e1000_ms_force_slave:
605 phy_data |= CTL1000_ENABLE_MASTER;
606 phy_data &= ~(CTL1000_AS_MASTER);
607 break;
608 case e1000_ms_auto:
609 phy_data &= ~CTL1000_ENABLE_MASTER;
610 fallthrough;
611 default:
612 break;
613 }
614
615 return e1e_wphy(hw, MII_CTRL1000, phy_data);
616}
617
618/**
619 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
620 * @hw: pointer to the HW structure
621 *
622 * Sets up Carrier-sense on Transmit and downshift values.
623 **/
624s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
625{
626 s32 ret_val;
627 u16 phy_data;
628
629 /* Enable CRS on Tx. This must be set for half-duplex operation. */
630 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
631 if (ret_val)
632 return ret_val;
633
634 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
635
636 /* Enable downshift */
637 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
638
639 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
640 if (ret_val)
641 return ret_val;
642
643 /* Set MDI/MDIX mode */
644 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
645 if (ret_val)
646 return ret_val;
647 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
648 /* Options:
649 * 0 - Auto (default)
650 * 1 - MDI mode
651 * 2 - MDI-X mode
652 */
653 switch (hw->phy.mdix) {
654 case 1:
655 break;
656 case 2:
657 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
658 break;
659 case 0:
660 default:
661 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
662 break;
663 }
664 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
665 if (ret_val)
666 return ret_val;
667
668 return e1000_set_master_slave_mode(hw);
669}
670
671/**
672 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
673 * @hw: pointer to the HW structure
674 *
675 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
676 * and downshift values are set also.
677 **/
678s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
679{
680 struct e1000_phy_info *phy = &hw->phy;
681 s32 ret_val;
682 u16 phy_data;
683
684 /* Enable CRS on Tx. This must be set for half-duplex operation. */
685 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
686 if (ret_val)
687 return ret_val;
688
689 /* For BM PHY this bit is downshift enable */
690 if (phy->type != e1000_phy_bm)
691 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
692
693 /* Options:
694 * MDI/MDI-X = 0 (default)
695 * 0 - Auto for all speeds
696 * 1 - MDI mode
697 * 2 - MDI-X mode
698 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
699 */
700 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
701
702 switch (phy->mdix) {
703 case 1:
704 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
705 break;
706 case 2:
707 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
708 break;
709 case 3:
710 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
711 break;
712 case 0:
713 default:
714 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
715 break;
716 }
717
718 /* Options:
719 * disable_polarity_correction = 0 (default)
720 * Automatic Correction for Reversed Cable Polarity
721 * 0 - Disabled
722 * 1 - Enabled
723 */
724 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
725 if (phy->disable_polarity_correction)
726 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
727
728 /* Enable downshift on BM (disabled by default) */
729 if (phy->type == e1000_phy_bm) {
730 /* For 82574/82583, first disable then enable downshift */
731 if (phy->id == BME1000_E_PHY_ID_R2) {
732 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
733 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
734 phy_data);
735 if (ret_val)
736 return ret_val;
737 /* Commit the changes. */
738 ret_val = phy->ops.commit(hw);
739 if (ret_val) {
740 e_dbg("Error committing the PHY changes\n");
741 return ret_val;
742 }
743 }
744
745 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
746 }
747
748 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
749 if (ret_val)
750 return ret_val;
751
752 if ((phy->type == e1000_phy_m88) &&
753 (phy->revision < E1000_REVISION_4) &&
754 (phy->id != BME1000_E_PHY_ID_R2)) {
755 /* Force TX_CLK in the Extended PHY Specific Control Register
756 * to 25MHz clock.
757 */
758 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
759 if (ret_val)
760 return ret_val;
761
762 phy_data |= M88E1000_EPSCR_TX_CLK_25;
763
764 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
765 /* 82573L PHY - set the downshift counter to 5x. */
766 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
767 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
768 } else {
769 /* Configure Master and Slave downshift values */
770 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
771 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
772 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
773 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
774 }
775 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
776 if (ret_val)
777 return ret_val;
778 }
779
780 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
781 /* Set PHY page 0, register 29 to 0x0003 */
782 ret_val = e1e_wphy(hw, 29, 0x0003);
783 if (ret_val)
784 return ret_val;
785
786 /* Set PHY page 0, register 30 to 0x0000 */
787 ret_val = e1e_wphy(hw, 30, 0x0000);
788 if (ret_val)
789 return ret_val;
790 }
791
792 /* Commit the changes. */
793 if (phy->ops.commit) {
794 ret_val = phy->ops.commit(hw);
795 if (ret_val) {
796 e_dbg("Error committing the PHY changes\n");
797 return ret_val;
798 }
799 }
800
801 if (phy->type == e1000_phy_82578) {
802 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
803 if (ret_val)
804 return ret_val;
805
806 /* 82578 PHY - set the downshift count to 1x. */
807 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
808 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
809 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
810 if (ret_val)
811 return ret_val;
812 }
813
814 return 0;
815}
816
817/**
818 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
819 * @hw: pointer to the HW structure
820 *
821 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
822 * igp PHY's.
823 **/
824s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
825{
826 struct e1000_phy_info *phy = &hw->phy;
827 s32 ret_val;
828 u16 data;
829
830 ret_val = e1000_phy_hw_reset(hw);
831 if (ret_val) {
832 e_dbg("Error resetting the PHY.\n");
833 return ret_val;
834 }
835
836 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
837 * timeout issues when LFS is enabled.
838 */
839 msleep(100);
840
841 /* disable lplu d0 during driver init */
842 if (hw->phy.ops.set_d0_lplu_state) {
843 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
844 if (ret_val) {
845 e_dbg("Error Disabling LPLU D0\n");
846 return ret_val;
847 }
848 }
849 /* Configure mdi-mdix settings */
850 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
851 if (ret_val)
852 return ret_val;
853
854 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
855
856 switch (phy->mdix) {
857 case 1:
858 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
859 break;
860 case 2:
861 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
862 break;
863 case 0:
864 default:
865 data |= IGP01E1000_PSCR_AUTO_MDIX;
866 break;
867 }
868 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
869 if (ret_val)
870 return ret_val;
871
872 /* set auto-master slave resolution settings */
873 if (hw->mac.autoneg) {
874 /* when autonegotiation advertisement is only 1000Mbps then we
875 * should disable SmartSpeed and enable Auto MasterSlave
876 * resolution as hardware default.
877 */
878 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
879 /* Disable SmartSpeed */
880 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
881 &data);
882 if (ret_val)
883 return ret_val;
884
885 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
887 data);
888 if (ret_val)
889 return ret_val;
890
891 /* Set auto Master/Slave resolution process */
892 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
893 if (ret_val)
894 return ret_val;
895
896 data &= ~CTL1000_ENABLE_MASTER;
897 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
898 if (ret_val)
899 return ret_val;
900 }
901
902 ret_val = e1000_set_master_slave_mode(hw);
903 }
904
905 return ret_val;
906}
907
908/**
909 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
910 * @hw: pointer to the HW structure
911 *
912 * Reads the MII auto-neg advertisement register and/or the 1000T control
913 * register and if the PHY is already setup for auto-negotiation, then
914 * return successful. Otherwise, setup advertisement and flow control to
915 * the appropriate values for the wanted auto-negotiation.
916 **/
917static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
918{
919 struct e1000_phy_info *phy = &hw->phy;
920 s32 ret_val;
921 u16 mii_autoneg_adv_reg;
922 u16 mii_1000t_ctrl_reg = 0;
923
924 phy->autoneg_advertised &= phy->autoneg_mask;
925
926 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
927 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
928 if (ret_val)
929 return ret_val;
930
931 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
932 /* Read the MII 1000Base-T Control Register (Address 9). */
933 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
934 if (ret_val)
935 return ret_val;
936 }
937
938 /* Need to parse both autoneg_advertised and fc and set up
939 * the appropriate PHY registers. First we will parse for
940 * autoneg_advertised software override. Since we can advertise
941 * a plethora of combinations, we need to check each bit
942 * individually.
943 */
944
945 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
946 * Advertisement Register (Address 4) and the 1000 mb speed bits in
947 * the 1000Base-T Control Register (Address 9).
948 */
949 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
950 ADVERTISE_100HALF |
951 ADVERTISE_10FULL | ADVERTISE_10HALF);
952 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
953
954 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
955
956 /* Do we want to advertise 10 Mb Half Duplex? */
957 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
958 e_dbg("Advertise 10mb Half duplex\n");
959 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
960 }
961
962 /* Do we want to advertise 10 Mb Full Duplex? */
963 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
964 e_dbg("Advertise 10mb Full duplex\n");
965 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
966 }
967
968 /* Do we want to advertise 100 Mb Half Duplex? */
969 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
970 e_dbg("Advertise 100mb Half duplex\n");
971 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
972 }
973
974 /* Do we want to advertise 100 Mb Full Duplex? */
975 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
976 e_dbg("Advertise 100mb Full duplex\n");
977 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
978 }
979
980 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
981 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
982 e_dbg("Advertise 1000mb Half duplex request denied!\n");
983
984 /* Do we want to advertise 1000 Mb Full Duplex? */
985 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
986 e_dbg("Advertise 1000mb Full duplex\n");
987 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
988 }
989
990 /* Check for a software override of the flow control settings, and
991 * setup the PHY advertisement registers accordingly. If
992 * auto-negotiation is enabled, then software will have to set the
993 * "PAUSE" bits to the correct value in the Auto-Negotiation
994 * Advertisement Register (MII_ADVERTISE) and re-start auto-
995 * negotiation.
996 *
997 * The possible values of the "fc" parameter are:
998 * 0: Flow control is completely disabled
999 * 1: Rx flow control is enabled (we can receive pause frames
1000 * but not send pause frames).
1001 * 2: Tx flow control is enabled (we can send pause frames
1002 * but we do not support receiving pause frames).
1003 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1004 * other: No software override. The flow control configuration
1005 * in the EEPROM is used.
1006 */
1007 switch (hw->fc.current_mode) {
1008 case e1000_fc_none:
1009 /* Flow control (Rx & Tx) is completely disabled by a
1010 * software over-ride.
1011 */
1012 mii_autoneg_adv_reg &=
1013 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1014 break;
1015 case e1000_fc_rx_pause:
1016 /* Rx Flow control is enabled, and Tx Flow control is
1017 * disabled, by a software over-ride.
1018 *
1019 * Since there really isn't a way to advertise that we are
1020 * capable of Rx Pause ONLY, we will advertise that we
1021 * support both symmetric and asymmetric Rx PAUSE. Later
1022 * (in e1000e_config_fc_after_link_up) we will disable the
1023 * hw's ability to send PAUSE frames.
1024 */
1025 mii_autoneg_adv_reg |=
1026 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1027 break;
1028 case e1000_fc_tx_pause:
1029 /* Tx Flow control is enabled, and Rx Flow control is
1030 * disabled, by a software over-ride.
1031 */
1032 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1033 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1034 break;
1035 case e1000_fc_full:
1036 /* Flow control (both Rx and Tx) is enabled by a software
1037 * over-ride.
1038 */
1039 mii_autoneg_adv_reg |=
1040 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1041 break;
1042 default:
1043 e_dbg("Flow control param set incorrectly\n");
1044 return -E1000_ERR_CONFIG;
1045 }
1046
1047 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1048 if (ret_val)
1049 return ret_val;
1050
1051 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1052
1053 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1054 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1055
1056 return ret_val;
1057}
1058
1059/**
1060 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1061 * @hw: pointer to the HW structure
1062 *
1063 * Performs initial bounds checking on autoneg advertisement parameter, then
1064 * configure to advertise the full capability. Setup the PHY to autoneg
1065 * and restart the negotiation process between the link partner. If
1066 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1067 **/
1068static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1069{
1070 struct e1000_phy_info *phy = &hw->phy;
1071 s32 ret_val;
1072 u16 phy_ctrl;
1073
1074 /* Perform some bounds checking on the autoneg advertisement
1075 * parameter.
1076 */
1077 phy->autoneg_advertised &= phy->autoneg_mask;
1078
1079 /* If autoneg_advertised is zero, we assume it was not defaulted
1080 * by the calling code so we set to advertise full capability.
1081 */
1082 if (!phy->autoneg_advertised)
1083 phy->autoneg_advertised = phy->autoneg_mask;
1084
1085 e_dbg("Reconfiguring auto-neg advertisement params\n");
1086 ret_val = e1000_phy_setup_autoneg(hw);
1087 if (ret_val) {
1088 e_dbg("Error Setting up Auto-Negotiation\n");
1089 return ret_val;
1090 }
1091 e_dbg("Restarting Auto-Neg\n");
1092
1093 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1094 * the Auto Neg Restart bit in the PHY control register.
1095 */
1096 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1097 if (ret_val)
1098 return ret_val;
1099
1100 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1101 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1102 if (ret_val)
1103 return ret_val;
1104
1105 /* Does the user want to wait for Auto-Neg to complete here, or
1106 * check at a later time (for example, callback routine).
1107 */
1108 if (phy->autoneg_wait_to_complete) {
1109 ret_val = e1000_wait_autoneg(hw);
1110 if (ret_val) {
1111 e_dbg("Error while waiting for autoneg to complete\n");
1112 return ret_val;
1113 }
1114 }
1115
1116 hw->mac.get_link_status = true;
1117
1118 return ret_val;
1119}
1120
1121/**
1122 * e1000e_setup_copper_link - Configure copper link settings
1123 * @hw: pointer to the HW structure
1124 *
1125 * Calls the appropriate function to configure the link for auto-neg or forced
1126 * speed and duplex. Then we check for link, once link is established calls
1127 * to configure collision distance and flow control are called. If link is
1128 * not established, we return -E1000_ERR_PHY (-2).
1129 **/
1130s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1131{
1132 s32 ret_val;
1133 bool link;
1134
1135 if (hw->mac.autoneg) {
1136 /* Setup autoneg and flow control advertisement and perform
1137 * autonegotiation.
1138 */
1139 ret_val = e1000_copper_link_autoneg(hw);
1140 if (ret_val)
1141 return ret_val;
1142 } else {
1143 /* PHY will be set to 10H, 10F, 100H or 100F
1144 * depending on user settings.
1145 */
1146 e_dbg("Forcing Speed and Duplex\n");
1147 ret_val = hw->phy.ops.force_speed_duplex(hw);
1148 if (ret_val) {
1149 e_dbg("Error Forcing Speed and Duplex\n");
1150 return ret_val;
1151 }
1152 }
1153
1154 /* Check link status. Wait up to 100 microseconds for link to become
1155 * valid.
1156 */
1157 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1158 &link);
1159 if (ret_val)
1160 return ret_val;
1161
1162 if (link) {
1163 e_dbg("Valid link established!!!\n");
1164 hw->mac.ops.config_collision_dist(hw);
1165 ret_val = e1000e_config_fc_after_link_up(hw);
1166 } else {
1167 e_dbg("Unable to establish link!!!\n");
1168 }
1169
1170 return ret_val;
1171}
1172
1173/**
1174 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1175 * @hw: pointer to the HW structure
1176 *
1177 * Calls the PHY setup function to force speed and duplex. Clears the
1178 * auto-crossover to force MDI manually. Waits for link and returns
1179 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1180 **/
1181s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1182{
1183 struct e1000_phy_info *phy = &hw->phy;
1184 s32 ret_val;
1185 u16 phy_data;
1186 bool link;
1187
1188 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1189 if (ret_val)
1190 return ret_val;
1191
1192 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1193
1194 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1195 if (ret_val)
1196 return ret_val;
1197
1198 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1199 * forced whenever speed and duplex are forced.
1200 */
1201 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1202 if (ret_val)
1203 return ret_val;
1204
1205 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1206 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1207
1208 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212 e_dbg("IGP PSCR: %X\n", phy_data);
1213
1214 udelay(1);
1215
1216 if (phy->autoneg_wait_to_complete) {
1217 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1218
1219 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1220 100000, &link);
1221 if (ret_val)
1222 return ret_val;
1223
1224 if (!link)
1225 e_dbg("Link taking longer than expected.\n");
1226
1227 /* Try once more */
1228 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1229 100000, &link);
1230 }
1231
1232 return ret_val;
1233}
1234
1235/**
1236 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1237 * @hw: pointer to the HW structure
1238 *
1239 * Calls the PHY setup function to force speed and duplex. Clears the
1240 * auto-crossover to force MDI manually. Resets the PHY to commit the
1241 * changes. If time expires while waiting for link up, we reset the DSP.
1242 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1243 * successful completion, else return corresponding error code.
1244 **/
1245s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1246{
1247 struct e1000_phy_info *phy = &hw->phy;
1248 s32 ret_val;
1249 u16 phy_data;
1250 bool link;
1251
1252 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1253 * forced whenever speed and duplex are forced.
1254 */
1255 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1256 if (ret_val)
1257 return ret_val;
1258
1259 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1260 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1265
1266 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1267 if (ret_val)
1268 return ret_val;
1269
1270 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1271
1272 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1273 if (ret_val)
1274 return ret_val;
1275
1276 /* Reset the phy to commit changes. */
1277 if (hw->phy.ops.commit) {
1278 ret_val = hw->phy.ops.commit(hw);
1279 if (ret_val)
1280 return ret_val;
1281 }
1282
1283 if (phy->autoneg_wait_to_complete) {
1284 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1285
1286 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1287 100000, &link);
1288 if (ret_val)
1289 return ret_val;
1290
1291 if (!link) {
1292 if (hw->phy.type != e1000_phy_m88) {
1293 e_dbg("Link taking longer than expected.\n");
1294 } else {
1295 /* We didn't get link.
1296 * Reset the DSP and cross our fingers.
1297 */
1298 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1299 0x001d);
1300 if (ret_val)
1301 return ret_val;
1302 ret_val = e1000e_phy_reset_dsp(hw);
1303 if (ret_val)
1304 return ret_val;
1305 }
1306 }
1307
1308 /* Try once more */
1309 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1310 100000, &link);
1311 if (ret_val)
1312 return ret_val;
1313 }
1314
1315 if (hw->phy.type != e1000_phy_m88)
1316 return 0;
1317
1318 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1319 if (ret_val)
1320 return ret_val;
1321
1322 /* Resetting the phy means we need to re-force TX_CLK in the
1323 * Extended PHY Specific Control Register to 25MHz clock from
1324 * the reset value of 2.5MHz.
1325 */
1326 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1327 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1328 if (ret_val)
1329 return ret_val;
1330
1331 /* In addition, we must re-enable CRS on Tx for both half and full
1332 * duplex.
1333 */
1334 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1335 if (ret_val)
1336 return ret_val;
1337
1338 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1339 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1340
1341 return ret_val;
1342}
1343
1344/**
1345 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1346 * @hw: pointer to the HW structure
1347 *
1348 * Forces the speed and duplex settings of the PHY.
1349 * This is a function pointer entry point only called by
1350 * PHY setup routines.
1351 **/
1352s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1353{
1354 struct e1000_phy_info *phy = &hw->phy;
1355 s32 ret_val;
1356 u16 data;
1357 bool link;
1358
1359 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1360 if (ret_val)
1361 return ret_val;
1362
1363 e1000e_phy_force_speed_duplex_setup(hw, &data);
1364
1365 ret_val = e1e_wphy(hw, MII_BMCR, data);
1366 if (ret_val)
1367 return ret_val;
1368
1369 /* Disable MDI-X support for 10/100 */
1370 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 data &= ~IFE_PMC_AUTO_MDIX;
1375 data &= ~IFE_PMC_FORCE_MDIX;
1376
1377 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 e_dbg("IFE PMC: %X\n", data);
1382
1383 udelay(1);
1384
1385 if (phy->autoneg_wait_to_complete) {
1386 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1387
1388 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1389 100000, &link);
1390 if (ret_val)
1391 return ret_val;
1392
1393 if (!link)
1394 e_dbg("Link taking longer than expected.\n");
1395
1396 /* Try once more */
1397 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1398 100000, &link);
1399 if (ret_val)
1400 return ret_val;
1401 }
1402
1403 return 0;
1404}
1405
1406/**
1407 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1408 * @hw: pointer to the HW structure
1409 * @phy_ctrl: pointer to current value of MII_BMCR
1410 *
1411 * Forces speed and duplex on the PHY by doing the following: disable flow
1412 * control, force speed/duplex on the MAC, disable auto speed detection,
1413 * disable auto-negotiation, configure duplex, configure speed, configure
1414 * the collision distance, write configuration to CTRL register. The
1415 * caller must write to the MII_BMCR register for these settings to
1416 * take affect.
1417 **/
1418void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1419{
1420 struct e1000_mac_info *mac = &hw->mac;
1421 u32 ctrl;
1422
1423 /* Turn off flow control when forcing speed/duplex */
1424 hw->fc.current_mode = e1000_fc_none;
1425
1426 /* Force speed/duplex on the mac */
1427 ctrl = er32(CTRL);
1428 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1429 ctrl &= ~E1000_CTRL_SPD_SEL;
1430
1431 /* Disable Auto Speed Detection */
1432 ctrl &= ~E1000_CTRL_ASDE;
1433
1434 /* Disable autoneg on the phy */
1435 *phy_ctrl &= ~BMCR_ANENABLE;
1436
1437 /* Forcing Full or Half Duplex? */
1438 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1439 ctrl &= ~E1000_CTRL_FD;
1440 *phy_ctrl &= ~BMCR_FULLDPLX;
1441 e_dbg("Half Duplex\n");
1442 } else {
1443 ctrl |= E1000_CTRL_FD;
1444 *phy_ctrl |= BMCR_FULLDPLX;
1445 e_dbg("Full Duplex\n");
1446 }
1447
1448 /* Forcing 10mb or 100mb? */
1449 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1450 ctrl |= E1000_CTRL_SPD_100;
1451 *phy_ctrl |= BMCR_SPEED100;
1452 *phy_ctrl &= ~BMCR_SPEED1000;
1453 e_dbg("Forcing 100mb\n");
1454 } else {
1455 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1456 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1457 e_dbg("Forcing 10mb\n");
1458 }
1459
1460 hw->mac.ops.config_collision_dist(hw);
1461
1462 ew32(CTRL, ctrl);
1463}
1464
1465/**
1466 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1467 * @hw: pointer to the HW structure
1468 * @active: boolean used to enable/disable lplu
1469 *
1470 * Success returns 0, Failure returns 1
1471 *
1472 * The low power link up (lplu) state is set to the power management level D3
1473 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1474 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1475 * is used during Dx states where the power conservation is most important.
1476 * During driver activity, SmartSpeed should be enabled so performance is
1477 * maintained.
1478 **/
1479s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1480{
1481 struct e1000_phy_info *phy = &hw->phy;
1482 s32 ret_val;
1483 u16 data;
1484
1485 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1486 if (ret_val)
1487 return ret_val;
1488
1489 if (!active) {
1490 data &= ~IGP02E1000_PM_D3_LPLU;
1491 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1492 if (ret_val)
1493 return ret_val;
1494 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1495 * during Dx states where the power conservation is most
1496 * important. During driver activity we should enable
1497 * SmartSpeed, so performance is maintained.
1498 */
1499 if (phy->smart_speed == e1000_smart_speed_on) {
1500 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1501 &data);
1502 if (ret_val)
1503 return ret_val;
1504
1505 data |= IGP01E1000_PSCFR_SMART_SPEED;
1506 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1507 data);
1508 if (ret_val)
1509 return ret_val;
1510 } else if (phy->smart_speed == e1000_smart_speed_off) {
1511 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1512 &data);
1513 if (ret_val)
1514 return ret_val;
1515
1516 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1517 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1518 data);
1519 if (ret_val)
1520 return ret_val;
1521 }
1522 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1523 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1524 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1525 data |= IGP02E1000_PM_D3_LPLU;
1526 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1527 if (ret_val)
1528 return ret_val;
1529
1530 /* When LPLU is enabled, we should disable SmartSpeed */
1531 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1537 }
1538
1539 return ret_val;
1540}
1541
1542/**
1543 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1544 * @hw: pointer to the HW structure
1545 *
1546 * Success returns 0, Failure returns 1
1547 *
1548 * A downshift is detected by querying the PHY link health.
1549 **/
1550s32 e1000e_check_downshift(struct e1000_hw *hw)
1551{
1552 struct e1000_phy_info *phy = &hw->phy;
1553 s32 ret_val;
1554 u16 phy_data, offset, mask;
1555
1556 switch (phy->type) {
1557 case e1000_phy_m88:
1558 case e1000_phy_gg82563:
1559 case e1000_phy_bm:
1560 case e1000_phy_82578:
1561 offset = M88E1000_PHY_SPEC_STATUS;
1562 mask = M88E1000_PSSR_DOWNSHIFT;
1563 break;
1564 case e1000_phy_igp_2:
1565 case e1000_phy_igp_3:
1566 offset = IGP01E1000_PHY_LINK_HEALTH;
1567 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1568 break;
1569 default:
1570 /* speed downshift not supported */
1571 phy->speed_downgraded = false;
1572 return 0;
1573 }
1574
1575 ret_val = e1e_rphy(hw, offset, &phy_data);
1576
1577 if (!ret_val)
1578 phy->speed_downgraded = !!(phy_data & mask);
1579
1580 return ret_val;
1581}
1582
1583/**
1584 * e1000_check_polarity_m88 - Checks the polarity.
1585 * @hw: pointer to the HW structure
1586 *
1587 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1588 *
1589 * Polarity is determined based on the PHY specific status register.
1590 **/
1591s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1592{
1593 struct e1000_phy_info *phy = &hw->phy;
1594 s32 ret_val;
1595 u16 data;
1596
1597 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1598
1599 if (!ret_val)
1600 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1601 ? e1000_rev_polarity_reversed
1602 : e1000_rev_polarity_normal);
1603
1604 return ret_val;
1605}
1606
1607/**
1608 * e1000_check_polarity_igp - Checks the polarity.
1609 * @hw: pointer to the HW structure
1610 *
1611 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1612 *
1613 * Polarity is determined based on the PHY port status register, and the
1614 * current speed (since there is no polarity at 100Mbps).
1615 **/
1616s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1617{
1618 struct e1000_phy_info *phy = &hw->phy;
1619 s32 ret_val;
1620 u16 data, offset, mask;
1621
1622 /* Polarity is determined based on the speed of
1623 * our connection.
1624 */
1625 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1626 if (ret_val)
1627 return ret_val;
1628
1629 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1630 IGP01E1000_PSSR_SPEED_1000MBPS) {
1631 offset = IGP01E1000_PHY_PCS_INIT_REG;
1632 mask = IGP01E1000_PHY_POLARITY_MASK;
1633 } else {
1634 /* This really only applies to 10Mbps since
1635 * there is no polarity for 100Mbps (always 0).
1636 */
1637 offset = IGP01E1000_PHY_PORT_STATUS;
1638 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1639 }
1640
1641 ret_val = e1e_rphy(hw, offset, &data);
1642
1643 if (!ret_val)
1644 phy->cable_polarity = ((data & mask)
1645 ? e1000_rev_polarity_reversed
1646 : e1000_rev_polarity_normal);
1647
1648 return ret_val;
1649}
1650
1651/**
1652 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1653 * @hw: pointer to the HW structure
1654 *
1655 * Polarity is determined on the polarity reversal feature being enabled.
1656 **/
1657s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1658{
1659 struct e1000_phy_info *phy = &hw->phy;
1660 s32 ret_val;
1661 u16 phy_data, offset, mask;
1662
1663 /* Polarity is determined based on the reversal feature being enabled.
1664 */
1665 if (phy->polarity_correction) {
1666 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1667 mask = IFE_PESC_POLARITY_REVERSED;
1668 } else {
1669 offset = IFE_PHY_SPECIAL_CONTROL;
1670 mask = IFE_PSC_FORCE_POLARITY;
1671 }
1672
1673 ret_val = e1e_rphy(hw, offset, &phy_data);
1674
1675 if (!ret_val)
1676 phy->cable_polarity = ((phy_data & mask)
1677 ? e1000_rev_polarity_reversed
1678 : e1000_rev_polarity_normal);
1679
1680 return ret_val;
1681}
1682
1683/**
1684 * e1000_wait_autoneg - Wait for auto-neg completion
1685 * @hw: pointer to the HW structure
1686 *
1687 * Waits for auto-negotiation to complete or for the auto-negotiation time
1688 * limit to expire, which ever happens first.
1689 **/
1690static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1691{
1692 s32 ret_val = 0;
1693 u16 i, phy_status;
1694
1695 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1696 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1697 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1698 if (ret_val)
1699 break;
1700 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1701 if (ret_val)
1702 break;
1703 if (phy_status & BMSR_ANEGCOMPLETE)
1704 break;
1705 msleep(100);
1706 }
1707
1708 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1709 * has completed.
1710 */
1711 return ret_val;
1712}
1713
1714/**
1715 * e1000e_phy_has_link_generic - Polls PHY for link
1716 * @hw: pointer to the HW structure
1717 * @iterations: number of times to poll for link
1718 * @usec_interval: delay between polling attempts
1719 * @success: pointer to whether polling was successful or not
1720 *
1721 * Polls the PHY status register for link, 'iterations' number of times.
1722 **/
1723s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1724 u32 usec_interval, bool *success)
1725{
1726 s32 ret_val = 0;
1727 u16 i, phy_status;
1728
1729 *success = false;
1730 for (i = 0; i < iterations; i++) {
1731 /* Some PHYs require the MII_BMSR register to be read
1732 * twice due to the link bit being sticky. No harm doing
1733 * it across the board.
1734 */
1735 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1736 if (ret_val) {
1737 /* If the first read fails, another entity may have
1738 * ownership of the resources, wait and try again to
1739 * see if they have relinquished the resources yet.
1740 */
1741 if (usec_interval >= 1000)
1742 msleep(usec_interval / 1000);
1743 else
1744 udelay(usec_interval);
1745 }
1746 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 if (ret_val)
1748 break;
1749 if (phy_status & BMSR_LSTATUS) {
1750 *success = true;
1751 break;
1752 }
1753 if (usec_interval >= 1000)
1754 msleep(usec_interval / 1000);
1755 else
1756 udelay(usec_interval);
1757 }
1758
1759 return ret_val;
1760}
1761
1762/**
1763 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1764 * @hw: pointer to the HW structure
1765 *
1766 * Reads the PHY specific status register to retrieve the cable length
1767 * information. The cable length is determined by averaging the minimum and
1768 * maximum values to get the "average" cable length. The m88 PHY has four
1769 * possible cable length values, which are:
1770 * Register Value Cable Length
1771 * 0 < 50 meters
1772 * 1 50 - 80 meters
1773 * 2 80 - 110 meters
1774 * 3 110 - 140 meters
1775 * 4 > 140 meters
1776 **/
1777s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1778{
1779 struct e1000_phy_info *phy = &hw->phy;
1780 s32 ret_val;
1781 u16 phy_data, index;
1782
1783 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1784 if (ret_val)
1785 return ret_val;
1786
1787 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1788 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1789
1790 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1791 return -E1000_ERR_PHY;
1792
1793 phy->min_cable_length = e1000_m88_cable_length_table[index];
1794 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1795
1796 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1797
1798 return 0;
1799}
1800
1801/**
1802 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1803 * @hw: pointer to the HW structure
1804 *
1805 * The automatic gain control (agc) normalizes the amplitude of the
1806 * received signal, adjusting for the attenuation produced by the
1807 * cable. By reading the AGC registers, which represent the
1808 * combination of coarse and fine gain value, the value can be put
1809 * into a lookup table to obtain the approximate cable length
1810 * for each channel.
1811 **/
1812s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1813{
1814 struct e1000_phy_info *phy = &hw->phy;
1815 s32 ret_val;
1816 u16 phy_data, i, agc_value = 0;
1817 u16 cur_agc_index, max_agc_index = 0;
1818 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1819 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1820 IGP02E1000_PHY_AGC_A,
1821 IGP02E1000_PHY_AGC_B,
1822 IGP02E1000_PHY_AGC_C,
1823 IGP02E1000_PHY_AGC_D
1824 };
1825
1826 /* Read the AGC registers for all channels */
1827 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1828 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1829 if (ret_val)
1830 return ret_val;
1831
1832 /* Getting bits 15:9, which represent the combination of
1833 * coarse and fine gain values. The result is a number
1834 * that can be put into the lookup table to obtain the
1835 * approximate cable length.
1836 */
1837 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1838 IGP02E1000_AGC_LENGTH_MASK);
1839
1840 /* Array index bound check. */
1841 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1842 (cur_agc_index == 0))
1843 return -E1000_ERR_PHY;
1844
1845 /* Remove min & max AGC values from calculation. */
1846 if (e1000_igp_2_cable_length_table[min_agc_index] >
1847 e1000_igp_2_cable_length_table[cur_agc_index])
1848 min_agc_index = cur_agc_index;
1849 if (e1000_igp_2_cable_length_table[max_agc_index] <
1850 e1000_igp_2_cable_length_table[cur_agc_index])
1851 max_agc_index = cur_agc_index;
1852
1853 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1854 }
1855
1856 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1857 e1000_igp_2_cable_length_table[max_agc_index]);
1858 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1859
1860 /* Calculate cable length with the error range of +/- 10 meters. */
1861 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1862 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1863 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1864
1865 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1866
1867 return 0;
1868}
1869
1870/**
1871 * e1000e_get_phy_info_m88 - Retrieve PHY information
1872 * @hw: pointer to the HW structure
1873 *
1874 * Valid for only copper links. Read the PHY status register (sticky read)
1875 * to verify that link is up. Read the PHY special control register to
1876 * determine the polarity and 10base-T extended distance. Read the PHY
1877 * special status register to determine MDI/MDIx and current speed. If
1878 * speed is 1000, then determine cable length, local and remote receiver.
1879 **/
1880s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1881{
1882 struct e1000_phy_info *phy = &hw->phy;
1883 s32 ret_val;
1884 u16 phy_data;
1885 bool link;
1886
1887 if (phy->media_type != e1000_media_type_copper) {
1888 e_dbg("Phy info is only valid for copper media\n");
1889 return -E1000_ERR_CONFIG;
1890 }
1891
1892 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1893 if (ret_val)
1894 return ret_val;
1895
1896 if (!link) {
1897 e_dbg("Phy info is only valid if link is up\n");
1898 return -E1000_ERR_CONFIG;
1899 }
1900
1901 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1902 if (ret_val)
1903 return ret_val;
1904
1905 phy->polarity_correction = !!(phy_data &
1906 M88E1000_PSCR_POLARITY_REVERSAL);
1907
1908 ret_val = e1000_check_polarity_m88(hw);
1909 if (ret_val)
1910 return ret_val;
1911
1912 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1913 if (ret_val)
1914 return ret_val;
1915
1916 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1917
1918 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1919 ret_val = hw->phy.ops.get_cable_length(hw);
1920 if (ret_val)
1921 return ret_val;
1922
1923 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1924 if (ret_val)
1925 return ret_val;
1926
1927 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1928 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1929
1930 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1931 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1932 } else {
1933 /* Set values to "undefined" */
1934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1935 phy->local_rx = e1000_1000t_rx_status_undefined;
1936 phy->remote_rx = e1000_1000t_rx_status_undefined;
1937 }
1938
1939 return ret_val;
1940}
1941
1942/**
1943 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1944 * @hw: pointer to the HW structure
1945 *
1946 * Read PHY status to determine if link is up. If link is up, then
1947 * set/determine 10base-T extended distance and polarity correction. Read
1948 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1949 * determine on the cable length, local and remote receiver.
1950 **/
1951s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1952{
1953 struct e1000_phy_info *phy = &hw->phy;
1954 s32 ret_val;
1955 u16 data;
1956 bool link;
1957
1958 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1959 if (ret_val)
1960 return ret_val;
1961
1962 if (!link) {
1963 e_dbg("Phy info is only valid if link is up\n");
1964 return -E1000_ERR_CONFIG;
1965 }
1966
1967 phy->polarity_correction = true;
1968
1969 ret_val = e1000_check_polarity_igp(hw);
1970 if (ret_val)
1971 return ret_val;
1972
1973 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1978
1979 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1980 IGP01E1000_PSSR_SPEED_1000MBPS) {
1981 ret_val = phy->ops.get_cable_length(hw);
1982 if (ret_val)
1983 return ret_val;
1984
1985 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1986 if (ret_val)
1987 return ret_val;
1988
1989 phy->local_rx = (data & LPA_1000LOCALRXOK)
1990 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1991
1992 phy->remote_rx = (data & LPA_1000REMRXOK)
1993 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1994 } else {
1995 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1996 phy->local_rx = e1000_1000t_rx_status_undefined;
1997 phy->remote_rx = e1000_1000t_rx_status_undefined;
1998 }
1999
2000 return ret_val;
2001}
2002
2003/**
2004 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2005 * @hw: pointer to the HW structure
2006 *
2007 * Populates "phy" structure with various feature states.
2008 **/
2009s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2010{
2011 struct e1000_phy_info *phy = &hw->phy;
2012 s32 ret_val;
2013 u16 data;
2014 bool link;
2015
2016 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2017 if (ret_val)
2018 return ret_val;
2019
2020 if (!link) {
2021 e_dbg("Phy info is only valid if link is up\n");
2022 return -E1000_ERR_CONFIG;
2023 }
2024
2025 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2026 if (ret_val)
2027 return ret_val;
2028 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2029
2030 if (phy->polarity_correction) {
2031 ret_val = e1000_check_polarity_ife(hw);
2032 if (ret_val)
2033 return ret_val;
2034 } else {
2035 /* Polarity is forced */
2036 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2037 ? e1000_rev_polarity_reversed
2038 : e1000_rev_polarity_normal);
2039 }
2040
2041 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2042 if (ret_val)
2043 return ret_val;
2044
2045 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2046
2047 /* The following parameters are undefined for 10/100 operation. */
2048 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2049 phy->local_rx = e1000_1000t_rx_status_undefined;
2050 phy->remote_rx = e1000_1000t_rx_status_undefined;
2051
2052 return 0;
2053}
2054
2055/**
2056 * e1000e_phy_sw_reset - PHY software reset
2057 * @hw: pointer to the HW structure
2058 *
2059 * Does a software reset of the PHY by reading the PHY control register and
2060 * setting/write the control register reset bit to the PHY.
2061 **/
2062s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2063{
2064 s32 ret_val;
2065 u16 phy_ctrl;
2066
2067 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2068 if (ret_val)
2069 return ret_val;
2070
2071 phy_ctrl |= BMCR_RESET;
2072 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2073 if (ret_val)
2074 return ret_val;
2075
2076 udelay(1);
2077
2078 return ret_val;
2079}
2080
2081/**
2082 * e1000e_phy_hw_reset_generic - PHY hardware reset
2083 * @hw: pointer to the HW structure
2084 *
2085 * Verify the reset block is not blocking us from resetting. Acquire
2086 * semaphore (if necessary) and read/set/write the device control reset
2087 * bit in the PHY. Wait the appropriate delay time for the device to
2088 * reset and release the semaphore (if necessary).
2089 **/
2090s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2091{
2092 struct e1000_phy_info *phy = &hw->phy;
2093 s32 ret_val;
2094 u32 ctrl;
2095
2096 if (phy->ops.check_reset_block) {
2097 ret_val = phy->ops.check_reset_block(hw);
2098 if (ret_val)
2099 return 0;
2100 }
2101
2102 ret_val = phy->ops.acquire(hw);
2103 if (ret_val)
2104 return ret_val;
2105
2106 ctrl = er32(CTRL);
2107 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2108 e1e_flush();
2109
2110 udelay(phy->reset_delay_us);
2111
2112 ew32(CTRL, ctrl);
2113 e1e_flush();
2114
2115 usleep_range(150, 300);
2116
2117 phy->ops.release(hw);
2118
2119 return phy->ops.get_cfg_done(hw);
2120}
2121
2122/**
2123 * e1000e_get_cfg_done_generic - Generic configuration done
2124 * @hw: pointer to the HW structure
2125 *
2126 * Generic function to wait 10 milli-seconds for configuration to complete
2127 * and return success.
2128 **/
2129s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2130{
2131 mdelay(10);
2132
2133 return 0;
2134}
2135
2136/**
2137 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2138 * @hw: pointer to the HW structure
2139 *
2140 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2141 **/
2142s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2143{
2144 e_dbg("Running IGP 3 PHY init script\n");
2145
2146 /* PHY init IGP 3 */
2147 /* Enable rise/fall, 10-mode work in class-A */
2148 e1e_wphy(hw, 0x2F5B, 0x9018);
2149 /* Remove all caps from Replica path filter */
2150 e1e_wphy(hw, 0x2F52, 0x0000);
2151 /* Bias trimming for ADC, AFE and Driver (Default) */
2152 e1e_wphy(hw, 0x2FB1, 0x8B24);
2153 /* Increase Hybrid poly bias */
2154 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2155 /* Add 4% to Tx amplitude in Gig mode */
2156 e1e_wphy(hw, 0x2010, 0x10B0);
2157 /* Disable trimming (TTT) */
2158 e1e_wphy(hw, 0x2011, 0x0000);
2159 /* Poly DC correction to 94.6% + 2% for all channels */
2160 e1e_wphy(hw, 0x20DD, 0x249A);
2161 /* ABS DC correction to 95.9% */
2162 e1e_wphy(hw, 0x20DE, 0x00D3);
2163 /* BG temp curve trim */
2164 e1e_wphy(hw, 0x28B4, 0x04CE);
2165 /* Increasing ADC OPAMP stage 1 currents to max */
2166 e1e_wphy(hw, 0x2F70, 0x29E4);
2167 /* Force 1000 ( required for enabling PHY regs configuration) */
2168 e1e_wphy(hw, 0x0000, 0x0140);
2169 /* Set upd_freq to 6 */
2170 e1e_wphy(hw, 0x1F30, 0x1606);
2171 /* Disable NPDFE */
2172 e1e_wphy(hw, 0x1F31, 0xB814);
2173 /* Disable adaptive fixed FFE (Default) */
2174 e1e_wphy(hw, 0x1F35, 0x002A);
2175 /* Enable FFE hysteresis */
2176 e1e_wphy(hw, 0x1F3E, 0x0067);
2177 /* Fixed FFE for short cable lengths */
2178 e1e_wphy(hw, 0x1F54, 0x0065);
2179 /* Fixed FFE for medium cable lengths */
2180 e1e_wphy(hw, 0x1F55, 0x002A);
2181 /* Fixed FFE for long cable lengths */
2182 e1e_wphy(hw, 0x1F56, 0x002A);
2183 /* Enable Adaptive Clip Threshold */
2184 e1e_wphy(hw, 0x1F72, 0x3FB0);
2185 /* AHT reset limit to 1 */
2186 e1e_wphy(hw, 0x1F76, 0xC0FF);
2187 /* Set AHT master delay to 127 msec */
2188 e1e_wphy(hw, 0x1F77, 0x1DEC);
2189 /* Set scan bits for AHT */
2190 e1e_wphy(hw, 0x1F78, 0xF9EF);
2191 /* Set AHT Preset bits */
2192 e1e_wphy(hw, 0x1F79, 0x0210);
2193 /* Change integ_factor of channel A to 3 */
2194 e1e_wphy(hw, 0x1895, 0x0003);
2195 /* Change prop_factor of channels BCD to 8 */
2196 e1e_wphy(hw, 0x1796, 0x0008);
2197 /* Change cg_icount + enable integbp for channels BCD */
2198 e1e_wphy(hw, 0x1798, 0xD008);
2199 /* Change cg_icount + enable integbp + change prop_factor_master
2200 * to 8 for channel A
2201 */
2202 e1e_wphy(hw, 0x1898, 0xD918);
2203 /* Disable AHT in Slave mode on channel A */
2204 e1e_wphy(hw, 0x187A, 0x0800);
2205 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2206 * Enable SPD+B2B
2207 */
2208 e1e_wphy(hw, 0x0019, 0x008D);
2209 /* Enable restart AN on an1000_dis change */
2210 e1e_wphy(hw, 0x001B, 0x2080);
2211 /* Enable wh_fifo read clock in 10/100 modes */
2212 e1e_wphy(hw, 0x0014, 0x0045);
2213 /* Restart AN, Speed selection is 1000 */
2214 e1e_wphy(hw, 0x0000, 0x1340);
2215
2216 return 0;
2217}
2218
2219/**
2220 * e1000e_get_phy_type_from_id - Get PHY type from id
2221 * @phy_id: phy_id read from the phy
2222 *
2223 * Returns the phy type from the id.
2224 **/
2225enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2226{
2227 enum e1000_phy_type phy_type = e1000_phy_unknown;
2228
2229 switch (phy_id) {
2230 case M88E1000_I_PHY_ID:
2231 case M88E1000_E_PHY_ID:
2232 case M88E1111_I_PHY_ID:
2233 case M88E1011_I_PHY_ID:
2234 phy_type = e1000_phy_m88;
2235 break;
2236 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2237 phy_type = e1000_phy_igp_2;
2238 break;
2239 case GG82563_E_PHY_ID:
2240 phy_type = e1000_phy_gg82563;
2241 break;
2242 case IGP03E1000_E_PHY_ID:
2243 phy_type = e1000_phy_igp_3;
2244 break;
2245 case IFE_E_PHY_ID:
2246 case IFE_PLUS_E_PHY_ID:
2247 case IFE_C_E_PHY_ID:
2248 phy_type = e1000_phy_ife;
2249 break;
2250 case BME1000_E_PHY_ID:
2251 case BME1000_E_PHY_ID_R2:
2252 phy_type = e1000_phy_bm;
2253 break;
2254 case I82578_E_PHY_ID:
2255 phy_type = e1000_phy_82578;
2256 break;
2257 case I82577_E_PHY_ID:
2258 phy_type = e1000_phy_82577;
2259 break;
2260 case I82579_E_PHY_ID:
2261 phy_type = e1000_phy_82579;
2262 break;
2263 case I217_E_PHY_ID:
2264 phy_type = e1000_phy_i217;
2265 break;
2266 default:
2267 phy_type = e1000_phy_unknown;
2268 break;
2269 }
2270 return phy_type;
2271}
2272
2273/**
2274 * e1000e_determine_phy_address - Determines PHY address.
2275 * @hw: pointer to the HW structure
2276 *
2277 * This uses a trial and error method to loop through possible PHY
2278 * addresses. It tests each by reading the PHY ID registers and
2279 * checking for a match.
2280 **/
2281s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2282{
2283 u32 phy_addr = 0;
2284 u32 i;
2285 enum e1000_phy_type phy_type = e1000_phy_unknown;
2286
2287 hw->phy.id = phy_type;
2288
2289 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2290 hw->phy.addr = phy_addr;
2291 i = 0;
2292
2293 do {
2294 e1000e_get_phy_id(hw);
2295 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2296
2297 /* If phy_type is valid, break - we found our
2298 * PHY address
2299 */
2300 if (phy_type != e1000_phy_unknown)
2301 return 0;
2302
2303 usleep_range(1000, 2000);
2304 i++;
2305 } while (i < 10);
2306 }
2307
2308 return -E1000_ERR_PHY_TYPE;
2309}
2310
2311/**
2312 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2313 * @page: page to access
2314 * @reg: register to check
2315 *
2316 * Returns the phy address for the page requested.
2317 **/
2318static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2319{
2320 u32 phy_addr = 2;
2321
2322 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2323 phy_addr = 1;
2324
2325 return phy_addr;
2326}
2327
2328/**
2329 * e1000e_write_phy_reg_bm - Write BM PHY register
2330 * @hw: pointer to the HW structure
2331 * @offset: register offset to write to
2332 * @data: data to write at register offset
2333 *
2334 * Acquires semaphore, if necessary, then writes the data to PHY register
2335 * at the offset. Release any acquired semaphores before exiting.
2336 **/
2337s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2338{
2339 s32 ret_val;
2340 u32 page = offset >> IGP_PAGE_SHIFT;
2341
2342 ret_val = hw->phy.ops.acquire(hw);
2343 if (ret_val)
2344 return ret_val;
2345
2346 /* Page 800 works differently than the rest so it has its own func */
2347 if (page == BM_WUC_PAGE) {
2348 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2349 false, false);
2350 goto release;
2351 }
2352
2353 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2354
2355 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2356 u32 page_shift, page_select;
2357
2358 /* Page select is register 31 for phy address 1 and 22 for
2359 * phy address 2 and 3. Page select is shifted only for
2360 * phy address 1.
2361 */
2362 if (hw->phy.addr == 1) {
2363 page_shift = IGP_PAGE_SHIFT;
2364 page_select = IGP01E1000_PHY_PAGE_SELECT;
2365 } else {
2366 page_shift = 0;
2367 page_select = BM_PHY_PAGE_SELECT;
2368 }
2369
2370 /* Page is shifted left, PHY expects (page x 32) */
2371 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2372 (page << page_shift));
2373 if (ret_val)
2374 goto release;
2375 }
2376
2377 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2378 data);
2379
2380release:
2381 hw->phy.ops.release(hw);
2382 return ret_val;
2383}
2384
2385/**
2386 * e1000e_read_phy_reg_bm - Read BM PHY register
2387 * @hw: pointer to the HW structure
2388 * @offset: register offset to be read
2389 * @data: pointer to the read data
2390 *
2391 * Acquires semaphore, if necessary, then reads the PHY register at offset
2392 * and storing the retrieved information in data. Release any acquired
2393 * semaphores before exiting.
2394 **/
2395s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2396{
2397 s32 ret_val;
2398 u32 page = offset >> IGP_PAGE_SHIFT;
2399
2400 ret_val = hw->phy.ops.acquire(hw);
2401 if (ret_val)
2402 return ret_val;
2403
2404 /* Page 800 works differently than the rest so it has its own func */
2405 if (page == BM_WUC_PAGE) {
2406 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2407 true, false);
2408 goto release;
2409 }
2410
2411 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2412
2413 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2414 u32 page_shift, page_select;
2415
2416 /* Page select is register 31 for phy address 1 and 22 for
2417 * phy address 2 and 3. Page select is shifted only for
2418 * phy address 1.
2419 */
2420 if (hw->phy.addr == 1) {
2421 page_shift = IGP_PAGE_SHIFT;
2422 page_select = IGP01E1000_PHY_PAGE_SELECT;
2423 } else {
2424 page_shift = 0;
2425 page_select = BM_PHY_PAGE_SELECT;
2426 }
2427
2428 /* Page is shifted left, PHY expects (page x 32) */
2429 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2430 (page << page_shift));
2431 if (ret_val)
2432 goto release;
2433 }
2434
2435 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2436 data);
2437release:
2438 hw->phy.ops.release(hw);
2439 return ret_val;
2440}
2441
2442/**
2443 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2444 * @hw: pointer to the HW structure
2445 * @offset: register offset to be read
2446 * @data: pointer to the read data
2447 *
2448 * Acquires semaphore, if necessary, then reads the PHY register at offset
2449 * and storing the retrieved information in data. Release any acquired
2450 * semaphores before exiting.
2451 **/
2452s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2453{
2454 s32 ret_val;
2455 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2456
2457 ret_val = hw->phy.ops.acquire(hw);
2458 if (ret_val)
2459 return ret_val;
2460
2461 /* Page 800 works differently than the rest so it has its own func */
2462 if (page == BM_WUC_PAGE) {
2463 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2464 true, false);
2465 goto release;
2466 }
2467
2468 hw->phy.addr = 1;
2469
2470 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2471 /* Page is shifted left, PHY expects (page x 32) */
2472 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2473 page);
2474
2475 if (ret_val)
2476 goto release;
2477 }
2478
2479 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2480 data);
2481release:
2482 hw->phy.ops.release(hw);
2483 return ret_val;
2484}
2485
2486/**
2487 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2488 * @hw: pointer to the HW structure
2489 * @offset: register offset to write to
2490 * @data: data to write at register offset
2491 *
2492 * Acquires semaphore, if necessary, then writes the data to PHY register
2493 * at the offset. Release any acquired semaphores before exiting.
2494 **/
2495s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2496{
2497 s32 ret_val;
2498 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2499
2500 ret_val = hw->phy.ops.acquire(hw);
2501 if (ret_val)
2502 return ret_val;
2503
2504 /* Page 800 works differently than the rest so it has its own func */
2505 if (page == BM_WUC_PAGE) {
2506 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2507 false, false);
2508 goto release;
2509 }
2510
2511 hw->phy.addr = 1;
2512
2513 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2514 /* Page is shifted left, PHY expects (page x 32) */
2515 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2516 page);
2517
2518 if (ret_val)
2519 goto release;
2520 }
2521
2522 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2523 data);
2524
2525release:
2526 hw->phy.ops.release(hw);
2527 return ret_val;
2528}
2529
2530/**
2531 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2532 * @hw: pointer to the HW structure
2533 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2534 *
2535 * Assumes semaphore already acquired and phy_reg points to a valid memory
2536 * address to store contents of the BM_WUC_ENABLE_REG register.
2537 **/
2538s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2539{
2540 s32 ret_val;
2541 u16 temp;
2542
2543 /* All page select, port ctrl and wakeup registers use phy address 1 */
2544 hw->phy.addr = 1;
2545
2546 /* Select Port Control Registers page */
2547 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2548 if (ret_val) {
2549 e_dbg("Could not set Port Control page\n");
2550 return ret_val;
2551 }
2552
2553 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2554 if (ret_val) {
2555 e_dbg("Could not read PHY register %d.%d\n",
2556 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2557 return ret_val;
2558 }
2559
2560 /* Enable both PHY wakeup mode and Wakeup register page writes.
2561 * Prevent a power state change by disabling ME and Host PHY wakeup.
2562 */
2563 temp = *phy_reg;
2564 temp |= BM_WUC_ENABLE_BIT;
2565 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2566
2567 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2568 if (ret_val) {
2569 e_dbg("Could not write PHY register %d.%d\n",
2570 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2571 return ret_val;
2572 }
2573
2574 /* Select Host Wakeup Registers page - caller now able to write
2575 * registers on the Wakeup registers page
2576 */
2577 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2578}
2579
2580/**
2581 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2582 * @hw: pointer to the HW structure
2583 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2584 *
2585 * Restore BM_WUC_ENABLE_REG to its original value.
2586 *
2587 * Assumes semaphore already acquired and *phy_reg is the contents of the
2588 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2589 * caller.
2590 **/
2591s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2592{
2593 s32 ret_val;
2594
2595 /* Select Port Control Registers page */
2596 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2597 if (ret_val) {
2598 e_dbg("Could not set Port Control page\n");
2599 return ret_val;
2600 }
2601
2602 /* Restore 769.17 to its original value */
2603 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2604 if (ret_val)
2605 e_dbg("Could not restore PHY register %d.%d\n",
2606 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2607
2608 return ret_val;
2609}
2610
2611/**
2612 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2613 * @hw: pointer to the HW structure
2614 * @offset: register offset to be read or written
2615 * @data: pointer to the data to read or write
2616 * @read: determines if operation is read or write
2617 * @page_set: BM_WUC_PAGE already set and access enabled
2618 *
2619 * Read the PHY register at offset and store the retrieved information in
2620 * data, or write data to PHY register at offset. Note the procedure to
2621 * access the PHY wakeup registers is different than reading the other PHY
2622 * registers. It works as such:
2623 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2624 * 2) Set page to 800 for host (801 if we were manageability)
2625 * 3) Write the address using the address opcode (0x11)
2626 * 4) Read or write the data using the data opcode (0x12)
2627 * 5) Restore 769.17.2 to its original value
2628 *
2629 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2630 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2631 *
2632 * Assumes semaphore is already acquired. When page_set==true, assumes
2633 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2634 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2635 **/
2636static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2637 u16 *data, bool read, bool page_set)
2638{
2639 s32 ret_val;
2640 u16 reg = BM_PHY_REG_NUM(offset);
2641 u16 page = BM_PHY_REG_PAGE(offset);
2642 u16 phy_reg = 0;
2643
2644 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2645 if ((hw->mac.type == e1000_pchlan) &&
2646 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2647 e_dbg("Attempting to access page %d while gig enabled.\n",
2648 page);
2649
2650 if (!page_set) {
2651 /* Enable access to PHY wakeup registers */
2652 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2653 if (ret_val) {
2654 e_dbg("Could not enable PHY wakeup reg access\n");
2655 return ret_val;
2656 }
2657 }
2658
2659 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2660
2661 /* Write the Wakeup register page offset value using opcode 0x11 */
2662 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2663 if (ret_val) {
2664 e_dbg("Could not write address opcode to page %d\n", page);
2665 return ret_val;
2666 }
2667
2668 if (read) {
2669 /* Read the Wakeup register page value using opcode 0x12 */
2670 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2671 data);
2672 } else {
2673 /* Write the Wakeup register page value using opcode 0x12 */
2674 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2675 *data);
2676 }
2677
2678 if (ret_val) {
2679 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2680 return ret_val;
2681 }
2682
2683 if (!page_set)
2684 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2685
2686 return ret_val;
2687}
2688
2689/**
2690 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2691 * @hw: pointer to the HW structure
2692 *
2693 * In the case of a PHY power down to save power, or to turn off link during a
2694 * driver unload, or wake on lan is not enabled, restore the link to previous
2695 * settings.
2696 **/
2697void e1000_power_up_phy_copper(struct e1000_hw *hw)
2698{
2699 u16 mii_reg = 0;
2700 int ret;
2701
2702 /* The PHY will retain its settings across a power down/up cycle */
2703 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2704 if (ret) {
2705 e_dbg("Error reading PHY register\n");
2706 return;
2707 }
2708 mii_reg &= ~BMCR_PDOWN;
2709 e1e_wphy(hw, MII_BMCR, mii_reg);
2710}
2711
2712/**
2713 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2714 * @hw: pointer to the HW structure
2715 *
2716 * In the case of a PHY power down to save power, or to turn off link during a
2717 * driver unload, or wake on lan is not enabled, restore the link to previous
2718 * settings.
2719 **/
2720void e1000_power_down_phy_copper(struct e1000_hw *hw)
2721{
2722 u16 mii_reg = 0;
2723 int ret;
2724
2725 /* The PHY will retain its settings across a power down/up cycle */
2726 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2727 if (ret) {
2728 e_dbg("Error reading PHY register\n");
2729 return;
2730 }
2731 mii_reg |= BMCR_PDOWN;
2732 e1e_wphy(hw, MII_BMCR, mii_reg);
2733 usleep_range(1000, 2000);
2734}
2735
2736/**
2737 * __e1000_read_phy_reg_hv - Read HV PHY register
2738 * @hw: pointer to the HW structure
2739 * @offset: register offset to be read
2740 * @data: pointer to the read data
2741 * @locked: semaphore has already been acquired or not
2742 * @page_set: BM_WUC_PAGE already set and access enabled
2743 *
2744 * Acquires semaphore, if necessary, then reads the PHY register at offset
2745 * and stores the retrieved information in data. Release any acquired
2746 * semaphore before exiting.
2747 **/
2748static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2749 bool locked, bool page_set)
2750{
2751 s32 ret_val;
2752 u16 page = BM_PHY_REG_PAGE(offset);
2753 u16 reg = BM_PHY_REG_NUM(offset);
2754 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2755
2756 if (!locked) {
2757 ret_val = hw->phy.ops.acquire(hw);
2758 if (ret_val)
2759 return ret_val;
2760 }
2761
2762 /* Page 800 works differently than the rest so it has its own func */
2763 if (page == BM_WUC_PAGE) {
2764 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2765 true, page_set);
2766 goto out;
2767 }
2768
2769 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2770 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2771 data, true);
2772 goto out;
2773 }
2774
2775 if (!page_set) {
2776 if (page == HV_INTC_FC_PAGE_START)
2777 page = 0;
2778
2779 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2780 /* Page is shifted left, PHY expects (page x 32) */
2781 ret_val = e1000_set_page_igp(hw,
2782 (page << IGP_PAGE_SHIFT));
2783
2784 hw->phy.addr = phy_addr;
2785
2786 if (ret_val)
2787 goto out;
2788 }
2789 }
2790
2791 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2792 page << IGP_PAGE_SHIFT, reg);
2793
2794 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2795out:
2796 if (!locked)
2797 hw->phy.ops.release(hw);
2798
2799 return ret_val;
2800}
2801
2802/**
2803 * e1000_read_phy_reg_hv - Read HV PHY register
2804 * @hw: pointer to the HW structure
2805 * @offset: register offset to be read
2806 * @data: pointer to the read data
2807 *
2808 * Acquires semaphore then reads the PHY register at offset and stores
2809 * the retrieved information in data. Release the acquired semaphore
2810 * before exiting.
2811 **/
2812s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2813{
2814 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2815}
2816
2817/**
2818 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2819 * @hw: pointer to the HW structure
2820 * @offset: register offset to be read
2821 * @data: pointer to the read data
2822 *
2823 * Reads the PHY register at offset and stores the retrieved information
2824 * in data. Assumes semaphore already acquired.
2825 **/
2826s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2827{
2828 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2829}
2830
2831/**
2832 * e1000_read_phy_reg_page_hv - Read HV PHY register
2833 * @hw: pointer to the HW structure
2834 * @offset: register offset to write to
2835 * @data: data to write at register offset
2836 *
2837 * Reads the PHY register at offset and stores the retrieved information
2838 * in data. Assumes semaphore already acquired and page already set.
2839 **/
2840s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2841{
2842 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2843}
2844
2845/**
2846 * __e1000_write_phy_reg_hv - Write HV PHY register
2847 * @hw: pointer to the HW structure
2848 * @offset: register offset to write to
2849 * @data: data to write at register offset
2850 * @locked: semaphore has already been acquired or not
2851 * @page_set: BM_WUC_PAGE already set and access enabled
2852 *
2853 * Acquires semaphore, if necessary, then writes the data to PHY register
2854 * at the offset. Release any acquired semaphores before exiting.
2855 **/
2856static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2857 bool locked, bool page_set)
2858{
2859 s32 ret_val;
2860 u16 page = BM_PHY_REG_PAGE(offset);
2861 u16 reg = BM_PHY_REG_NUM(offset);
2862 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2863
2864 if (!locked) {
2865 ret_val = hw->phy.ops.acquire(hw);
2866 if (ret_val)
2867 return ret_val;
2868 }
2869
2870 /* Page 800 works differently than the rest so it has its own func */
2871 if (page == BM_WUC_PAGE) {
2872 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2873 false, page_set);
2874 goto out;
2875 }
2876
2877 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2878 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2879 &data, false);
2880 goto out;
2881 }
2882
2883 if (!page_set) {
2884 if (page == HV_INTC_FC_PAGE_START)
2885 page = 0;
2886
2887 /* Workaround MDIO accesses being disabled after entering IEEE
2888 * Power Down (when bit 11 of the PHY Control register is set)
2889 */
2890 if ((hw->phy.type == e1000_phy_82578) &&
2891 (hw->phy.revision >= 1) &&
2892 (hw->phy.addr == 2) &&
2893 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2894 u16 data2 = 0x7EFF;
2895
2896 ret_val = e1000_access_phy_debug_regs_hv(hw,
2897 BIT(6) | 0x3,
2898 &data2, false);
2899 if (ret_val)
2900 goto out;
2901 }
2902
2903 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2904 /* Page is shifted left, PHY expects (page x 32) */
2905 ret_val = e1000_set_page_igp(hw,
2906 (page << IGP_PAGE_SHIFT));
2907
2908 hw->phy.addr = phy_addr;
2909
2910 if (ret_val)
2911 goto out;
2912 }
2913 }
2914
2915 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2916 page << IGP_PAGE_SHIFT, reg);
2917
2918 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2919 data);
2920
2921out:
2922 if (!locked)
2923 hw->phy.ops.release(hw);
2924
2925 return ret_val;
2926}
2927
2928/**
2929 * e1000_write_phy_reg_hv - Write HV PHY register
2930 * @hw: pointer to the HW structure
2931 * @offset: register offset to write to
2932 * @data: data to write at register offset
2933 *
2934 * Acquires semaphore then writes the data to PHY register at the offset.
2935 * Release the acquired semaphores before exiting.
2936 **/
2937s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2938{
2939 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2940}
2941
2942/**
2943 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2944 * @hw: pointer to the HW structure
2945 * @offset: register offset to write to
2946 * @data: data to write at register offset
2947 *
2948 * Writes the data to PHY register at the offset. Assumes semaphore
2949 * already acquired.
2950 **/
2951s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2952{
2953 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2954}
2955
2956/**
2957 * e1000_write_phy_reg_page_hv - Write HV PHY register
2958 * @hw: pointer to the HW structure
2959 * @offset: register offset to write to
2960 * @data: data to write at register offset
2961 *
2962 * Writes the data to PHY register at the offset. Assumes semaphore
2963 * already acquired and page already set.
2964 **/
2965s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2966{
2967 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2968}
2969
2970/**
2971 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2972 * @page: page to be accessed
2973 **/
2974static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2975{
2976 u32 phy_addr = 2;
2977
2978 if (page >= HV_INTC_FC_PAGE_START)
2979 phy_addr = 1;
2980
2981 return phy_addr;
2982}
2983
2984/**
2985 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2986 * @hw: pointer to the HW structure
2987 * @offset: register offset to be read or written
2988 * @data: pointer to the data to be read or written
2989 * @read: determines if operation is read or write
2990 *
2991 * Reads the PHY register at offset and stores the retrieved information
2992 * in data. Assumes semaphore already acquired. Note that the procedure
2993 * to access these regs uses the address port and data port to read/write.
2994 * These accesses done with PHY address 2 and without using pages.
2995 **/
2996static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2997 u16 *data, bool read)
2998{
2999 s32 ret_val;
3000 u32 addr_reg;
3001 u32 data_reg;
3002
3003 /* This takes care of the difference with desktop vs mobile phy */
3004 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3005 I82578_ADDR_REG : I82577_ADDR_REG);
3006 data_reg = addr_reg + 1;
3007
3008 /* All operations in this function are phy address 2 */
3009 hw->phy.addr = 2;
3010
3011 /* masking with 0x3F to remove the page from offset */
3012 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3013 if (ret_val) {
3014 e_dbg("Could not write the Address Offset port register\n");
3015 return ret_val;
3016 }
3017
3018 /* Read or write the data value next */
3019 if (read)
3020 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3021 else
3022 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3023
3024 if (ret_val)
3025 e_dbg("Could not access the Data port register\n");
3026
3027 return ret_val;
3028}
3029
3030/**
3031 * e1000_link_stall_workaround_hv - Si workaround
3032 * @hw: pointer to the HW structure
3033 *
3034 * This function works around a Si bug where the link partner can get
3035 * a link up indication before the PHY does. If small packets are sent
3036 * by the link partner they can be placed in the packet buffer without
3037 * being properly accounted for by the PHY and will stall preventing
3038 * further packets from being received. The workaround is to clear the
3039 * packet buffer after the PHY detects link up.
3040 **/
3041s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3042{
3043 s32 ret_val = 0;
3044 u16 data;
3045
3046 if (hw->phy.type != e1000_phy_82578)
3047 return 0;
3048
3049 /* Do not apply workaround if in PHY loopback bit 14 set */
3050 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3051 if (ret_val) {
3052 e_dbg("Error reading PHY register\n");
3053 return ret_val;
3054 }
3055 if (data & BMCR_LOOPBACK)
3056 return 0;
3057
3058 /* check if link is up and at 1Gbps */
3059 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3060 if (ret_val)
3061 return ret_val;
3062
3063 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3064 BM_CS_STATUS_SPEED_MASK);
3065
3066 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3067 BM_CS_STATUS_SPEED_1000))
3068 return 0;
3069
3070 msleep(200);
3071
3072 /* flush the packets in the fifo buffer */
3073 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3074 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3075 HV_MUX_DATA_CTRL_FORCE_SPEED));
3076 if (ret_val)
3077 return ret_val;
3078
3079 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3080}
3081
3082/**
3083 * e1000_check_polarity_82577 - Checks the polarity.
3084 * @hw: pointer to the HW structure
3085 *
3086 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3087 *
3088 * Polarity is determined based on the PHY specific status register.
3089 **/
3090s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3091{
3092 struct e1000_phy_info *phy = &hw->phy;
3093 s32 ret_val;
3094 u16 data;
3095
3096 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3097
3098 if (!ret_val)
3099 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3100 ? e1000_rev_polarity_reversed
3101 : e1000_rev_polarity_normal);
3102
3103 return ret_val;
3104}
3105
3106/**
3107 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3108 * @hw: pointer to the HW structure
3109 *
3110 * Calls the PHY setup function to force speed and duplex.
3111 **/
3112s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3113{
3114 struct e1000_phy_info *phy = &hw->phy;
3115 s32 ret_val;
3116 u16 phy_data;
3117 bool link;
3118
3119 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3120 if (ret_val)
3121 return ret_val;
3122
3123 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3124
3125 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3126 if (ret_val)
3127 return ret_val;
3128
3129 udelay(1);
3130
3131 if (phy->autoneg_wait_to_complete) {
3132 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3133
3134 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3135 100000, &link);
3136 if (ret_val)
3137 return ret_val;
3138
3139 if (!link)
3140 e_dbg("Link taking longer than expected.\n");
3141
3142 /* Try once more */
3143 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3144 100000, &link);
3145 }
3146
3147 return ret_val;
3148}
3149
3150/**
3151 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3152 * @hw: pointer to the HW structure
3153 *
3154 * Read PHY status to determine if link is up. If link is up, then
3155 * set/determine 10base-T extended distance and polarity correction. Read
3156 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3157 * determine on the cable length, local and remote receiver.
3158 **/
3159s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3160{
3161 struct e1000_phy_info *phy = &hw->phy;
3162 s32 ret_val;
3163 u16 data;
3164 bool link;
3165
3166 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3167 if (ret_val)
3168 return ret_val;
3169
3170 if (!link) {
3171 e_dbg("Phy info is only valid if link is up\n");
3172 return -E1000_ERR_CONFIG;
3173 }
3174
3175 phy->polarity_correction = true;
3176
3177 ret_val = e1000_check_polarity_82577(hw);
3178 if (ret_val)
3179 return ret_val;
3180
3181 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3182 if (ret_val)
3183 return ret_val;
3184
3185 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3186
3187 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3188 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3189 ret_val = hw->phy.ops.get_cable_length(hw);
3190 if (ret_val)
3191 return ret_val;
3192
3193 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3194 if (ret_val)
3195 return ret_val;
3196
3197 phy->local_rx = (data & LPA_1000LOCALRXOK)
3198 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3199
3200 phy->remote_rx = (data & LPA_1000REMRXOK)
3201 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3202 } else {
3203 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3204 phy->local_rx = e1000_1000t_rx_status_undefined;
3205 phy->remote_rx = e1000_1000t_rx_status_undefined;
3206 }
3207
3208 return 0;
3209}
3210
3211/**
3212 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3213 * @hw: pointer to the HW structure
3214 *
3215 * Reads the diagnostic status register and verifies result is valid before
3216 * placing it in the phy_cable_length field.
3217 **/
3218s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3219{
3220 struct e1000_phy_info *phy = &hw->phy;
3221 s32 ret_val;
3222 u16 phy_data, length;
3223
3224 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3225 if (ret_val)
3226 return ret_val;
3227
3228 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3229 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3230
3231 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3232 return -E1000_ERR_PHY;
3233
3234 phy->cable_length = length;
3235
3236 return 0;
3237}