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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5#include <linux/ethtool.h>
6
7static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14/* Cable length tables */
15static const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17};
18
19#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 ARRAY_SIZE(e1000_m88_cable_length_table)
21
22static const u16 e1000_igp_2_cable_length_table[] = {
23 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 124
31};
32
33#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 ARRAY_SIZE(e1000_igp_2_cable_length_table)
35
36/**
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
39 *
40 * Read the PHY management control register and check whether a PHY reset
41 * is blocked. If a reset is not blocked return 0, otherwise
42 * return E1000_BLK_PHY_RESET (12).
43 **/
44s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45{
46 u32 manc;
47
48 manc = er32(MANC);
49
50 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51}
52
53/**
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
56 *
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
58 * revision in the hardware structure.
59 **/
60s32 e1000e_get_phy_id(struct e1000_hw *hw)
61{
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = 0;
64 u16 phy_id;
65 u16 retry_count = 0;
66
67 if (!phy->ops.read_reg)
68 return 0;
69
70 while (retry_count < 2) {
71 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 if (ret_val)
73 return ret_val;
74
75 phy->id = (u32)(phy_id << 16);
76 usleep_range(20, 40);
77 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 if (ret_val)
79 return ret_val;
80
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 return 0;
86
87 retry_count++;
88 }
89
90 return 0;
91}
92
93/**
94 * e1000e_phy_reset_dsp - Reset PHY DSP
95 * @hw: pointer to the HW structure
96 *
97 * Reset the digital signal processor.
98 **/
99s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100{
101 s32 ret_val;
102
103 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 if (ret_val)
105 return ret_val;
106
107 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108}
109
110void e1000e_disable_phy_retry(struct e1000_hw *hw)
111{
112 hw->phy.retry_enabled = false;
113}
114
115void e1000e_enable_phy_retry(struct e1000_hw *hw)
116{
117 hw->phy.retry_enabled = true;
118}
119
120/**
121 * e1000e_read_phy_reg_mdic - Read MDI control register
122 * @hw: pointer to the HW structure
123 * @offset: register offset to be read
124 * @data: pointer to the read data
125 *
126 * Reads the MDI control register in the PHY at offset and stores the
127 * information read to data.
128 **/
129s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
130{
131 u32 i, mdic = 0, retry_counter, retry_max;
132 struct e1000_phy_info *phy = &hw->phy;
133 bool success;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 e_dbg("PHY Address %d is out of range\n", offset);
137 return -E1000_ERR_PARAM;
138 }
139
140 retry_max = phy->retry_enabled ? phy->retry_count : 0;
141
142 /* Set up Op-code, Phy Address, and register offset in the MDI
143 * Control register. The MAC will take care of interfacing with the
144 * PHY to retrieve the desired data.
145 */
146 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
147 success = true;
148
149 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
150 (phy->addr << E1000_MDIC_PHY_SHIFT) |
151 (E1000_MDIC_OP_READ));
152
153 ew32(MDIC, mdic);
154
155 /* Poll the ready bit to see if the MDI read completed
156 * Increasing the time out as testing showed failures with
157 * the lower time out
158 */
159 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
160 udelay(50);
161 mdic = er32(MDIC);
162 if (mdic & E1000_MDIC_READY)
163 break;
164 }
165 if (!(mdic & E1000_MDIC_READY)) {
166 e_dbg("MDI Read PHY Reg Address %d did not complete\n",
167 offset);
168 success = false;
169 }
170 if (mdic & E1000_MDIC_ERROR) {
171 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
172 success = false;
173 }
174 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
175 e_dbg("MDI Read offset error - requested %d, returned %d\n",
176 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
177 success = false;
178 }
179
180 /* Allow some time after each MDIC transaction to avoid
181 * reading duplicate data in the next MDIC transaction.
182 */
183 if (hw->mac.type == e1000_pch2lan)
184 udelay(100);
185
186 if (success) {
187 *data = (u16)mdic;
188 return 0;
189 }
190
191 if (retry_counter != retry_max) {
192 e_dbg("Perform retry on PHY transaction...\n");
193 mdelay(10);
194 }
195 }
196
197 return -E1000_ERR_PHY;
198}
199
200/**
201 * e1000e_write_phy_reg_mdic - Write MDI control register
202 * @hw: pointer to the HW structure
203 * @offset: register offset to write to
204 * @data: data to write to register at offset
205 *
206 * Writes data to MDI control register in the PHY at offset.
207 **/
208s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
209{
210 u32 i, mdic = 0, retry_counter, retry_max;
211 struct e1000_phy_info *phy = &hw->phy;
212 bool success;
213
214 if (offset > MAX_PHY_REG_ADDRESS) {
215 e_dbg("PHY Address %d is out of range\n", offset);
216 return -E1000_ERR_PARAM;
217 }
218
219 retry_max = phy->retry_enabled ? phy->retry_count : 0;
220
221 /* Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
224 */
225 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
226 success = true;
227
228 mdic = (((u32)data) |
229 (offset << E1000_MDIC_REG_SHIFT) |
230 (phy->addr << E1000_MDIC_PHY_SHIFT) |
231 (E1000_MDIC_OP_WRITE));
232
233 ew32(MDIC, mdic);
234
235 /* Poll the ready bit to see if the MDI read completed
236 * Increasing the time out as testing showed failures with
237 * the lower time out
238 */
239 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
240 udelay(50);
241 mdic = er32(MDIC);
242 if (mdic & E1000_MDIC_READY)
243 break;
244 }
245 if (!(mdic & E1000_MDIC_READY)) {
246 e_dbg("MDI Write PHY Reg Address %d did not complete\n",
247 offset);
248 success = false;
249 }
250 if (mdic & E1000_MDIC_ERROR) {
251 e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
252 success = false;
253 }
254 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
255 e_dbg("MDI Write offset error - requested %d, returned %d\n",
256 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
257 success = false;
258 }
259
260 /* Allow some time after each MDIC transaction to avoid
261 * reading duplicate data in the next MDIC transaction.
262 */
263 if (hw->mac.type == e1000_pch2lan)
264 udelay(100);
265
266 if (success)
267 return 0;
268
269 if (retry_counter != retry_max) {
270 e_dbg("Perform retry on PHY transaction...\n");
271 mdelay(10);
272 }
273 }
274
275 return -E1000_ERR_PHY;
276}
277
278/**
279 * e1000e_read_phy_reg_m88 - Read m88 PHY register
280 * @hw: pointer to the HW structure
281 * @offset: register offset to be read
282 * @data: pointer to the read data
283 *
284 * Acquires semaphore, if necessary, then reads the PHY register at offset
285 * and storing the retrieved information in data. Release any acquired
286 * semaphores before exiting.
287 **/
288s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
289{
290 s32 ret_val;
291
292 ret_val = hw->phy.ops.acquire(hw);
293 if (ret_val)
294 return ret_val;
295
296 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
297 data);
298
299 hw->phy.ops.release(hw);
300
301 return ret_val;
302}
303
304/**
305 * e1000e_write_phy_reg_m88 - Write m88 PHY register
306 * @hw: pointer to the HW structure
307 * @offset: register offset to write to
308 * @data: data to write at register offset
309 *
310 * Acquires semaphore, if necessary, then writes the data to PHY register
311 * at the offset. Release any acquired semaphores before exiting.
312 **/
313s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
314{
315 s32 ret_val;
316
317 ret_val = hw->phy.ops.acquire(hw);
318 if (ret_val)
319 return ret_val;
320
321 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
322 data);
323
324 hw->phy.ops.release(hw);
325
326 return ret_val;
327}
328
329/**
330 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
331 * @hw: pointer to the HW structure
332 * @page: page to set (shifted left when necessary)
333 *
334 * Sets PHY page required for PHY register access. Assumes semaphore is
335 * already acquired. Note, this function sets phy.addr to 1 so the caller
336 * must set it appropriately (if necessary) after this function returns.
337 **/
338s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
339{
340 e_dbg("Setting page 0x%x\n", page);
341
342 hw->phy.addr = 1;
343
344 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
345}
346
347/**
348 * __e1000e_read_phy_reg_igp - Read igp PHY register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to be read
351 * @data: pointer to the read data
352 * @locked: semaphore has already been acquired or not
353 *
354 * Acquires semaphore, if necessary, then reads the PHY register at offset
355 * and stores the retrieved information in data. Release any acquired
356 * semaphores before exiting.
357 **/
358static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
359 bool locked)
360{
361 s32 ret_val = 0;
362
363 if (!locked) {
364 if (!hw->phy.ops.acquire)
365 return 0;
366
367 ret_val = hw->phy.ops.acquire(hw);
368 if (ret_val)
369 return ret_val;
370 }
371
372 if (offset > MAX_PHY_MULTI_PAGE_REG)
373 ret_val = e1000e_write_phy_reg_mdic(hw,
374 IGP01E1000_PHY_PAGE_SELECT,
375 (u16)offset);
376 if (!ret_val)
377 ret_val = e1000e_read_phy_reg_mdic(hw,
378 MAX_PHY_REG_ADDRESS & offset,
379 data);
380 if (!locked)
381 hw->phy.ops.release(hw);
382
383 return ret_val;
384}
385
386/**
387 * e1000e_read_phy_reg_igp - Read igp PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
391 *
392 * Acquires semaphore then reads the PHY register at offset and stores the
393 * retrieved information in data.
394 * Release the acquired semaphore before exiting.
395 **/
396s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
397{
398 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
399}
400
401/**
402 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
403 * @hw: pointer to the HW structure
404 * @offset: register offset to be read
405 * @data: pointer to the read data
406 *
407 * Reads the PHY register at offset and stores the retrieved information
408 * in data. Assumes semaphore already acquired.
409 **/
410s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
411{
412 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
413}
414
415/**
416 * __e1000e_write_phy_reg_igp - Write igp PHY register
417 * @hw: pointer to the HW structure
418 * @offset: register offset to write to
419 * @data: data to write at register offset
420 * @locked: semaphore has already been acquired or not
421 *
422 * Acquires semaphore, if necessary, then writes the data to PHY register
423 * at the offset. Release any acquired semaphores before exiting.
424 **/
425static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
426 bool locked)
427{
428 s32 ret_val = 0;
429
430 if (!locked) {
431 if (!hw->phy.ops.acquire)
432 return 0;
433
434 ret_val = hw->phy.ops.acquire(hw);
435 if (ret_val)
436 return ret_val;
437 }
438
439 if (offset > MAX_PHY_MULTI_PAGE_REG)
440 ret_val = e1000e_write_phy_reg_mdic(hw,
441 IGP01E1000_PHY_PAGE_SELECT,
442 (u16)offset);
443 if (!ret_val)
444 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
445 offset, data);
446 if (!locked)
447 hw->phy.ops.release(hw);
448
449 return ret_val;
450}
451
452/**
453 * e1000e_write_phy_reg_igp - Write igp PHY register
454 * @hw: pointer to the HW structure
455 * @offset: register offset to write to
456 * @data: data to write at register offset
457 *
458 * Acquires semaphore then writes the data to PHY register
459 * at the offset. Release any acquired semaphores before exiting.
460 **/
461s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
462{
463 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
464}
465
466/**
467 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
468 * @hw: pointer to the HW structure
469 * @offset: register offset to write to
470 * @data: data to write at register offset
471 *
472 * Writes the data to PHY register at the offset.
473 * Assumes semaphore already acquired.
474 **/
475s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
476{
477 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
478}
479
480/**
481 * __e1000_read_kmrn_reg - Read kumeran register
482 * @hw: pointer to the HW structure
483 * @offset: register offset to be read
484 * @data: pointer to the read data
485 * @locked: semaphore has already been acquired or not
486 *
487 * Acquires semaphore, if necessary. Then reads the PHY register at offset
488 * using the kumeran interface. The information retrieved is stored in data.
489 * Release any acquired semaphores before exiting.
490 **/
491static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
492 bool locked)
493{
494 u32 kmrnctrlsta;
495
496 if (!locked) {
497 s32 ret_val = 0;
498
499 if (!hw->phy.ops.acquire)
500 return 0;
501
502 ret_val = hw->phy.ops.acquire(hw);
503 if (ret_val)
504 return ret_val;
505 }
506
507 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
508 E1000_KMRNCTRLSTA_REN;
509 ew32(KMRNCTRLSTA, kmrnctrlsta);
510 e1e_flush();
511
512 udelay(2);
513
514 kmrnctrlsta = er32(KMRNCTRLSTA);
515 *data = (u16)kmrnctrlsta;
516
517 if (!locked)
518 hw->phy.ops.release(hw);
519
520 return 0;
521}
522
523/**
524 * e1000e_read_kmrn_reg - Read kumeran register
525 * @hw: pointer to the HW structure
526 * @offset: register offset to be read
527 * @data: pointer to the read data
528 *
529 * Acquires semaphore then reads the PHY register at offset using the
530 * kumeran interface. The information retrieved is stored in data.
531 * Release the acquired semaphore before exiting.
532 **/
533s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
534{
535 return __e1000_read_kmrn_reg(hw, offset, data, false);
536}
537
538/**
539 * e1000e_read_kmrn_reg_locked - Read kumeran register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be read
542 * @data: pointer to the read data
543 *
544 * Reads the PHY register at offset using the kumeran interface. The
545 * information retrieved is stored in data.
546 * Assumes semaphore already acquired.
547 **/
548s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
549{
550 return __e1000_read_kmrn_reg(hw, offset, data, true);
551}
552
553/**
554 * __e1000_write_kmrn_reg - Write kumeran register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to write to
557 * @data: data to write at register offset
558 * @locked: semaphore has already been acquired or not
559 *
560 * Acquires semaphore, if necessary. Then write the data to PHY register
561 * at the offset using the kumeran interface. Release any acquired semaphores
562 * before exiting.
563 **/
564static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
565 bool locked)
566{
567 u32 kmrnctrlsta;
568
569 if (!locked) {
570 s32 ret_val = 0;
571
572 if (!hw->phy.ops.acquire)
573 return 0;
574
575 ret_val = hw->phy.ops.acquire(hw);
576 if (ret_val)
577 return ret_val;
578 }
579
580 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
581 ew32(KMRNCTRLSTA, kmrnctrlsta);
582 e1e_flush();
583
584 udelay(2);
585
586 if (!locked)
587 hw->phy.ops.release(hw);
588
589 return 0;
590}
591
592/**
593 * e1000e_write_kmrn_reg - Write kumeran register
594 * @hw: pointer to the HW structure
595 * @offset: register offset to write to
596 * @data: data to write at register offset
597 *
598 * Acquires semaphore then writes the data to the PHY register at the offset
599 * using the kumeran interface. Release the acquired semaphore before exiting.
600 **/
601s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
602{
603 return __e1000_write_kmrn_reg(hw, offset, data, false);
604}
605
606/**
607 * e1000e_write_kmrn_reg_locked - Write kumeran register
608 * @hw: pointer to the HW structure
609 * @offset: register offset to write to
610 * @data: data to write at register offset
611 *
612 * Write the data to PHY register at the offset using the kumeran interface.
613 * Assumes semaphore already acquired.
614 **/
615s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
616{
617 return __e1000_write_kmrn_reg(hw, offset, data, true);
618}
619
620/**
621 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
622 * @hw: pointer to the HW structure
623 *
624 * Sets up Master/slave mode
625 **/
626static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
627{
628 s32 ret_val;
629 u16 phy_data;
630
631 /* Resolve Master/Slave mode */
632 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
633 if (ret_val)
634 return ret_val;
635
636 /* load defaults for future use */
637 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
638 ((phy_data & CTL1000_AS_MASTER) ?
639 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
640
641 switch (hw->phy.ms_type) {
642 case e1000_ms_force_master:
643 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
644 break;
645 case e1000_ms_force_slave:
646 phy_data |= CTL1000_ENABLE_MASTER;
647 phy_data &= ~(CTL1000_AS_MASTER);
648 break;
649 case e1000_ms_auto:
650 phy_data &= ~CTL1000_ENABLE_MASTER;
651 fallthrough;
652 default:
653 break;
654 }
655
656 return e1e_wphy(hw, MII_CTRL1000, phy_data);
657}
658
659/**
660 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
661 * @hw: pointer to the HW structure
662 *
663 * Sets up Carrier-sense on Transmit and downshift values.
664 **/
665s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
666{
667 s32 ret_val;
668 u16 phy_data;
669
670 /* Enable CRS on Tx. This must be set for half-duplex operation. */
671 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
672 if (ret_val)
673 return ret_val;
674
675 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
676
677 /* Enable downshift */
678 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
679
680 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
681 if (ret_val)
682 return ret_val;
683
684 /* Set MDI/MDIX mode */
685 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
686 if (ret_val)
687 return ret_val;
688 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
689 /* Options:
690 * 0 - Auto (default)
691 * 1 - MDI mode
692 * 2 - MDI-X mode
693 */
694 switch (hw->phy.mdix) {
695 case 1:
696 break;
697 case 2:
698 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
699 break;
700 case 0:
701 default:
702 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
703 break;
704 }
705 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
706 if (ret_val)
707 return ret_val;
708
709 return e1000_set_master_slave_mode(hw);
710}
711
712/**
713 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
714 * @hw: pointer to the HW structure
715 *
716 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
717 * and downshift values are set also.
718 **/
719s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
720{
721 struct e1000_phy_info *phy = &hw->phy;
722 s32 ret_val;
723 u16 phy_data;
724
725 /* Enable CRS on Tx. This must be set for half-duplex operation. */
726 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
727 if (ret_val)
728 return ret_val;
729
730 /* For BM PHY this bit is downshift enable */
731 if (phy->type != e1000_phy_bm)
732 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
733
734 /* Options:
735 * MDI/MDI-X = 0 (default)
736 * 0 - Auto for all speeds
737 * 1 - MDI mode
738 * 2 - MDI-X mode
739 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
740 */
741 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
742
743 switch (phy->mdix) {
744 case 1:
745 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
746 break;
747 case 2:
748 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
749 break;
750 case 3:
751 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
752 break;
753 case 0:
754 default:
755 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
756 break;
757 }
758
759 /* Options:
760 * disable_polarity_correction = 0 (default)
761 * Automatic Correction for Reversed Cable Polarity
762 * 0 - Disabled
763 * 1 - Enabled
764 */
765 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
766 if (phy->disable_polarity_correction)
767 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
768
769 /* Enable downshift on BM (disabled by default) */
770 if (phy->type == e1000_phy_bm) {
771 /* For 82574/82583, first disable then enable downshift */
772 if (phy->id == BME1000_E_PHY_ID_R2) {
773 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
774 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
775 phy_data);
776 if (ret_val)
777 return ret_val;
778 /* Commit the changes. */
779 ret_val = phy->ops.commit(hw);
780 if (ret_val) {
781 e_dbg("Error committing the PHY changes\n");
782 return ret_val;
783 }
784 }
785
786 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
787 }
788
789 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
790 if (ret_val)
791 return ret_val;
792
793 if ((phy->type == e1000_phy_m88) &&
794 (phy->revision < E1000_REVISION_4) &&
795 (phy->id != BME1000_E_PHY_ID_R2)) {
796 /* Force TX_CLK in the Extended PHY Specific Control Register
797 * to 25MHz clock.
798 */
799 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
800 if (ret_val)
801 return ret_val;
802
803 phy_data |= M88E1000_EPSCR_TX_CLK_25;
804
805 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
806 /* 82573L PHY - set the downshift counter to 5x. */
807 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
808 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
809 } else {
810 /* Configure Master and Slave downshift values */
811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
812 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
814 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
815 }
816 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
817 if (ret_val)
818 return ret_val;
819 }
820
821 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
822 /* Set PHY page 0, register 29 to 0x0003 */
823 ret_val = e1e_wphy(hw, 29, 0x0003);
824 if (ret_val)
825 return ret_val;
826
827 /* Set PHY page 0, register 30 to 0x0000 */
828 ret_val = e1e_wphy(hw, 30, 0x0000);
829 if (ret_val)
830 return ret_val;
831 }
832
833 /* Commit the changes. */
834 if (phy->ops.commit) {
835 ret_val = phy->ops.commit(hw);
836 if (ret_val) {
837 e_dbg("Error committing the PHY changes\n");
838 return ret_val;
839 }
840 }
841
842 if (phy->type == e1000_phy_82578) {
843 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
844 if (ret_val)
845 return ret_val;
846
847 /* 82578 PHY - set the downshift count to 1x. */
848 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
849 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
850 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
851 if (ret_val)
852 return ret_val;
853 }
854
855 return 0;
856}
857
858/**
859 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
860 * @hw: pointer to the HW structure
861 *
862 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
863 * igp PHY's.
864 **/
865s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
866{
867 struct e1000_phy_info *phy = &hw->phy;
868 s32 ret_val;
869 u16 data;
870
871 ret_val = e1000_phy_hw_reset(hw);
872 if (ret_val) {
873 e_dbg("Error resetting the PHY.\n");
874 return ret_val;
875 }
876
877 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
878 * timeout issues when LFS is enabled.
879 */
880 msleep(100);
881
882 /* disable lplu d0 during driver init */
883 if (hw->phy.ops.set_d0_lplu_state) {
884 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
885 if (ret_val) {
886 e_dbg("Error Disabling LPLU D0\n");
887 return ret_val;
888 }
889 }
890 /* Configure mdi-mdix settings */
891 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
892 if (ret_val)
893 return ret_val;
894
895 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
896
897 switch (phy->mdix) {
898 case 1:
899 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
900 break;
901 case 2:
902 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
903 break;
904 case 0:
905 default:
906 data |= IGP01E1000_PSCR_AUTO_MDIX;
907 break;
908 }
909 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
910 if (ret_val)
911 return ret_val;
912
913 /* set auto-master slave resolution settings */
914 if (hw->mac.autoneg) {
915 /* when autonegotiation advertisement is only 1000Mbps then we
916 * should disable SmartSpeed and enable Auto MasterSlave
917 * resolution as hardware default.
918 */
919 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
920 /* Disable SmartSpeed */
921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
922 &data);
923 if (ret_val)
924 return ret_val;
925
926 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
927 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
928 data);
929 if (ret_val)
930 return ret_val;
931
932 /* Set auto Master/Slave resolution process */
933 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
934 if (ret_val)
935 return ret_val;
936
937 data &= ~CTL1000_ENABLE_MASTER;
938 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
939 if (ret_val)
940 return ret_val;
941 }
942
943 ret_val = e1000_set_master_slave_mode(hw);
944 }
945
946 return ret_val;
947}
948
949/**
950 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
951 * @hw: pointer to the HW structure
952 *
953 * Reads the MII auto-neg advertisement register and/or the 1000T control
954 * register and if the PHY is already setup for auto-negotiation, then
955 * return successful. Otherwise, setup advertisement and flow control to
956 * the appropriate values for the wanted auto-negotiation.
957 **/
958static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
959{
960 struct e1000_phy_info *phy = &hw->phy;
961 s32 ret_val;
962 u16 mii_autoneg_adv_reg;
963 u16 mii_1000t_ctrl_reg = 0;
964
965 phy->autoneg_advertised &= phy->autoneg_mask;
966
967 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
968 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
969 if (ret_val)
970 return ret_val;
971
972 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
973 /* Read the MII 1000Base-T Control Register (Address 9). */
974 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
975 if (ret_val)
976 return ret_val;
977 }
978
979 /* Need to parse both autoneg_advertised and fc and set up
980 * the appropriate PHY registers. First we will parse for
981 * autoneg_advertised software override. Since we can advertise
982 * a plethora of combinations, we need to check each bit
983 * individually.
984 */
985
986 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
987 * Advertisement Register (Address 4) and the 1000 mb speed bits in
988 * the 1000Base-T Control Register (Address 9).
989 */
990 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
991 ADVERTISE_100HALF |
992 ADVERTISE_10FULL | ADVERTISE_10HALF);
993 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
994
995 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
996
997 /* Do we want to advertise 10 Mb Half Duplex? */
998 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
999 e_dbg("Advertise 10mb Half duplex\n");
1000 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
1001 }
1002
1003 /* Do we want to advertise 10 Mb Full Duplex? */
1004 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1005 e_dbg("Advertise 10mb Full duplex\n");
1006 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
1007 }
1008
1009 /* Do we want to advertise 100 Mb Half Duplex? */
1010 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1011 e_dbg("Advertise 100mb Half duplex\n");
1012 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
1013 }
1014
1015 /* Do we want to advertise 100 Mb Full Duplex? */
1016 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1017 e_dbg("Advertise 100mb Full duplex\n");
1018 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
1019 }
1020
1021 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1022 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1023 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1024
1025 /* Do we want to advertise 1000 Mb Full Duplex? */
1026 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1027 e_dbg("Advertise 1000mb Full duplex\n");
1028 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1029 }
1030
1031 /* Check for a software override of the flow control settings, and
1032 * setup the PHY advertisement registers accordingly. If
1033 * auto-negotiation is enabled, then software will have to set the
1034 * "PAUSE" bits to the correct value in the Auto-Negotiation
1035 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1036 * negotiation.
1037 *
1038 * The possible values of the "fc" parameter are:
1039 * 0: Flow control is completely disabled
1040 * 1: Rx flow control is enabled (we can receive pause frames
1041 * but not send pause frames).
1042 * 2: Tx flow control is enabled (we can send pause frames
1043 * but we do not support receiving pause frames).
1044 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1045 * other: No software override. The flow control configuration
1046 * in the EEPROM is used.
1047 */
1048 switch (hw->fc.current_mode) {
1049 case e1000_fc_none:
1050 /* Flow control (Rx & Tx) is completely disabled by a
1051 * software over-ride.
1052 */
1053 mii_autoneg_adv_reg &=
1054 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1055 phy->autoneg_advertised &=
1056 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1057 break;
1058 case e1000_fc_rx_pause:
1059 /* Rx Flow control is enabled, and Tx Flow control is
1060 * disabled, by a software over-ride.
1061 *
1062 * Since there really isn't a way to advertise that we are
1063 * capable of Rx Pause ONLY, we will advertise that we
1064 * support both symmetric and asymmetric Rx PAUSE. Later
1065 * (in e1000e_config_fc_after_link_up) we will disable the
1066 * hw's ability to send PAUSE frames.
1067 */
1068 mii_autoneg_adv_reg |=
1069 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1070 phy->autoneg_advertised |=
1071 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1072 break;
1073 case e1000_fc_tx_pause:
1074 /* Tx Flow control is enabled, and Rx Flow control is
1075 * disabled, by a software over-ride.
1076 */
1077 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1078 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1079 phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1080 phy->autoneg_advertised &= ~ADVERTISED_Pause;
1081 break;
1082 case e1000_fc_full:
1083 /* Flow control (both Rx and Tx) is enabled by a software
1084 * over-ride.
1085 */
1086 mii_autoneg_adv_reg |=
1087 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1088 phy->autoneg_advertised |=
1089 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1090 break;
1091 default:
1092 e_dbg("Flow control param set incorrectly\n");
1093 return -E1000_ERR_CONFIG;
1094 }
1095
1096 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1097 if (ret_val)
1098 return ret_val;
1099
1100 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1101
1102 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1103 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1104
1105 return ret_val;
1106}
1107
1108/**
1109 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1110 * @hw: pointer to the HW structure
1111 *
1112 * Performs initial bounds checking on autoneg advertisement parameter, then
1113 * configure to advertise the full capability. Setup the PHY to autoneg
1114 * and restart the negotiation process between the link partner. If
1115 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1116 **/
1117static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1118{
1119 struct e1000_phy_info *phy = &hw->phy;
1120 s32 ret_val;
1121 u16 phy_ctrl;
1122
1123 /* Perform some bounds checking on the autoneg advertisement
1124 * parameter.
1125 */
1126 phy->autoneg_advertised &= phy->autoneg_mask;
1127
1128 /* If autoneg_advertised is zero, we assume it was not defaulted
1129 * by the calling code so we set to advertise full capability.
1130 */
1131 if (!phy->autoneg_advertised)
1132 phy->autoneg_advertised = phy->autoneg_mask;
1133
1134 e_dbg("Reconfiguring auto-neg advertisement params\n");
1135 ret_val = e1000_phy_setup_autoneg(hw);
1136 if (ret_val) {
1137 e_dbg("Error Setting up Auto-Negotiation\n");
1138 return ret_val;
1139 }
1140 e_dbg("Restarting Auto-Neg\n");
1141
1142 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1143 * the Auto Neg Restart bit in the PHY control register.
1144 */
1145 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1146 if (ret_val)
1147 return ret_val;
1148
1149 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1150 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1151 if (ret_val)
1152 return ret_val;
1153
1154 /* Does the user want to wait for Auto-Neg to complete here, or
1155 * check at a later time (for example, callback routine).
1156 */
1157 if (phy->autoneg_wait_to_complete) {
1158 ret_val = e1000_wait_autoneg(hw);
1159 if (ret_val) {
1160 e_dbg("Error while waiting for autoneg to complete\n");
1161 return ret_val;
1162 }
1163 }
1164
1165 hw->mac.get_link_status = true;
1166
1167 return ret_val;
1168}
1169
1170/**
1171 * e1000e_setup_copper_link - Configure copper link settings
1172 * @hw: pointer to the HW structure
1173 *
1174 * Calls the appropriate function to configure the link for auto-neg or forced
1175 * speed and duplex. Then we check for link, once link is established calls
1176 * to configure collision distance and flow control are called. If link is
1177 * not established, we return -E1000_ERR_PHY (-2).
1178 **/
1179s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1180{
1181 s32 ret_val;
1182 bool link;
1183
1184 if (hw->mac.autoneg) {
1185 /* Setup autoneg and flow control advertisement and perform
1186 * autonegotiation.
1187 */
1188 ret_val = e1000_copper_link_autoneg(hw);
1189 if (ret_val)
1190 return ret_val;
1191 } else {
1192 /* PHY will be set to 10H, 10F, 100H or 100F
1193 * depending on user settings.
1194 */
1195 e_dbg("Forcing Speed and Duplex\n");
1196 ret_val = hw->phy.ops.force_speed_duplex(hw);
1197 if (ret_val) {
1198 e_dbg("Error Forcing Speed and Duplex\n");
1199 return ret_val;
1200 }
1201 }
1202
1203 /* Check link status. Wait up to 100 microseconds for link to become
1204 * valid.
1205 */
1206 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1207 &link);
1208 if (ret_val)
1209 return ret_val;
1210
1211 if (link) {
1212 e_dbg("Valid link established!!!\n");
1213 hw->mac.ops.config_collision_dist(hw);
1214 ret_val = e1000e_config_fc_after_link_up(hw);
1215 } else {
1216 e_dbg("Unable to establish link!!!\n");
1217 }
1218
1219 return ret_val;
1220}
1221
1222/**
1223 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1224 * @hw: pointer to the HW structure
1225 *
1226 * Calls the PHY setup function to force speed and duplex. Clears the
1227 * auto-crossover to force MDI manually. Waits for link and returns
1228 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1229 **/
1230s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1231{
1232 struct e1000_phy_info *phy = &hw->phy;
1233 s32 ret_val;
1234 u16 phy_data;
1235 bool link;
1236
1237 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1238 if (ret_val)
1239 return ret_val;
1240
1241 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1242
1243 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1244 if (ret_val)
1245 return ret_val;
1246
1247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1248 * forced whenever speed and duplex are forced.
1249 */
1250 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1251 if (ret_val)
1252 return ret_val;
1253
1254 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1255 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1256
1257 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1258 if (ret_val)
1259 return ret_val;
1260
1261 e_dbg("IGP PSCR: %X\n", phy_data);
1262
1263 udelay(1);
1264
1265 if (phy->autoneg_wait_to_complete) {
1266 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1267
1268 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1269 100000, &link);
1270 if (ret_val)
1271 return ret_val;
1272
1273 if (!link)
1274 e_dbg("Link taking longer than expected.\n");
1275
1276 /* Try once more */
1277 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1278 100000, &link);
1279 }
1280
1281 return ret_val;
1282}
1283
1284/**
1285 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1286 * @hw: pointer to the HW structure
1287 *
1288 * Calls the PHY setup function to force speed and duplex. Clears the
1289 * auto-crossover to force MDI manually. Resets the PHY to commit the
1290 * changes. If time expires while waiting for link up, we reset the DSP.
1291 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1292 * successful completion, else return corresponding error code.
1293 **/
1294s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1295{
1296 struct e1000_phy_info *phy = &hw->phy;
1297 s32 ret_val;
1298 u16 phy_data;
1299 bool link;
1300
1301 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1302 * forced whenever speed and duplex are forced.
1303 */
1304 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1305 if (ret_val)
1306 return ret_val;
1307
1308 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1309 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1310 if (ret_val)
1311 return ret_val;
1312
1313 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1314
1315 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1316 if (ret_val)
1317 return ret_val;
1318
1319 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1320
1321 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1322 if (ret_val)
1323 return ret_val;
1324
1325 /* Reset the phy to commit changes. */
1326 if (hw->phy.ops.commit) {
1327 ret_val = hw->phy.ops.commit(hw);
1328 if (ret_val)
1329 return ret_val;
1330 }
1331
1332 if (phy->autoneg_wait_to_complete) {
1333 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1334
1335 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1336 100000, &link);
1337 if (ret_val)
1338 return ret_val;
1339
1340 if (!link) {
1341 if (hw->phy.type != e1000_phy_m88) {
1342 e_dbg("Link taking longer than expected.\n");
1343 } else {
1344 /* We didn't get link.
1345 * Reset the DSP and cross our fingers.
1346 */
1347 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1348 0x001d);
1349 if (ret_val)
1350 return ret_val;
1351 ret_val = e1000e_phy_reset_dsp(hw);
1352 if (ret_val)
1353 return ret_val;
1354 }
1355 }
1356
1357 /* Try once more */
1358 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1359 100000, &link);
1360 if (ret_val)
1361 return ret_val;
1362 }
1363
1364 if (hw->phy.type != e1000_phy_m88)
1365 return 0;
1366
1367 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1368 if (ret_val)
1369 return ret_val;
1370
1371 /* Resetting the phy means we need to re-force TX_CLK in the
1372 * Extended PHY Specific Control Register to 25MHz clock from
1373 * the reset value of 2.5MHz.
1374 */
1375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1376 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1377 if (ret_val)
1378 return ret_val;
1379
1380 /* In addition, we must re-enable CRS on Tx for both half and full
1381 * duplex.
1382 */
1383 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1388 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1389
1390 return ret_val;
1391}
1392
1393/**
1394 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1395 * @hw: pointer to the HW structure
1396 *
1397 * Forces the speed and duplex settings of the PHY.
1398 * This is a function pointer entry point only called by
1399 * PHY setup routines.
1400 **/
1401s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1402{
1403 struct e1000_phy_info *phy = &hw->phy;
1404 s32 ret_val;
1405 u16 data;
1406 bool link;
1407
1408 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1409 if (ret_val)
1410 return ret_val;
1411
1412 e1000e_phy_force_speed_duplex_setup(hw, &data);
1413
1414 ret_val = e1e_wphy(hw, MII_BMCR, data);
1415 if (ret_val)
1416 return ret_val;
1417
1418 /* Disable MDI-X support for 10/100 */
1419 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1420 if (ret_val)
1421 return ret_val;
1422
1423 data &= ~IFE_PMC_AUTO_MDIX;
1424 data &= ~IFE_PMC_FORCE_MDIX;
1425
1426 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1427 if (ret_val)
1428 return ret_val;
1429
1430 e_dbg("IFE PMC: %X\n", data);
1431
1432 udelay(1);
1433
1434 if (phy->autoneg_wait_to_complete) {
1435 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1436
1437 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1438 100000, &link);
1439 if (ret_val)
1440 return ret_val;
1441
1442 if (!link)
1443 e_dbg("Link taking longer than expected.\n");
1444
1445 /* Try once more */
1446 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1447 100000, &link);
1448 if (ret_val)
1449 return ret_val;
1450 }
1451
1452 return 0;
1453}
1454
1455/**
1456 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1457 * @hw: pointer to the HW structure
1458 * @phy_ctrl: pointer to current value of MII_BMCR
1459 *
1460 * Forces speed and duplex on the PHY by doing the following: disable flow
1461 * control, force speed/duplex on the MAC, disable auto speed detection,
1462 * disable auto-negotiation, configure duplex, configure speed, configure
1463 * the collision distance, write configuration to CTRL register. The
1464 * caller must write to the MII_BMCR register for these settings to
1465 * take affect.
1466 **/
1467void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1468{
1469 struct e1000_mac_info *mac = &hw->mac;
1470 u32 ctrl;
1471
1472 /* Turn off flow control when forcing speed/duplex */
1473 hw->fc.current_mode = e1000_fc_none;
1474
1475 /* Force speed/duplex on the mac */
1476 ctrl = er32(CTRL);
1477 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1478 ctrl &= ~E1000_CTRL_SPD_SEL;
1479
1480 /* Disable Auto Speed Detection */
1481 ctrl &= ~E1000_CTRL_ASDE;
1482
1483 /* Disable autoneg on the phy */
1484 *phy_ctrl &= ~BMCR_ANENABLE;
1485
1486 /* Forcing Full or Half Duplex? */
1487 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1488 ctrl &= ~E1000_CTRL_FD;
1489 *phy_ctrl &= ~BMCR_FULLDPLX;
1490 e_dbg("Half Duplex\n");
1491 } else {
1492 ctrl |= E1000_CTRL_FD;
1493 *phy_ctrl |= BMCR_FULLDPLX;
1494 e_dbg("Full Duplex\n");
1495 }
1496
1497 /* Forcing 10mb or 100mb? */
1498 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1499 ctrl |= E1000_CTRL_SPD_100;
1500 *phy_ctrl |= BMCR_SPEED100;
1501 *phy_ctrl &= ~BMCR_SPEED1000;
1502 e_dbg("Forcing 100mb\n");
1503 } else {
1504 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1505 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1506 e_dbg("Forcing 10mb\n");
1507 }
1508
1509 hw->mac.ops.config_collision_dist(hw);
1510
1511 ew32(CTRL, ctrl);
1512}
1513
1514/**
1515 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1516 * @hw: pointer to the HW structure
1517 * @active: boolean used to enable/disable lplu
1518 *
1519 * Success returns 0, Failure returns 1
1520 *
1521 * The low power link up (lplu) state is set to the power management level D3
1522 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1523 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1524 * is used during Dx states where the power conservation is most important.
1525 * During driver activity, SmartSpeed should be enabled so performance is
1526 * maintained.
1527 **/
1528s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1529{
1530 struct e1000_phy_info *phy = &hw->phy;
1531 s32 ret_val;
1532 u16 data;
1533
1534 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1535 if (ret_val)
1536 return ret_val;
1537
1538 if (!active) {
1539 data &= ~IGP02E1000_PM_D3_LPLU;
1540 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1541 if (ret_val)
1542 return ret_val;
1543 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1544 * during Dx states where the power conservation is most
1545 * important. During driver activity we should enable
1546 * SmartSpeed, so performance is maintained.
1547 */
1548 if (phy->smart_speed == e1000_smart_speed_on) {
1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1550 &data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 data |= IGP01E1000_PSCFR_SMART_SPEED;
1555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1556 data);
1557 if (ret_val)
1558 return ret_val;
1559 } else if (phy->smart_speed == e1000_smart_speed_off) {
1560 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1561 &data);
1562 if (ret_val)
1563 return ret_val;
1564
1565 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1566 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1567 data);
1568 if (ret_val)
1569 return ret_val;
1570 }
1571 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1572 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1573 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1574 data |= IGP02E1000_PM_D3_LPLU;
1575 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1576 if (ret_val)
1577 return ret_val;
1578
1579 /* When LPLU is enabled, we should disable SmartSpeed */
1580 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1581 if (ret_val)
1582 return ret_val;
1583
1584 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1585 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1586 }
1587
1588 return ret_val;
1589}
1590
1591/**
1592 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1593 * @hw: pointer to the HW structure
1594 *
1595 * Success returns 0, Failure returns 1
1596 *
1597 * A downshift is detected by querying the PHY link health.
1598 **/
1599s32 e1000e_check_downshift(struct e1000_hw *hw)
1600{
1601 struct e1000_phy_info *phy = &hw->phy;
1602 s32 ret_val;
1603 u16 phy_data, offset, mask;
1604
1605 switch (phy->type) {
1606 case e1000_phy_m88:
1607 case e1000_phy_gg82563:
1608 case e1000_phy_bm:
1609 case e1000_phy_82578:
1610 offset = M88E1000_PHY_SPEC_STATUS;
1611 mask = M88E1000_PSSR_DOWNSHIFT;
1612 break;
1613 case e1000_phy_igp_2:
1614 case e1000_phy_igp_3:
1615 offset = IGP01E1000_PHY_LINK_HEALTH;
1616 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1617 break;
1618 default:
1619 /* speed downshift not supported */
1620 phy->speed_downgraded = false;
1621 return 0;
1622 }
1623
1624 ret_val = e1e_rphy(hw, offset, &phy_data);
1625
1626 if (!ret_val)
1627 phy->speed_downgraded = !!(phy_data & mask);
1628
1629 return ret_val;
1630}
1631
1632/**
1633 * e1000_check_polarity_m88 - Checks the polarity.
1634 * @hw: pointer to the HW structure
1635 *
1636 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1637 *
1638 * Polarity is determined based on the PHY specific status register.
1639 **/
1640s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1641{
1642 struct e1000_phy_info *phy = &hw->phy;
1643 s32 ret_val;
1644 u16 data;
1645
1646 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1647
1648 if (!ret_val)
1649 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1650 ? e1000_rev_polarity_reversed
1651 : e1000_rev_polarity_normal);
1652
1653 return ret_val;
1654}
1655
1656/**
1657 * e1000_check_polarity_igp - Checks the polarity.
1658 * @hw: pointer to the HW structure
1659 *
1660 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1661 *
1662 * Polarity is determined based on the PHY port status register, and the
1663 * current speed (since there is no polarity at 100Mbps).
1664 **/
1665s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1666{
1667 struct e1000_phy_info *phy = &hw->phy;
1668 s32 ret_val;
1669 u16 data, offset, mask;
1670
1671 /* Polarity is determined based on the speed of
1672 * our connection.
1673 */
1674 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1675 if (ret_val)
1676 return ret_val;
1677
1678 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1679 IGP01E1000_PSSR_SPEED_1000MBPS) {
1680 offset = IGP01E1000_PHY_PCS_INIT_REG;
1681 mask = IGP01E1000_PHY_POLARITY_MASK;
1682 } else {
1683 /* This really only applies to 10Mbps since
1684 * there is no polarity for 100Mbps (always 0).
1685 */
1686 offset = IGP01E1000_PHY_PORT_STATUS;
1687 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1688 }
1689
1690 ret_val = e1e_rphy(hw, offset, &data);
1691
1692 if (!ret_val)
1693 phy->cable_polarity = ((data & mask)
1694 ? e1000_rev_polarity_reversed
1695 : e1000_rev_polarity_normal);
1696
1697 return ret_val;
1698}
1699
1700/**
1701 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1702 * @hw: pointer to the HW structure
1703 *
1704 * Polarity is determined on the polarity reversal feature being enabled.
1705 **/
1706s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1707{
1708 struct e1000_phy_info *phy = &hw->phy;
1709 s32 ret_val;
1710 u16 phy_data, offset, mask;
1711
1712 /* Polarity is determined based on the reversal feature being enabled.
1713 */
1714 if (phy->polarity_correction) {
1715 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1716 mask = IFE_PESC_POLARITY_REVERSED;
1717 } else {
1718 offset = IFE_PHY_SPECIAL_CONTROL;
1719 mask = IFE_PSC_FORCE_POLARITY;
1720 }
1721
1722 ret_val = e1e_rphy(hw, offset, &phy_data);
1723
1724 if (!ret_val)
1725 phy->cable_polarity = ((phy_data & mask)
1726 ? e1000_rev_polarity_reversed
1727 : e1000_rev_polarity_normal);
1728
1729 return ret_val;
1730}
1731
1732/**
1733 * e1000_wait_autoneg - Wait for auto-neg completion
1734 * @hw: pointer to the HW structure
1735 *
1736 * Waits for auto-negotiation to complete or for the auto-negotiation time
1737 * limit to expire, which ever happens first.
1738 **/
1739static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1740{
1741 s32 ret_val = 0;
1742 u16 i, phy_status;
1743
1744 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1745 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1746 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 if (ret_val)
1748 break;
1749 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1750 if (ret_val)
1751 break;
1752 if (phy_status & BMSR_ANEGCOMPLETE)
1753 break;
1754 msleep(100);
1755 }
1756
1757 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1758 * has completed.
1759 */
1760 return ret_val;
1761}
1762
1763/**
1764 * e1000e_phy_has_link_generic - Polls PHY for link
1765 * @hw: pointer to the HW structure
1766 * @iterations: number of times to poll for link
1767 * @usec_interval: delay between polling attempts
1768 * @success: pointer to whether polling was successful or not
1769 *
1770 * Polls the PHY status register for link, 'iterations' number of times.
1771 **/
1772s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1773 u32 usec_interval, bool *success)
1774{
1775 s32 ret_val = 0;
1776 u16 i, phy_status;
1777
1778 *success = false;
1779 for (i = 0; i < iterations; i++) {
1780 /* Some PHYs require the MII_BMSR register to be read
1781 * twice due to the link bit being sticky. No harm doing
1782 * it across the board.
1783 */
1784 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1785 if (ret_val) {
1786 /* If the first read fails, another entity may have
1787 * ownership of the resources, wait and try again to
1788 * see if they have relinquished the resources yet.
1789 */
1790 if (usec_interval >= 1000)
1791 msleep(usec_interval / 1000);
1792 else
1793 udelay(usec_interval);
1794 }
1795 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1796 if (ret_val)
1797 break;
1798 if (phy_status & BMSR_LSTATUS) {
1799 *success = true;
1800 break;
1801 }
1802 if (usec_interval >= 1000)
1803 msleep(usec_interval / 1000);
1804 else
1805 udelay(usec_interval);
1806 }
1807
1808 return ret_val;
1809}
1810
1811/**
1812 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1813 * @hw: pointer to the HW structure
1814 *
1815 * Reads the PHY specific status register to retrieve the cable length
1816 * information. The cable length is determined by averaging the minimum and
1817 * maximum values to get the "average" cable length. The m88 PHY has four
1818 * possible cable length values, which are:
1819 * Register Value Cable Length
1820 * 0 < 50 meters
1821 * 1 50 - 80 meters
1822 * 2 80 - 110 meters
1823 * 3 110 - 140 meters
1824 * 4 > 140 meters
1825 **/
1826s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1827{
1828 struct e1000_phy_info *phy = &hw->phy;
1829 s32 ret_val;
1830 u16 phy_data, index;
1831
1832 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1837
1838 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1839 return -E1000_ERR_PHY;
1840
1841 phy->min_cable_length = e1000_m88_cable_length_table[index];
1842 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1843
1844 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1845
1846 return 0;
1847}
1848
1849/**
1850 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1851 * @hw: pointer to the HW structure
1852 *
1853 * The automatic gain control (agc) normalizes the amplitude of the
1854 * received signal, adjusting for the attenuation produced by the
1855 * cable. By reading the AGC registers, which represent the
1856 * combination of coarse and fine gain value, the value can be put
1857 * into a lookup table to obtain the approximate cable length
1858 * for each channel.
1859 **/
1860s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1861{
1862 struct e1000_phy_info *phy = &hw->phy;
1863 s32 ret_val;
1864 u16 phy_data, i, agc_value = 0;
1865 u16 cur_agc_index, max_agc_index = 0;
1866 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1867 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1868 IGP02E1000_PHY_AGC_A,
1869 IGP02E1000_PHY_AGC_B,
1870 IGP02E1000_PHY_AGC_C,
1871 IGP02E1000_PHY_AGC_D
1872 };
1873
1874 /* Read the AGC registers for all channels */
1875 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1876 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1877 if (ret_val)
1878 return ret_val;
1879
1880 /* Getting bits 15:9, which represent the combination of
1881 * coarse and fine gain values. The result is a number
1882 * that can be put into the lookup table to obtain the
1883 * approximate cable length.
1884 */
1885 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1886 IGP02E1000_AGC_LENGTH_MASK);
1887
1888 /* Array index bound check. */
1889 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1890 (cur_agc_index == 0))
1891 return -E1000_ERR_PHY;
1892
1893 /* Remove min & max AGC values from calculation. */
1894 if (e1000_igp_2_cable_length_table[min_agc_index] >
1895 e1000_igp_2_cable_length_table[cur_agc_index])
1896 min_agc_index = cur_agc_index;
1897 if (e1000_igp_2_cable_length_table[max_agc_index] <
1898 e1000_igp_2_cable_length_table[cur_agc_index])
1899 max_agc_index = cur_agc_index;
1900
1901 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1902 }
1903
1904 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1905 e1000_igp_2_cable_length_table[max_agc_index]);
1906 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1907
1908 /* Calculate cable length with the error range of +/- 10 meters. */
1909 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1910 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1911 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1912
1913 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1914
1915 return 0;
1916}
1917
1918/**
1919 * e1000e_get_phy_info_m88 - Retrieve PHY information
1920 * @hw: pointer to the HW structure
1921 *
1922 * Valid for only copper links. Read the PHY status register (sticky read)
1923 * to verify that link is up. Read the PHY special control register to
1924 * determine the polarity and 10base-T extended distance. Read the PHY
1925 * special status register to determine MDI/MDIx and current speed. If
1926 * speed is 1000, then determine cable length, local and remote receiver.
1927 **/
1928s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1929{
1930 struct e1000_phy_info *phy = &hw->phy;
1931 s32 ret_val;
1932 u16 phy_data;
1933 bool link;
1934
1935 if (phy->media_type != e1000_media_type_copper) {
1936 e_dbg("Phy info is only valid for copper media\n");
1937 return -E1000_ERR_CONFIG;
1938 }
1939
1940 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1941 if (ret_val)
1942 return ret_val;
1943
1944 if (!link) {
1945 e_dbg("Phy info is only valid if link is up\n");
1946 return -E1000_ERR_CONFIG;
1947 }
1948
1949 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1950 if (ret_val)
1951 return ret_val;
1952
1953 phy->polarity_correction = !!(phy_data &
1954 M88E1000_PSCR_POLARITY_REVERSAL);
1955
1956 ret_val = e1000_check_polarity_m88(hw);
1957 if (ret_val)
1958 return ret_val;
1959
1960 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1961 if (ret_val)
1962 return ret_val;
1963
1964 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1965
1966 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1967 ret_val = hw->phy.ops.get_cable_length(hw);
1968 if (ret_val)
1969 return ret_val;
1970
1971 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1972 if (ret_val)
1973 return ret_val;
1974
1975 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1976 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1977
1978 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1979 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1980 } else {
1981 /* Set values to "undefined" */
1982 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1983 phy->local_rx = e1000_1000t_rx_status_undefined;
1984 phy->remote_rx = e1000_1000t_rx_status_undefined;
1985 }
1986
1987 return ret_val;
1988}
1989
1990/**
1991 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1992 * @hw: pointer to the HW structure
1993 *
1994 * Read PHY status to determine if link is up. If link is up, then
1995 * set/determine 10base-T extended distance and polarity correction. Read
1996 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1997 * determine on the cable length, local and remote receiver.
1998 **/
1999s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2000{
2001 struct e1000_phy_info *phy = &hw->phy;
2002 s32 ret_val;
2003 u16 data;
2004 bool link;
2005
2006 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2007 if (ret_val)
2008 return ret_val;
2009
2010 if (!link) {
2011 e_dbg("Phy info is only valid if link is up\n");
2012 return -E1000_ERR_CONFIG;
2013 }
2014
2015 phy->polarity_correction = true;
2016
2017 ret_val = e1000_check_polarity_igp(hw);
2018 if (ret_val)
2019 return ret_val;
2020
2021 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2022 if (ret_val)
2023 return ret_val;
2024
2025 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2026
2027 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2028 IGP01E1000_PSSR_SPEED_1000MBPS) {
2029 ret_val = phy->ops.get_cable_length(hw);
2030 if (ret_val)
2031 return ret_val;
2032
2033 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2034 if (ret_val)
2035 return ret_val;
2036
2037 phy->local_rx = (data & LPA_1000LOCALRXOK)
2038 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2039
2040 phy->remote_rx = (data & LPA_1000REMRXOK)
2041 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2042 } else {
2043 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2044 phy->local_rx = e1000_1000t_rx_status_undefined;
2045 phy->remote_rx = e1000_1000t_rx_status_undefined;
2046 }
2047
2048 return ret_val;
2049}
2050
2051/**
2052 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2053 * @hw: pointer to the HW structure
2054 *
2055 * Populates "phy" structure with various feature states.
2056 **/
2057s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2058{
2059 struct e1000_phy_info *phy = &hw->phy;
2060 s32 ret_val;
2061 u16 data;
2062 bool link;
2063
2064 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2065 if (ret_val)
2066 return ret_val;
2067
2068 if (!link) {
2069 e_dbg("Phy info is only valid if link is up\n");
2070 return -E1000_ERR_CONFIG;
2071 }
2072
2073 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2074 if (ret_val)
2075 return ret_val;
2076 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2077
2078 if (phy->polarity_correction) {
2079 ret_val = e1000_check_polarity_ife(hw);
2080 if (ret_val)
2081 return ret_val;
2082 } else {
2083 /* Polarity is forced */
2084 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2085 ? e1000_rev_polarity_reversed
2086 : e1000_rev_polarity_normal);
2087 }
2088
2089 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2090 if (ret_val)
2091 return ret_val;
2092
2093 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2094
2095 /* The following parameters are undefined for 10/100 operation. */
2096 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2097 phy->local_rx = e1000_1000t_rx_status_undefined;
2098 phy->remote_rx = e1000_1000t_rx_status_undefined;
2099
2100 return 0;
2101}
2102
2103/**
2104 * e1000e_phy_sw_reset - PHY software reset
2105 * @hw: pointer to the HW structure
2106 *
2107 * Does a software reset of the PHY by reading the PHY control register and
2108 * setting/write the control register reset bit to the PHY.
2109 **/
2110s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2111{
2112 s32 ret_val;
2113 u16 phy_ctrl;
2114
2115 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2116 if (ret_val)
2117 return ret_val;
2118
2119 phy_ctrl |= BMCR_RESET;
2120 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2121 if (ret_val)
2122 return ret_val;
2123
2124 udelay(1);
2125
2126 return ret_val;
2127}
2128
2129/**
2130 * e1000e_phy_hw_reset_generic - PHY hardware reset
2131 * @hw: pointer to the HW structure
2132 *
2133 * Verify the reset block is not blocking us from resetting. Acquire
2134 * semaphore (if necessary) and read/set/write the device control reset
2135 * bit in the PHY. Wait the appropriate delay time for the device to
2136 * reset and release the semaphore (if necessary).
2137 **/
2138s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2139{
2140 struct e1000_phy_info *phy = &hw->phy;
2141 s32 ret_val;
2142 u32 ctrl;
2143
2144 if (phy->ops.check_reset_block) {
2145 ret_val = phy->ops.check_reset_block(hw);
2146 if (ret_val)
2147 return 0;
2148 }
2149
2150 ret_val = phy->ops.acquire(hw);
2151 if (ret_val)
2152 return ret_val;
2153
2154 ctrl = er32(CTRL);
2155 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2156 e1e_flush();
2157
2158 udelay(phy->reset_delay_us);
2159
2160 ew32(CTRL, ctrl);
2161 e1e_flush();
2162
2163 usleep_range(150, 300);
2164
2165 phy->ops.release(hw);
2166
2167 return phy->ops.get_cfg_done(hw);
2168}
2169
2170/**
2171 * e1000e_get_cfg_done_generic - Generic configuration done
2172 * @hw: pointer to the HW structure
2173 *
2174 * Generic function to wait 10 milli-seconds for configuration to complete
2175 * and return success.
2176 **/
2177s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2178{
2179 mdelay(10);
2180
2181 return 0;
2182}
2183
2184/**
2185 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2186 * @hw: pointer to the HW structure
2187 *
2188 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2189 **/
2190s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2191{
2192 e_dbg("Running IGP 3 PHY init script\n");
2193
2194 /* PHY init IGP 3 */
2195 /* Enable rise/fall, 10-mode work in class-A */
2196 e1e_wphy(hw, 0x2F5B, 0x9018);
2197 /* Remove all caps from Replica path filter */
2198 e1e_wphy(hw, 0x2F52, 0x0000);
2199 /* Bias trimming for ADC, AFE and Driver (Default) */
2200 e1e_wphy(hw, 0x2FB1, 0x8B24);
2201 /* Increase Hybrid poly bias */
2202 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2203 /* Add 4% to Tx amplitude in Gig mode */
2204 e1e_wphy(hw, 0x2010, 0x10B0);
2205 /* Disable trimming (TTT) */
2206 e1e_wphy(hw, 0x2011, 0x0000);
2207 /* Poly DC correction to 94.6% + 2% for all channels */
2208 e1e_wphy(hw, 0x20DD, 0x249A);
2209 /* ABS DC correction to 95.9% */
2210 e1e_wphy(hw, 0x20DE, 0x00D3);
2211 /* BG temp curve trim */
2212 e1e_wphy(hw, 0x28B4, 0x04CE);
2213 /* Increasing ADC OPAMP stage 1 currents to max */
2214 e1e_wphy(hw, 0x2F70, 0x29E4);
2215 /* Force 1000 ( required for enabling PHY regs configuration) */
2216 e1e_wphy(hw, 0x0000, 0x0140);
2217 /* Set upd_freq to 6 */
2218 e1e_wphy(hw, 0x1F30, 0x1606);
2219 /* Disable NPDFE */
2220 e1e_wphy(hw, 0x1F31, 0xB814);
2221 /* Disable adaptive fixed FFE (Default) */
2222 e1e_wphy(hw, 0x1F35, 0x002A);
2223 /* Enable FFE hysteresis */
2224 e1e_wphy(hw, 0x1F3E, 0x0067);
2225 /* Fixed FFE for short cable lengths */
2226 e1e_wphy(hw, 0x1F54, 0x0065);
2227 /* Fixed FFE for medium cable lengths */
2228 e1e_wphy(hw, 0x1F55, 0x002A);
2229 /* Fixed FFE for long cable lengths */
2230 e1e_wphy(hw, 0x1F56, 0x002A);
2231 /* Enable Adaptive Clip Threshold */
2232 e1e_wphy(hw, 0x1F72, 0x3FB0);
2233 /* AHT reset limit to 1 */
2234 e1e_wphy(hw, 0x1F76, 0xC0FF);
2235 /* Set AHT master delay to 127 msec */
2236 e1e_wphy(hw, 0x1F77, 0x1DEC);
2237 /* Set scan bits for AHT */
2238 e1e_wphy(hw, 0x1F78, 0xF9EF);
2239 /* Set AHT Preset bits */
2240 e1e_wphy(hw, 0x1F79, 0x0210);
2241 /* Change integ_factor of channel A to 3 */
2242 e1e_wphy(hw, 0x1895, 0x0003);
2243 /* Change prop_factor of channels BCD to 8 */
2244 e1e_wphy(hw, 0x1796, 0x0008);
2245 /* Change cg_icount + enable integbp for channels BCD */
2246 e1e_wphy(hw, 0x1798, 0xD008);
2247 /* Change cg_icount + enable integbp + change prop_factor_master
2248 * to 8 for channel A
2249 */
2250 e1e_wphy(hw, 0x1898, 0xD918);
2251 /* Disable AHT in Slave mode on channel A */
2252 e1e_wphy(hw, 0x187A, 0x0800);
2253 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2254 * Enable SPD+B2B
2255 */
2256 e1e_wphy(hw, 0x0019, 0x008D);
2257 /* Enable restart AN on an1000_dis change */
2258 e1e_wphy(hw, 0x001B, 0x2080);
2259 /* Enable wh_fifo read clock in 10/100 modes */
2260 e1e_wphy(hw, 0x0014, 0x0045);
2261 /* Restart AN, Speed selection is 1000 */
2262 e1e_wphy(hw, 0x0000, 0x1340);
2263
2264 return 0;
2265}
2266
2267/**
2268 * e1000e_get_phy_type_from_id - Get PHY type from id
2269 * @phy_id: phy_id read from the phy
2270 *
2271 * Returns the phy type from the id.
2272 **/
2273enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2274{
2275 enum e1000_phy_type phy_type = e1000_phy_unknown;
2276
2277 switch (phy_id) {
2278 case M88E1000_I_PHY_ID:
2279 case M88E1000_E_PHY_ID:
2280 case M88E1111_I_PHY_ID:
2281 case M88E1011_I_PHY_ID:
2282 phy_type = e1000_phy_m88;
2283 break;
2284 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2285 phy_type = e1000_phy_igp_2;
2286 break;
2287 case GG82563_E_PHY_ID:
2288 phy_type = e1000_phy_gg82563;
2289 break;
2290 case IGP03E1000_E_PHY_ID:
2291 phy_type = e1000_phy_igp_3;
2292 break;
2293 case IFE_E_PHY_ID:
2294 case IFE_PLUS_E_PHY_ID:
2295 case IFE_C_E_PHY_ID:
2296 phy_type = e1000_phy_ife;
2297 break;
2298 case BME1000_E_PHY_ID:
2299 case BME1000_E_PHY_ID_R2:
2300 phy_type = e1000_phy_bm;
2301 break;
2302 case I82578_E_PHY_ID:
2303 phy_type = e1000_phy_82578;
2304 break;
2305 case I82577_E_PHY_ID:
2306 phy_type = e1000_phy_82577;
2307 break;
2308 case I82579_E_PHY_ID:
2309 phy_type = e1000_phy_82579;
2310 break;
2311 case I217_E_PHY_ID:
2312 phy_type = e1000_phy_i217;
2313 break;
2314 default:
2315 phy_type = e1000_phy_unknown;
2316 break;
2317 }
2318 return phy_type;
2319}
2320
2321/**
2322 * e1000e_determine_phy_address - Determines PHY address.
2323 * @hw: pointer to the HW structure
2324 *
2325 * This uses a trial and error method to loop through possible PHY
2326 * addresses. It tests each by reading the PHY ID registers and
2327 * checking for a match.
2328 **/
2329s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2330{
2331 u32 phy_addr = 0;
2332 u32 i;
2333 enum e1000_phy_type phy_type = e1000_phy_unknown;
2334
2335 hw->phy.id = phy_type;
2336
2337 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2338 hw->phy.addr = phy_addr;
2339 i = 0;
2340
2341 do {
2342 e1000e_get_phy_id(hw);
2343 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2344
2345 /* If phy_type is valid, break - we found our
2346 * PHY address
2347 */
2348 if (phy_type != e1000_phy_unknown)
2349 return 0;
2350
2351 usleep_range(1000, 2000);
2352 i++;
2353 } while (i < 10);
2354 }
2355
2356 return -E1000_ERR_PHY_TYPE;
2357}
2358
2359/**
2360 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2361 * @page: page to access
2362 * @reg: register to check
2363 *
2364 * Returns the phy address for the page requested.
2365 **/
2366static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2367{
2368 u32 phy_addr = 2;
2369
2370 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2371 phy_addr = 1;
2372
2373 return phy_addr;
2374}
2375
2376/**
2377 * e1000e_write_phy_reg_bm - Write BM PHY register
2378 * @hw: pointer to the HW structure
2379 * @offset: register offset to write to
2380 * @data: data to write at register offset
2381 *
2382 * Acquires semaphore, if necessary, then writes the data to PHY register
2383 * at the offset. Release any acquired semaphores before exiting.
2384 **/
2385s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2386{
2387 s32 ret_val;
2388 u32 page = offset >> IGP_PAGE_SHIFT;
2389
2390 ret_val = hw->phy.ops.acquire(hw);
2391 if (ret_val)
2392 return ret_val;
2393
2394 /* Page 800 works differently than the rest so it has its own func */
2395 if (page == BM_WUC_PAGE) {
2396 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2397 false, false);
2398 goto release;
2399 }
2400
2401 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2402
2403 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2404 u32 page_shift, page_select;
2405
2406 /* Page select is register 31 for phy address 1 and 22 for
2407 * phy address 2 and 3. Page select is shifted only for
2408 * phy address 1.
2409 */
2410 if (hw->phy.addr == 1) {
2411 page_shift = IGP_PAGE_SHIFT;
2412 page_select = IGP01E1000_PHY_PAGE_SELECT;
2413 } else {
2414 page_shift = 0;
2415 page_select = BM_PHY_PAGE_SELECT;
2416 }
2417
2418 /* Page is shifted left, PHY expects (page x 32) */
2419 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2420 (page << page_shift));
2421 if (ret_val)
2422 goto release;
2423 }
2424
2425 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2426 data);
2427
2428release:
2429 hw->phy.ops.release(hw);
2430 return ret_val;
2431}
2432
2433/**
2434 * e1000e_read_phy_reg_bm - Read BM PHY register
2435 * @hw: pointer to the HW structure
2436 * @offset: register offset to be read
2437 * @data: pointer to the read data
2438 *
2439 * Acquires semaphore, if necessary, then reads the PHY register at offset
2440 * and storing the retrieved information in data. Release any acquired
2441 * semaphores before exiting.
2442 **/
2443s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2444{
2445 s32 ret_val;
2446 u32 page = offset >> IGP_PAGE_SHIFT;
2447
2448 ret_val = hw->phy.ops.acquire(hw);
2449 if (ret_val)
2450 return ret_val;
2451
2452 /* Page 800 works differently than the rest so it has its own func */
2453 if (page == BM_WUC_PAGE) {
2454 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2455 true, false);
2456 goto release;
2457 }
2458
2459 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2460
2461 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2462 u32 page_shift, page_select;
2463
2464 /* Page select is register 31 for phy address 1 and 22 for
2465 * phy address 2 and 3. Page select is shifted only for
2466 * phy address 1.
2467 */
2468 if (hw->phy.addr == 1) {
2469 page_shift = IGP_PAGE_SHIFT;
2470 page_select = IGP01E1000_PHY_PAGE_SELECT;
2471 } else {
2472 page_shift = 0;
2473 page_select = BM_PHY_PAGE_SELECT;
2474 }
2475
2476 /* Page is shifted left, PHY expects (page x 32) */
2477 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2478 (page << page_shift));
2479 if (ret_val)
2480 goto release;
2481 }
2482
2483 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2484 data);
2485release:
2486 hw->phy.ops.release(hw);
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2492 * @hw: pointer to the HW structure
2493 * @offset: register offset to be read
2494 * @data: pointer to the read data
2495 *
2496 * Acquires semaphore, if necessary, then reads the PHY register at offset
2497 * and storing the retrieved information in data. Release any acquired
2498 * semaphores before exiting.
2499 **/
2500s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2501{
2502 s32 ret_val;
2503 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2504
2505 ret_val = hw->phy.ops.acquire(hw);
2506 if (ret_val)
2507 return ret_val;
2508
2509 /* Page 800 works differently than the rest so it has its own func */
2510 if (page == BM_WUC_PAGE) {
2511 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2512 true, false);
2513 goto release;
2514 }
2515
2516 hw->phy.addr = 1;
2517
2518 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2519 /* Page is shifted left, PHY expects (page x 32) */
2520 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2521 page);
2522
2523 if (ret_val)
2524 goto release;
2525 }
2526
2527 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2528 data);
2529release:
2530 hw->phy.ops.release(hw);
2531 return ret_val;
2532}
2533
2534/**
2535 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2536 * @hw: pointer to the HW structure
2537 * @offset: register offset to write to
2538 * @data: data to write at register offset
2539 *
2540 * Acquires semaphore, if necessary, then writes the data to PHY register
2541 * at the offset. Release any acquired semaphores before exiting.
2542 **/
2543s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2544{
2545 s32 ret_val;
2546 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2547
2548 ret_val = hw->phy.ops.acquire(hw);
2549 if (ret_val)
2550 return ret_val;
2551
2552 /* Page 800 works differently than the rest so it has its own func */
2553 if (page == BM_WUC_PAGE) {
2554 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2555 false, false);
2556 goto release;
2557 }
2558
2559 hw->phy.addr = 1;
2560
2561 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2562 /* Page is shifted left, PHY expects (page x 32) */
2563 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2564 page);
2565
2566 if (ret_val)
2567 goto release;
2568 }
2569
2570 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2571 data);
2572
2573release:
2574 hw->phy.ops.release(hw);
2575 return ret_val;
2576}
2577
2578/**
2579 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2580 * @hw: pointer to the HW structure
2581 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2582 *
2583 * Assumes semaphore already acquired and phy_reg points to a valid memory
2584 * address to store contents of the BM_WUC_ENABLE_REG register.
2585 **/
2586s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2587{
2588 s32 ret_val;
2589 u16 temp;
2590
2591 /* All page select, port ctrl and wakeup registers use phy address 1 */
2592 hw->phy.addr = 1;
2593
2594 /* Select Port Control Registers page */
2595 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2596 if (ret_val) {
2597 e_dbg("Could not set Port Control page\n");
2598 return ret_val;
2599 }
2600
2601 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2602 if (ret_val) {
2603 e_dbg("Could not read PHY register %d.%d\n",
2604 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2605 return ret_val;
2606 }
2607
2608 /* Enable both PHY wakeup mode and Wakeup register page writes.
2609 * Prevent a power state change by disabling ME and Host PHY wakeup.
2610 */
2611 temp = *phy_reg;
2612 temp |= BM_WUC_ENABLE_BIT;
2613 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2614
2615 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2616 if (ret_val) {
2617 e_dbg("Could not write PHY register %d.%d\n",
2618 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2619 return ret_val;
2620 }
2621
2622 /* Select Host Wakeup Registers page - caller now able to write
2623 * registers on the Wakeup registers page
2624 */
2625 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2626}
2627
2628/**
2629 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2630 * @hw: pointer to the HW structure
2631 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2632 *
2633 * Restore BM_WUC_ENABLE_REG to its original value.
2634 *
2635 * Assumes semaphore already acquired and *phy_reg is the contents of the
2636 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2637 * caller.
2638 **/
2639s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2640{
2641 s32 ret_val;
2642
2643 /* Select Port Control Registers page */
2644 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2645 if (ret_val) {
2646 e_dbg("Could not set Port Control page\n");
2647 return ret_val;
2648 }
2649
2650 /* Restore 769.17 to its original value */
2651 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2652 if (ret_val)
2653 e_dbg("Could not restore PHY register %d.%d\n",
2654 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2655
2656 return ret_val;
2657}
2658
2659/**
2660 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2661 * @hw: pointer to the HW structure
2662 * @offset: register offset to be read or written
2663 * @data: pointer to the data to read or write
2664 * @read: determines if operation is read or write
2665 * @page_set: BM_WUC_PAGE already set and access enabled
2666 *
2667 * Read the PHY register at offset and store the retrieved information in
2668 * data, or write data to PHY register at offset. Note the procedure to
2669 * access the PHY wakeup registers is different than reading the other PHY
2670 * registers. It works as such:
2671 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2672 * 2) Set page to 800 for host (801 if we were manageability)
2673 * 3) Write the address using the address opcode (0x11)
2674 * 4) Read or write the data using the data opcode (0x12)
2675 * 5) Restore 769.17.2 to its original value
2676 *
2677 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2678 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2679 *
2680 * Assumes semaphore is already acquired. When page_set==true, assumes
2681 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2682 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2683 **/
2684static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2685 u16 *data, bool read, bool page_set)
2686{
2687 s32 ret_val;
2688 u16 reg = BM_PHY_REG_NUM(offset);
2689 u16 page = BM_PHY_REG_PAGE(offset);
2690 u16 phy_reg = 0;
2691
2692 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2693 if ((hw->mac.type == e1000_pchlan) &&
2694 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2695 e_dbg("Attempting to access page %d while gig enabled.\n",
2696 page);
2697
2698 if (!page_set) {
2699 /* Enable access to PHY wakeup registers */
2700 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2701 if (ret_val) {
2702 e_dbg("Could not enable PHY wakeup reg access\n");
2703 return ret_val;
2704 }
2705 }
2706
2707 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2708
2709 /* Write the Wakeup register page offset value using opcode 0x11 */
2710 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2711 if (ret_val) {
2712 e_dbg("Could not write address opcode to page %d\n", page);
2713 return ret_val;
2714 }
2715
2716 if (read) {
2717 /* Read the Wakeup register page value using opcode 0x12 */
2718 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2719 data);
2720 } else {
2721 /* Write the Wakeup register page value using opcode 0x12 */
2722 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2723 *data);
2724 }
2725
2726 if (ret_val) {
2727 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2728 return ret_val;
2729 }
2730
2731 if (!page_set)
2732 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2733
2734 return ret_val;
2735}
2736
2737/**
2738 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2739 * @hw: pointer to the HW structure
2740 *
2741 * In the case of a PHY power down to save power, or to turn off link during a
2742 * driver unload, or wake on lan is not enabled, restore the link to previous
2743 * settings.
2744 **/
2745void e1000_power_up_phy_copper(struct e1000_hw *hw)
2746{
2747 u16 mii_reg = 0;
2748 int ret;
2749
2750 /* The PHY will retain its settings across a power down/up cycle */
2751 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2752 if (ret) {
2753 e_dbg("Error reading PHY register\n");
2754 return;
2755 }
2756 mii_reg &= ~BMCR_PDOWN;
2757 e1e_wphy(hw, MII_BMCR, mii_reg);
2758}
2759
2760/**
2761 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2762 * @hw: pointer to the HW structure
2763 *
2764 * In the case of a PHY power down to save power, or to turn off link during a
2765 * driver unload, or wake on lan is not enabled, restore the link to previous
2766 * settings.
2767 **/
2768void e1000_power_down_phy_copper(struct e1000_hw *hw)
2769{
2770 u16 mii_reg = 0;
2771 int ret;
2772
2773 /* The PHY will retain its settings across a power down/up cycle */
2774 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2775 if (ret) {
2776 e_dbg("Error reading PHY register\n");
2777 return;
2778 }
2779 mii_reg |= BMCR_PDOWN;
2780 e1e_wphy(hw, MII_BMCR, mii_reg);
2781 usleep_range(1000, 2000);
2782}
2783
2784/**
2785 * __e1000_read_phy_reg_hv - Read HV PHY register
2786 * @hw: pointer to the HW structure
2787 * @offset: register offset to be read
2788 * @data: pointer to the read data
2789 * @locked: semaphore has already been acquired or not
2790 * @page_set: BM_WUC_PAGE already set and access enabled
2791 *
2792 * Acquires semaphore, if necessary, then reads the PHY register at offset
2793 * and stores the retrieved information in data. Release any acquired
2794 * semaphore before exiting.
2795 **/
2796static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2797 bool locked, bool page_set)
2798{
2799 s32 ret_val;
2800 u16 page = BM_PHY_REG_PAGE(offset);
2801 u16 reg = BM_PHY_REG_NUM(offset);
2802 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2803
2804 if (!locked) {
2805 ret_val = hw->phy.ops.acquire(hw);
2806 if (ret_val)
2807 return ret_val;
2808 }
2809
2810 /* Page 800 works differently than the rest so it has its own func */
2811 if (page == BM_WUC_PAGE) {
2812 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2813 true, page_set);
2814 goto out;
2815 }
2816
2817 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2818 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2819 data, true);
2820 goto out;
2821 }
2822
2823 if (!page_set) {
2824 if (page == HV_INTC_FC_PAGE_START)
2825 page = 0;
2826
2827 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2828 /* Page is shifted left, PHY expects (page x 32) */
2829 ret_val = e1000_set_page_igp(hw,
2830 (page << IGP_PAGE_SHIFT));
2831
2832 hw->phy.addr = phy_addr;
2833
2834 if (ret_val)
2835 goto out;
2836 }
2837 }
2838
2839 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2840 page << IGP_PAGE_SHIFT, reg);
2841
2842 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2843out:
2844 if (!locked)
2845 hw->phy.ops.release(hw);
2846
2847 return ret_val;
2848}
2849
2850/**
2851 * e1000_read_phy_reg_hv - Read HV PHY register
2852 * @hw: pointer to the HW structure
2853 * @offset: register offset to be read
2854 * @data: pointer to the read data
2855 *
2856 * Acquires semaphore then reads the PHY register at offset and stores
2857 * the retrieved information in data. Release the acquired semaphore
2858 * before exiting.
2859 **/
2860s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2861{
2862 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2863}
2864
2865/**
2866 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2867 * @hw: pointer to the HW structure
2868 * @offset: register offset to be read
2869 * @data: pointer to the read data
2870 *
2871 * Reads the PHY register at offset and stores the retrieved information
2872 * in data. Assumes semaphore already acquired.
2873 **/
2874s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2875{
2876 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2877}
2878
2879/**
2880 * e1000_read_phy_reg_page_hv - Read HV PHY register
2881 * @hw: pointer to the HW structure
2882 * @offset: register offset to write to
2883 * @data: data to write at register offset
2884 *
2885 * Reads the PHY register at offset and stores the retrieved information
2886 * in data. Assumes semaphore already acquired and page already set.
2887 **/
2888s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2889{
2890 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2891}
2892
2893/**
2894 * __e1000_write_phy_reg_hv - Write HV PHY register
2895 * @hw: pointer to the HW structure
2896 * @offset: register offset to write to
2897 * @data: data to write at register offset
2898 * @locked: semaphore has already been acquired or not
2899 * @page_set: BM_WUC_PAGE already set and access enabled
2900 *
2901 * Acquires semaphore, if necessary, then writes the data to PHY register
2902 * at the offset. Release any acquired semaphores before exiting.
2903 **/
2904static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2905 bool locked, bool page_set)
2906{
2907 s32 ret_val;
2908 u16 page = BM_PHY_REG_PAGE(offset);
2909 u16 reg = BM_PHY_REG_NUM(offset);
2910 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2911
2912 if (!locked) {
2913 ret_val = hw->phy.ops.acquire(hw);
2914 if (ret_val)
2915 return ret_val;
2916 }
2917
2918 /* Page 800 works differently than the rest so it has its own func */
2919 if (page == BM_WUC_PAGE) {
2920 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2921 false, page_set);
2922 goto out;
2923 }
2924
2925 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2926 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2927 &data, false);
2928 goto out;
2929 }
2930
2931 if (!page_set) {
2932 if (page == HV_INTC_FC_PAGE_START)
2933 page = 0;
2934
2935 /* Workaround MDIO accesses being disabled after entering IEEE
2936 * Power Down (when bit 11 of the PHY Control register is set)
2937 */
2938 if ((hw->phy.type == e1000_phy_82578) &&
2939 (hw->phy.revision >= 1) &&
2940 (hw->phy.addr == 2) &&
2941 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2942 u16 data2 = 0x7EFF;
2943
2944 ret_val = e1000_access_phy_debug_regs_hv(hw,
2945 BIT(6) | 0x3,
2946 &data2, false);
2947 if (ret_val)
2948 goto out;
2949 }
2950
2951 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2952 /* Page is shifted left, PHY expects (page x 32) */
2953 ret_val = e1000_set_page_igp(hw,
2954 (page << IGP_PAGE_SHIFT));
2955
2956 hw->phy.addr = phy_addr;
2957
2958 if (ret_val)
2959 goto out;
2960 }
2961 }
2962
2963 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2964 page << IGP_PAGE_SHIFT, reg);
2965
2966 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2967 data);
2968
2969out:
2970 if (!locked)
2971 hw->phy.ops.release(hw);
2972
2973 return ret_val;
2974}
2975
2976/**
2977 * e1000_write_phy_reg_hv - Write HV PHY register
2978 * @hw: pointer to the HW structure
2979 * @offset: register offset to write to
2980 * @data: data to write at register offset
2981 *
2982 * Acquires semaphore then writes the data to PHY register at the offset.
2983 * Release the acquired semaphores before exiting.
2984 **/
2985s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2986{
2987 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2988}
2989
2990/**
2991 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2992 * @hw: pointer to the HW structure
2993 * @offset: register offset to write to
2994 * @data: data to write at register offset
2995 *
2996 * Writes the data to PHY register at the offset. Assumes semaphore
2997 * already acquired.
2998 **/
2999s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3000{
3001 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3002}
3003
3004/**
3005 * e1000_write_phy_reg_page_hv - Write HV PHY register
3006 * @hw: pointer to the HW structure
3007 * @offset: register offset to write to
3008 * @data: data to write at register offset
3009 *
3010 * Writes the data to PHY register at the offset. Assumes semaphore
3011 * already acquired and page already set.
3012 **/
3013s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3014{
3015 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3016}
3017
3018/**
3019 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3020 * @page: page to be accessed
3021 **/
3022static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3023{
3024 u32 phy_addr = 2;
3025
3026 if (page >= HV_INTC_FC_PAGE_START)
3027 phy_addr = 1;
3028
3029 return phy_addr;
3030}
3031
3032/**
3033 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3034 * @hw: pointer to the HW structure
3035 * @offset: register offset to be read or written
3036 * @data: pointer to the data to be read or written
3037 * @read: determines if operation is read or write
3038 *
3039 * Reads the PHY register at offset and stores the retrieved information
3040 * in data. Assumes semaphore already acquired. Note that the procedure
3041 * to access these regs uses the address port and data port to read/write.
3042 * These accesses done with PHY address 2 and without using pages.
3043 **/
3044static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3045 u16 *data, bool read)
3046{
3047 s32 ret_val;
3048 u32 addr_reg;
3049 u32 data_reg;
3050
3051 /* This takes care of the difference with desktop vs mobile phy */
3052 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3053 I82578_ADDR_REG : I82577_ADDR_REG);
3054 data_reg = addr_reg + 1;
3055
3056 /* All operations in this function are phy address 2 */
3057 hw->phy.addr = 2;
3058
3059 /* masking with 0x3F to remove the page from offset */
3060 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3061 if (ret_val) {
3062 e_dbg("Could not write the Address Offset port register\n");
3063 return ret_val;
3064 }
3065
3066 /* Read or write the data value next */
3067 if (read)
3068 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3069 else
3070 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3071
3072 if (ret_val)
3073 e_dbg("Could not access the Data port register\n");
3074
3075 return ret_val;
3076}
3077
3078/**
3079 * e1000_link_stall_workaround_hv - Si workaround
3080 * @hw: pointer to the HW structure
3081 *
3082 * This function works around a Si bug where the link partner can get
3083 * a link up indication before the PHY does. If small packets are sent
3084 * by the link partner they can be placed in the packet buffer without
3085 * being properly accounted for by the PHY and will stall preventing
3086 * further packets from being received. The workaround is to clear the
3087 * packet buffer after the PHY detects link up.
3088 **/
3089s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3090{
3091 s32 ret_val = 0;
3092 u16 data;
3093
3094 if (hw->phy.type != e1000_phy_82578)
3095 return 0;
3096
3097 /* Do not apply workaround if in PHY loopback bit 14 set */
3098 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3099 if (ret_val) {
3100 e_dbg("Error reading PHY register\n");
3101 return ret_val;
3102 }
3103 if (data & BMCR_LOOPBACK)
3104 return 0;
3105
3106 /* check if link is up and at 1Gbps */
3107 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3108 if (ret_val)
3109 return ret_val;
3110
3111 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3112 BM_CS_STATUS_SPEED_MASK);
3113
3114 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3115 BM_CS_STATUS_SPEED_1000))
3116 return 0;
3117
3118 msleep(200);
3119
3120 /* flush the packets in the fifo buffer */
3121 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3122 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3123 HV_MUX_DATA_CTRL_FORCE_SPEED));
3124 if (ret_val)
3125 return ret_val;
3126
3127 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3128}
3129
3130/**
3131 * e1000_check_polarity_82577 - Checks the polarity.
3132 * @hw: pointer to the HW structure
3133 *
3134 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3135 *
3136 * Polarity is determined based on the PHY specific status register.
3137 **/
3138s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3139{
3140 struct e1000_phy_info *phy = &hw->phy;
3141 s32 ret_val;
3142 u16 data;
3143
3144 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3145
3146 if (!ret_val)
3147 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3148 ? e1000_rev_polarity_reversed
3149 : e1000_rev_polarity_normal);
3150
3151 return ret_val;
3152}
3153
3154/**
3155 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3156 * @hw: pointer to the HW structure
3157 *
3158 * Calls the PHY setup function to force speed and duplex.
3159 **/
3160s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3161{
3162 struct e1000_phy_info *phy = &hw->phy;
3163 s32 ret_val;
3164 u16 phy_data;
3165 bool link;
3166
3167 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3168 if (ret_val)
3169 return ret_val;
3170
3171 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3172
3173 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3174 if (ret_val)
3175 return ret_val;
3176
3177 udelay(1);
3178
3179 if (phy->autoneg_wait_to_complete) {
3180 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3181
3182 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3183 100000, &link);
3184 if (ret_val)
3185 return ret_val;
3186
3187 if (!link)
3188 e_dbg("Link taking longer than expected.\n");
3189
3190 /* Try once more */
3191 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3192 100000, &link);
3193 }
3194
3195 return ret_val;
3196}
3197
3198/**
3199 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3200 * @hw: pointer to the HW structure
3201 *
3202 * Read PHY status to determine if link is up. If link is up, then
3203 * set/determine 10base-T extended distance and polarity correction. Read
3204 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3205 * determine on the cable length, local and remote receiver.
3206 **/
3207s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3208{
3209 struct e1000_phy_info *phy = &hw->phy;
3210 s32 ret_val;
3211 u16 data;
3212 bool link;
3213
3214 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3215 if (ret_val)
3216 return ret_val;
3217
3218 if (!link) {
3219 e_dbg("Phy info is only valid if link is up\n");
3220 return -E1000_ERR_CONFIG;
3221 }
3222
3223 phy->polarity_correction = true;
3224
3225 ret_val = e1000_check_polarity_82577(hw);
3226 if (ret_val)
3227 return ret_val;
3228
3229 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3230 if (ret_val)
3231 return ret_val;
3232
3233 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3234
3235 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3236 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3237 ret_val = hw->phy.ops.get_cable_length(hw);
3238 if (ret_val)
3239 return ret_val;
3240
3241 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3242 if (ret_val)
3243 return ret_val;
3244
3245 phy->local_rx = (data & LPA_1000LOCALRXOK)
3246 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3247
3248 phy->remote_rx = (data & LPA_1000REMRXOK)
3249 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3250 } else {
3251 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3252 phy->local_rx = e1000_1000t_rx_status_undefined;
3253 phy->remote_rx = e1000_1000t_rx_status_undefined;
3254 }
3255
3256 return 0;
3257}
3258
3259/**
3260 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3261 * @hw: pointer to the HW structure
3262 *
3263 * Reads the diagnostic status register and verifies result is valid before
3264 * placing it in the phy_cable_length field.
3265 **/
3266s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3267{
3268 struct e1000_phy_info *phy = &hw->phy;
3269 s32 ret_val;
3270 u16 phy_data, length;
3271
3272 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3273 if (ret_val)
3274 return ret_val;
3275
3276 length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);
3277
3278 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3279 return -E1000_ERR_PHY;
3280
3281 phy->cable_length = length;
3282
3283 return 0;
3284}
1// SPDX-License-Identifier: GPL-2.0
2/* Intel PRO/1000 Linux driver
3 * Copyright(c) 1999 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 * Contact Information:
18 * Linux NICS <linux.nics@intel.com>
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 */
22
23#include "e1000.h"
24
25static s32 e1000_wait_autoneg(struct e1000_hw *hw);
26static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
27 u16 *data, bool read, bool page_set);
28static u32 e1000_get_phy_addr_for_hv_page(u32 page);
29static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
30 u16 *data, bool read);
31
32/* Cable length tables */
33static const u16 e1000_m88_cable_length_table[] = {
34 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
35};
36
37#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
38 ARRAY_SIZE(e1000_m88_cable_length_table)
39
40static const u16 e1000_igp_2_cable_length_table[] = {
41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
42 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
43 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
44 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
45 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
46 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
47 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
48 124
49};
50
51#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
53
54/**
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
57 *
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
61 **/
62s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
63{
64 u32 manc;
65
66 manc = er32(MANC);
67
68 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
69}
70
71/**
72 * e1000e_get_phy_id - Retrieve the PHY ID and revision
73 * @hw: pointer to the HW structure
74 *
75 * Reads the PHY registers and stores the PHY ID and possibly the PHY
76 * revision in the hardware structure.
77 **/
78s32 e1000e_get_phy_id(struct e1000_hw *hw)
79{
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val = 0;
82 u16 phy_id;
83 u16 retry_count = 0;
84
85 if (!phy->ops.read_reg)
86 return 0;
87
88 while (retry_count < 2) {
89 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
90 if (ret_val)
91 return ret_val;
92
93 phy->id = (u32)(phy_id << 16);
94 usleep_range(20, 40);
95 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
96 if (ret_val)
97 return ret_val;
98
99 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
100 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
101
102 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
103 return 0;
104
105 retry_count++;
106 }
107
108 return 0;
109}
110
111/**
112 * e1000e_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure
114 *
115 * Reset the digital signal processor.
116 **/
117s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
118{
119 s32 ret_val;
120
121 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
122 if (ret_val)
123 return ret_val;
124
125 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
126}
127
128/**
129 * e1000e_read_phy_reg_mdic - Read MDI control register
130 * @hw: pointer to the HW structure
131 * @offset: register offset to be read
132 * @data: pointer to the read data
133 *
134 * Reads the MDI control register in the PHY at offset and stores the
135 * information read to data.
136 **/
137s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
138{
139 struct e1000_phy_info *phy = &hw->phy;
140 u32 i, mdic = 0;
141
142 if (offset > MAX_PHY_REG_ADDRESS) {
143 e_dbg("PHY Address %d is out of range\n", offset);
144 return -E1000_ERR_PARAM;
145 }
146
147 /* Set up Op-code, Phy Address, and register offset in the MDI
148 * Control register. The MAC will take care of interfacing with the
149 * PHY to retrieve the desired data.
150 */
151 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
152 (phy->addr << E1000_MDIC_PHY_SHIFT) |
153 (E1000_MDIC_OP_READ));
154
155 ew32(MDIC, mdic);
156
157 /* Poll the ready bit to see if the MDI read completed
158 * Increasing the time out as testing showed failures with
159 * the lower time out
160 */
161 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
162 udelay(50);
163 mdic = er32(MDIC);
164 if (mdic & E1000_MDIC_READY)
165 break;
166 }
167 if (!(mdic & E1000_MDIC_READY)) {
168 e_dbg("MDI Read did not complete\n");
169 return -E1000_ERR_PHY;
170 }
171 if (mdic & E1000_MDIC_ERROR) {
172 e_dbg("MDI Error\n");
173 return -E1000_ERR_PHY;
174 }
175 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
176 e_dbg("MDI Read offset error - requested %d, returned %d\n",
177 offset,
178 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
179 return -E1000_ERR_PHY;
180 }
181 *data = (u16)mdic;
182
183 /* Allow some time after each MDIC transaction to avoid
184 * reading duplicate data in the next MDIC transaction.
185 */
186 if (hw->mac.type == e1000_pch2lan)
187 udelay(100);
188
189 return 0;
190}
191
192/**
193 * e1000e_write_phy_reg_mdic - Write MDI control register
194 * @hw: pointer to the HW structure
195 * @offset: register offset to write to
196 * @data: data to write to register at offset
197 *
198 * Writes data to MDI control register in the PHY at offset.
199 **/
200s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
201{
202 struct e1000_phy_info *phy = &hw->phy;
203 u32 i, mdic = 0;
204
205 if (offset > MAX_PHY_REG_ADDRESS) {
206 e_dbg("PHY Address %d is out of range\n", offset);
207 return -E1000_ERR_PARAM;
208 }
209
210 /* Set up Op-code, Phy Address, and register offset in the MDI
211 * Control register. The MAC will take care of interfacing with the
212 * PHY to retrieve the desired data.
213 */
214 mdic = (((u32)data) |
215 (offset << E1000_MDIC_REG_SHIFT) |
216 (phy->addr << E1000_MDIC_PHY_SHIFT) |
217 (E1000_MDIC_OP_WRITE));
218
219 ew32(MDIC, mdic);
220
221 /* Poll the ready bit to see if the MDI read completed
222 * Increasing the time out as testing showed failures with
223 * the lower time out
224 */
225 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
226 udelay(50);
227 mdic = er32(MDIC);
228 if (mdic & E1000_MDIC_READY)
229 break;
230 }
231 if (!(mdic & E1000_MDIC_READY)) {
232 e_dbg("MDI Write did not complete\n");
233 return -E1000_ERR_PHY;
234 }
235 if (mdic & E1000_MDIC_ERROR) {
236 e_dbg("MDI Error\n");
237 return -E1000_ERR_PHY;
238 }
239 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
240 e_dbg("MDI Write offset error - requested %d, returned %d\n",
241 offset,
242 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
243 return -E1000_ERR_PHY;
244 }
245
246 /* Allow some time after each MDIC transaction to avoid
247 * reading duplicate data in the next MDIC transaction.
248 */
249 if (hw->mac.type == e1000_pch2lan)
250 udelay(100);
251
252 return 0;
253}
254
255/**
256 * e1000e_read_phy_reg_m88 - Read m88 PHY register
257 * @hw: pointer to the HW structure
258 * @offset: register offset to be read
259 * @data: pointer to the read data
260 *
261 * Acquires semaphore, if necessary, then reads the PHY register at offset
262 * and storing the retrieved information in data. Release any acquired
263 * semaphores before exiting.
264 **/
265s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
266{
267 s32 ret_val;
268
269 ret_val = hw->phy.ops.acquire(hw);
270 if (ret_val)
271 return ret_val;
272
273 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
274 data);
275
276 hw->phy.ops.release(hw);
277
278 return ret_val;
279}
280
281/**
282 * e1000e_write_phy_reg_m88 - Write m88 PHY register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to write to
285 * @data: data to write at register offset
286 *
287 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semaphores before exiting.
289 **/
290s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
291{
292 s32 ret_val;
293
294 ret_val = hw->phy.ops.acquire(hw);
295 if (ret_val)
296 return ret_val;
297
298 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
299 data);
300
301 hw->phy.ops.release(hw);
302
303 return ret_val;
304}
305
306/**
307 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
308 * @hw: pointer to the HW structure
309 * @page: page to set (shifted left when necessary)
310 *
311 * Sets PHY page required for PHY register access. Assumes semaphore is
312 * already acquired. Note, this function sets phy.addr to 1 so the caller
313 * must set it appropriately (if necessary) after this function returns.
314 **/
315s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
316{
317 e_dbg("Setting page 0x%x\n", page);
318
319 hw->phy.addr = 1;
320
321 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
322}
323
324/**
325 * __e1000e_read_phy_reg_igp - Read igp PHY register
326 * @hw: pointer to the HW structure
327 * @offset: register offset to be read
328 * @data: pointer to the read data
329 * @locked: semaphore has already been acquired or not
330 *
331 * Acquires semaphore, if necessary, then reads the PHY register at offset
332 * and stores the retrieved information in data. Release any acquired
333 * semaphores before exiting.
334 **/
335static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
336 bool locked)
337{
338 s32 ret_val = 0;
339
340 if (!locked) {
341 if (!hw->phy.ops.acquire)
342 return 0;
343
344 ret_val = hw->phy.ops.acquire(hw);
345 if (ret_val)
346 return ret_val;
347 }
348
349 if (offset > MAX_PHY_MULTI_PAGE_REG)
350 ret_val = e1000e_write_phy_reg_mdic(hw,
351 IGP01E1000_PHY_PAGE_SELECT,
352 (u16)offset);
353 if (!ret_val)
354 ret_val = e1000e_read_phy_reg_mdic(hw,
355 MAX_PHY_REG_ADDRESS & offset,
356 data);
357 if (!locked)
358 hw->phy.ops.release(hw);
359
360 return ret_val;
361}
362
363/**
364 * e1000e_read_phy_reg_igp - Read igp PHY register
365 * @hw: pointer to the HW structure
366 * @offset: register offset to be read
367 * @data: pointer to the read data
368 *
369 * Acquires semaphore then reads the PHY register at offset and stores the
370 * retrieved information in data.
371 * Release the acquired semaphore before exiting.
372 **/
373s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
374{
375 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
376}
377
378/**
379 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
380 * @hw: pointer to the HW structure
381 * @offset: register offset to be read
382 * @data: pointer to the read data
383 *
384 * Reads the PHY register at offset and stores the retrieved information
385 * in data. Assumes semaphore already acquired.
386 **/
387s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
388{
389 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
390}
391
392/**
393 * e1000e_write_phy_reg_igp - Write igp PHY register
394 * @hw: pointer to the HW structure
395 * @offset: register offset to write to
396 * @data: data to write at register offset
397 * @locked: semaphore has already been acquired or not
398 *
399 * Acquires semaphore, if necessary, then writes the data to PHY register
400 * at the offset. Release any acquired semaphores before exiting.
401 **/
402static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
403 bool locked)
404{
405 s32 ret_val = 0;
406
407 if (!locked) {
408 if (!hw->phy.ops.acquire)
409 return 0;
410
411 ret_val = hw->phy.ops.acquire(hw);
412 if (ret_val)
413 return ret_val;
414 }
415
416 if (offset > MAX_PHY_MULTI_PAGE_REG)
417 ret_val = e1000e_write_phy_reg_mdic(hw,
418 IGP01E1000_PHY_PAGE_SELECT,
419 (u16)offset);
420 if (!ret_val)
421 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
422 offset, data);
423 if (!locked)
424 hw->phy.ops.release(hw);
425
426 return ret_val;
427}
428
429/**
430 * e1000e_write_phy_reg_igp - Write igp PHY register
431 * @hw: pointer to the HW structure
432 * @offset: register offset to write to
433 * @data: data to write at register offset
434 *
435 * Acquires semaphore then writes the data to PHY register
436 * at the offset. Release any acquired semaphores before exiting.
437 **/
438s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
439{
440 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
441}
442
443/**
444 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
445 * @hw: pointer to the HW structure
446 * @offset: register offset to write to
447 * @data: data to write at register offset
448 *
449 * Writes the data to PHY register at the offset.
450 * Assumes semaphore already acquired.
451 **/
452s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
453{
454 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
455}
456
457/**
458 * __e1000_read_kmrn_reg - Read kumeran register
459 * @hw: pointer to the HW structure
460 * @offset: register offset to be read
461 * @data: pointer to the read data
462 * @locked: semaphore has already been acquired or not
463 *
464 * Acquires semaphore, if necessary. Then reads the PHY register at offset
465 * using the kumeran interface. The information retrieved is stored in data.
466 * Release any acquired semaphores before exiting.
467 **/
468static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
469 bool locked)
470{
471 u32 kmrnctrlsta;
472
473 if (!locked) {
474 s32 ret_val = 0;
475
476 if (!hw->phy.ops.acquire)
477 return 0;
478
479 ret_val = hw->phy.ops.acquire(hw);
480 if (ret_val)
481 return ret_val;
482 }
483
484 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
485 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
486 ew32(KMRNCTRLSTA, kmrnctrlsta);
487 e1e_flush();
488
489 udelay(2);
490
491 kmrnctrlsta = er32(KMRNCTRLSTA);
492 *data = (u16)kmrnctrlsta;
493
494 if (!locked)
495 hw->phy.ops.release(hw);
496
497 return 0;
498}
499
500/**
501 * e1000e_read_kmrn_reg - Read kumeran register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 *
506 * Acquires semaphore then reads the PHY register at offset using the
507 * kumeran interface. The information retrieved is stored in data.
508 * Release the acquired semaphore before exiting.
509 **/
510s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
511{
512 return __e1000_read_kmrn_reg(hw, offset, data, false);
513}
514
515/**
516 * e1000e_read_kmrn_reg_locked - Read kumeran register
517 * @hw: pointer to the HW structure
518 * @offset: register offset to be read
519 * @data: pointer to the read data
520 *
521 * Reads the PHY register at offset using the kumeran interface. The
522 * information retrieved is stored in data.
523 * Assumes semaphore already acquired.
524 **/
525s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
526{
527 return __e1000_read_kmrn_reg(hw, offset, data, true);
528}
529
530/**
531 * __e1000_write_kmrn_reg - Write kumeran register
532 * @hw: pointer to the HW structure
533 * @offset: register offset to write to
534 * @data: data to write at register offset
535 * @locked: semaphore has already been acquired or not
536 *
537 * Acquires semaphore, if necessary. Then write the data to PHY register
538 * at the offset using the kumeran interface. Release any acquired semaphores
539 * before exiting.
540 **/
541static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
542 bool locked)
543{
544 u32 kmrnctrlsta;
545
546 if (!locked) {
547 s32 ret_val = 0;
548
549 if (!hw->phy.ops.acquire)
550 return 0;
551
552 ret_val = hw->phy.ops.acquire(hw);
553 if (ret_val)
554 return ret_val;
555 }
556
557 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
558 E1000_KMRNCTRLSTA_OFFSET) | data;
559 ew32(KMRNCTRLSTA, kmrnctrlsta);
560 e1e_flush();
561
562 udelay(2);
563
564 if (!locked)
565 hw->phy.ops.release(hw);
566
567 return 0;
568}
569
570/**
571 * e1000e_write_kmrn_reg - Write kumeran register
572 * @hw: pointer to the HW structure
573 * @offset: register offset to write to
574 * @data: data to write at register offset
575 *
576 * Acquires semaphore then writes the data to the PHY register at the offset
577 * using the kumeran interface. Release the acquired semaphore before exiting.
578 **/
579s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
580{
581 return __e1000_write_kmrn_reg(hw, offset, data, false);
582}
583
584/**
585 * e1000e_write_kmrn_reg_locked - Write kumeran register
586 * @hw: pointer to the HW structure
587 * @offset: register offset to write to
588 * @data: data to write at register offset
589 *
590 * Write the data to PHY register at the offset using the kumeran interface.
591 * Assumes semaphore already acquired.
592 **/
593s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
594{
595 return __e1000_write_kmrn_reg(hw, offset, data, true);
596}
597
598/**
599 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
600 * @hw: pointer to the HW structure
601 *
602 * Sets up Master/slave mode
603 **/
604static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
605{
606 s32 ret_val;
607 u16 phy_data;
608
609 /* Resolve Master/Slave mode */
610 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
611 if (ret_val)
612 return ret_val;
613
614 /* load defaults for future use */
615 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
616 ((phy_data & CTL1000_AS_MASTER) ?
617 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
618
619 switch (hw->phy.ms_type) {
620 case e1000_ms_force_master:
621 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
622 break;
623 case e1000_ms_force_slave:
624 phy_data |= CTL1000_ENABLE_MASTER;
625 phy_data &= ~(CTL1000_AS_MASTER);
626 break;
627 case e1000_ms_auto:
628 phy_data &= ~CTL1000_ENABLE_MASTER;
629 /* fall-through */
630 default:
631 break;
632 }
633
634 return e1e_wphy(hw, MII_CTRL1000, phy_data);
635}
636
637/**
638 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
639 * @hw: pointer to the HW structure
640 *
641 * Sets up Carrier-sense on Transmit and downshift values.
642 **/
643s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
644{
645 s32 ret_val;
646 u16 phy_data;
647
648 /* Enable CRS on Tx. This must be set for half-duplex operation. */
649 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
650 if (ret_val)
651 return ret_val;
652
653 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
654
655 /* Enable downshift */
656 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
657
658 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
659 if (ret_val)
660 return ret_val;
661
662 /* Set MDI/MDIX mode */
663 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
664 if (ret_val)
665 return ret_val;
666 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
667 /* Options:
668 * 0 - Auto (default)
669 * 1 - MDI mode
670 * 2 - MDI-X mode
671 */
672 switch (hw->phy.mdix) {
673 case 1:
674 break;
675 case 2:
676 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
677 break;
678 case 0:
679 default:
680 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
681 break;
682 }
683 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
684 if (ret_val)
685 return ret_val;
686
687 return e1000_set_master_slave_mode(hw);
688}
689
690/**
691 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
692 * @hw: pointer to the HW structure
693 *
694 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
695 * and downshift values are set also.
696 **/
697s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
698{
699 struct e1000_phy_info *phy = &hw->phy;
700 s32 ret_val;
701 u16 phy_data;
702
703 /* Enable CRS on Tx. This must be set for half-duplex operation. */
704 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
705 if (ret_val)
706 return ret_val;
707
708 /* For BM PHY this bit is downshift enable */
709 if (phy->type != e1000_phy_bm)
710 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
711
712 /* Options:
713 * MDI/MDI-X = 0 (default)
714 * 0 - Auto for all speeds
715 * 1 - MDI mode
716 * 2 - MDI-X mode
717 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
718 */
719 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
720
721 switch (phy->mdix) {
722 case 1:
723 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
724 break;
725 case 2:
726 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
727 break;
728 case 3:
729 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
730 break;
731 case 0:
732 default:
733 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
734 break;
735 }
736
737 /* Options:
738 * disable_polarity_correction = 0 (default)
739 * Automatic Correction for Reversed Cable Polarity
740 * 0 - Disabled
741 * 1 - Enabled
742 */
743 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
744 if (phy->disable_polarity_correction)
745 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
746
747 /* Enable downshift on BM (disabled by default) */
748 if (phy->type == e1000_phy_bm) {
749 /* For 82574/82583, first disable then enable downshift */
750 if (phy->id == BME1000_E_PHY_ID_R2) {
751 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
752 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
753 phy_data);
754 if (ret_val)
755 return ret_val;
756 /* Commit the changes. */
757 ret_val = phy->ops.commit(hw);
758 if (ret_val) {
759 e_dbg("Error committing the PHY changes\n");
760 return ret_val;
761 }
762 }
763
764 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
765 }
766
767 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
768 if (ret_val)
769 return ret_val;
770
771 if ((phy->type == e1000_phy_m88) &&
772 (phy->revision < E1000_REVISION_4) &&
773 (phy->id != BME1000_E_PHY_ID_R2)) {
774 /* Force TX_CLK in the Extended PHY Specific Control Register
775 * to 25MHz clock.
776 */
777 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
778 if (ret_val)
779 return ret_val;
780
781 phy_data |= M88E1000_EPSCR_TX_CLK_25;
782
783 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
784 /* 82573L PHY - set the downshift counter to 5x. */
785 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
786 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
787 } else {
788 /* Configure Master and Slave downshift values */
789 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
790 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
791 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
792 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
793 }
794 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
795 if (ret_val)
796 return ret_val;
797 }
798
799 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
800 /* Set PHY page 0, register 29 to 0x0003 */
801 ret_val = e1e_wphy(hw, 29, 0x0003);
802 if (ret_val)
803 return ret_val;
804
805 /* Set PHY page 0, register 30 to 0x0000 */
806 ret_val = e1e_wphy(hw, 30, 0x0000);
807 if (ret_val)
808 return ret_val;
809 }
810
811 /* Commit the changes. */
812 if (phy->ops.commit) {
813 ret_val = phy->ops.commit(hw);
814 if (ret_val) {
815 e_dbg("Error committing the PHY changes\n");
816 return ret_val;
817 }
818 }
819
820 if (phy->type == e1000_phy_82578) {
821 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
822 if (ret_val)
823 return ret_val;
824
825 /* 82578 PHY - set the downshift count to 1x. */
826 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
827 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
828 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
829 if (ret_val)
830 return ret_val;
831 }
832
833 return 0;
834}
835
836/**
837 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
838 * @hw: pointer to the HW structure
839 *
840 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
841 * igp PHY's.
842 **/
843s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
844{
845 struct e1000_phy_info *phy = &hw->phy;
846 s32 ret_val;
847 u16 data;
848
849 ret_val = e1000_phy_hw_reset(hw);
850 if (ret_val) {
851 e_dbg("Error resetting the PHY.\n");
852 return ret_val;
853 }
854
855 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
856 * timeout issues when LFS is enabled.
857 */
858 msleep(100);
859
860 /* disable lplu d0 during driver init */
861 if (hw->phy.ops.set_d0_lplu_state) {
862 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
863 if (ret_val) {
864 e_dbg("Error Disabling LPLU D0\n");
865 return ret_val;
866 }
867 }
868 /* Configure mdi-mdix settings */
869 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
870 if (ret_val)
871 return ret_val;
872
873 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
874
875 switch (phy->mdix) {
876 case 1:
877 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
878 break;
879 case 2:
880 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
881 break;
882 case 0:
883 default:
884 data |= IGP01E1000_PSCR_AUTO_MDIX;
885 break;
886 }
887 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
888 if (ret_val)
889 return ret_val;
890
891 /* set auto-master slave resolution settings */
892 if (hw->mac.autoneg) {
893 /* when autonegotiation advertisement is only 1000Mbps then we
894 * should disable SmartSpeed and enable Auto MasterSlave
895 * resolution as hardware default.
896 */
897 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
898 /* Disable SmartSpeed */
899 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
900 &data);
901 if (ret_val)
902 return ret_val;
903
904 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
905 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
906 data);
907 if (ret_val)
908 return ret_val;
909
910 /* Set auto Master/Slave resolution process */
911 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
912 if (ret_val)
913 return ret_val;
914
915 data &= ~CTL1000_ENABLE_MASTER;
916 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
917 if (ret_val)
918 return ret_val;
919 }
920
921 ret_val = e1000_set_master_slave_mode(hw);
922 }
923
924 return ret_val;
925}
926
927/**
928 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
929 * @hw: pointer to the HW structure
930 *
931 * Reads the MII auto-neg advertisement register and/or the 1000T control
932 * register and if the PHY is already setup for auto-negotiation, then
933 * return successful. Otherwise, setup advertisement and flow control to
934 * the appropriate values for the wanted auto-negotiation.
935 **/
936static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
937{
938 struct e1000_phy_info *phy = &hw->phy;
939 s32 ret_val;
940 u16 mii_autoneg_adv_reg;
941 u16 mii_1000t_ctrl_reg = 0;
942
943 phy->autoneg_advertised &= phy->autoneg_mask;
944
945 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
946 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
947 if (ret_val)
948 return ret_val;
949
950 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
951 /* Read the MII 1000Base-T Control Register (Address 9). */
952 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
953 if (ret_val)
954 return ret_val;
955 }
956
957 /* Need to parse both autoneg_advertised and fc and set up
958 * the appropriate PHY registers. First we will parse for
959 * autoneg_advertised software override. Since we can advertise
960 * a plethora of combinations, we need to check each bit
961 * individually.
962 */
963
964 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
965 * Advertisement Register (Address 4) and the 1000 mb speed bits in
966 * the 1000Base-T Control Register (Address 9).
967 */
968 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
969 ADVERTISE_100HALF |
970 ADVERTISE_10FULL | ADVERTISE_10HALF);
971 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
972
973 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
974
975 /* Do we want to advertise 10 Mb Half Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
977 e_dbg("Advertise 10mb Half duplex\n");
978 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
979 }
980
981 /* Do we want to advertise 10 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
983 e_dbg("Advertise 10mb Full duplex\n");
984 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
985 }
986
987 /* Do we want to advertise 100 Mb Half Duplex? */
988 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
989 e_dbg("Advertise 100mb Half duplex\n");
990 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
991 }
992
993 /* Do we want to advertise 100 Mb Full Duplex? */
994 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
995 e_dbg("Advertise 100mb Full duplex\n");
996 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
997 }
998
999 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1000 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1001 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1002
1003 /* Do we want to advertise 1000 Mb Full Duplex? */
1004 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1005 e_dbg("Advertise 1000mb Full duplex\n");
1006 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1007 }
1008
1009 /* Check for a software override of the flow control settings, and
1010 * setup the PHY advertisement registers accordingly. If
1011 * auto-negotiation is enabled, then software will have to set the
1012 * "PAUSE" bits to the correct value in the Auto-Negotiation
1013 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1014 * negotiation.
1015 *
1016 * The possible values of the "fc" parameter are:
1017 * 0: Flow control is completely disabled
1018 * 1: Rx flow control is enabled (we can receive pause frames
1019 * but not send pause frames).
1020 * 2: Tx flow control is enabled (we can send pause frames
1021 * but we do not support receiving pause frames).
1022 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1023 * other: No software override. The flow control configuration
1024 * in the EEPROM is used.
1025 */
1026 switch (hw->fc.current_mode) {
1027 case e1000_fc_none:
1028 /* Flow control (Rx & Tx) is completely disabled by a
1029 * software over-ride.
1030 */
1031 mii_autoneg_adv_reg &=
1032 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1033 break;
1034 case e1000_fc_rx_pause:
1035 /* Rx Flow control is enabled, and Tx Flow control is
1036 * disabled, by a software over-ride.
1037 *
1038 * Since there really isn't a way to advertise that we are
1039 * capable of Rx Pause ONLY, we will advertise that we
1040 * support both symmetric and asymmetric Rx PAUSE. Later
1041 * (in e1000e_config_fc_after_link_up) we will disable the
1042 * hw's ability to send PAUSE frames.
1043 */
1044 mii_autoneg_adv_reg |=
1045 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1046 break;
1047 case e1000_fc_tx_pause:
1048 /* Tx Flow control is enabled, and Rx Flow control is
1049 * disabled, by a software over-ride.
1050 */
1051 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1052 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1053 break;
1054 case e1000_fc_full:
1055 /* Flow control (both Rx and Tx) is enabled by a software
1056 * over-ride.
1057 */
1058 mii_autoneg_adv_reg |=
1059 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1060 break;
1061 default:
1062 e_dbg("Flow control param set incorrectly\n");
1063 return -E1000_ERR_CONFIG;
1064 }
1065
1066 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1067 if (ret_val)
1068 return ret_val;
1069
1070 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1071
1072 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1073 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1074
1075 return ret_val;
1076}
1077
1078/**
1079 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1080 * @hw: pointer to the HW structure
1081 *
1082 * Performs initial bounds checking on autoneg advertisement parameter, then
1083 * configure to advertise the full capability. Setup the PHY to autoneg
1084 * and restart the negotiation process between the link partner. If
1085 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1086 **/
1087static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1088{
1089 struct e1000_phy_info *phy = &hw->phy;
1090 s32 ret_val;
1091 u16 phy_ctrl;
1092
1093 /* Perform some bounds checking on the autoneg advertisement
1094 * parameter.
1095 */
1096 phy->autoneg_advertised &= phy->autoneg_mask;
1097
1098 /* If autoneg_advertised is zero, we assume it was not defaulted
1099 * by the calling code so we set to advertise full capability.
1100 */
1101 if (!phy->autoneg_advertised)
1102 phy->autoneg_advertised = phy->autoneg_mask;
1103
1104 e_dbg("Reconfiguring auto-neg advertisement params\n");
1105 ret_val = e1000_phy_setup_autoneg(hw);
1106 if (ret_val) {
1107 e_dbg("Error Setting up Auto-Negotiation\n");
1108 return ret_val;
1109 }
1110 e_dbg("Restarting Auto-Neg\n");
1111
1112 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1113 * the Auto Neg Restart bit in the PHY control register.
1114 */
1115 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1116 if (ret_val)
1117 return ret_val;
1118
1119 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1120 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1121 if (ret_val)
1122 return ret_val;
1123
1124 /* Does the user want to wait for Auto-Neg to complete here, or
1125 * check at a later time (for example, callback routine).
1126 */
1127 if (phy->autoneg_wait_to_complete) {
1128 ret_val = e1000_wait_autoneg(hw);
1129 if (ret_val) {
1130 e_dbg("Error while waiting for autoneg to complete\n");
1131 return ret_val;
1132 }
1133 }
1134
1135 hw->mac.get_link_status = true;
1136
1137 return ret_val;
1138}
1139
1140/**
1141 * e1000e_setup_copper_link - Configure copper link settings
1142 * @hw: pointer to the HW structure
1143 *
1144 * Calls the appropriate function to configure the link for auto-neg or forced
1145 * speed and duplex. Then we check for link, once link is established calls
1146 * to configure collision distance and flow control are called. If link is
1147 * not established, we return -E1000_ERR_PHY (-2).
1148 **/
1149s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1150{
1151 s32 ret_val;
1152 bool link;
1153
1154 if (hw->mac.autoneg) {
1155 /* Setup autoneg and flow control advertisement and perform
1156 * autonegotiation.
1157 */
1158 ret_val = e1000_copper_link_autoneg(hw);
1159 if (ret_val)
1160 return ret_val;
1161 } else {
1162 /* PHY will be set to 10H, 10F, 100H or 100F
1163 * depending on user settings.
1164 */
1165 e_dbg("Forcing Speed and Duplex\n");
1166 ret_val = hw->phy.ops.force_speed_duplex(hw);
1167 if (ret_val) {
1168 e_dbg("Error Forcing Speed and Duplex\n");
1169 return ret_val;
1170 }
1171 }
1172
1173 /* Check link status. Wait up to 100 microseconds for link to become
1174 * valid.
1175 */
1176 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1177 &link);
1178 if (ret_val)
1179 return ret_val;
1180
1181 if (link) {
1182 e_dbg("Valid link established!!!\n");
1183 hw->mac.ops.config_collision_dist(hw);
1184 ret_val = e1000e_config_fc_after_link_up(hw);
1185 } else {
1186 e_dbg("Unable to establish link!!!\n");
1187 }
1188
1189 return ret_val;
1190}
1191
1192/**
1193 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1194 * @hw: pointer to the HW structure
1195 *
1196 * Calls the PHY setup function to force speed and duplex. Clears the
1197 * auto-crossover to force MDI manually. Waits for link and returns
1198 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1199 **/
1200s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1201{
1202 struct e1000_phy_info *phy = &hw->phy;
1203 s32 ret_val;
1204 u16 phy_data;
1205 bool link;
1206
1207 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1208 if (ret_val)
1209 return ret_val;
1210
1211 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1212
1213 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1214 if (ret_val)
1215 return ret_val;
1216
1217 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1218 * forced whenever speed and duplex are forced.
1219 */
1220 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1221 if (ret_val)
1222 return ret_val;
1223
1224 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1225 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1226
1227 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1228 if (ret_val)
1229 return ret_val;
1230
1231 e_dbg("IGP PSCR: %X\n", phy_data);
1232
1233 udelay(1);
1234
1235 if (phy->autoneg_wait_to_complete) {
1236 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1237
1238 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1239 100000, &link);
1240 if (ret_val)
1241 return ret_val;
1242
1243 if (!link)
1244 e_dbg("Link taking longer than expected.\n");
1245
1246 /* Try once more */
1247 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1248 100000, &link);
1249 }
1250
1251 return ret_val;
1252}
1253
1254/**
1255 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1256 * @hw: pointer to the HW structure
1257 *
1258 * Calls the PHY setup function to force speed and duplex. Clears the
1259 * auto-crossover to force MDI manually. Resets the PHY to commit the
1260 * changes. If time expires while waiting for link up, we reset the DSP.
1261 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1262 * successful completion, else return corresponding error code.
1263 **/
1264s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1265{
1266 struct e1000_phy_info *phy = &hw->phy;
1267 s32 ret_val;
1268 u16 phy_data;
1269 bool link;
1270
1271 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1272 * forced whenever speed and duplex are forced.
1273 */
1274 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1275 if (ret_val)
1276 return ret_val;
1277
1278 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1279 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1280 if (ret_val)
1281 return ret_val;
1282
1283 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1284
1285 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1286 if (ret_val)
1287 return ret_val;
1288
1289 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1290
1291 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1292 if (ret_val)
1293 return ret_val;
1294
1295 /* Reset the phy to commit changes. */
1296 if (hw->phy.ops.commit) {
1297 ret_val = hw->phy.ops.commit(hw);
1298 if (ret_val)
1299 return ret_val;
1300 }
1301
1302 if (phy->autoneg_wait_to_complete) {
1303 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1304
1305 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1306 100000, &link);
1307 if (ret_val)
1308 return ret_val;
1309
1310 if (!link) {
1311 if (hw->phy.type != e1000_phy_m88) {
1312 e_dbg("Link taking longer than expected.\n");
1313 } else {
1314 /* We didn't get link.
1315 * Reset the DSP and cross our fingers.
1316 */
1317 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1318 0x001d);
1319 if (ret_val)
1320 return ret_val;
1321 ret_val = e1000e_phy_reset_dsp(hw);
1322 if (ret_val)
1323 return ret_val;
1324 }
1325 }
1326
1327 /* Try once more */
1328 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1329 100000, &link);
1330 if (ret_val)
1331 return ret_val;
1332 }
1333
1334 if (hw->phy.type != e1000_phy_m88)
1335 return 0;
1336
1337 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1338 if (ret_val)
1339 return ret_val;
1340
1341 /* Resetting the phy means we need to re-force TX_CLK in the
1342 * Extended PHY Specific Control Register to 25MHz clock from
1343 * the reset value of 2.5MHz.
1344 */
1345 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1346 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1347 if (ret_val)
1348 return ret_val;
1349
1350 /* In addition, we must re-enable CRS on Tx for both half and full
1351 * duplex.
1352 */
1353 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1354 if (ret_val)
1355 return ret_val;
1356
1357 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1358 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1359
1360 return ret_val;
1361}
1362
1363/**
1364 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1365 * @hw: pointer to the HW structure
1366 *
1367 * Forces the speed and duplex settings of the PHY.
1368 * This is a function pointer entry point only called by
1369 * PHY setup routines.
1370 **/
1371s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1372{
1373 struct e1000_phy_info *phy = &hw->phy;
1374 s32 ret_val;
1375 u16 data;
1376 bool link;
1377
1378 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1379 if (ret_val)
1380 return ret_val;
1381
1382 e1000e_phy_force_speed_duplex_setup(hw, &data);
1383
1384 ret_val = e1e_wphy(hw, MII_BMCR, data);
1385 if (ret_val)
1386 return ret_val;
1387
1388 /* Disable MDI-X support for 10/100 */
1389 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1390 if (ret_val)
1391 return ret_val;
1392
1393 data &= ~IFE_PMC_AUTO_MDIX;
1394 data &= ~IFE_PMC_FORCE_MDIX;
1395
1396 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1397 if (ret_val)
1398 return ret_val;
1399
1400 e_dbg("IFE PMC: %X\n", data);
1401
1402 udelay(1);
1403
1404 if (phy->autoneg_wait_to_complete) {
1405 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1406
1407 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1408 100000, &link);
1409 if (ret_val)
1410 return ret_val;
1411
1412 if (!link)
1413 e_dbg("Link taking longer than expected.\n");
1414
1415 /* Try once more */
1416 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1417 100000, &link);
1418 if (ret_val)
1419 return ret_val;
1420 }
1421
1422 return 0;
1423}
1424
1425/**
1426 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1427 * @hw: pointer to the HW structure
1428 * @phy_ctrl: pointer to current value of MII_BMCR
1429 *
1430 * Forces speed and duplex on the PHY by doing the following: disable flow
1431 * control, force speed/duplex on the MAC, disable auto speed detection,
1432 * disable auto-negotiation, configure duplex, configure speed, configure
1433 * the collision distance, write configuration to CTRL register. The
1434 * caller must write to the MII_BMCR register for these settings to
1435 * take affect.
1436 **/
1437void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1438{
1439 struct e1000_mac_info *mac = &hw->mac;
1440 u32 ctrl;
1441
1442 /* Turn off flow control when forcing speed/duplex */
1443 hw->fc.current_mode = e1000_fc_none;
1444
1445 /* Force speed/duplex on the mac */
1446 ctrl = er32(CTRL);
1447 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1448 ctrl &= ~E1000_CTRL_SPD_SEL;
1449
1450 /* Disable Auto Speed Detection */
1451 ctrl &= ~E1000_CTRL_ASDE;
1452
1453 /* Disable autoneg on the phy */
1454 *phy_ctrl &= ~BMCR_ANENABLE;
1455
1456 /* Forcing Full or Half Duplex? */
1457 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1458 ctrl &= ~E1000_CTRL_FD;
1459 *phy_ctrl &= ~BMCR_FULLDPLX;
1460 e_dbg("Half Duplex\n");
1461 } else {
1462 ctrl |= E1000_CTRL_FD;
1463 *phy_ctrl |= BMCR_FULLDPLX;
1464 e_dbg("Full Duplex\n");
1465 }
1466
1467 /* Forcing 10mb or 100mb? */
1468 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1469 ctrl |= E1000_CTRL_SPD_100;
1470 *phy_ctrl |= BMCR_SPEED100;
1471 *phy_ctrl &= ~BMCR_SPEED1000;
1472 e_dbg("Forcing 100mb\n");
1473 } else {
1474 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1475 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1476 e_dbg("Forcing 10mb\n");
1477 }
1478
1479 hw->mac.ops.config_collision_dist(hw);
1480
1481 ew32(CTRL, ctrl);
1482}
1483
1484/**
1485 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1486 * @hw: pointer to the HW structure
1487 * @active: boolean used to enable/disable lplu
1488 *
1489 * Success returns 0, Failure returns 1
1490 *
1491 * The low power link up (lplu) state is set to the power management level D3
1492 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1493 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1494 * is used during Dx states where the power conservation is most important.
1495 * During driver activity, SmartSpeed should be enabled so performance is
1496 * maintained.
1497 **/
1498s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1499{
1500 struct e1000_phy_info *phy = &hw->phy;
1501 s32 ret_val;
1502 u16 data;
1503
1504 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1505 if (ret_val)
1506 return ret_val;
1507
1508 if (!active) {
1509 data &= ~IGP02E1000_PM_D3_LPLU;
1510 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1511 if (ret_val)
1512 return ret_val;
1513 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1514 * during Dx states where the power conservation is most
1515 * important. During driver activity we should enable
1516 * SmartSpeed, so performance is maintained.
1517 */
1518 if (phy->smart_speed == e1000_smart_speed_on) {
1519 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1520 &data);
1521 if (ret_val)
1522 return ret_val;
1523
1524 data |= IGP01E1000_PSCFR_SMART_SPEED;
1525 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1526 data);
1527 if (ret_val)
1528 return ret_val;
1529 } else if (phy->smart_speed == e1000_smart_speed_off) {
1530 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 data);
1538 if (ret_val)
1539 return ret_val;
1540 }
1541 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1542 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1543 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1544 data |= IGP02E1000_PM_D3_LPLU;
1545 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1546 if (ret_val)
1547 return ret_val;
1548
1549 /* When LPLU is enabled, we should disable SmartSpeed */
1550 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1556 }
1557
1558 return ret_val;
1559}
1560
1561/**
1562 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1563 * @hw: pointer to the HW structure
1564 *
1565 * Success returns 0, Failure returns 1
1566 *
1567 * A downshift is detected by querying the PHY link health.
1568 **/
1569s32 e1000e_check_downshift(struct e1000_hw *hw)
1570{
1571 struct e1000_phy_info *phy = &hw->phy;
1572 s32 ret_val;
1573 u16 phy_data, offset, mask;
1574
1575 switch (phy->type) {
1576 case e1000_phy_m88:
1577 case e1000_phy_gg82563:
1578 case e1000_phy_bm:
1579 case e1000_phy_82578:
1580 offset = M88E1000_PHY_SPEC_STATUS;
1581 mask = M88E1000_PSSR_DOWNSHIFT;
1582 break;
1583 case e1000_phy_igp_2:
1584 case e1000_phy_igp_3:
1585 offset = IGP01E1000_PHY_LINK_HEALTH;
1586 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1587 break;
1588 default:
1589 /* speed downshift not supported */
1590 phy->speed_downgraded = false;
1591 return 0;
1592 }
1593
1594 ret_val = e1e_rphy(hw, offset, &phy_data);
1595
1596 if (!ret_val)
1597 phy->speed_downgraded = !!(phy_data & mask);
1598
1599 return ret_val;
1600}
1601
1602/**
1603 * e1000_check_polarity_m88 - Checks the polarity.
1604 * @hw: pointer to the HW structure
1605 *
1606 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1607 *
1608 * Polarity is determined based on the PHY specific status register.
1609 **/
1610s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1611{
1612 struct e1000_phy_info *phy = &hw->phy;
1613 s32 ret_val;
1614 u16 data;
1615
1616 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1617
1618 if (!ret_val)
1619 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1620 ? e1000_rev_polarity_reversed
1621 : e1000_rev_polarity_normal);
1622
1623 return ret_val;
1624}
1625
1626/**
1627 * e1000_check_polarity_igp - Checks the polarity.
1628 * @hw: pointer to the HW structure
1629 *
1630 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1631 *
1632 * Polarity is determined based on the PHY port status register, and the
1633 * current speed (since there is no polarity at 100Mbps).
1634 **/
1635s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1636{
1637 struct e1000_phy_info *phy = &hw->phy;
1638 s32 ret_val;
1639 u16 data, offset, mask;
1640
1641 /* Polarity is determined based on the speed of
1642 * our connection.
1643 */
1644 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1645 if (ret_val)
1646 return ret_val;
1647
1648 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1649 IGP01E1000_PSSR_SPEED_1000MBPS) {
1650 offset = IGP01E1000_PHY_PCS_INIT_REG;
1651 mask = IGP01E1000_PHY_POLARITY_MASK;
1652 } else {
1653 /* This really only applies to 10Mbps since
1654 * there is no polarity for 100Mbps (always 0).
1655 */
1656 offset = IGP01E1000_PHY_PORT_STATUS;
1657 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1658 }
1659
1660 ret_val = e1e_rphy(hw, offset, &data);
1661
1662 if (!ret_val)
1663 phy->cable_polarity = ((data & mask)
1664 ? e1000_rev_polarity_reversed
1665 : e1000_rev_polarity_normal);
1666
1667 return ret_val;
1668}
1669
1670/**
1671 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1672 * @hw: pointer to the HW structure
1673 *
1674 * Polarity is determined on the polarity reversal feature being enabled.
1675 **/
1676s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1677{
1678 struct e1000_phy_info *phy = &hw->phy;
1679 s32 ret_val;
1680 u16 phy_data, offset, mask;
1681
1682 /* Polarity is determined based on the reversal feature being enabled.
1683 */
1684 if (phy->polarity_correction) {
1685 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1686 mask = IFE_PESC_POLARITY_REVERSED;
1687 } else {
1688 offset = IFE_PHY_SPECIAL_CONTROL;
1689 mask = IFE_PSC_FORCE_POLARITY;
1690 }
1691
1692 ret_val = e1e_rphy(hw, offset, &phy_data);
1693
1694 if (!ret_val)
1695 phy->cable_polarity = ((phy_data & mask)
1696 ? e1000_rev_polarity_reversed
1697 : e1000_rev_polarity_normal);
1698
1699 return ret_val;
1700}
1701
1702/**
1703 * e1000_wait_autoneg - Wait for auto-neg completion
1704 * @hw: pointer to the HW structure
1705 *
1706 * Waits for auto-negotiation to complete or for the auto-negotiation time
1707 * limit to expire, which ever happens first.
1708 **/
1709static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1710{
1711 s32 ret_val = 0;
1712 u16 i, phy_status;
1713
1714 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1715 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1716 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1717 if (ret_val)
1718 break;
1719 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1720 if (ret_val)
1721 break;
1722 if (phy_status & BMSR_ANEGCOMPLETE)
1723 break;
1724 msleep(100);
1725 }
1726
1727 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1728 * has completed.
1729 */
1730 return ret_val;
1731}
1732
1733/**
1734 * e1000e_phy_has_link_generic - Polls PHY for link
1735 * @hw: pointer to the HW structure
1736 * @iterations: number of times to poll for link
1737 * @usec_interval: delay between polling attempts
1738 * @success: pointer to whether polling was successful or not
1739 *
1740 * Polls the PHY status register for link, 'iterations' number of times.
1741 **/
1742s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1743 u32 usec_interval, bool *success)
1744{
1745 s32 ret_val = 0;
1746 u16 i, phy_status;
1747
1748 *success = false;
1749 for (i = 0; i < iterations; i++) {
1750 /* Some PHYs require the MII_BMSR register to be read
1751 * twice due to the link bit being sticky. No harm doing
1752 * it across the board.
1753 */
1754 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1755 if (ret_val) {
1756 /* If the first read fails, another entity may have
1757 * ownership of the resources, wait and try again to
1758 * see if they have relinquished the resources yet.
1759 */
1760 if (usec_interval >= 1000)
1761 msleep(usec_interval / 1000);
1762 else
1763 udelay(usec_interval);
1764 }
1765 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1766 if (ret_val)
1767 break;
1768 if (phy_status & BMSR_LSTATUS) {
1769 *success = true;
1770 break;
1771 }
1772 if (usec_interval >= 1000)
1773 msleep(usec_interval / 1000);
1774 else
1775 udelay(usec_interval);
1776 }
1777
1778 return ret_val;
1779}
1780
1781/**
1782 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1783 * @hw: pointer to the HW structure
1784 *
1785 * Reads the PHY specific status register to retrieve the cable length
1786 * information. The cable length is determined by averaging the minimum and
1787 * maximum values to get the "average" cable length. The m88 PHY has four
1788 * possible cable length values, which are:
1789 * Register Value Cable Length
1790 * 0 < 50 meters
1791 * 1 50 - 80 meters
1792 * 2 80 - 110 meters
1793 * 3 110 - 140 meters
1794 * 4 > 140 meters
1795 **/
1796s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1797{
1798 struct e1000_phy_info *phy = &hw->phy;
1799 s32 ret_val;
1800 u16 phy_data, index;
1801
1802 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1803 if (ret_val)
1804 return ret_val;
1805
1806 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1807 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1808
1809 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1810 return -E1000_ERR_PHY;
1811
1812 phy->min_cable_length = e1000_m88_cable_length_table[index];
1813 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1814
1815 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1816
1817 return 0;
1818}
1819
1820/**
1821 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1822 * @hw: pointer to the HW structure
1823 *
1824 * The automatic gain control (agc) normalizes the amplitude of the
1825 * received signal, adjusting for the attenuation produced by the
1826 * cable. By reading the AGC registers, which represent the
1827 * combination of coarse and fine gain value, the value can be put
1828 * into a lookup table to obtain the approximate cable length
1829 * for each channel.
1830 **/
1831s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1832{
1833 struct e1000_phy_info *phy = &hw->phy;
1834 s32 ret_val;
1835 u16 phy_data, i, agc_value = 0;
1836 u16 cur_agc_index, max_agc_index = 0;
1837 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1838 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1839 IGP02E1000_PHY_AGC_A,
1840 IGP02E1000_PHY_AGC_B,
1841 IGP02E1000_PHY_AGC_C,
1842 IGP02E1000_PHY_AGC_D
1843 };
1844
1845 /* Read the AGC registers for all channels */
1846 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1847 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1848 if (ret_val)
1849 return ret_val;
1850
1851 /* Getting bits 15:9, which represent the combination of
1852 * coarse and fine gain values. The result is a number
1853 * that can be put into the lookup table to obtain the
1854 * approximate cable length.
1855 */
1856 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1857 IGP02E1000_AGC_LENGTH_MASK);
1858
1859 /* Array index bound check. */
1860 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1861 (cur_agc_index == 0))
1862 return -E1000_ERR_PHY;
1863
1864 /* Remove min & max AGC values from calculation. */
1865 if (e1000_igp_2_cable_length_table[min_agc_index] >
1866 e1000_igp_2_cable_length_table[cur_agc_index])
1867 min_agc_index = cur_agc_index;
1868 if (e1000_igp_2_cable_length_table[max_agc_index] <
1869 e1000_igp_2_cable_length_table[cur_agc_index])
1870 max_agc_index = cur_agc_index;
1871
1872 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1873 }
1874
1875 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1876 e1000_igp_2_cable_length_table[max_agc_index]);
1877 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1878
1879 /* Calculate cable length with the error range of +/- 10 meters. */
1880 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1881 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1882 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1883
1884 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1885
1886 return 0;
1887}
1888
1889/**
1890 * e1000e_get_phy_info_m88 - Retrieve PHY information
1891 * @hw: pointer to the HW structure
1892 *
1893 * Valid for only copper links. Read the PHY status register (sticky read)
1894 * to verify that link is up. Read the PHY special control register to
1895 * determine the polarity and 10base-T extended distance. Read the PHY
1896 * special status register to determine MDI/MDIx and current speed. If
1897 * speed is 1000, then determine cable length, local and remote receiver.
1898 **/
1899s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1900{
1901 struct e1000_phy_info *phy = &hw->phy;
1902 s32 ret_val;
1903 u16 phy_data;
1904 bool link;
1905
1906 if (phy->media_type != e1000_media_type_copper) {
1907 e_dbg("Phy info is only valid for copper media\n");
1908 return -E1000_ERR_CONFIG;
1909 }
1910
1911 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1912 if (ret_val)
1913 return ret_val;
1914
1915 if (!link) {
1916 e_dbg("Phy info is only valid if link is up\n");
1917 return -E1000_ERR_CONFIG;
1918 }
1919
1920 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1921 if (ret_val)
1922 return ret_val;
1923
1924 phy->polarity_correction = !!(phy_data &
1925 M88E1000_PSCR_POLARITY_REVERSAL);
1926
1927 ret_val = e1000_check_polarity_m88(hw);
1928 if (ret_val)
1929 return ret_val;
1930
1931 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1932 if (ret_val)
1933 return ret_val;
1934
1935 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1936
1937 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1938 ret_val = hw->phy.ops.get_cable_length(hw);
1939 if (ret_val)
1940 return ret_val;
1941
1942 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1943 if (ret_val)
1944 return ret_val;
1945
1946 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1947 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1948
1949 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1950 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1951 } else {
1952 /* Set values to "undefined" */
1953 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1954 phy->local_rx = e1000_1000t_rx_status_undefined;
1955 phy->remote_rx = e1000_1000t_rx_status_undefined;
1956 }
1957
1958 return ret_val;
1959}
1960
1961/**
1962 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1963 * @hw: pointer to the HW structure
1964 *
1965 * Read PHY status to determine if link is up. If link is up, then
1966 * set/determine 10base-T extended distance and polarity correction. Read
1967 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1968 * determine on the cable length, local and remote receiver.
1969 **/
1970s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1971{
1972 struct e1000_phy_info *phy = &hw->phy;
1973 s32 ret_val;
1974 u16 data;
1975 bool link;
1976
1977 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1978 if (ret_val)
1979 return ret_val;
1980
1981 if (!link) {
1982 e_dbg("Phy info is only valid if link is up\n");
1983 return -E1000_ERR_CONFIG;
1984 }
1985
1986 phy->polarity_correction = true;
1987
1988 ret_val = e1000_check_polarity_igp(hw);
1989 if (ret_val)
1990 return ret_val;
1991
1992 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1993 if (ret_val)
1994 return ret_val;
1995
1996 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1997
1998 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1999 IGP01E1000_PSSR_SPEED_1000MBPS) {
2000 ret_val = phy->ops.get_cable_length(hw);
2001 if (ret_val)
2002 return ret_val;
2003
2004 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2005 if (ret_val)
2006 return ret_val;
2007
2008 phy->local_rx = (data & LPA_1000LOCALRXOK)
2009 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2010
2011 phy->remote_rx = (data & LPA_1000REMRXOK)
2012 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2013 } else {
2014 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2015 phy->local_rx = e1000_1000t_rx_status_undefined;
2016 phy->remote_rx = e1000_1000t_rx_status_undefined;
2017 }
2018
2019 return ret_val;
2020}
2021
2022/**
2023 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2024 * @hw: pointer to the HW structure
2025 *
2026 * Populates "phy" structure with various feature states.
2027 **/
2028s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2029{
2030 struct e1000_phy_info *phy = &hw->phy;
2031 s32 ret_val;
2032 u16 data;
2033 bool link;
2034
2035 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2036 if (ret_val)
2037 return ret_val;
2038
2039 if (!link) {
2040 e_dbg("Phy info is only valid if link is up\n");
2041 return -E1000_ERR_CONFIG;
2042 }
2043
2044 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2045 if (ret_val)
2046 return ret_val;
2047 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2048
2049 if (phy->polarity_correction) {
2050 ret_val = e1000_check_polarity_ife(hw);
2051 if (ret_val)
2052 return ret_val;
2053 } else {
2054 /* Polarity is forced */
2055 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2056 ? e1000_rev_polarity_reversed
2057 : e1000_rev_polarity_normal);
2058 }
2059
2060 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2061 if (ret_val)
2062 return ret_val;
2063
2064 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2065
2066 /* The following parameters are undefined for 10/100 operation. */
2067 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2068 phy->local_rx = e1000_1000t_rx_status_undefined;
2069 phy->remote_rx = e1000_1000t_rx_status_undefined;
2070
2071 return 0;
2072}
2073
2074/**
2075 * e1000e_phy_sw_reset - PHY software reset
2076 * @hw: pointer to the HW structure
2077 *
2078 * Does a software reset of the PHY by reading the PHY control register and
2079 * setting/write the control register reset bit to the PHY.
2080 **/
2081s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2082{
2083 s32 ret_val;
2084 u16 phy_ctrl;
2085
2086 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2087 if (ret_val)
2088 return ret_val;
2089
2090 phy_ctrl |= BMCR_RESET;
2091 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2092 if (ret_val)
2093 return ret_val;
2094
2095 udelay(1);
2096
2097 return ret_val;
2098}
2099
2100/**
2101 * e1000e_phy_hw_reset_generic - PHY hardware reset
2102 * @hw: pointer to the HW structure
2103 *
2104 * Verify the reset block is not blocking us from resetting. Acquire
2105 * semaphore (if necessary) and read/set/write the device control reset
2106 * bit in the PHY. Wait the appropriate delay time for the device to
2107 * reset and release the semaphore (if necessary).
2108 **/
2109s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2110{
2111 struct e1000_phy_info *phy = &hw->phy;
2112 s32 ret_val;
2113 u32 ctrl;
2114
2115 if (phy->ops.check_reset_block) {
2116 ret_val = phy->ops.check_reset_block(hw);
2117 if (ret_val)
2118 return 0;
2119 }
2120
2121 ret_val = phy->ops.acquire(hw);
2122 if (ret_val)
2123 return ret_val;
2124
2125 ctrl = er32(CTRL);
2126 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2127 e1e_flush();
2128
2129 udelay(phy->reset_delay_us);
2130
2131 ew32(CTRL, ctrl);
2132 e1e_flush();
2133
2134 usleep_range(150, 300);
2135
2136 phy->ops.release(hw);
2137
2138 return phy->ops.get_cfg_done(hw);
2139}
2140
2141/**
2142 * e1000e_get_cfg_done_generic - Generic configuration done
2143 * @hw: pointer to the HW structure
2144 *
2145 * Generic function to wait 10 milli-seconds for configuration to complete
2146 * and return success.
2147 **/
2148s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2149{
2150 mdelay(10);
2151
2152 return 0;
2153}
2154
2155/**
2156 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2157 * @hw: pointer to the HW structure
2158 *
2159 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2160 **/
2161s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2162{
2163 e_dbg("Running IGP 3 PHY init script\n");
2164
2165 /* PHY init IGP 3 */
2166 /* Enable rise/fall, 10-mode work in class-A */
2167 e1e_wphy(hw, 0x2F5B, 0x9018);
2168 /* Remove all caps from Replica path filter */
2169 e1e_wphy(hw, 0x2F52, 0x0000);
2170 /* Bias trimming for ADC, AFE and Driver (Default) */
2171 e1e_wphy(hw, 0x2FB1, 0x8B24);
2172 /* Increase Hybrid poly bias */
2173 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2174 /* Add 4% to Tx amplitude in Gig mode */
2175 e1e_wphy(hw, 0x2010, 0x10B0);
2176 /* Disable trimming (TTT) */
2177 e1e_wphy(hw, 0x2011, 0x0000);
2178 /* Poly DC correction to 94.6% + 2% for all channels */
2179 e1e_wphy(hw, 0x20DD, 0x249A);
2180 /* ABS DC correction to 95.9% */
2181 e1e_wphy(hw, 0x20DE, 0x00D3);
2182 /* BG temp curve trim */
2183 e1e_wphy(hw, 0x28B4, 0x04CE);
2184 /* Increasing ADC OPAMP stage 1 currents to max */
2185 e1e_wphy(hw, 0x2F70, 0x29E4);
2186 /* Force 1000 ( required for enabling PHY regs configuration) */
2187 e1e_wphy(hw, 0x0000, 0x0140);
2188 /* Set upd_freq to 6 */
2189 e1e_wphy(hw, 0x1F30, 0x1606);
2190 /* Disable NPDFE */
2191 e1e_wphy(hw, 0x1F31, 0xB814);
2192 /* Disable adaptive fixed FFE (Default) */
2193 e1e_wphy(hw, 0x1F35, 0x002A);
2194 /* Enable FFE hysteresis */
2195 e1e_wphy(hw, 0x1F3E, 0x0067);
2196 /* Fixed FFE for short cable lengths */
2197 e1e_wphy(hw, 0x1F54, 0x0065);
2198 /* Fixed FFE for medium cable lengths */
2199 e1e_wphy(hw, 0x1F55, 0x002A);
2200 /* Fixed FFE for long cable lengths */
2201 e1e_wphy(hw, 0x1F56, 0x002A);
2202 /* Enable Adaptive Clip Threshold */
2203 e1e_wphy(hw, 0x1F72, 0x3FB0);
2204 /* AHT reset limit to 1 */
2205 e1e_wphy(hw, 0x1F76, 0xC0FF);
2206 /* Set AHT master delay to 127 msec */
2207 e1e_wphy(hw, 0x1F77, 0x1DEC);
2208 /* Set scan bits for AHT */
2209 e1e_wphy(hw, 0x1F78, 0xF9EF);
2210 /* Set AHT Preset bits */
2211 e1e_wphy(hw, 0x1F79, 0x0210);
2212 /* Change integ_factor of channel A to 3 */
2213 e1e_wphy(hw, 0x1895, 0x0003);
2214 /* Change prop_factor of channels BCD to 8 */
2215 e1e_wphy(hw, 0x1796, 0x0008);
2216 /* Change cg_icount + enable integbp for channels BCD */
2217 e1e_wphy(hw, 0x1798, 0xD008);
2218 /* Change cg_icount + enable integbp + change prop_factor_master
2219 * to 8 for channel A
2220 */
2221 e1e_wphy(hw, 0x1898, 0xD918);
2222 /* Disable AHT in Slave mode on channel A */
2223 e1e_wphy(hw, 0x187A, 0x0800);
2224 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2225 * Enable SPD+B2B
2226 */
2227 e1e_wphy(hw, 0x0019, 0x008D);
2228 /* Enable restart AN on an1000_dis change */
2229 e1e_wphy(hw, 0x001B, 0x2080);
2230 /* Enable wh_fifo read clock in 10/100 modes */
2231 e1e_wphy(hw, 0x0014, 0x0045);
2232 /* Restart AN, Speed selection is 1000 */
2233 e1e_wphy(hw, 0x0000, 0x1340);
2234
2235 return 0;
2236}
2237
2238/**
2239 * e1000e_get_phy_type_from_id - Get PHY type from id
2240 * @phy_id: phy_id read from the phy
2241 *
2242 * Returns the phy type from the id.
2243 **/
2244enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2245{
2246 enum e1000_phy_type phy_type = e1000_phy_unknown;
2247
2248 switch (phy_id) {
2249 case M88E1000_I_PHY_ID:
2250 case M88E1000_E_PHY_ID:
2251 case M88E1111_I_PHY_ID:
2252 case M88E1011_I_PHY_ID:
2253 phy_type = e1000_phy_m88;
2254 break;
2255 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2256 phy_type = e1000_phy_igp_2;
2257 break;
2258 case GG82563_E_PHY_ID:
2259 phy_type = e1000_phy_gg82563;
2260 break;
2261 case IGP03E1000_E_PHY_ID:
2262 phy_type = e1000_phy_igp_3;
2263 break;
2264 case IFE_E_PHY_ID:
2265 case IFE_PLUS_E_PHY_ID:
2266 case IFE_C_E_PHY_ID:
2267 phy_type = e1000_phy_ife;
2268 break;
2269 case BME1000_E_PHY_ID:
2270 case BME1000_E_PHY_ID_R2:
2271 phy_type = e1000_phy_bm;
2272 break;
2273 case I82578_E_PHY_ID:
2274 phy_type = e1000_phy_82578;
2275 break;
2276 case I82577_E_PHY_ID:
2277 phy_type = e1000_phy_82577;
2278 break;
2279 case I82579_E_PHY_ID:
2280 phy_type = e1000_phy_82579;
2281 break;
2282 case I217_E_PHY_ID:
2283 phy_type = e1000_phy_i217;
2284 break;
2285 default:
2286 phy_type = e1000_phy_unknown;
2287 break;
2288 }
2289 return phy_type;
2290}
2291
2292/**
2293 * e1000e_determine_phy_address - Determines PHY address.
2294 * @hw: pointer to the HW structure
2295 *
2296 * This uses a trial and error method to loop through possible PHY
2297 * addresses. It tests each by reading the PHY ID registers and
2298 * checking for a match.
2299 **/
2300s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2301{
2302 u32 phy_addr = 0;
2303 u32 i;
2304 enum e1000_phy_type phy_type = e1000_phy_unknown;
2305
2306 hw->phy.id = phy_type;
2307
2308 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2309 hw->phy.addr = phy_addr;
2310 i = 0;
2311
2312 do {
2313 e1000e_get_phy_id(hw);
2314 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2315
2316 /* If phy_type is valid, break - we found our
2317 * PHY address
2318 */
2319 if (phy_type != e1000_phy_unknown)
2320 return 0;
2321
2322 usleep_range(1000, 2000);
2323 i++;
2324 } while (i < 10);
2325 }
2326
2327 return -E1000_ERR_PHY_TYPE;
2328}
2329
2330/**
2331 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2332 * @page: page to access
2333 *
2334 * Returns the phy address for the page requested.
2335 **/
2336static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2337{
2338 u32 phy_addr = 2;
2339
2340 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2341 phy_addr = 1;
2342
2343 return phy_addr;
2344}
2345
2346/**
2347 * e1000e_write_phy_reg_bm - Write BM PHY register
2348 * @hw: pointer to the HW structure
2349 * @offset: register offset to write to
2350 * @data: data to write at register offset
2351 *
2352 * Acquires semaphore, if necessary, then writes the data to PHY register
2353 * at the offset. Release any acquired semaphores before exiting.
2354 **/
2355s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2356{
2357 s32 ret_val;
2358 u32 page = offset >> IGP_PAGE_SHIFT;
2359
2360 ret_val = hw->phy.ops.acquire(hw);
2361 if (ret_val)
2362 return ret_val;
2363
2364 /* Page 800 works differently than the rest so it has its own func */
2365 if (page == BM_WUC_PAGE) {
2366 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2367 false, false);
2368 goto release;
2369 }
2370
2371 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2372
2373 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2374 u32 page_shift, page_select;
2375
2376 /* Page select is register 31 for phy address 1 and 22 for
2377 * phy address 2 and 3. Page select is shifted only for
2378 * phy address 1.
2379 */
2380 if (hw->phy.addr == 1) {
2381 page_shift = IGP_PAGE_SHIFT;
2382 page_select = IGP01E1000_PHY_PAGE_SELECT;
2383 } else {
2384 page_shift = 0;
2385 page_select = BM_PHY_PAGE_SELECT;
2386 }
2387
2388 /* Page is shifted left, PHY expects (page x 32) */
2389 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2390 (page << page_shift));
2391 if (ret_val)
2392 goto release;
2393 }
2394
2395 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2396 data);
2397
2398release:
2399 hw->phy.ops.release(hw);
2400 return ret_val;
2401}
2402
2403/**
2404 * e1000e_read_phy_reg_bm - Read BM PHY register
2405 * @hw: pointer to the HW structure
2406 * @offset: register offset to be read
2407 * @data: pointer to the read data
2408 *
2409 * Acquires semaphore, if necessary, then reads the PHY register at offset
2410 * and storing the retrieved information in data. Release any acquired
2411 * semaphores before exiting.
2412 **/
2413s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2414{
2415 s32 ret_val;
2416 u32 page = offset >> IGP_PAGE_SHIFT;
2417
2418 ret_val = hw->phy.ops.acquire(hw);
2419 if (ret_val)
2420 return ret_val;
2421
2422 /* Page 800 works differently than the rest so it has its own func */
2423 if (page == BM_WUC_PAGE) {
2424 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2425 true, false);
2426 goto release;
2427 }
2428
2429 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2430
2431 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2432 u32 page_shift, page_select;
2433
2434 /* Page select is register 31 for phy address 1 and 22 for
2435 * phy address 2 and 3. Page select is shifted only for
2436 * phy address 1.
2437 */
2438 if (hw->phy.addr == 1) {
2439 page_shift = IGP_PAGE_SHIFT;
2440 page_select = IGP01E1000_PHY_PAGE_SELECT;
2441 } else {
2442 page_shift = 0;
2443 page_select = BM_PHY_PAGE_SELECT;
2444 }
2445
2446 /* Page is shifted left, PHY expects (page x 32) */
2447 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2448 (page << page_shift));
2449 if (ret_val)
2450 goto release;
2451 }
2452
2453 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2454 data);
2455release:
2456 hw->phy.ops.release(hw);
2457 return ret_val;
2458}
2459
2460/**
2461 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2462 * @hw: pointer to the HW structure
2463 * @offset: register offset to be read
2464 * @data: pointer to the read data
2465 *
2466 * Acquires semaphore, if necessary, then reads the PHY register at offset
2467 * and storing the retrieved information in data. Release any acquired
2468 * semaphores before exiting.
2469 **/
2470s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2471{
2472 s32 ret_val;
2473 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2474
2475 ret_val = hw->phy.ops.acquire(hw);
2476 if (ret_val)
2477 return ret_val;
2478
2479 /* Page 800 works differently than the rest so it has its own func */
2480 if (page == BM_WUC_PAGE) {
2481 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2482 true, false);
2483 goto release;
2484 }
2485
2486 hw->phy.addr = 1;
2487
2488 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2489 /* Page is shifted left, PHY expects (page x 32) */
2490 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2491 page);
2492
2493 if (ret_val)
2494 goto release;
2495 }
2496
2497 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2498 data);
2499release:
2500 hw->phy.ops.release(hw);
2501 return ret_val;
2502}
2503
2504/**
2505 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2506 * @hw: pointer to the HW structure
2507 * @offset: register offset to write to
2508 * @data: data to write at register offset
2509 *
2510 * Acquires semaphore, if necessary, then writes the data to PHY register
2511 * at the offset. Release any acquired semaphores before exiting.
2512 **/
2513s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2514{
2515 s32 ret_val;
2516 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2517
2518 ret_val = hw->phy.ops.acquire(hw);
2519 if (ret_val)
2520 return ret_val;
2521
2522 /* Page 800 works differently than the rest so it has its own func */
2523 if (page == BM_WUC_PAGE) {
2524 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2525 false, false);
2526 goto release;
2527 }
2528
2529 hw->phy.addr = 1;
2530
2531 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2532 /* Page is shifted left, PHY expects (page x 32) */
2533 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2534 page);
2535
2536 if (ret_val)
2537 goto release;
2538 }
2539
2540 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2541 data);
2542
2543release:
2544 hw->phy.ops.release(hw);
2545 return ret_val;
2546}
2547
2548/**
2549 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2550 * @hw: pointer to the HW structure
2551 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2552 *
2553 * Assumes semaphore already acquired and phy_reg points to a valid memory
2554 * address to store contents of the BM_WUC_ENABLE_REG register.
2555 **/
2556s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2557{
2558 s32 ret_val;
2559 u16 temp;
2560
2561 /* All page select, port ctrl and wakeup registers use phy address 1 */
2562 hw->phy.addr = 1;
2563
2564 /* Select Port Control Registers page */
2565 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2566 if (ret_val) {
2567 e_dbg("Could not set Port Control page\n");
2568 return ret_val;
2569 }
2570
2571 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2572 if (ret_val) {
2573 e_dbg("Could not read PHY register %d.%d\n",
2574 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2575 return ret_val;
2576 }
2577
2578 /* Enable both PHY wakeup mode and Wakeup register page writes.
2579 * Prevent a power state change by disabling ME and Host PHY wakeup.
2580 */
2581 temp = *phy_reg;
2582 temp |= BM_WUC_ENABLE_BIT;
2583 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2584
2585 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2586 if (ret_val) {
2587 e_dbg("Could not write PHY register %d.%d\n",
2588 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2589 return ret_val;
2590 }
2591
2592 /* Select Host Wakeup Registers page - caller now able to write
2593 * registers on the Wakeup registers page
2594 */
2595 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2596}
2597
2598/**
2599 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2600 * @hw: pointer to the HW structure
2601 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2602 *
2603 * Restore BM_WUC_ENABLE_REG to its original value.
2604 *
2605 * Assumes semaphore already acquired and *phy_reg is the contents of the
2606 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2607 * caller.
2608 **/
2609s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2610{
2611 s32 ret_val;
2612
2613 /* Select Port Control Registers page */
2614 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2615 if (ret_val) {
2616 e_dbg("Could not set Port Control page\n");
2617 return ret_val;
2618 }
2619
2620 /* Restore 769.17 to its original value */
2621 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2622 if (ret_val)
2623 e_dbg("Could not restore PHY register %d.%d\n",
2624 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2625
2626 return ret_val;
2627}
2628
2629/**
2630 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2631 * @hw: pointer to the HW structure
2632 * @offset: register offset to be read or written
2633 * @data: pointer to the data to read or write
2634 * @read: determines if operation is read or write
2635 * @page_set: BM_WUC_PAGE already set and access enabled
2636 *
2637 * Read the PHY register at offset and store the retrieved information in
2638 * data, or write data to PHY register at offset. Note the procedure to
2639 * access the PHY wakeup registers is different than reading the other PHY
2640 * registers. It works as such:
2641 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2642 * 2) Set page to 800 for host (801 if we were manageability)
2643 * 3) Write the address using the address opcode (0x11)
2644 * 4) Read or write the data using the data opcode (0x12)
2645 * 5) Restore 769.17.2 to its original value
2646 *
2647 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2648 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2649 *
2650 * Assumes semaphore is already acquired. When page_set==true, assumes
2651 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2652 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2653 **/
2654static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2655 u16 *data, bool read, bool page_set)
2656{
2657 s32 ret_val;
2658 u16 reg = BM_PHY_REG_NUM(offset);
2659 u16 page = BM_PHY_REG_PAGE(offset);
2660 u16 phy_reg = 0;
2661
2662 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2663 if ((hw->mac.type == e1000_pchlan) &&
2664 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2665 e_dbg("Attempting to access page %d while gig enabled.\n",
2666 page);
2667
2668 if (!page_set) {
2669 /* Enable access to PHY wakeup registers */
2670 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2671 if (ret_val) {
2672 e_dbg("Could not enable PHY wakeup reg access\n");
2673 return ret_val;
2674 }
2675 }
2676
2677 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2678
2679 /* Write the Wakeup register page offset value using opcode 0x11 */
2680 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2681 if (ret_val) {
2682 e_dbg("Could not write address opcode to page %d\n", page);
2683 return ret_val;
2684 }
2685
2686 if (read) {
2687 /* Read the Wakeup register page value using opcode 0x12 */
2688 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2689 data);
2690 } else {
2691 /* Write the Wakeup register page value using opcode 0x12 */
2692 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2693 *data);
2694 }
2695
2696 if (ret_val) {
2697 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2698 return ret_val;
2699 }
2700
2701 if (!page_set)
2702 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2703
2704 return ret_val;
2705}
2706
2707/**
2708 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2709 * @hw: pointer to the HW structure
2710 *
2711 * In the case of a PHY power down to save power, or to turn off link during a
2712 * driver unload, or wake on lan is not enabled, restore the link to previous
2713 * settings.
2714 **/
2715void e1000_power_up_phy_copper(struct e1000_hw *hw)
2716{
2717 u16 mii_reg = 0;
2718
2719 /* The PHY will retain its settings across a power down/up cycle */
2720 e1e_rphy(hw, MII_BMCR, &mii_reg);
2721 mii_reg &= ~BMCR_PDOWN;
2722 e1e_wphy(hw, MII_BMCR, mii_reg);
2723}
2724
2725/**
2726 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2727 * @hw: pointer to the HW structure
2728 *
2729 * In the case of a PHY power down to save power, or to turn off link during a
2730 * driver unload, or wake on lan is not enabled, restore the link to previous
2731 * settings.
2732 **/
2733void e1000_power_down_phy_copper(struct e1000_hw *hw)
2734{
2735 u16 mii_reg = 0;
2736
2737 /* The PHY will retain its settings across a power down/up cycle */
2738 e1e_rphy(hw, MII_BMCR, &mii_reg);
2739 mii_reg |= BMCR_PDOWN;
2740 e1e_wphy(hw, MII_BMCR, mii_reg);
2741 usleep_range(1000, 2000);
2742}
2743
2744/**
2745 * __e1000_read_phy_reg_hv - Read HV PHY register
2746 * @hw: pointer to the HW structure
2747 * @offset: register offset to be read
2748 * @data: pointer to the read data
2749 * @locked: semaphore has already been acquired or not
2750 *
2751 * Acquires semaphore, if necessary, then reads the PHY register at offset
2752 * and stores the retrieved information in data. Release any acquired
2753 * semaphore before exiting.
2754 **/
2755static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2756 bool locked, bool page_set)
2757{
2758 s32 ret_val;
2759 u16 page = BM_PHY_REG_PAGE(offset);
2760 u16 reg = BM_PHY_REG_NUM(offset);
2761 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2762
2763 if (!locked) {
2764 ret_val = hw->phy.ops.acquire(hw);
2765 if (ret_val)
2766 return ret_val;
2767 }
2768
2769 /* Page 800 works differently than the rest so it has its own func */
2770 if (page == BM_WUC_PAGE) {
2771 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2772 true, page_set);
2773 goto out;
2774 }
2775
2776 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2777 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2778 data, true);
2779 goto out;
2780 }
2781
2782 if (!page_set) {
2783 if (page == HV_INTC_FC_PAGE_START)
2784 page = 0;
2785
2786 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2787 /* Page is shifted left, PHY expects (page x 32) */
2788 ret_val = e1000_set_page_igp(hw,
2789 (page << IGP_PAGE_SHIFT));
2790
2791 hw->phy.addr = phy_addr;
2792
2793 if (ret_val)
2794 goto out;
2795 }
2796 }
2797
2798 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2799 page << IGP_PAGE_SHIFT, reg);
2800
2801 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2802out:
2803 if (!locked)
2804 hw->phy.ops.release(hw);
2805
2806 return ret_val;
2807}
2808
2809/**
2810 * e1000_read_phy_reg_hv - Read HV PHY register
2811 * @hw: pointer to the HW structure
2812 * @offset: register offset to be read
2813 * @data: pointer to the read data
2814 *
2815 * Acquires semaphore then reads the PHY register at offset and stores
2816 * the retrieved information in data. Release the acquired semaphore
2817 * before exiting.
2818 **/
2819s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2820{
2821 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2822}
2823
2824/**
2825 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2826 * @hw: pointer to the HW structure
2827 * @offset: register offset to be read
2828 * @data: pointer to the read data
2829 *
2830 * Reads the PHY register at offset and stores the retrieved information
2831 * in data. Assumes semaphore already acquired.
2832 **/
2833s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2834{
2835 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2836}
2837
2838/**
2839 * e1000_read_phy_reg_page_hv - Read HV PHY register
2840 * @hw: pointer to the HW structure
2841 * @offset: register offset to write to
2842 * @data: data to write at register offset
2843 *
2844 * Reads the PHY register at offset and stores the retrieved information
2845 * in data. Assumes semaphore already acquired and page already set.
2846 **/
2847s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2848{
2849 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2850}
2851
2852/**
2853 * __e1000_write_phy_reg_hv - Write HV PHY register
2854 * @hw: pointer to the HW structure
2855 * @offset: register offset to write to
2856 * @data: data to write at register offset
2857 * @locked: semaphore has already been acquired or not
2858 *
2859 * Acquires semaphore, if necessary, then writes the data to PHY register
2860 * at the offset. Release any acquired semaphores before exiting.
2861 **/
2862static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2863 bool locked, bool page_set)
2864{
2865 s32 ret_val;
2866 u16 page = BM_PHY_REG_PAGE(offset);
2867 u16 reg = BM_PHY_REG_NUM(offset);
2868 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2869
2870 if (!locked) {
2871 ret_val = hw->phy.ops.acquire(hw);
2872 if (ret_val)
2873 return ret_val;
2874 }
2875
2876 /* Page 800 works differently than the rest so it has its own func */
2877 if (page == BM_WUC_PAGE) {
2878 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2879 false, page_set);
2880 goto out;
2881 }
2882
2883 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2884 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2885 &data, false);
2886 goto out;
2887 }
2888
2889 if (!page_set) {
2890 if (page == HV_INTC_FC_PAGE_START)
2891 page = 0;
2892
2893 /* Workaround MDIO accesses being disabled after entering IEEE
2894 * Power Down (when bit 11 of the PHY Control register is set)
2895 */
2896 if ((hw->phy.type == e1000_phy_82578) &&
2897 (hw->phy.revision >= 1) &&
2898 (hw->phy.addr == 2) &&
2899 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2900 u16 data2 = 0x7EFF;
2901
2902 ret_val = e1000_access_phy_debug_regs_hv(hw,
2903 BIT(6) | 0x3,
2904 &data2, false);
2905 if (ret_val)
2906 goto out;
2907 }
2908
2909 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2910 /* Page is shifted left, PHY expects (page x 32) */
2911 ret_val = e1000_set_page_igp(hw,
2912 (page << IGP_PAGE_SHIFT));
2913
2914 hw->phy.addr = phy_addr;
2915
2916 if (ret_val)
2917 goto out;
2918 }
2919 }
2920
2921 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2922 page << IGP_PAGE_SHIFT, reg);
2923
2924 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2925 data);
2926
2927out:
2928 if (!locked)
2929 hw->phy.ops.release(hw);
2930
2931 return ret_val;
2932}
2933
2934/**
2935 * e1000_write_phy_reg_hv - Write HV PHY register
2936 * @hw: pointer to the HW structure
2937 * @offset: register offset to write to
2938 * @data: data to write at register offset
2939 *
2940 * Acquires semaphore then writes the data to PHY register at the offset.
2941 * Release the acquired semaphores before exiting.
2942 **/
2943s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2944{
2945 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2946}
2947
2948/**
2949 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2950 * @hw: pointer to the HW structure
2951 * @offset: register offset to write to
2952 * @data: data to write at register offset
2953 *
2954 * Writes the data to PHY register at the offset. Assumes semaphore
2955 * already acquired.
2956 **/
2957s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2958{
2959 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2960}
2961
2962/**
2963 * e1000_write_phy_reg_page_hv - Write HV PHY register
2964 * @hw: pointer to the HW structure
2965 * @offset: register offset to write to
2966 * @data: data to write at register offset
2967 *
2968 * Writes the data to PHY register at the offset. Assumes semaphore
2969 * already acquired and page already set.
2970 **/
2971s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2972{
2973 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2974}
2975
2976/**
2977 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2978 * @page: page to be accessed
2979 **/
2980static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2981{
2982 u32 phy_addr = 2;
2983
2984 if (page >= HV_INTC_FC_PAGE_START)
2985 phy_addr = 1;
2986
2987 return phy_addr;
2988}
2989
2990/**
2991 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2992 * @hw: pointer to the HW structure
2993 * @offset: register offset to be read or written
2994 * @data: pointer to the data to be read or written
2995 * @read: determines if operation is read or write
2996 *
2997 * Reads the PHY register at offset and stores the retreived information
2998 * in data. Assumes semaphore already acquired. Note that the procedure
2999 * to access these regs uses the address port and data port to read/write.
3000 * These accesses done with PHY address 2 and without using pages.
3001 **/
3002static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3003 u16 *data, bool read)
3004{
3005 s32 ret_val;
3006 u32 addr_reg;
3007 u32 data_reg;
3008
3009 /* This takes care of the difference with desktop vs mobile phy */
3010 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3011 I82578_ADDR_REG : I82577_ADDR_REG);
3012 data_reg = addr_reg + 1;
3013
3014 /* All operations in this function are phy address 2 */
3015 hw->phy.addr = 2;
3016
3017 /* masking with 0x3F to remove the page from offset */
3018 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3019 if (ret_val) {
3020 e_dbg("Could not write the Address Offset port register\n");
3021 return ret_val;
3022 }
3023
3024 /* Read or write the data value next */
3025 if (read)
3026 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3027 else
3028 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3029
3030 if (ret_val)
3031 e_dbg("Could not access the Data port register\n");
3032
3033 return ret_val;
3034}
3035
3036/**
3037 * e1000_link_stall_workaround_hv - Si workaround
3038 * @hw: pointer to the HW structure
3039 *
3040 * This function works around a Si bug where the link partner can get
3041 * a link up indication before the PHY does. If small packets are sent
3042 * by the link partner they can be placed in the packet buffer without
3043 * being properly accounted for by the PHY and will stall preventing
3044 * further packets from being received. The workaround is to clear the
3045 * packet buffer after the PHY detects link up.
3046 **/
3047s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3048{
3049 s32 ret_val = 0;
3050 u16 data;
3051
3052 if (hw->phy.type != e1000_phy_82578)
3053 return 0;
3054
3055 /* Do not apply workaround if in PHY loopback bit 14 set */
3056 e1e_rphy(hw, MII_BMCR, &data);
3057 if (data & BMCR_LOOPBACK)
3058 return 0;
3059
3060 /* check if link is up and at 1Gbps */
3061 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3062 if (ret_val)
3063 return ret_val;
3064
3065 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3066 BM_CS_STATUS_SPEED_MASK);
3067
3068 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3069 BM_CS_STATUS_SPEED_1000))
3070 return 0;
3071
3072 msleep(200);
3073
3074 /* flush the packets in the fifo buffer */
3075 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3076 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3077 HV_MUX_DATA_CTRL_FORCE_SPEED));
3078 if (ret_val)
3079 return ret_val;
3080
3081 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3082}
3083
3084/**
3085 * e1000_check_polarity_82577 - Checks the polarity.
3086 * @hw: pointer to the HW structure
3087 *
3088 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3089 *
3090 * Polarity is determined based on the PHY specific status register.
3091 **/
3092s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3093{
3094 struct e1000_phy_info *phy = &hw->phy;
3095 s32 ret_val;
3096 u16 data;
3097
3098 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3099
3100 if (!ret_val)
3101 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3102 ? e1000_rev_polarity_reversed
3103 : e1000_rev_polarity_normal);
3104
3105 return ret_val;
3106}
3107
3108/**
3109 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3110 * @hw: pointer to the HW structure
3111 *
3112 * Calls the PHY setup function to force speed and duplex.
3113 **/
3114s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3115{
3116 struct e1000_phy_info *phy = &hw->phy;
3117 s32 ret_val;
3118 u16 phy_data;
3119 bool link;
3120
3121 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3122 if (ret_val)
3123 return ret_val;
3124
3125 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3126
3127 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3128 if (ret_val)
3129 return ret_val;
3130
3131 udelay(1);
3132
3133 if (phy->autoneg_wait_to_complete) {
3134 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3135
3136 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3137 100000, &link);
3138 if (ret_val)
3139 return ret_val;
3140
3141 if (!link)
3142 e_dbg("Link taking longer than expected.\n");
3143
3144 /* Try once more */
3145 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3146 100000, &link);
3147 }
3148
3149 return ret_val;
3150}
3151
3152/**
3153 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3154 * @hw: pointer to the HW structure
3155 *
3156 * Read PHY status to determine if link is up. If link is up, then
3157 * set/determine 10base-T extended distance and polarity correction. Read
3158 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3159 * determine on the cable length, local and remote receiver.
3160 **/
3161s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3162{
3163 struct e1000_phy_info *phy = &hw->phy;
3164 s32 ret_val;
3165 u16 data;
3166 bool link;
3167
3168 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3169 if (ret_val)
3170 return ret_val;
3171
3172 if (!link) {
3173 e_dbg("Phy info is only valid if link is up\n");
3174 return -E1000_ERR_CONFIG;
3175 }
3176
3177 phy->polarity_correction = true;
3178
3179 ret_val = e1000_check_polarity_82577(hw);
3180 if (ret_val)
3181 return ret_val;
3182
3183 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3184 if (ret_val)
3185 return ret_val;
3186
3187 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3188
3189 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3190 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3191 ret_val = hw->phy.ops.get_cable_length(hw);
3192 if (ret_val)
3193 return ret_val;
3194
3195 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3196 if (ret_val)
3197 return ret_val;
3198
3199 phy->local_rx = (data & LPA_1000LOCALRXOK)
3200 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3201
3202 phy->remote_rx = (data & LPA_1000REMRXOK)
3203 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3204 } else {
3205 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3206 phy->local_rx = e1000_1000t_rx_status_undefined;
3207 phy->remote_rx = e1000_1000t_rx_status_undefined;
3208 }
3209
3210 return 0;
3211}
3212
3213/**
3214 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3215 * @hw: pointer to the HW structure
3216 *
3217 * Reads the diagnostic status register and verifies result is valid before
3218 * placing it in the phy_cable_length field.
3219 **/
3220s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3221{
3222 struct e1000_phy_info *phy = &hw->phy;
3223 s32 ret_val;
3224 u16 phy_data, length;
3225
3226 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3227 if (ret_val)
3228 return ret_val;
3229
3230 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3231 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3232
3233 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3234 return -E1000_ERR_PHY;
3235
3236 phy->cable_length = length;
3237
3238 return 0;
3239}